Semiconductor device

Abstract

A semiconductor device can include a substrate including a first active region and a second active region and a field region therebetween, a first active pattern and a second active pattern provided on the first active region and the second active region, respectively, a first source / drain pattern and a second source / drain pattern provided on the first active pattern and the second active pattern, respectively, a first channel pattern between the first source / drain pattern and a second channel pattern between the second source / drain pattern, and a gate electrode extending from the first channel pattern to the second channel pattern to straddle the field region. Each of the first channel pattern and the second channel pattern can include semiconductor patterns stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region can decrease as a distance from a top surface of the substrate decreases.

Description

Technical Field

[0001] This disclosure relates to integrated circuit devices, and more particularly, to highly integrated field-effect transistors (e.g., PMOS, NMOS) and methods of manufacturing them. Background Technology

[0002] An example of a semiconductor device within an integrated circuit includes a metal-oxide-semiconductor field-effect transistor (MOSFET). To meet the growing demand for semiconductor devices with small pattern dimensions (e.g., small layout footprint) and reduced design rules, MOSFETs are being actively scaled down. Unfortunately, scaling down MOSFETs can lead to a degradation in the operating characteristics of these semiconductor devices. Various studies are underway to overcome the technological limitations associated with the scaling down of semiconductor devices and to achieve higher-performance semiconductor devices with high yield and reliability. Summary of the Invention

[0003] Embodiments of the present invention provide semiconductor devices with improved electrical characteristics and higher reliability, as well as methods for manufacturing the same.

[0004] According to one embodiment of the present invention, a semiconductor device may include a substrate comprising a first active region, a second active region, and a field region extending between the first and second active regions. A first active pattern is provided on the first active region, and a second active pattern is provided on the second active region. A first source / drain pattern is provided on the first active pattern, and a second source / drain pattern is provided on the second active pattern. A first channel pattern is provided between the first source / drain patterns, and a second channel pattern is provided between the second source / drain patterns. Each of the first and second channel patterns includes semiconductor patterns stacked and spaced apart from each other. A gate electrode is provided extending from the first channel pattern to the second channel pattern to cross the field region. Advantageously, the width of the lower portion of the gate electrode extending on and across the field region is configured to decrease as the distance to the top surface of the underlying substrate decreases.

[0005] According to another embodiment of the present invention, a semiconductor device may include an active pattern on a substrate and a first channel pattern and a second channel pattern on the active pattern. Each of the first channel pattern and the second channel pattern includes first to third semiconductor patterns stacked vertically and spaced apart from each other. A source / drain pattern is provided, interposed between the first channel pattern and the second channel pattern. A first gate electrode and a second gate electrode are provided, respectively overlapping the first channel pattern and the second channel pattern. A first gate spacer and a second gate spacer are provided on opposite side surfaces of the first gate electrode and the second gate electrode, respectively. In a plan view taken horizontally of the first semiconductor pattern, the source / drain pattern may extend from the first semiconductor pattern to the space between the first gate spacer and the second gate spacer. Each of the first gate spacer and the second gate spacer may include a first portion provided on the side surface of the gate electrode corresponding thereto, and a second portion protruding into the region between the first semiconductor pattern and the gate electrode. The second portion may be provided between the first semiconductor pattern and the gate electrode, and between the source / drain pattern and the gate electrode.

[0006] According to another embodiment of the present invention, a semiconductor device may include a substrate having a first active region, a second active region, and a field region therein. The field region may extend between the first and second active regions, and the first and second active regions may be adjacent to each other in a first direction. A first active pattern and a second active pattern are provided on the first and second active regions, respectively. A pair of first source / drain patterns are provided on the first active pattern, and a pair of second source / drain patterns are provided on the second active pattern. A first channel pattern is interposed between the pair of first source / drain patterns, and a second channel pattern is interposed between the pair of second source / drain patterns. Each of the first and second channel patterns includes a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern vertically stacked and spaced apart from each other. A gate electrode is provided extending from the first channel pattern to the second channel pattern and across the field region in a first direction. A first gate insulating layer and a second gate insulating layer are interposed between the first channel pattern and the gate electrode, and between the second channel pattern and the gate electrode, respectively. A gate spacer is provided on the side surface of the gate electrode, and a gate overlay pattern is provided on the top surface of the gate electrode. A first interlayer insulating layer is provided on the gate overlay pattern. An active contact is provided to penetrate the first interlayer insulating layer. The active contact is electrically connected to at least one of a first source / drain pattern and a second source / drain pattern. A gate contact is provided to penetrate the first interlayer insulating layer and is electrically connected to a gate electrode. A second interlayer insulating layer is provided on the first interlayer insulating layer. A first metal layer is provided in the second interlayer insulating layer. The first metal layer includes a first interconnect electrically connected to the active contact and the gate contact. A third interlayer insulating layer is provided on the second interlayer insulating layer, and a second metal layer is provided in the third interlayer insulating layer. The second metal layer may include a second interconnect electrically connected to the first interconnect. On each of the first and second active regions, the gate electrode may include a first portion interposed between the substrate and the first semiconductor pattern, a second portion interposed between the first and second semiconductor patterns, a third portion interposed between the second and third semiconductor patterns, and a fourth portion on the third semiconductor pattern. On the field region, the width of the lower portion of the gate electrode may decrease as the distance from the top surface of the substrate decreases. Attached Figure Description

[0007] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0008] Figure 2A , Figure 3 , Figure 4A , Figure 5 and Figure 6 They are along Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C', D-D', and E-E'.

[0009] Figure 2B yes Figure 2A Enlarged cross-sectional view of part M.

[0010] Figure 2C It is along Figure 2A The top view is taken by line F-F'.

[0011] Figure 4B yes Figure 4A A magnified cross-sectional view of part N.

[0012] Figures 7 to 41 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention.

[0013] Figure 7 , Figure 9 , Figure 12 , Figure 15 , Figure 20 , Figure 25 , Figure 30 , Figure 34 and Figure 38 It is along Figure 1 A cross-sectional view of a manufacturing method according to an embodiment of the present invention is shown by taking a section along line A-A'.

[0014] Figure 16 , Figure 21 , Figure 26 , Figure 31 , Figure 35 and Figure 39 It is along Figure 1 A cross-sectional view of a manufacturing method according to an embodiment of the present invention is shown by taking a section along line B-B'.

[0015] Figure 10 , Figure 13 , Figure 17 , Figure 22 , Figure 27 , Figure 32 , Figure 36 and Figure 40 It is along Figure 1 The line C-C' is cut to show a cross-sectional view of a manufacturing method according to an embodiment of the present invention.

[0016] Figure 18 , Figure 23 and Figure 28 It is along Figure 1 The line D-D' is cut to show a cross-sectional view of a manufacturing method according to an embodiment of the present invention.

[0017] Figure 8 , Figure 11 , Figure 14 , Figure 19 , Figure 24 , Figure 29 , Figure 33 , Figure 37 and Figure 41 It is along Figure 1 The line E-E' is cut to show a cross-sectional view of a manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0018] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention. Figure 2A , Figure 3 , Figure 4A , Figure 5 and Figure 6 They are along Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C', D-D', and E-E'. Figure 2B It is shown Figure 2A The highlighted portion M is an enlarged cross-sectional view, while Figure 2C It is along Figure 2A The top view is taken by line F-F'. Figure 4B It is shown Figure 4A The highlighted portion N is an enlarged cross-sectional view.

[0019] Reference Figure 1 , Figure 2A , Figure 3 , Figure 4A , Figure 5 and Figure 6 The logic cell LC can be provided on the substrate 100. Logic transistors, which are components of the logic circuit, can be disposed on the logic cell LC. The substrate 100 can be a semiconductor substrate formed of or including silicon, germanium, silicon-germanium, etc., or it can be a compound semiconductor substrate. As an example, the substrate 100 can be a silicon wafer, a silicon die, or a semiconductor-on-insulator (SOI) substrate.

[0020] The logic cell LC may include a PMOSFET region PR, an NMOSFET region NR, and a field region FR. The PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR2 formed in the lower portion of the substrate 100. In other words, the second trench TR2 may be placed between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1, with the second trench TR2 interposed therebetween. The field region FR may be interposed between the PMOSFET region PR and the NMOSFET region NR. The field region FR may represent the region between the PMOSFET region PR and the NMOSFET region NR. In this specification, the PMOSFET region PR may be referred to as the first active region PR, and the NMOSFET region NR may be referred to as the second active region NR.

[0021] The first active pattern AP1 and the second active pattern AP2 may be defined by a first trench TR1 formed in the upper portion of the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be provided on the PMOSFET region PR and the NMOSFET region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may not be provided on the field region FR. The first trench TR1 may be shallower than the second trench TR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertical protrusions of the substrate 100.

[0022] A device isolation layer ST may be provided to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a silicon oxide layer. The upper portions of the first active pattern AP1 and the second active pattern AP2 may protrude vertically above the device isolation layer ST (e.g., see...). Figure 6 The device isolation layer ST may not cover the upper part of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover the lower side surface of the first active pattern AP1 and the second active pattern AP2.

[0023] The first active pattern AP1 may include the upper portion serving as the first channel pattern CH1. The second active pattern AP2 may include the upper portion serving as the second channel pattern CH2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction (i.e., the third third direction D3).

[0024] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or comprise silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In one embodiment, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or comprise crystalline silicon.

[0025] Multiple first recesses RS1 can be formed in the upper portion of the first active pattern AP1. First source / drain patterns SD1 can be provided in the first recesses RS1 respectively. The first source / drain patterns SD1 can be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be interposed between each pair of first source / drain patterns SD1. In other words, each pair of first source / drain patterns SD1 can be interconnected with each other through the stacked first to third semiconductor patterns SP1, SP2, and SP3 of the first channel patterns CH1.

[0026] Multiple second recesses RS2 can be formed in the upper portion of the second active pattern AP2. Second source / drain patterns SD2 can be provided in the second recesses RS2 respectively. The second source / drain patterns SD2 can be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern CH2 can be interposed between each pair of second source / drain patterns SD2. In other words, each pair of second source / drain patterns SD2 can be interconnected through the stacked first to third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2.

[0027] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. As an example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface located at substantially the same level as the top surface of the third semiconductor pattern SP3. However, in one embodiment, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surface of the third semiconductor pattern SP3.

[0028] The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. In this case, a pair of first source / drain patterns SD1 may apply compressive stress to a first channel pattern CH1 between them. The second source / drain pattern SD2 may be formed of or comprise the same semiconductor material (e.g., Si) as the substrate 100.

[0029] Each first source / drain pattern SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 stacked sequentially. (Refer to...) Figure 2A Describe the cross-sectional shape of the first source / drain pattern SD1 taken parallel to the second direction D2.

[0030] The first semiconductor layer SEL1 may cover the inner surface of the first recess RS1. The first semiconductor layer SEL1 may have a decreasing thickness in the upward direction. For example, the thickness of the first semiconductor layer SEL1 measured along a third direction D3 at the bottom level of the first recess RS1 may be greater than the thickness of the first semiconductor layer SEL1 measured along a second direction D2 at the top level of the first recess RS1. Due to the cross-sectional profile of the first recess RS1, the first semiconductor layer SEL1 may have a "U" shaped cross-section.

[0031] The second semiconductor layer SEL2 can fill the remaining space of the first recess RS1 that excludes the first semiconductor layer SEL1. The volume of the second semiconductor layer SEL2 can be larger than the volume of the first semiconductor layer SEL1. In other words, the ratio of the volume of the second semiconductor layer SEL2 to the total volume of the first source / drain pattern SD1 can be greater than the ratio of the volume of the first semiconductor layer SEL1 to the total volume of the first source / drain pattern SD1.

[0032] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may be formed of or comprise silicon germanium (SiGe). Specifically, the first semiconductor layer SEL1 may be provided with a relatively low germanium concentration. In another embodiment, the first semiconductor layer SEL1 may be provided to comprise only silicon (Si) and not germanium (Ge). The germanium concentration of the first semiconductor layer SEL1 may be in the range of 0 at% to 10 at% (where at% represents atomic percentage).

[0033] The second semiconductor layer SEL2 can be provided with a relatively high germanium concentration. As an example, the germanium concentration of the second semiconductor layer SEL2 can be in the range of 30 at% to 70 at%. The germanium concentration of the second semiconductor layer SEL2 can be increased towards D3. For example, the germanium concentration of the second semiconductor layer SEL2 can be approximately 40 at% near the first semiconductor layer SEL1, but approximately 60 at% at its top level.

[0034] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include impurities (e.g., boron) to allow the first source / drain pattern SD1 to have p-type conductivity. In one embodiment, the impurity concentration (in at%) in the second semiconductor layer SEL2 may be greater than the impurity concentration in the first semiconductor layer SEL1.

[0035] The first semiconductor layer SEL1 can prevent stacking faults from occurring between the substrate 100 and the second semiconductor layer SEL2, and between the first to third semiconductor patterns SP1, SP2, and SP3 and the second semiconductor layer SEL2. Stacking faults can lead to an increase in channel resistance. Stacking faults can easily occur at the bottom of the first recess RS1. Therefore, if the first semiconductor layer SEL1 adjacent to the first recess RS1 is provided with a relatively large thickness, stacking faults can be prevented.

[0036] In a process where the sacrificial layer SAL is replaced by the first to third portions PO1, PO2, and PO3 of the gate electrode GE, the first semiconductor layer SEL1 can protect the second semiconductor layer SEL2. For example, the first semiconductor layer SEL1 can prevent the second semiconductor layer SEL2 from being undesirably etched by the etch material used to remove the sacrificial layer SAL.

[0037] The gate electrode GE can be provided to intersect with the first active pattern AP1 and the second active pattern AP2 and extend in a first direction D1. The gate electrode GE can be arranged in a second direction D2 with a first pitch P1. When viewed in a plan view, each gate electrode GE can overlap with the first channel pattern CH1 and the second channel pattern CH2.

[0038] The gate electrode GE may include a first portion PO1 inserted between the substrate 100 and the first semiconductor pattern SP1, a second portion PO2 inserted between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 inserted between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0039] Return to reference Figure 2A The first to third portions PO1, PO2, and PO3 of the gate electrode GE on the PMOSFET region PR can have different widths. For example, the maximum width of the third portion PO3 in the second direction D2 can be greater than the maximum width of the second portion PO2 in the second direction D2. The maximum width of the first portion PO1 in the second direction D2 can be greater than the maximum width of the third portion PO3 in the second direction D2.

[0040] Return to reference Figure 6 The gate electrode GE can be provided on the top surface TS, bottom surface BS, and opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. In other words, the logic transistor according to this embodiment can be a three-dimensional field-effect transistor (e.g., a multi-bridge channel field-effect transistor (MBCFET)) in which the gate electrode GE is provided three-dimensionally around the channel pattern.

[0041] Reference Figure 1, Figure 2A , Figure 3 , Figure 4A , Figure 5 and Figure 6 A pair of gate spacers GS can be disposed on opposite side surfaces of the fourth portion PO4 of the gate electrode GE. The gate spacers GS can extend along the gate electrode GE in a first direction D1. The top surface of the gate spacers GS can be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS can be coplanar with the top surface of the first interlayer insulating layer 110, as will be described below. The gate spacers GS can be formed of or include at least one of SiCN, SiCON, and SiN. In one embodiment, the gate spacers GS can have a multilayer structure comprising at least two layers, each of which is made of SiCN, SiCON, or SiN. (Refer to...) Figure 2B , Figure 2C and Figure 4B A more detailed description of the gate spacer GS.

[0042] A gate overlay pattern GP can be provided on the gate electrode GE. The gate overlay pattern GP can extend along the gate electrode GE and in a first direction D1. The gate overlay pattern GP can be formed of or include a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, as will be described below. For example, the gate overlay pattern GP can be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0043] The gate insulating layer GI can be interposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI can cover the top surface TS, bottom surface BS, and opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI can cover the top surface of the device isolation layer ST beneath the gate electrode GE (e.g., see...). Figure 6 ).

[0044] In one embodiment, the gate insulating layer GI may include a silicon oxide layer, a silicon oxide nitride layer, and / or a high-k dielectric layer. The high-k dielectric layer may be formed of or include at least one of high-k dielectric materials whose dielectric constant is higher than that of silicon oxide. As an example, the high-k dielectric material may be formed of or include at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0045] In another embodiment, the semiconductor device may include a negative capacitance (NC) FET that uses a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric material properties and a paraelectric layer exhibiting paraelectric material properties.

[0046] The ferroelectric layer can have negative capacitance, and the paraelectric layer can have positive capacitance. When two or more capacitors are connected in series and each capacitor has positive capacitance, the total capacitance can be less than the capacitance of each individual capacitor. In contrast, when at least one of the capacitors connected in series has negative capacitance, the total capacitance of the series-connected capacitors can have a positive value and can be greater than the absolute value of each individual capacitor.

[0047] When a ferroelectric layer with negative capacitance and a paraelectric layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric layers can be increased. Due to this increase in total capacitance, transistors including ferroelectric layers can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0048] The ferroelectric layer can possess ferroelectric material properties. The ferroelectric layer can be formed from or include at least one of the following: hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Here, hafnium zirconium oxide can be a zirconium-doped hafnium oxide. Alternatively, hafnium zirconium oxide can be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0049] The ferroelectric layer may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material included in the ferroelectric layer.

[0050] When the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0051] When the dopant is aluminum (Al), the aluminum content in the ferroelectric layer can range from 3 to 8 at% (atomic percentage). Here, the aluminum content as a dopant can be the ratio of the number of aluminum atoms to the number of hafnium atoms and aluminum atoms.

[0052] When the dopant is silicon (Si), the silicon content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is yttrium (Y), the yttrium content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is gadolinium (Gd), the gadolinium content in the ferroelectric layer can range from 1 at% to 7 at%. When the dopant is zirconium (Zr), the zirconium content in the ferroelectric layer can range from 50 at% to 80 at%.

[0053] The paraelectric layer may possess paraelectric material properties. The paraelectric layer may be formed of or include at least one of, for example, silicon oxide and / or high-k metal oxides. The metal oxide that can be used as the paraelectric layer may include at least one of, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0054] The ferroelectric layer and the paraelectric layer can be formed of the same material or comprise the same material. The ferroelectric layer may have ferroelectric material properties, while the paraelectric layer may not. For example, in the case where both the ferroelectric and paraelectric layers contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may differ from the crystal structure of the hafnium oxide in the paraelectric layer.

[0055] A ferroelectric layer may exhibit ferroelectric properties only when it is within a specific thickness range. In one embodiment, the ferroelectric layer may have a thickness in the range of 0.5 to 10 nm, but the inventive concept is not limited to this example. Because the critical thickness associated with the occurrence of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer may also vary depending on the type of ferroelectric material.

[0056] As an example, the gate insulating layer GI may include a single ferroelectric layer. As another example, the gate insulating layer GI may include multiple ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which multiple ferroelectric layers and multiple paraelectric layers are stacked alternately.

[0057] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be realized. For example, the first to third portions PO1, PO2, and PO3 of the gate electrode GE may be composed of the first metal pattern or a work function metal.

[0058] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In one embodiment, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked work function metal layers.

[0059] The second metal pattern may include a metallic material whose resistance is lower than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0060] Return to reference Figure 3 An insulating pattern IP can be provided on the NMOSFET region NR. Each insulating pattern IP can be interposed between a corresponding one of the second source / drain pattern SD2 and the first to third portions PO1, PO2, and PO3 of the gate electrode GE. The insulating pattern IP can be in direct contact with the second source / drain pattern SD2. Each of the first to third portions PO1, PO2, and PO3 of the gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the insulating pattern IP.

[0061] A first interlayer insulating layer 110 may be provided on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first interlayer insulating layer 110 may have a top surface substantially coplanar with the top surface of the gate cover pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 to cover the gate cover pattern GP. In one embodiment, at least one of the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may comprise a silicon oxide layer.

[0062] A pair of separator structures DB, opposite each other in the second direction D2, can be provided on both sides of the logic cell LC. The separator structures DB can extend in the first direction D1 and parallel to the gate electrode GE. The pitch between adjacent separator structures DB and gate electrode GE can be equal to the first pitch P1.

[0063] The separator structure DB can be provided to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The separator structure DB can penetrate the upper portion of each of the first active pattern AP1 and the second active pattern AP2. The separator structure DB can actively separate the PMOSFET region PR and NMOSFET region NR of the logic cell LC from the adjacent logic cell.

[0064] The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may further include a sacrificial layer SAL adjacent to the separator structure DB. The sacrificial layers SAL may be stacked and spaced apart from each other. Each sacrificial layer SAL may be located at the same level as a corresponding one of the first to third portions PO1, PO2, and PO3 of the gate electrode GE. The separator structure DB may be provided to penetrate the sacrificial layers SAL.

[0065] The sacrificial layer SAL can be formed of or comprise silicon germanium (SiGe). The germanium concentration of each sacrificial layer SAL can range from 10 at% to 30 at%. The germanium concentration of the sacrificial layer SAL can be higher than that of the first semiconductor layer SEL1 described above.

[0066] Active contacts AC can be provided to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be provided on both sides of the gate electrode GE, respectively. When viewed in a plan view, the active contacts AC can have a strip shape that extends in the first direction D1.

[0067] The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed using a gate overlay pattern GP and a gate spacer GS via a self-aligned process. In one embodiment, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC can be provided to cover a portion of the top surface of the gate overlay pattern GP.

[0068] The silicide pattern SC can be inserted between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC can be formed of or include at least one of the metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide).

[0069] The gate contact GC, electrically connected to the gate electrode GE, can be provided as penetrating the second interlayer insulating layer 120 and the gate cover pattern GP. (See reference...) Figure 3 The upper region of each active contact AC adjacent to the gate contact GC can be filled with an upper insulating pattern UIP. Therefore, process faults (e.g., short circuits) that may occur when the gate contact GC comes into contact with an active contact AC adjacent to it can be prevented.

[0070] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of or include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may be provided to cover the side and bottom surfaces of the conductive pattern FM. In one embodiment, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0071] A first metal layer M1 may be provided within the third interlayer insulating layer 130. The first metal layer M1 may include a first lower interconnect M1_R, a second lower interconnect M1_I, and a lower pass VI1. The lower pass VI1 may be provided below the first lower interconnect M1_R and the second lower interconnect M1_I.

[0072] Each first lower interconnect M1_R can extend in the second direction D2 to span the logic cell LC. Each first lower interconnect M1_R can be a power supply line. For example, a drain voltage VDD or a source voltage VSS can be applied to the first lower interconnect M1_R.

[0073] Reference Figure 1A first cell boundary CB1 extending in the second direction D2 can be defined within the region of the logic cell LC. A second cell boundary CB2 extending in the second direction D2 can be defined within the region of the logic cell LC opposite to the first cell boundary CB1. A first lower interconnect M1_R to which a drain voltage VDD (i.e., power supply voltage) is applied can be located on the first cell boundary CB1. The first lower interconnect M1_R to which a drain voltage VDD is applied can extend along the first cell boundary CB1 in the second direction D2. A first lower interconnect M1_R to which a source voltage VSS (i.e., ground voltage) is applied can be located on the second cell boundary CB2. The first lower interconnect M1_R to which a source voltage VSS is applied can extend along the second cell boundary CB2 in the second direction D2.

[0074] The second lower interconnect M1_I can be disposed on the first direction D1 between the first lower interconnect M1_R, to which the drain voltage VDD and source voltage VSS are respectively applied. Each second lower interconnect M1_I can be a linear or strip pattern extending on the second direction D2. The second lower interconnects M1_I can be arranged to be spaced apart from each other on the first direction D1 by a second pitch P2. The second pitch P2 can be smaller than the first pitch P1.

[0075] The lower path VI1 can be provided below the first lower interconnect M1_R and the second lower interconnect M1_I of the first metal layer M1. The lower path VI1 can be interposed between the active contact AC and the first and second lower interconnects M1_R and M1_I, respectively. The lower path VI1 can be interposed between the gate contact GC and the second lower interconnect M1_I, respectively.

[0076] The lower interconnect M1_R or M1_I of the first metal layer M1 and the lower pass VI1 thereunder can be formed by separate processes. In other words, each of the lower interconnect M1_R or M1_I and the lower pass VI1 can be formed by a single damascene process. The semiconductor device according to this embodiment can be manufactured using a sub-20nm process.

[0077] A second metal layer M2 may be provided within the fourth interlayer insulating layer 140. The second metal layer M2 may include upper interconnects M2_I. Each upper interconnect M2_I may be a linear or stripe pattern extending in the first direction D1. In other words, the upper interconnects M2_I may extend parallel to each other in the first direction D1. When viewed in a plan view, the upper interconnects M2_I may be parallel to the gate electrode GE. The upper interconnects M2_I may be arranged in the second direction D2 with a third pitch P3. The third pitch P3 may be smaller than the first pitch P1. The third pitch P3 may be larger than the second pitch P2.

[0078] The second metal layer M2 may also include an upper pass VI2. The upper pass VI2 may be provided below the upper interconnect M2_I. The upper pass VI2 may be inserted between the lower interconnect M1_R and M1_I and the upper interconnect M2_I, respectively.

[0079] The upper interconnect M2_I of the second metal layer M2 and the upper pass VI2 below it can be formed using the same process and can be formed as a single object. In other words, the upper interconnect M2_I and the upper pass VI2 of the second metal layer M2 can be formed using a dual damascene process.

[0080] The lower interconnects M1_R and M1_I of the first metal layer M1 and the upper interconnect M2_I of the second metal layer M2 can be formed or comprise the same or different conductive materials. For example, the lower interconnects M1_R and M1_I and the upper interconnect M2_I can be formed or comprise at least one of metallic materials (e.g., aluminum, copper, tungsten, molybdenum, or cobalt).

[0081] In one embodiment, although not shown, additional metal layers (e.g., M3, M4, M5, etc.) may be further stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers may include wiring.

[0082] Figure 2B It is shown Figure 2A The highlighted portion M is an enlarged cross-sectional view. Figure 2C It is along Figure 2A The top view is taken by line F-F'. Figure 4B It is shown Figure 4A A magnified cross-sectional view of part N. (Refer to...) Figure 2A and Figure 2B The gate electrode GE can be provided in the first active region PR. In the first active region PR and the second active region NR, the gate electrode GE may include a first portion PO1 interposed between the substrate 100 and the first semiconductor pattern SP1, a second portion PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 provided on the third semiconductor pattern SP3. The width W0 of the fourth portion PO4 of the gate electrode GE in the second direction D2 may decrease as the distance from the first channel pattern CH1 decreases. More specifically, the corner portions PO4s where the lower side surface and bottom surface of the fourth portion PO4 are connected may protrude toward the adjacent first source / drain pattern SD1. Therefore, when viewed in a cross-sectional view, the lower portion of the fourth portion PO4 adjacent to the first channel pattern CH1 may have a rectangular shape with rounded corners.

[0083] A gate insulating layer GI can be provided on the side and bottom surfaces of the fourth portion PO4 of the gate electrode GE. The gate insulating layer GI can conformally cover the side and bottom surfaces of the fourth portion PO4 of the gate electrode GE. For example, the gate insulating layer GI can have a profile corresponding to the side, bottom, and corner surfaces of the fourth portion PO4 of the gate electrode GE.

[0084] A gate spacer GS can be provided on the sidewall of the fourth portion PO4 of the gate electrode GE. The gate spacer GS can extend vertically along the sidewall of the fourth portion PO4 of the gate electrode GE. More specifically, the gate spacer GS can include a vertically extending first portion GSv and a second portion GSw protruding toward its adjacent gate electrode GE. The first portion GSv can extend in the third direction D3 and parallel to the sidewall of the fourth portion PO4 of the gate electrode GE. As shown, the width W1 of the first portion GSv in the second direction D2 can be substantially constant. The second portion GSw can be connected to the first portion GSv and can be provided between the lower portion of the first portion GSv and the gate insulating layer GI. The second portion GSw can extend from the first portion GSv toward the contact surface between the gate insulating layer GI and the uppermost semiconductor pattern SP3. The second portion GSw can overlap the gate insulating layer GI vertically. As shown, the non-uniform width W2 of the second portion GSw in the second direction D2 can increase as the distance from the uppermost semiconductor pattern SP3 decreases, and can be in the range of, for example, 1 nm to 5 nm. The height H1 of the second part GSw on the third direction D3 can decrease as the distance from the contact surface decreases. The gate electrode GE and gate spacer GS in the second active region NR can be configured to have the same height as the reference. Figure 2B The features described are basically the same.

[0085] Reference Figure 2C The planar structure of the gate spacer GS in the first active region PR and the second active region NR is described in more detail. (Refer to...) Figure 2C A first channel pattern CH1_1 and a first second channel pattern CH1_2 may be provided on a first active region PR, spaced apart from each other in a second direction D2. Each of the first channel pattern CH1_1 and the first second channel pattern CH1_2 may include first to third semiconductor patterns SP1, SP2, and SP3 stacked sequentially. A first source / drain pattern SD1 may be provided between the first channel pattern CH1_1 and the first second channel pattern CH1_2. A gate electrode GE may extend in a first direction D1 to intersect each of the first channel pattern CH1_1 and the first second channel pattern CH1_2. For simplicity, the following description will only refer to one gate electrode GE.

[0086] More specifically, the gate electrode GE can be aligned with the first semiconductor pattern SP1 in the first direction D1. The corner portion of the gate electrode GE adjacent to the first source / drain pattern SD1 can have a curved surface protruding toward the first source / drain pattern SD1. The gate insulating layer GI can be interposed between the first semiconductor pattern SP1 and the gate electrode GE, and between the gate electrode GE and the gate spacer GS.

[0087] A gate spacer GS can be provided on the sidewall of the gate electrode GE. The gate spacer GS may include a first portion GSv provided on the sidewall of the gate electrode GE and a second portion GSw protruding in the region between the first semiconductor pattern SP1 and the gate electrode GE. The first portion GSv may extend along the sidewall of the gate electrode GE in a first direction D1 and may have a constant width W7 in a second direction D2. As an example, the first portion GSv may be a portion of the gate spacer GS that does not contact the first source / drain pattern SD1, but the inventive concept is not limited to this example.

[0088] The second portion GSW can be connected to the first portion GSv and can be provided between the first semiconductor pattern SP1 and the gate electrode GE, and between the first source / drain pattern SD1 and the gate electrode GE. The second portion GSW can contact the gate insulating layer GI, the first source / drain pattern SD1, and the first semiconductor pattern SP1 located adjacent to it. The second contact surface SW2 between the second portion GSW and the gate insulating layer GI can be a curved surface convex toward the first source / drain pattern SD1, while the first contact surface SW1 between the first semiconductor pattern SP1 and the gate insulating layer GI can be a flat surface. The width W6 of the second portion GSW in the second direction D2 can decrease as the distance from the first semiconductor pattern SP1 decreases. For example, the width W6 of the second portion GSW in the second direction D2 can be in the range of 1 nm to 5 nm. The first source / drain pattern SD1 can be spaced apart from the gate electrode GE, and the second portion GSW is interposed therebetween. The gate electrode GE and the gate spacer GS in the second active region NR can be configured to have the same characteristics as the reference... Figure 2C The features described are basically the same.

[0089] According to one embodiment of the present invention, the gate spacer GS may include a first portion GSv extending parallel to the sidewall of the gate electrode GE and a second portion GSw protruding toward the gate electrode GE. The source / drain patterns SD1 and SD2 adjacent to the gate spacer GS may be spaced apart from the gate electrode GE by the second portion GSw of the gate spacer GS. In this embodiment, the second portion GSw may be formed to have sufficient thickness or to separate the source / drain patterns SD1 and SD2 from the gate electrode GE by a sufficient distance. Therefore, the electrical insulation characteristics between the gate electrode GE and the source / drain patterns SD1 and SD2 can be improved, thereby improving the electrical characteristics of the semiconductor device. Although not shown, the present invention can be applied not only to MBCFET devices but also to FINFET devices including embedded silicon germanium (eSiGe) layers.

[0090] Reference Figure 4B A more detailed description is provided of the gate electrode GE and gate spacer GS on the field region FR. Combined with... Figure 4A Reference Figure 4B In the field region FR, the gate electrode GE can be provided on the device isolation layer ST. The lower portion of the gate electrode GE can have a width W3 in the second direction D2, which decreases as the distance from the top surface 100a of the substrate 100 decreases. More specifically, the bottom surface GEb of the gate electrode GE can protrude toward the top surface 100a of the substrate 100. Therefore, in the field region FR, the bottom surface GEb of the gate electrode GE can have a "U" shape.

[0091] A gate insulating layer GI can be provided on the side surfaces GEs and the bottom surface GEb of the gate electrode GE. The gate insulating layer GI can be interposed between the gate electrode GE and the gate spacer GS, and between the gate electrode GE and the device isolation layer ST. The gate insulating layer GI can conformally cover the side surfaces GEs and the bottom surface GEb of the gate electrode GE. More specifically, the gate insulating layer GI can have a profile corresponding to the side surfaces GEs and the bottom surface GEb of the gate electrode GE.

[0092] Gate spacers GS can be provided on the sidewalls of the gate electrode GE. More specifically, gate spacers GS can be interposed between the gate electrodes GE positioned adjacent to each other and the first interlayer insulating layer 110. Gate spacers GS can extend vertically along the side surfaces GEs of the gate electrodes GE.

[0093] More specifically, the gate spacer GS may include a first portion GSU and a second portion GSB provided below the first portion GSU. The first portion GSU may extend parallel to the side surfaces GEs of the gate electrode GE. The first portion GSU may have a constant width W4 in the second direction D2. The second portion GSB may be connected to the first portion GSU. The second portion GSB may have a width W5 in the second direction D2, where the width W5 may vary when measured along a path parallel to the third direction D3. For example, as the distance from the top surface 100a of the substrate 100 decreases, the width W5 of the second portion GSB in the second direction D2 may increase until it reaches its maximum width, and then may decrease.

[0094] The bottom surface GSBb of the second portion GSB can be tilted at an angle relative to the top surface 100a of the substrate 100. More specifically, the vertical level of the bottom surface GSBb of the second portion GSB can increase as the distance from the gate electrode GE decreases. The lowest level of the second portion GSB can be a first level lv1, which can be the lowest level of the gate spacer GS in the field region FR. The lowest level of the gate electrode GE can be a second level lv2, which can be the lowest level of the gate electrode GE in the field region FR. In one embodiment of the present invention, the lowest level lv2 of the gate electrode GE can be lower than the lowest level lv1 of the gate spacer GS. In the field region FR, the height H2 of the gate electrode GE in the third direction D3 can be in the range of 50 nm to 100 nm (e.g., see...). Figure 4A ).

[0095] Therefore, as mentioned above... Figure 1 , Figure 2A-2C , Figure 3 , Figures 4A-4B and Figure 5-6 As shown, the integrated circuit device may include a substrate 100, a first active pattern AP1 of a first conductivity type (e.g., P-type) on a first portion (PR) of the substrate 100, and a second active pattern AP2 of a second conductivity type (e.g., N-type) on a second portion (NR) of the substrate 100, the second active pattern AP2 being separated from the first active pattern AP1 by an electrically insulating field region FR. A first pair of source / drain patterns SD1 is provided on the first active pattern AP1, and a second pair of source / drain patterns SD2 is provided on the second active pattern AP2. A first stack of vertically spaced semiconductor patterns extending between the first pair of source / drain patterns SD1 is provided, and a second stack of vertically spaced semiconductor patterns extending between the second pair of source / drain patterns SD2 is provided. A gate electrode GE is provided extending over the first stack of vertically spaced semiconductor patterns, the field region FR, and the second stack of vertically spaced semiconductor patterns.

[0096] As by Figure 4B As best shown, the gate electrode GE has a gradually tapering width, such that the width of the lower portion of the gate electrode GE decreases as the distance from the lower portion of the device isolation layer ST decreases. An electrically insulating gate spacer GS is provided on the sidewall of the gate electrode GE. The gate spacer GS has a bottom surface GSBb angled relative to the upper surface of the substrate 100. The gate spacer GS is separated from the sidewall of the gate electrode GE by the gate insulating layer GI; and the bottom surface GSBb of the gate spacer GS intersects the sidewall of the gate insulating layer GI at an acute angle. The gate spacer GS on the device isolation layer ST includes a second portion GSB and a first portion GSU with a uniform width, the second portion GSB extending between the first portion GSU and the substrate 100 and having a non-uniform width, which generally widens in a "downward" direction toward the upper surface of the substrate 100 until it reaches its maximum width, and then can decrease. Furthermore, the lowermost portion of the gate electrode GE ( Figure 4B (In the middle) the gate spacer GS extends deeper into the device isolation layer ST than the electrically insulating gate spacer GS.

[0097] As those skilled in the art will understand, such as Figure 5-6 The first stack of the first pair of source / drain patterns SD1 and the vertically spaced semiconductor patterns shown is a component of a PMOS transistor. In contrast, the second stack of the second pair of source / drain patterns SD2 and the vertically spaced semiconductor patterns is a component of an NMOS transistor. Therefore, the first segment of the gate electrode GE operates as the gate terminal of a PMOS transistor, and the second segment of the gate electrode GE operates as the gate terminal of an NMOS transistor. Furthermore, as shown by... Figure 6 As best illustrated, each of the spaced-apart semiconductor patterns (SP1, SP2, SP3) within the first stack is surrounded by a gate insulating layer GI. (See diagram below.) Figure 2B As shown, the fourth portion PO4 of the first segment of the gate electrode GE is further spaced from the electrically insulating gate spacers GS (GSv, GSW) on the sidewall of the first segment of the gate electrode GE and the uppermost third semiconductor pattern SP3 of the semiconductor pattern in the first stack. Furthermore, the gate insulating layer GI extends between the first segment of the gate electrode GE and the uppermost third semiconductor pattern SP3 of the semiconductor pattern in the first stack, and the bottom surfaces of the electrically insulating gate spacers GS (GSv, GSW) and the bottom surface of the gate insulating layer GI contact the uppermost third semiconductor pattern SP3 of the semiconductor pattern in the first stack.

[0098] Figures 7 to 41 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the concept of the present invention. More specifically, Figure 7 , Figure 9 , Figure 12, Figure 15 , Figure 20 , Figure 25 , Figure 30 , Figure 34 and Figure 38 It is along Figure 1 A cross-sectional view of a manufacturing method according to an embodiment of the present invention is shown by taking a section along line A-A'. Figure 16 , Figure 21 , Figure 26 , Figure 31 , Figure 35 and Figure 39 It is along Figure 1 A cross-sectional view of a manufacturing method according to an embodiment of the present invention is shown by taking a section along line B-B'. Figure 10 , Figure 13 , Figure 17 , Figure 22 , Figure 27 , Figure 32 , Figure 36 and Figure 40 It is along Figure 1 The line C-C' is cut to show a cross-sectional view of a manufacturing method according to an embodiment of the present invention. Figure 18 , Figure 23 and Figure 28 It is along Figure 1 The line D-D' is cut to show a cross-sectional view of a manufacturing method according to an embodiment of the present invention. Figure 8 , Figure 11 , Figure 14 , Figure 19 , Figure 24 , Figure 29 , Figure 33 , Figure 37 and Figure 41 It is along Figure 1 The line E-E' is cut to show a cross-sectional view of a manufacturing method according to an embodiment of the present invention.

[0099] Reference Figure 7 and Figure 8A substrate 100 may be provided, comprising a PMOSFET region PR and an NMOSFET region NR. A sacrificial layer SAL and an active layer ACL may be alternately stacked on the substrate 100. The sacrificial layer SAL may be formed or comprise at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layer ACL may be formed or comprise at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the sacrificial layer SAL may be formed (or comprise silicon-germanium (SiGe)), and the active layer ACL may be formed or comprise silicon (Si). The germanium concentration of each sacrificial layer SAL may be in the range of 10 at% to 30 at%.

[0100] Mask patterns can be formed on the PMOSFET region PR and NMOSFET region NR of the substrate 100, respectively. The mask patterns can be linear or stripe patterns extending in the second direction D2. For example, the mask patterns can be formed of or include silicon nitride.

[0101] A first patterning process, in which a mask pattern is used as an etching mask, can be performed to form a first trench TR1 defining a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can be formed on a PMOSFET region PR and an NMOSFET region NR, respectively. Each of the first active pattern AP1 and the second active pattern AP2 may include a sacrificial layer SAL and an active layer ACL alternately stacked on its upper portion.

[0102] A second patterning process can be performed on the substrate 100 to form a second trench TR2 that defines the PMOSFET region PR and the NMOSFET region NR. The second trench TR2 can be formed to be deeper than the first trench TR1.

[0103] A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. For example, an insulating layer can be formed on the substrate 100 to cover the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can be formed by recessing the insulating layer until the sacrificial layer SAL is exposed.

[0104] The device isolation layer ST may be formed of or comprise an insulating material (e.g., silicon oxide). Each of the first active pattern AP1 and the second active pattern AP2 may include an upper portion protruding above the device isolation layer ST. For example, the upper portion of each of the first active pattern AP1 and the second active pattern AP2 may protrude vertically above the device isolation layer ST.

[0105] Reference Figure 9 , Figure 10 and Figure 11 The first sacrificial pattern EG and the second sacrificial pattern PP can be formed on the substrate 100 to intersect with the first active pattern AP1 and the second active pattern AP2. Each of the first sacrificial pattern EG and the second sacrificial pattern PP can be a linear or strip pattern extending in a first direction D1. The first sacrificial pattern EG and the second sacrificial pattern PP can be arranged at a specific pitch in a second direction D2.

[0106] In detail, the formation of the first sacrificial pattern EG and the second sacrificial pattern PP may include forming a first sacrificial layer on the substrate 100, forming a second sacrificial layer on the first sacrificial layer, forming a hard mask pattern MP on the second sacrificial layer, and using the hard mask pattern MP as an etch mask to pattern the first and second sacrificial layers. The first sacrificial layer may be formed of or comprise silicon oxide or nitrogen-doped silicon oxide, and the second sacrificial layer may be formed of or comprise polysilicon. The first sacrificial pattern EG may be interposed between the second sacrificial pattern PP and the first active pattern AP1, and between the second sacrificial pattern PP and the second active pattern AP2. Each of the first active pattern AP1 and the second active pattern AP2 may have a first sidewall SW3 and a second sidewall SW4 that are opposite to each other. The first sacrificial pattern EG may be formed to cover both the first sidewall SW3 and the second sidewall SW4 (e.g., see...). Figure 11 ).

[0107] An etching process can be performed on the substrate 100 to form a third recess RS3 on the device isolation layer ST. More specifically, the formation of the third recess RS3 may include performing an etching process to remove the upper portion of the device isolation layer ST and the sides of the first sacrificial pattern EG. For example, the etching process may be a dry etching process. The third recess RS3 may have a bottom surface that protrudes toward the top surface of the substrate 100, and the side surfaces EGc of the first sacrificial pattern EG may be recessed by the etching process and thus may have a curved surface profile. After the etching process, each first sacrificial pattern EG may have a width smaller than the width of each second sacrificial pattern PP.

[0108] Reference Figure 12 , Figure 13 and Figure 14A gate spacer layer GSp can be formed to cover the entire top surface of the substrate 100. The gate spacer layer GSp can conformally cover the mask pattern MP, the first sacrificial pattern EG, and the second sacrificial pattern PP. More specifically, the gate spacer layer GSp can conformally cover the top and side surfaces of the mask pattern MP, the side surface of the second sacrificial pattern PP, and the side surface of the first sacrificial pattern EG. In the field region FR, the gate spacer layer GSp can conformally cover the inner surface of the third recess RS3. The gate spacer layer GSp can be formed of or include at least one of SiCN, SiCON, and SiN. In one embodiment, the gate spacer layer GSp can be a multilayer structure including at least two of SiCN, SiCON, and SiN.

[0109] Reference Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 A fourth recess RS4 can be formed in the upper portion of the first active pattern AP1. A fifth recess RS5 can be formed in the upper portion of the second active pattern AP2. During the formation of the fourth recess RS4 and the fifth recess RS5, a portion of the gate spacer layer GSp can be removed. A sixth recess RS6 can be formed by recessing portions of the device isolation layer ST located on both sides of each of the first active pattern AP1 and the second active pattern AP2 during the formation of the fourth recess RS4 and the fifth recess RS5 (e.g., see...). Figure 17 The fourth recess RS4 and the fifth recess RS5 can be formed between a pair of sacrificial patterns PP.

[0110] Reference Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 A first source / drain pattern SD1 can be formed in the fourth recess RS4. Specifically, a first SEG process in which the inner surface of the fourth recess RS4 is used as a seed layer can be performed to form the first semiconductor layer SEL1. The first to third semiconductor patterns SP1, SP2, and SP3 exposed through the fourth recess RS4 and the substrate 100 can be used as seed layers to grow the first semiconductor layer SEL1. As an example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0111] The first semiconductor layer SEL1 may be formed of or comprise a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. The first semiconductor layer SEL1 may be formed with a relatively low germanium concentration. In another embodiment, the first semiconductor layer SEL1 may be provided as containing only silicon (Si) and no germanium (Ge). The germanium concentration of the first semiconductor layer SEL1 may be in the range of 0 at% to 10 at%.

[0112] The second semiconductor layer SEL2 can be formed by performing a second SEG process on the first semiconductor layer SEL1. The second semiconductor layer SEL2 can be formed to completely fill the fourth recess RS4. The second semiconductor layer SEL2 can be provided to have a relatively high germanium concentration. As an example, the germanium concentration of the second semiconductor layer SEL2 can be in the range of 30 at% to 70 at%.

[0113] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can form a first source / drain pattern SD1. The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can be doped in situ with impurities during the first SEG process and the second SEG process. Alternatively, after forming the first source / drain pattern SD1, the first source / drain pattern SD1 can be doped with impurities. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0114] A second source / drain pattern SD2 can be formed in the fifth recess RS5. Specifically, the second source / drain pattern SD2 can be formed using a SEG process that uses the inner surface of the fifth recess RS5 as a seed layer. As an example, the second source / drain pattern SD2 can be formed of or comprise the same semiconductor material (e.g., Si) as the substrate 100. The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type).

[0115] Reference Figure 25 , Figure 26 , Figure 27 , Figure 28 and Figure 29A first interlayer insulating layer 110 can be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer layer GSp. As an example, the first interlayer insulating layer 110 can be formed of or comprise silicon oxide. In the field region FR, the first interlayer insulating layer 110 can be formed to fill the sixth recess RS6. Therefore, in the field region FR, the lower portion of the first interlayer insulating layer 110 can have a shape that protrudes toward the top surface of the substrate 100.

[0116] The gate spacer GS can be formed by planarizing the first interlayer insulating layer 110 to expose the top surface of the second sacrificial pattern PP. Planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, all hard mask patterns MP can be removed. As a result, the top surface of the first interlayer insulating layer 110 can be coplanar with the top surface of both the sacrificial pattern PP and the gate spacer GS.

[0117] The exposed second sacrificial pattern PP can be selectively removed by an etching process. Some of the second sacrificial pattern PP can be removed to form a first empty space ET1 exposing the first sacrificial pattern EG (e.g., see...). Figure 25 The etching process can be, for example, a wet etching process. However, it is possible to leave another second sacrificial pattern in the second sacrificial pattern PP unremoved. For example, the second sacrificial pattern PP located at the cell boundary may not be removed. In detail, by forming a mask layer on the second sacrificial pattern PP that should not be removed, the unintentional removal of the second sacrificial pattern PP can be prevented. As a result of the selective removal of the second sacrificial pattern PP, the first sacrificial pattern EG can be exposed through the first empty space ET1.

[0118] Reference Figure 30 , Figure 31 , Figure 32 and Figure 33 The first sacrificial pattern EG exposed through the first empty space ET1 can be removed by an etching process. As a result of removing the first sacrificial pattern EG, the first active pattern AP1 and the second active pattern AP2 can be exposed through the first empty space ET1 (e.g., see...). Figure 33More specifically, the sacrificial layer SAL of each of the first active pattern AP1 and the second active pattern AP2 can be exposed through the first empty space ET1. The etching process can be, for example, a dry etching process. In the first active region PR and the second active region NR, the inner sidewall of the gate spacer GS and the lower portion of the gate spacer GS adjacent to the first sacrificial pattern EG can also be partially removed during the removal of the first sacrificial pattern EG. Therefore, the inner sidewall of the gate spacer GS exposed through the first empty space ET1 can have a curved surface profile. For example, the width of each gate spacer GS can increase as the distance from the substrate 100 decreases. In the field region FR, the inner sidewall of the gate spacer GS, the lower portion of the gate spacer GS adjacent to the first sacrificial pattern EG, and the upper portion of the device isolation layer ST can also be partially removed during the removal of the first sacrificial pattern EG. More specifically, because the device isolation layer ST comprises the same material as the first sacrificial pattern EG, the device isolation layer ST can be etched during the process of removing the first sacrificial pattern EG. Therefore, the top surface STa of the device isolation layer ST exposed through the first empty space ET1 in the field region FR can protrude toward the top surface 100a of the substrate 100.

[0119] Reference Figure 34 , Figure 35 , Figure 36 and Figure 37 The sacrificial layer SAL exposed through the first empty space ET1 can be selectively removed. Specifically, an etching process can be performed to selectively etch only the sacrificial layer SAL, leaving the first to third semiconductor patterns SP1, SP2, and SP3. In some embodiments, the etching process can be selected to exhibit a high etching rate for materials with relatively high germanium concentrations (e.g., SiGe). For example, the etching process can have a high etching rate for silicon-germanium with a germanium concentration higher than 10 at%.

[0120] Return to reference Figure 37 Because the sacrificial layer SAL is selectively removed, only the first to third semiconductor patterns SP1, SP2, and SP3 can remain on each of the first active pattern AP1 and the second active pattern AP2. Therefore, as a result of removing the sacrificial layer SAL, a second empty space ET2 can be formed. The second empty space ET2 can be formed between the first to third semiconductor patterns SP1, SP2, and SP3.

[0121] Reference Figure 38 , Figure 39 , Figure 40 and Figure 41A gate insulating layer GI can be conventionally formed in the first empty space ET1 and the second empty space ET2. A gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE can be formed to fill the first empty space ET1 and the second empty space ET2. Specifically, the gate electrode GE can include the first to third portions PO1, PO2, and PO3 filling the second empty space ET2. The gate electrode GE can also include a fourth portion PO4 filling the first empty space ET1. A gate overlay pattern GP can be formed on the gate electrode GE.

[0122] In one embodiment, an insulating pattern IP can be formed on the second active region NR before forming the gate insulating layer GI. The insulating pattern IP can be formed to partially fill the second empty space ET2. In this case, the gate electrode GE on the NMOSFET region NR can be spaced apart from the second source / drain pattern SD2, and the insulating pattern IP is interposed therebetween.

[0123] Return to reference Figure 1 , Figure 2A , Figure 3 , Figure 4A , Figure 5 and Figure 6 A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. An active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and the gate cover pattern GP and be electrically connected to the gate electrode GE.

[0124] A pair of separator structures DB can be formed on both sides of the logic cell LC. In one embodiment, the separator structure DB can be formed to penetrate the second interlayer insulating layer 120, the remainder of the second sacrificial pattern PP, and the upper part of the active pattern AP1 or AP2 below the second sacrificial pattern PP. The separator structure DB can be formed of or include at least one of insulating materials (e.g., silicon oxide or silicon nitride).

[0125] A third interlayer insulating layer 130 can be formed on the active contact AC and the gate contact GC. A first metal layer M1 can be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 can be formed on the third interlayer insulating layer 130. A second metal layer M2 can be formed in the fourth interlayer insulating layer 140. A semiconductor device according to an embodiment of the present invention can be manufactured by the aforementioned method.

[0126] According to one embodiment of the present invention, a semiconductor device may include a gate spacer comprising a first portion extending parallel to a side surface of a gate electrode and a second portion protruding toward the gate electrode. Due to the presence of the second portion, the distance between the gate electrode and its adjacent source / drain pattern can be increased. Therefore, the electrical insulation characteristics between the gate electrode and the source / drain pattern can be improved.

[0127] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0128] This application claims priority to Korean Patent Application No. 10-2020-0159293, filed on November 24, 2020, the disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, comprising: The substrate includes a first active region, a second active region, and a field region between the first active region and the second active region; A first active pattern on the first active region and a second active pattern on the second active region; The first source / drain pattern on the first active pattern and the second source / drain pattern on the second active pattern; A first channel pattern between the first source / drain patterns and a second channel pattern between the second source / drain patterns, each of the first channel pattern and the second channel pattern comprising semiconductor patterns stacked and spaced apart from each other; A gate electrode extends from the first channel pattern to the second channel pattern to span the field region; as well as A gate spacer is provided on the side surface of the gate electrode and extends across the first active region, the second active region, and the field region. Wherein, in the field region, the lowermost portion of the gate electrode is provided at a level below the lowermost portion of the gate spacer, and The width of the lower portion of the gate electrode in the field region decreases as the distance from the top surface of the substrate decreases.

2. The semiconductor device according to claim 1, The bottom surface of the gate spacer in the field region is inclined at an angle relative to the top surface of the substrate.

3. The semiconductor device of claim 2, wherein the level of the bottom surface of the gate spacer in the field region increases as the distance from the gate electrode decreases.

4. The semiconductor device according to claim 1, The gate spacer in the field region includes: The first part has a constant width and extends vertically; as well as The second part is connected to the first part and positioned adjacent to the lower part of the gate electrode. As the distance from the top surface of the substrate decreases, the width of the second portion increases until it reaches its maximum width, and then decreases.

5. The semiconductor device according to claim 1, wherein, In the field region, the height of the gate electrode is in the range of 50 nm to 100 nm.

6. The semiconductor device according to claim 1, in, On the first and second active regions of the substrate, the width of the gate spacer increases as the distance from the top surface of the substrate decreases.

7. The semiconductor device according to claim 1, further comprising: A gate insulating layer is inserted between the gate spacer and the gate electrode. Wherein, in the first active region and the second active region, the gate spacer includes a vertically extending first portion and a second portion protruding toward the gate electrode, and The second portion extends toward the contact surface between the gate insulating layer and the uppermost semiconductor pattern in the semiconductor pattern, and overlaps perpendicularly with the gate insulating layer.

8. The semiconductor device of claim 7, wherein the height of the second portion of the gate spacer decreases as the distance from the contact surface decreases.

9. The semiconductor device of claim 7, wherein the width of the second portion of the gate spacer is in the range of 1 nm to 5 nm.

10. The semiconductor device of claim 1, wherein the gate electrode on the first active region and the second active region comprises: The first part is provided on the semiconductor pattern; as well as The second part provides [the following] between the semiconductor patterns and between the semiconductor patterns and the substrate. The width of the first portion of the gate electrode decreases as the distance from the semiconductor pattern decreases.

11. A semiconductor device, comprising: Active patterns on a substrate; The first channel pattern and the second channel pattern on the active pattern, each of the first channel pattern and the second channel pattern includes first to third semiconductor patterns stacked sequentially and spaced apart from each other; Source / drain patterns inserted between the first channel pattern and the second channel pattern; A first gate electrode and a second gate electrode that overlap with the first channel pattern and the second channel pattern, respectively; as well as A first gate spacer and a second gate spacer are respectively provided on opposite side surfaces of the first gate electrode and the second gate electrode. In a planar view taken horizontally from the first semiconductor pattern, the source / drain pattern extends from the first semiconductor pattern to the space between the first gate spacer and the second gate spacer. Each of the first gate spacer and the second gate spacer includes: The first part is provided on the side surface of the corresponding gate electrode; and The second part protrudes into the region between the first semiconductor pattern and the gate electrode. The second portion is provided between the first semiconductor pattern and the gate electrode, and between the source / drain pattern and the gate electrode.

12. The semiconductor device of claim 11, further comprising a first gate insulating layer and a second gate insulating layer respectively disposed between the first gate electrode and the first gate spacer and between the second gate electrode and the second gate spacer. The second portion of the first gate spacer contacts the corresponding first gate insulating layer, the source / drain pattern, and the first semiconductor pattern, and The second portion of the second gate spacer is in contact with the corresponding second gate insulating layer, the source / drain pattern, and the first semiconductor pattern.

13. The semiconductor device of claim 12, wherein the second portion of each of the first gate spacer and the second gate spacer has a contact surface between it and the corresponding gate insulating layer protruding toward the source / drain pattern.

14. The semiconductor device of claim 11, wherein the source / drain pattern is spaced apart from the first gate electrode and the second gate electrode, and the second portion of each of the first gate spacer and the second gate spacer is interposed therebetween.

15. The semiconductor device of claim 11, wherein the width of the second portion of each of the first gate spacer and the second gate spacer decreases as the distance from the first semiconductor pattern corresponding thereto decreases.

16. A semiconductor device, comprising: The substrate includes a first active region, a second active region, and a field region between the first active region and the second active region, wherein the first active region and the second active region are adjacent to each other in a first direction; A first active pattern and a second active pattern are respectively provided on the first active region and the second active region; A pair of first source / drain patterns on the first active pattern and a pair of second source / drain patterns on the second active pattern; A first channel pattern inserted between a pair of first source / drain patterns and a second channel pattern inserted between a pair of second source / drain patterns, each of the first channel pattern and the second channel pattern comprising a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern stacked sequentially and spaced apart from each other; A gate electrode extends in the first direction from the first channel pattern to the second channel pattern to span the field region; A first gate insulating layer and a second gate insulating layer are respectively inserted between the first channel pattern and the gate electrode, and between the second channel pattern and the gate electrode; Gate spacers are provided on the side surface of the gate electrode; A gate overlay pattern is provided on the top surface of the gate electrode; A first interlayer insulating layer is on the gate cover pattern; An active contact is provided to penetrate the first interlayer insulation layer and be electrically connected to at least one of the first source / drain pattern and the second source / drain pattern; A gate contact is provided to penetrate the first interlayer insulating layer and be electrically connected to the gate electrode; The second interlayer insulation layer is on top of the first interlayer insulation layer; A first metal layer is provided in the second interlayer insulating layer, the first metal layer including a first interconnect electrically connected to the active contact and the gate contact; The third interlayer insulation layer is on top of the second interlayer insulation layer; as well as A second metal layer is provided in the third interlayer insulating layer. The second metal layer includes a second interconnect that is electrically connected to the first interconnect. In each of the first and second active regions, the gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern, a second portion interposed between the first and second semiconductor patterns, a third portion interposed between the second and third semiconductor patterns, and a fourth portion on the third semiconductor pattern. In the field region, the width of the lower portion of the gate electrode decreases as the distance from the top surface of the substrate decreases.

17. The semiconductor device according to claim 16, wherein, In the field region, the bottom surface of the gate spacer is inclined at an angle relative to the top surface of the substrate.

18. The semiconductor device according to claim 16, wherein, In the field region, the gate spacer includes: The first part has a constant width and extends vertically; and The second part is connected to the first part and positioned adjacent to the lower part of the gate electrode. As the distance from the top surface of the substrate decreases, the width of the second portion increases until it reaches its maximum width, and then decreases.

19. The semiconductor device according to claim 16, wherein, In the field region, the lowermost portion of the gate electrode is provided at a level below the lowermost portion of the gate spacer.

Images