A memory device and a method of manufacturing the same

Abstract

The application provides a storage device and a manufacturing method thereof. The method comprises the following steps: providing a substrate structure, wherein the substrate structure comprises a first substrate, a first oxide layer, a first buffer layer and a stack structure on the first substrate, and the stack structure comprises alternately stacked interlayer insulation layers and gate sacrificial layers; forming a hole structure penetrating through the stack structure and the first buffer layer in sequence; and forming a first epitaxial layer on the exposed side of the first buffer layer in the hole structure. In the method, the first epitaxial layer is formed on the exposed side of the first buffer layer in the hole structure after the hole structure is formed by etching, and the first epitaxial layer forms the bottom of the hole structure, so that the bottoms of different hole structures are basically flush without controlling the bottoms of the hole structures to be flush by etching process, which can greatly reduce the difficulty of the etching process and improve the consistency of the hole structure.

Description

Technical Field

[0001] This application relates to semiconductor manufacturing technology, and more particularly to a memory device and a method for manufacturing the same. Background Technology

[0002] Typically, a memory device includes a gate stack structure formed by alternating stacks of gate layers and interlayer insulating layers. Electrical connections between the gate layer and external circuitry are achieved through stepped contacts located in the stepped regions of the gate stack structure. In the fabrication of a three-dimensional memory, multiple channel vias penetrating the gate stack structure need to be etched. These channel vias are arranged in an array, and a barrier layer, a memory layer, a tunneling layer, and a channel layer are sequentially deposited into the channel vias to form the channel via structure.

[0003] However, as the number of stacked layers in 3D memory increases, the etching depth of the hole structure also becomes deeper, making the etching and control of the hole structure increasingly difficult. Summary of the Invention

[0004] In view of this, this application provides a storage device and a method for manufacturing the same.

[0005] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0006] In a first aspect, embodiments of this application provide a method for manufacturing a storage device, the method comprising:

[0007] A substrate structure is provided, the substrate structure comprising: a first substrate and a first oxide layer, a first buffer layer and a stacked structure located on the first substrate, the stacked structure comprising alternately stacked interlayer insulating layers and gate sacrificial layers;

[0008] A hole structure is formed that sequentially penetrates the stacked structure and the first buffer layer;

[0009] A first epitaxial layer is formed on the exposed side of the first buffer layer within the hole structure.

[0010] In some embodiments of this application, forming a hole structure that sequentially penetrates the stacked structure and the first buffer layer includes:

[0011] Forming a lower layered structure;

[0012] A first lower hole structure is formed, which sequentially penetrates the lower stacked structure, the first buffer layer, and the first oxide layer and extends into the first substrate; a support layer is formed within the first lower hole structure.

[0013] An upper stacked structure is formed on the lower stacked structure;

[0014] A first upper hole structure is formed that penetrates the upper stacked structure; wherein the first upper hole structure is connected to the first lower hole structure.

[0015] In some embodiments of this application, the method further includes:

[0016] The support layer is etched to form a second lower hole structure that exposes the side of the first buffer layer. The second lower hole structure communicates with the first upper hole structure to form the hole structure.

[0017] In some embodiments of this application, the first epitaxial layer is formed on the side exposed by the first buffer layer within the second lower hole structure.

[0018] In some embodiments of this application, the method further includes:

[0019] The support layer is etched to form a third lower hole structure that exposes the side of the first oxide layer, the third lower hole structure being connected to the first upper hole structure to form the hole structure.

[0020] In some embodiments of this application, the first epitaxial layer is formed on the exposed side of the first buffer layer within the third lower hole structure.

[0021] In some embodiments of this application, the method further includes:

[0022] The support layer is etched to form a fourth lower hole structure that exposes the side surface of the first substrate. The fourth lower hole structure communicates with the first upper hole structure to form the hole structure.

[0023] In some embodiments of this application, a second epitaxial layer is epitaxially formed on the exposed side of the first substrate within the fourth lower hole structure.

[0024] In some embodiments of this application, the hole structure includes channel holes, virtual channel holes, and / or grid line slots.

[0025] In some embodiments of this application, after the first epitaxial layer is formed in a direction perpendicular to the first substrate, the bottoms of the different hole structures are substantially flush.

[0026] In some embodiments of this application, forming a hole structure that sequentially penetrates the stacked structure and the first buffer layer includes:

[0027] A pore structure is formed that sequentially penetrates the stacked structure, the first buffer layer, and the first oxide layer, and extends into the first substrate.

[0028] In some embodiments of this application, the substrate structure further includes: a second oxide layer and a second buffer layer located sequentially between the first substrate and the first oxide layer;

[0029] A hole structure is formed that sequentially penetrates the stacked structure and the first buffer layer.

[0030] In some embodiments of this application, forming a hole structure that sequentially penetrates the stacked structure and the first buffer layer includes:

[0031] Forming a lower layered structure;

[0032] A fifth lower hole structure is formed, which sequentially penetrates the lower stacked structure, the first buffer layer, and the first oxide layer and extends into the second buffer layer; a support layer is formed within the fifth lower hole structure.

[0033] An upper stacked structure is formed on the lower stacked structure;

[0034] A second upper hole structure is formed that penetrates the upper stacked structure; wherein the second upper hole structure is connected to the fifth lower hole structure.

[0035] In some embodiments of this application, the method further includes:

[0036] The support layer is etched to form a sixth lower hole structure that exposes the side of the first buffer layer. The sixth lower hole structure communicates with the second upper hole structure to form the hole structure.

[0037] In some embodiments of this application, the first epitaxial layer is formed on the exposed side of the first buffer layer within the sixth lower hole structure.

[0038] In some embodiments of this application, the method further includes:

[0039] The support layer is etched to form a seventh lower hole structure that exposes the side of the first oxide layer, the seventh lower hole structure being connected to the second upper hole structure to form the hole structure.

[0040] In some embodiments of this application, the first epitaxial layer is formed on the exposed side of the first buffer layer within the seventh lower hole structure.

[0041] In some embodiments of this application, the method further includes:

[0042] The support layer is etched to form an eighth lower hole structure that exposes the side of the second buffer layer. The eighth lower hole structure communicates with the second upper hole structure to form the hole structure.

[0043] In some embodiments of this application, a third epitaxial layer is formed on the exposed side of the second buffer layer within the eighth lower hole structure.

[0044] In some embodiments of this application, the material of the first buffer layer includes polycrystalline silicon.

[0045] In some embodiments of this application, when the hole structure is a channel hole, the method further includes:

[0046] A storage film and a channel layer are sequentially formed within the pore structure to form the channel structure.

[0047] In some embodiments of this application, the method further includes:

[0048] A first bonding layer is formed on the stacked structure;

[0049] A second substrate is provided, on which a peripheral circuit is formed and a second bonding layer is formed on the peripheral circuit;

[0050] The first bonding layer and the second bonding layer are bonded together.

[0051] In some embodiments of this application, the method further includes:

[0052] Remove the first substrate and the first epitaxial layer to expose the first oxide layer and the end of the channel structure;

[0053] Remove the storage membrane at the end of the channel structure to expose the channel layer.

[0054] In some embodiments of this application, the method further includes:

[0055] Remove the first oxide layer to expose the first buffer layer;

[0056] Ion implantation is performed on the exposed channel layer to form a doped channel layer.

[0057] In some embodiments of this application, the method further includes:

[0058] A semiconductor layer is formed, the semiconductor layer covering the first buffer layer and the doped channel layer;

[0059] Peripheral contacts and source contacts are formed on the semiconductor layer; wherein the peripheral contacts are in contact with the ends of the peripheral contacts.

[0060] Secondly, embodiments of this application provide a storage device, the storage device comprising:

[0061] A first semiconductor structure, the first semiconductor structure including a semiconductor layer, a doped buffer layer and a gate stack structure and a channel structure extending through the gate stack structure, the gate stack structure including alternately stacked interlayer insulating layers and gate layers;

[0062] The semiconductor layer covers the ends of the channel structure and the gate stack structure.

[0063] In some embodiments of this application, the bottoms of the different channel structures are substantially flush.

[0064] In some embodiments of this application, the material of the doped buffer layer includes doped polycrystalline silicon.

[0065] In some embodiments of this application, the storage device further includes:

[0066] A second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure including peripheral circuitry.

[0067] In some embodiments of this application, the storage device further includes:

[0068] The source contact and peripheral contact are located on the semiconductor layer; wherein the peripheral contact is in contact with the end of the peripheral contact element.

[0069] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the channel layer includes a doped channel layer that is in contact with the semiconductor layer.

[0070] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the semiconductor layer includes a portion extending into the bottom of the channel structure and contacting the channel layer; along the radial direction of the channel structure, the width of the portion of the semiconductor layer in contact with the channel layer is greater than the width of the channel structure.

[0071] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the semiconductor layer includes a portion extending into the bottom of the channel structure and contacting the channel layer; along the radial direction of the channel structure, the width of the portion of the semiconductor layer in contact with the channel layer is equal to the width of the channel structure.

[0072] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the semiconductor layer extends into the bottom of the channel structure and contacts the storage film and the channel layer; along the axial direction of the channel structure, the thickness of the portion of the semiconductor layer that contacts the storage film is greater than or equal to the thickness of the portion of the semiconductor layer that contacts the channel layer.

[0073] In some embodiments of this application, the storage film includes a barrier layer, a storage layer, and a tunneling layer in sequence along the radially inward direction of the channel structure; the thickness of the portion of the semiconductor layer in contact with the barrier layer and the thickness of the portion of the semiconductor layer in contact with the tunneling layer are the same or different.

[0074] In some embodiments of this application, the storage film includes, in a radially inward direction along the channel structure, a barrier layer, a storage layer, and a tunneling layer in sequence; the storage layer extends into the semiconductor layer, or the semiconductor layer extends into the storage layer.

[0075] In some embodiments of this application, the first semiconductor structure includes at least one memory plane, each memory plane includes at least one memory block, and each memory block includes at least one pointer memory region.

[0076] This application provides a memory device and a method for manufacturing the same. The method includes: providing a substrate structure, the substrate structure including a first substrate and a first oxide layer, a first buffer layer, and a stacked structure located on the first substrate, the stacked structure including alternately stacked interlayer insulating layers and gate sacrificial layers; forming a via structure that sequentially penetrates the stacked structure and the first buffer layer; and epitaxially forming a first epitaxial layer on the exposed side of the first buffer layer within the via structure. In the method for manufacturing the memory device provided in this application, after etching to form the via structure, the first epitaxial layer is epitaxially formed on the exposed side of the first buffer layer within the via structure, and the first epitaxial layer forms the bottom of the via structure. This ensures that the bottoms of different via structures are substantially flush in the direction perpendicular to the first substrate without needing to control the flushness of the bottom of the via structure through an etching process. This not only greatly reduces the difficulty of the etching process but also improves the consistency of the via structure. Attached Figure Description

[0077] Figure 1A This is a schematic cross-sectional view of a storage device with a channel hole formed in a related technology.

[0078] Figure 1B Electron micrographs of storage devices with formed channel holes in related technologies;

[0079] Figure 2 An optional process diagram illustrating a method for manufacturing a storage device provided in an embodiment of this application;

[0080] Figures 3A to 3M A cross-sectional structural schematic diagram of the main processes in the manufacturing process of a storage device provided in an embodiment of this application;

[0081] Figures 4A to 4N A cross-sectional structural schematic diagram of the main processes in the manufacturing process of another storage device provided in the embodiments of this application;

[0082] Figure 5A A schematic cross-sectional view of an optional storage device provided in an embodiment of this application;

[0083] Figure 5B A schematic diagram of another optional cross-sectional structure of the storage device provided in an embodiment of this application;

[0084] Figures 6A to 6G A partial cross-sectional structural schematic diagram illustrating seven optional relative positional relationships between the memory layer and the semiconductor layer provided in the embodiments of this application;

[0085] Figure 7A A partial top view of the die structure provided in an embodiment of this application;

[0086] Figure 7B A partial top view of the die structure provided in the embodiments of this application is shown in Figure 2.

[0087] The figure includes: 100-substrate; 101-pad oxide layer; 102-bottom sacrificial layer; 103-stacked structure; 104-interlayer insulating layer; 105-gate sacrificial layer; 106-channel via; 300, 400-first substrate; 301, 401-first oxide layer; 302, 402-first buffer layer; 403-second oxide layer; 404-second buffer layer; 305, 405-lower stacked structure; 306, 406-interlayer insulating layer; 307, 407-gate sacrificial layer; 3081-first lower channel via; 30 82 - Second lower channel hole; 4081 - Fifth lower channel hole; 4082 - Sixth lower channel hole; 309, 409 - Support layer; 310, 410 - Upper stacked structure; 311, 411 - Stacked structure; 312 - First upper channel hole; 412 - Second upper channel hole; 313, 413 - Channel hole; 314, 414 - First epitaxial layer; 315, 415, 615 - Storage film; 316, 416, 616 - Barrier layer; 317, 417, 617 - Storage layer; 318, 418, 618 - Tunneling layer; 319, 419, 619 - Channel layer; 320, 420 - Insulating layer; 321, 421 - Channel structure; 322, 422 - Virtual channel structure; 323, 423 - Gate line spacers; 324, 424 - Polysilicon layer; 325, 425 - Gate layer; 326, 426 - Stepped contact; 327, 427, 527 - Peripheral contact; 328, 428, 528 - First bonding layer; 329, 429, 529 - Second substrate; 330, 430, 530 - Second bonding layer; 331... 431, 531, 631 - Doped buffer layers; 332, 432, 532 - Doped channel layers; 333, 433 - Doped polysilicon layers; 334, 434, 534, 634 - Semiconductor layers; 335, 435, 535 - Transition layers; 336, 436, 536 - Interconnect layers; 337, 437, 537 - Source contacts; 338, 438, 538 - Peripheral contacts; W1, W2 are the widths of the semiconductor layers in contact with the ends of the channel vias; 739 - Storage plane; 740 - Storage block; 741 - Refers to the storage region. Detailed Implementation

[0088] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0089] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0090] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0091] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0092] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0093] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0094] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0095] As used herein, the term “three-dimensional memory” refers to a semiconductor device having vertically oriented memory cell transistors on a laterally oriented substrate, such that the memory cell transistors extend in a direction perpendicular to the substrate, and as used herein, the term “vertical” refers to a surface perpendicular to the lateral surface of the substrate.

[0096] refer to Figure 1A , Figure 1A This is a schematic cross-sectional view of a storage device with formed channel holes in related technologies. For example... Figure 1A As shown, a pad oxide layer 101, a bottom sacrificial layer 102, and a stacked structure 103 are formed on a substrate 100. The stacked structure 103 includes alternating stacked interlayer insulating layers 104 and gate sacrificial layers 105. Figure 1A It is also shown that a channel hole 106 is etched along a direction perpendicular to the substrate 100 to form a through-layer structure 103, and the etching stops at the bottom sacrificial layer 102.

[0097] It should be noted that, although Figure 1A Only a cross-sectional structure of a memory device with a single channel hole is shown. However, in the fabrication of 3D memory, multiple channel holes need to be etched to form a through-layer structure, and these multiple channel holes are arranged in an array. Therefore, as the number of stacked layers of the 3D memory increases, the etching depth of the channel holes also becomes deeper, and controlling the consistency of the multiple channel holes becomes increasingly difficult.

[0098] refer to Figure 1B , Figure 1B Electron microscope images of storage devices with formed channel holes in related technologies. For example... Figure 1BAs shown, etching creates multiple through-thickness channel holes, but the bottoms of these holes are not flush, resulting in poor consistency. Similarly, not only during the etching process for channel holes (CH), where the depths are inconsistent and the bottoms are not flush, but this issue can also occur during the etching process for dummy channel holes (DCH) and gate line slits (GLS). This unevenness at the bottom of the channel holes can even negatively impact the back-side routing architecture.

[0099] In view of this, embodiments of this application provide a storage device and a method for manufacturing the same. The method can form a first epitaxial layer on the exposed side of the first buffer layer within the hole structure after etching to form a hole structure, and the first epitaxial layer forms the bottom of the hole structure, thereby ensuring that the bottoms of different hole structures are substantially flush in the direction perpendicular to the first substrate, so as to improve the gouging uniformity of the bottom of the hole structure.

[0100] refer to Figure 2 , Figure 2 This is an optional flowchart illustrating a method for manufacturing a storage device provided in an embodiment of this application. (As shown...) Figure 2 As shown, this application embodiment provides a method for manufacturing a storage device, the method comprising:

[0101] Step S201: Provide a substrate structure, the substrate structure including: a first substrate and a first oxide layer, a first buffer layer and a stacked structure located on the first substrate, the stacked structure including alternately stacked interlayer insulating layers and gate sacrificial layers;

[0102] Step S202: Form a hole structure that sequentially penetrates the stacked structure and the first buffer layer;

[0103] Step S203: An epitaxial layer is formed on the exposed side of the first buffer layer within the hole structure.

[0104] In the embodiments of this application, the hole structure includes channel holes, virtual channel holes, and / or grid line slots. It should be noted that the following description uses channel holes as an example of hole structure.

[0105] refer to Figures 3A to 3M , Figures 3A to 3M This is a cross-sectional structural schematic diagram illustrating the main processes involved in the manufacturing of a storage device according to an embodiment of this application. The following section will combine... Figures 3A to 3M The manufacturing method of the storage device provided in the embodiments of this application will be further described in detail.

[0106] like Figure 3A As shown, a first oxide layer 301, a first buffer layer 302, and a lower stacked structure 305 are formed on the first substrate 300. The lower stacked structure 305 includes alternating stacked interlayer insulating layers 306 and gate sacrificial layers 307.

[0107] Here, the direction perpendicular to the first substrate is defined as the third direction. A first direction and a second direction, intersecting each other, are defined on the top or bottom surface of the first substrate perpendicular to the third direction. Based on the first and second directions, the top or bottom surface of the first substrate perpendicular to the third direction can be determined. For example, the first and second directions are perpendicular to each other, thus the first direction, the second direction, and the third direction are all mutually perpendicular. Of course, the first direction can also form a certain angle with the second direction.

[0108] In some embodiments of this application, the first substrate may be a single-element semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate; or the first substrate may be a composite semiconductor material substrate, such as a silicon-germanium (SiGe) substrate; or the first substrate may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0109] In some embodiments of this application, the material of the first buffer layer may include polysilicon.

[0110] In some embodiments of this application, the formation of the lower stacked structure on the first substrate can be achieved through one or more deposition processes. These deposition processes may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof. It is understood that the number and thickness of the interlayer insulating layer and the gate sacrificial layer are not limited to... Figure 3A The quantity and thickness are shown. Those skilled in the art can configure any number and thickness of interlayer insulating layers and gate sacrificial layers according to actual needs. Furthermore, the materials of the interlayer insulating layers and gate sacrificial layers can be selected from suitable materials known in the art. Here, the interlayer insulating layer can be an oxide layer, for example, a silicon oxide layer; the gate sacrificial layer can be a nitride layer, for example, a silicon nitride layer.

[0111] like Figure 3B As shown, a first low channel hole (LCH) 3081 is formed through the lower stacked structure 305, and a support layer 309 is formed within the first low channel hole 3081. Figure 3BThe first lower channel hole 3081 shown sequentially penetrates the lower stacked structure 305, the first buffer layer 302 and the first oxide layer 301, and extends into the first substrate 300. The depths to which each of the first lower channel holes 3081 extends into the first substrate 300 are different, that is, the bottoms of each of the first lower channel holes 3081 are not at the same horizontal plane.

[0112] It should be noted that as the number of layers in the lower stacked structure increases, it becomes increasingly difficult to control the bottom of the first lower channel hole to be flush with the bottom by controlling the etching process during the etching process to form the first lower channel hole penetrating the lower stacked structure. In other words, it becomes increasingly difficult to control the bottom of the first lower channel hole to be at the same horizontal level. Therefore, Figure 3B The different first lower channel holes shown have different depths, that is, the bottoms of the different first lower channel holes are not at the same horizontal level.

[0113] In this application embodiment, wet etching, dry etching, or a combination thereof can be used to etch the lower stacked structure to form a first lower channel hole.

[0114] This application does not impose any special limitations on the material of the support layer. For example, insulating materials or polysilicon can be used to fill the first lower channel via. By utilizing the supporting effect of the support layer, deformation of the lower stacked structure can be prevented when the upper stacked structure is formed on the lower stacked structure, thereby improving the stability of the sequential stacking of each stacked structure in the storage device.

[0115] Still referencing Figure 3B After the support layer 309 is formed in the first lower channel hole 3081, in order to ensure that the surface of the support layer 309 away from the first substrate 300 is on the same horizontal plane as the surface of the lower stacked structure 305 away from the first substrate 300, that is, to ensure that the upper surface of the support layer 309 is flush with the upper surface of the lower stacked structure 305, the support layer 309 can be planarized. For example, the upper surface of the support layer can be chemically mechanically polished (CMP) to make the lower surface of the upper stacked structure flush with the upper surface of the support layer, thereby improving the stability of the upper stacked structure formed on the lower stacked structure and reducing the risk of tilting or collapse of each stacked structure.

[0116] like Figure 3CAs shown, an upper stacked structure 310 is formed on the surface of the lower stacked structure 305 away from the first substrate 300. The lower stacked structure 305 and the upper stacked structure 310 together constitute a stacked structure 311, forming a first upper channel hole 312 penetrating the upper stacked structure 310. The first upper channel hole 312 is connected to a first lower channel hole 3081, meaning the first upper channel hole 312 communicates with the first lower channel hole 3081. Here, the first upper channel hole is etched to form penetrating the upper stacked structure, and the first upper channel hole extends into the support layer within the first lower channel hole. Optionally, the axis of the first upper channel hole coincides with the axis of the first lower channel hole.

[0117] In some embodiments of this application, the formation of the upper layered structure on the lower layered structure can be achieved by one or more deposition processes. These deposition processes may include, but are not limited to, physical vapor deposition, chemical vapor deposition, atomic layer deposition, or any combination thereof.

[0118] In this application embodiment, wet etching, dry etching, or a combination thereof can be used to etch the upper stacked structure to form the first upper channel hole.

[0119] like Figure 3D As shown, the support layer 309 is etched to form a second lower channel hole 3082 that exposes the side of the first buffer layer 302. The second lower channel hole 3082 communicates with the first upper channel hole 312 to form a channel hole 313.

[0120] It should be noted that, as mentioned earlier, the bottoms of the various first lower channel holes are not at the same horizontal level. Therefore, the bottoms of the support layer formed by filling the first lower channel holes are also not at the same horizontal level. Completely removing the support layer within the channel holes using etching is very difficult and may even damage the morphology of the channel holes. (Refer to...) Figure 3D At this point, only a portion of the support layer needs to be removed, ensuring that the upper surface of the remaining support layer is no higher than the first buffer layer. However, after removing part of the support layer, a portion of the support layer remains at the bottom of the channel hole, making it impossible to achieve a flush bottom. It should be noted that as the number of layers in the stacked structure increases, controlling the etching process to ensure the bottom of the second lower channel hole is flush becomes increasingly difficult; that is, controlling the etching process to ensure the bottom of the second lower channel hole is at the same horizontal level becomes increasingly challenging. Therefore, Figure 3D The different second lower channel holes shown have different depths, meaning that the bottoms of the different second lower channel holes are not at the same horizontal level.

[0121] like Figure 3E As shown, a first epitaxial layer 314 is formed on the exposed side of the first buffer layer 302 within the second lower channel hole 3082.

[0122] Here, a first epitaxial layer is epitaxially formed on the exposed side of the first buffer layer within the channel hole. The first epitaxial layer grows epitaxially from this exposed side, proceeding radially inwards along the channel hole until it seals the bottom of the channel hole. In other words, the first epitaxial layer forms a "new bottom" of the channel hole above its original bottom. Although the bottom depths of the etched channel holes differ, the thickness of the first epitaxial layer grown on the exposed side of the first buffer layer is essentially the same, and the height of the first buffer layer exposed in different channel holes is also essentially the same. That is, the distance between the first buffer layer exposed in different channel holes and the first substrate in the third direction is essentially the same. Therefore, the height of the first epitaxial layer formed on the exposed side of the first buffer layer within the channel hole is also essentially the same, enabling the bottoms of different channel holes to be essentially flush.

[0123] In this embodiment, after selective epitaxial growth (SEG) is used to form a first epitaxial layer at the location corresponding to the first buffer layer within the channel hole, the first epitaxial layer forms the bottom of the channel hole, thereby achieving the sealing of the bottom of the channel hole. It should be noted that after forming the first epitaxial layer, the bottoms of the different channel holes are essentially flush in the direction perpendicular to the first substrate, thereby improving the consistency of the bottoms of each channel hole, that is, improving the depth uniformity of each channel hole. Furthermore, the manufacturing method provided in this embodiment eliminates the need to control the flush bottom of the hole structure through etching processes, greatly reducing the difficulty of the etching process.

[0124] In other embodiments of this application, the method further includes:

[0125] The support layer is etched to form a third lower hole structure that exposes the side of the first oxide layer, the third lower hole structure being connected to the first upper hole structure to form the hole structure.

[0126] In some other embodiments of this application, the first epitaxial layer is formed on the exposed side of the first buffer layer within the third lower hole structure.

[0127] Here, the support layer is etched to form a third lower channel hole that exposes the sides of the first buffer layer and the first oxide layer. The third lower channel hole and the first upper channel hole are connected to form a channel hole. Thus, the sides of the first buffer layer and the first oxide layer are simultaneously exposed within the channel hole. Compared to the above scheme where only the sides of the first buffer layer are exposed, this scheme removes more support layer material through etching, resulting in a third lower channel hole with a greater depth than the second lower channel hole. Therefore, a first epitaxial layer can be epitaxially grown on the exposed sides of the first buffer layer within the channel hole. In this embodiment, the height of the first epitaxial layer formed on the exposed sides of the first buffer layer within the channel hole is substantially the same, thereby achieving substantially flush bottoms for different channel holes. For example, the first epitaxial layer may include polysilicon.

[0128] In other embodiments of this application, the method further includes:

[0129] The support layer is etched to form a fourth lower hole structure that exposes the side surface of the first substrate. The fourth lower hole structure communicates with the first upper hole structure to form the hole structure.

[0130] In some other embodiments of this application, a second epitaxial layer is epitaxially formed on the exposed side of the first substrate within the fourth lower hole structure.

[0131] Here, the support layer is etched to form a fourth lower channel hole that exposes the sides of the first buffer layer, the first oxide layer, and the first substrate. The fourth lower channel hole is connected to the first upper channel hole to form a channel hole. Thus, the sides of the first buffer layer, the first oxide layer, and the first substrate are simultaneously exposed within the channel hole. Compared to the above scheme where the sides of the first buffer layer and the first oxide layer are exposed, this scheme removes more support layer material through etching, resulting in a fourth lower channel hole with a greater depth than the third lower channel hole. Therefore, a first epitaxial layer can be epitaxially grown on the exposed sides of the first buffer layer within the channel hole, and a second epitaxial layer can be epitaxially grown on the exposed sides of the first substrate within the channel hole. In this embodiment, the height of the first epitaxial layer formed on the exposed sides of the first buffer layer within the channel hole is substantially the same, thereby achieving substantially flush bottoms for different channel holes. Furthermore, the second epitaxial layer is located directly below the first epitaxial layer, providing support for the first epitaxial layer. For example, the first epitaxial layer may include polysilicon, and the second epitaxial layer may also include polysilicon.

[0132] Figure 3F A cross-sectional structural diagram of the stepped region along the X direction and the core region along the Y direction of the storage device is shown. In the embodiments of this application, the X and Y directions can be perpendicular to each other, and both the X and Y directions are parallel to the first substrate. The following... Figures 3F to 3MBoth diagrams show cross-sectional structural schematics of the stepped region along the X-direction and the core region along the Y-direction of the storage device, which will not be described again hereafter. Figure 3F As shown, the vertical memory cell string of the memory device is formed by a channel structure. The channel structure 321 may have a columnar shape extending in a direction perpendicular to the first substrate, that is, the channel structure 321 extends in a third direction. The channel structure 321 may include a memory film 315 and a channel layer 319. The memory film 315 includes a three-layer structure, namely, a barrier layer 316, a memory layer 317, and a tunneling layer 318. The barrier layer is located as the outermost layer of the three-layer structure, the tunneling layer is located as the innermost layer of the three-layer structure, and the memory layer is located between the barrier layer and the tunneling layer. The barrier layer 316, the memory layer 317, the tunneling layer 318, the channel layer 319, and the insulating layer 320 are sequentially formed within the channel hole, and an air gap may also be formed within the insulating layer 320.

[0133] Here, the barrier layer can be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The storage layer is used to store charge, and its material can be, but is not limited to, silicon nitride, silicon oxynitride, or combinations thereof. The tunneling layer can be made of an insulating material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The channel layer can be a polycrystalline silicon layer. The insulating layer can be a silicon oxide or silicon nitride layer. This can be achieved through one or more deposition processes. The deposition processes can include, but are not limited to, physical vapor deposition, chemical vapor deposition, atomic layer deposition, or any combination thereof.

[0134] In some embodiments of this application, the channel structure is distributed in an array in the core region of the stacked structure. The array of the channel structure can have any suitable array shape, such as a rectangular array shape along a first direction and a second direction, a honeycomb (e.g., a hexagonal) array shape, etc.

[0135] In some embodiments of this application, the channel structure may have any suitable shape. For example, the channel structure may have a circular shape in a plane parallel to the first substrate, or a cylindrical shape in a plane perpendicular to the first substrate.

[0136] Still referencing Figure 3F The stacked structure may include a stepped region and a core region, wherein the core region is used to form array memory cell strings, which are multiple interconnected memory cells formed perpendicular to the substrate direction; the stepped region is used to form stepped contacts to draw out electrical signals therefrom.

[0137] In some embodiments of this application, multi-level steps can be formed at the edges of alternately stacked gate sacrificial layers and interlayer insulating layers. For example, multi-level steps can be formed in the step region by performing repeated etch-trimming processes on the stacked structure using a patterned mask layer. The patterned mask layer may include a photoresist or a carbon-based polymer material and can be removed after the multi-level steps have been formed.

[0138] In some embodiments of this application, the stepped area may be formed at the center of the stacked structure, or it may be formed on one or more edges of the stacked structure.

[0139] In some embodiments of this application, the height of each step in the step region may gradually decrease along the direction away from the core region of the stacked structure, or the height of each step in the step region may gradually increase along the direction away from the core region of the stacked structure.

[0140] In some embodiments of this application, a medium layer is formed above each step in the step region, that is, a medium layer covering the stacked structure is formed, and the medium layer provides a flat upper surface for the stacked structure.

[0141] Here, the dielectric layer can be a multilayer structure, for example, including a first dielectric layer and a second dielectric layer, and the first and second dielectric layers can be formed by depositing oxides. The first dielectric layer can be formed of a material with good step coverage, for example, the first dielectric layer can be silicon oxide formed by atomic layer deposition. The second dielectric layer can be formed of a material with high filling efficiency, for example, the second dielectric layer can be tetraethyl orthosilicate-based silicon oxide (TEOS-based SiO2). The density of the first dielectric layer is higher than that of the second dielectric layer; therefore, the first dielectric layer has good step coverage, while the second dielectric layer has high filling efficiency.

[0142] Here, a chemical mechanical polishing process can also be used to planarize the second dielectric layer, so that the second dielectric layer provides a basically flat upper surface for the stepped area of ​​the laminated structure.

[0143] Still referencing Figure 3F A virtual channel hole is formed in the stepped region, penetrating the stacked structure and extending to the first substrate 300. The virtual channel hole is filled to form a virtual channel structure 322, that is, the virtual channel structure 322 extends in a direction perpendicular to the first substrate, i.e., in a third direction. In addition, an air gap can also be formed within the virtual channel structure.

[0144] Here, insulating material can be filled into the virtual channel holes to form a virtual channel structure. By forming virtual channel structures in the stepped regions of the laminated structure, and having an array distribution similar to the channel structures formed in the core region of the laminated structure, the virtual channel structures provide support, thus ensuring the overall stress balance of the laminated structure.

[0145] Here, insulating and conductive materials can be sequentially filled into the virtual channel holes to form a virtual channel structure. The conductive material within the virtual channel structure has no electrical connection to the external circuit; therefore, the virtual channel structure still provides support.

[0146] It should be noted that the etching forms a virtual channel hole that penetrates the stacked structure, the first buffer layer, and the first oxide layer, extending into the first substrate. As the number of layers in the stacked structure increases, the etching depth of the virtual channel hole also increases, making it difficult to control the bottom of the virtual channel hole to be flush. (Refer to...) Figure 3F The bottoms of the multiple virtual channel holes formed by etching are not at the same horizontal level.

[0147] In some embodiments of this application, the virtual channel structure is arrayed in the core region of the stacked structure. The array of the virtual channel structure can have any suitable array shape, such as a rectangular array shape along the first and second directions, a honeycomb (e.g., hexagonal) array shape, etc.

[0148] In some embodiments of this application, the virtual channel structure can have any suitable shape. For example, the virtual channel structure has a circular shape in a plane parallel to the first substrate, or a cylindrical shape in a plane perpendicular to the first substrate.

[0149] Still referencing Figure 3F A gate line slot 323 is formed that penetrates the stacked structure. The gate sacrificial layer in the stacked structure is removed through the gate line slot 323 to form a gap, thereby forming a void between each pair of adjacent interlayer insulating layers. Then, conductive material is filled into each void to form each gate layer 325. Here, the alternately stacked gate layers and interlayer insulating layers constitute a gate stacked structure.

[0150] Here, the thickness of the gate layer can be the same as or different from the thickness of the interlayer insulating layer. The gate layer is made of a conductive material, which can include, but is not limited to, tungsten, copper, aluminum, and doped silicon. The gate layer can include a multilayer structure; for example, the gate layer can include a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer can include, but is not limited to, a high dielectric constant (HIK) layer, the first conductive layer can include, but is not limited to, a titanium nitride (TIN) layer, and the second conductive layer can include, but is not limited to, a tungsten (W) layer.

[0151] Still referencing Figure 3F After forming an isolation material layer on the sidewall of the gate slot 323, polysilicon is filled into the gate slot to form a polysilicon layer 324.

[0152] Still referencing Figure 3F The etching process forms step contact holes that penetrate the dielectric layer and extend to the gate layer 325 of each step. That is, the step contact holes are connected to the gate layer of each step. Conductive material can be filled into the step contact holes to form step contacts 326. The step contacts in the step region are used to lead out electrical signals.

[0153] Still referencing Figure 3F It can also form an outer contact 327, which can extend vertically into the first buffer layer 302.

[0154] like Figure 3G As shown, a first bonding layer 328 is formed on the stacked structure, and the stacked first substrate 300, first oxide layer 301, first buffer layer 302, stacked structure, and first bonding layer 328 constitute a first semiconductor structure. A peripheral circuit is formed on a second substrate 329, and a second bonding layer 330 is formed on the peripheral circuit. The stacked second substrate 329, peripheral circuit, and second bonding layer 330 constitute a second semiconductor structure. The first semiconductor structure and the second semiconductor structure are bonded together in a "face-to-face" manner.

[0155] In some embodiments of this application, the second substrate may be a single-element semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate; or the second substrate may be a composite semiconductor material substrate, such as a silicon-germanium (SiGe) substrate; or the second substrate may be a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0156] Here, peripheral circuitry is used to control and sense the three-dimensional memory. Peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to facilitate the operation of the three-dimensional memory, including but not limited to page buffers, decoders, sense amplifiers, drivers, charge pumps, current or voltage references, or any active or passive components of the circuitry. Peripheral circuitry may include transistors formed on a second substrate, wherein the transistors may be wholly or partially formed on the second substrate.

[0157] In some embodiments of this application, metal fusion bonding can be used to bond the first semiconductor structure and the second semiconductor structure. In some embodiments of this application, non-metallic bonding methods, including but not limited to using adhesives, can also be used to bond the first semiconductor structure and the second semiconductor structure. In other embodiments of this application, hybrid bonding, i.e., metal / non-metal hybrid bonding, can also be used to form a bonding layer between the first semiconductor structure and the second semiconductor structure.

[0158] like Figure 3H As shown, the first substrate is removed to expose the upper surface of the first oxide layer 301.

[0159] like Figure 3I As shown, the first epitaxial layer is removed to expose the end of the channel structure.

[0160] like Figure 3J As shown, the storage membrane at the end of the channel structure is removed to expose the channel layer 319 at the end of the channel structure.

[0161] Still referencing Figure 3J Remove the first oxide layer to expose the upper surface of the first buffer layer 302.

[0162] like Figure 3K As shown, ion implantation is performed on the exposed channel layer to form a doped channel layer 332 (e.g., Figure 3K (As shown in the dashed box). The doped channel layer is partially located in the stacked structure. In the ion implantation process, dopant ions are implanted into the channel layer in the form of an ion beam. The high-energy ions lose energy due to collisions with electrons and atomic nuclei in the channel layer and eventually stop at a certain depth within the crystal lattice. Figure 3K The area within the dashed box represents the depth of the doped channel layer. It should be noted that in this embodiment, ion implantation is used to dope the channel layer, and the doping depth is the ion implantation depth. Different doping depths, doping concentrations, or doping impurity distributions can be set according to the actual needs of the three-dimensional memory. The doping depth can be controlled by adjusting the acceleration energy of the ion beam, while the doping concentration, i.e., the impurity dose, can be controlled by monitoring the ion current during implantation.

[0163] Still referencing Figure 3K Furthermore, ion implantation can be performed on the exposed first buffer layer to form a doped buffer layer 331. As mentioned earlier, the material of the first buffer layer can be polycrystalline silicon, and therefore the doped buffer layer can be doped polycrystalline silicon.

[0164] Still referencing Figure 3K Furthermore, ion implantation can be performed on the polysilicon layer within the exposed gate trenches to form a doped polysilicon layer 333.

[0165] like Figure 3L As shown, a semiconductor layer 334 is formed, which covers a doped buffer layer 331, a doped channel layer 332, and a doped polysilicon layer 333. The semiconductor layer 334 includes a portion that contacts the doped polysilicon layer 333, a portion that extends into the bottom of the channel structure and contacts the doped channel layer 332, and a portion that extends into the doped buffer layer 331.

[0166] like Figure 3M As shown, a transition layer 335 is formed, the transition layer 335 is etched to form a source contact opening, and a conductive material is filled in the source contact opening to form a source contact 337.

[0167] Here, one or more thin film deposition processes, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, any other suitable process, or combinations thereof, can be used to form a transition layer on the semiconductor layer. After the transition layer is formed, it is planarized, for example, using a chemical mechanical polishing process, to ensure a smooth surface of the transition layer.

[0168] Still referencing Figure 3M While forming the source contact 337, the transition layer 335 and the semiconductor layer 334 can be etched to form a peripheral contact opening. The peripheral contact opening is filled with conductive material to form a peripheral contact 338, wherein the peripheral contact 338 contacts the end of the peripheral contact 327.

[0169] Here, wet etching or dry etching can be used to form peripheral contact openings that penetrate the transition layer and the semiconductor layer. In the embodiments of this application, photolithography is used to pattern the peripheral contact openings and align them with the peripheral contacts. The etching of the peripheral contact openings can stop at the upper end of the peripheral contacts.

[0170] In this embodiment, the peripheral contacts are connected to the peripheral contact elements, enabling the transmission of electrical signals with the peripheral circuit of the second semiconductor structure; the source contacts can be connected to the doped channel layer through the semiconductor layer.

[0171] Still referencing Figure 3M Furthermore, an interconnect layer 336 can be formed above the source contact 337 and the peripheral contact 338, and electrically connected to the source contact 337 and the peripheral contact 338, to enable pad take-out. For example, it can transmit electrical signals between the first semiconductor structure and the second semiconductor structure.

[0172] refer to Figures 4A to 4N , Figures 4A to 4N A cross-sectional structural schematic diagram of the main processes in the manufacturing of another storage device provided in an embodiment of this application. The following is combined with... Figures 4A to 4NA method for manufacturing a storage device according to another embodiment of this application will be described in further detail.

[0173] like Figure 4A As shown, a second oxide layer 403, a second buffer layer 404, a first oxide layer 401, a first buffer layer 402, and a lower stacked structure 405 are sequentially formed on the first substrate 400. The lower stacked structure 405 includes an interlayer insulating layer 406 and a gate sacrificial layer 407 that are alternately stacked.

[0174] Here, the thickness of the second buffer layer can be greater than the thickness of the first buffer layer. For example, the thickness of the second buffer layer can range from 50 to 100 nm.

[0175] In some embodiments of this application, the material of the first buffer layer may include polycrystalline silicon.

[0176] In some embodiments of this application, the material of the second buffer layer may include polycrystalline silicon.

[0177] Here, the materials of the first buffer layer and the second buffer layer can be the same or different.

[0178] like Figure 4B As shown, a fifth lower channel hole 4081 is formed through the lower stacked structure 405, and a support layer 409 is formed within the fifth lower channel hole 4081. Figure 4B The fifth lower channel hole 4081 shown sequentially penetrates the lower stacked structure 405, the first buffer layer 402, and the first oxide layer 401, and extends into the second buffer layer 404. The depths to which each of the fifth lower channel holes 4081 extends into the second buffer layer 404 are different, that is, the bottoms of each of the fifth lower channel holes 4081 are not at the same horizontal plane.

[0179] Here, as the number of layers in the lower stacked structure increases, it becomes increasingly difficult to control the bottom of the fifth lower channel hole to be flush with the bottom by controlling the etching process during the etching process to form the fifth lower channel hole that penetrates the lower stacked structure. In other words, it becomes increasingly difficult to control the bottom of the fifth lower channel hole to be at the same horizontal level by controlling the etching process. Therefore, Figure 4B The different fifth lower channel holes shown have different depths, meaning that the bottoms of the different fifth lower channel holes are not at the same horizontal level.

[0180] like Figure 4CAs shown, an upper stacked structure 410 is formed on the surface of the lower stacked structure 405 away from the first substrate 400. The lower stacked structure 405 and the upper stacked structure 410 together constitute a stacked structure 411, forming a second upper channel hole 412 penetrating the upper stacked structure 410. The second upper channel hole 412 is connected to a fifth lower channel hole 4081, meaning the second upper channel hole 412 and the fifth lower channel hole 4081 are interconnected. Here, a first upper channel hole penetrating the upper stacked structure is formed by etching, and the second upper channel hole extends into the support layer within the fifth lower channel hole. Optionally, the axis of the second upper channel hole coincides with the axis of the fifth lower channel hole.

[0181] like Figure 4D As shown, the support layer 409 is etched to form a sixth lower channel hole 4082 that exposes the side of the first buffer layer 402. The sixth lower channel hole 4082 communicates with the second upper channel hole 412 to form a channel hole 413.

[0182] It should be noted that, as mentioned earlier, the bottoms of the various fifth lower channel holes are not at the same horizontal level. Therefore, the bottoms of the support layer formed by filling the fifth lower channel holes are also not at the same horizontal level. Completely removing the support layer within the channel holes using etching is very difficult and may even damage the morphology of the channel holes. (Refer to...) Figure 4D At this point, only a portion of the support layer needs to be removed, ensuring that the upper surface of the remaining support layer is no higher than the first buffer layer. However, after removing part of the support layer, a portion of the support layer remains at the bottom of the channel hole, making it impossible to achieve a flush bottom. It should be noted that as the number of layers in the stacked structure increases, controlling the etching process to ensure the bottom of the sixth lower channel hole is flush becomes increasingly difficult; that is, controlling the etching process to ensure the bottom of the sixth lower channel hole is at the same horizontal level becomes increasingly challenging. Therefore, Figure 4D The different sixth lower channel holes shown have different depths, meaning that the bottoms of the different sixth lower channel holes are not at the same horizontal level.

[0183] like Figure 4E As shown, a first epitaxial layer 414 is formed on the exposed side of the first buffer layer 302 within the sixth lower channel hole 4082.

[0184] Here, a first epitaxial layer is epitaxially formed on the exposed side of the first buffer layer within the channel hole. The first epitaxial layer grows epitaxially from this exposed side, proceeding radially inwards along the channel hole until it seals the bottom of the channel hole. In other words, the first epitaxial layer forms a "new bottom" of the channel hole above its original bottom. Although the bottom depths of the etched channel holes differ, the thickness of the first epitaxial layer grown on the exposed side of the first buffer layer is essentially the same, and the height of the first buffer layer exposed in different channel holes is also essentially the same. That is, the distance between the first buffer layer exposed in different channel holes and the first substrate in the third direction is essentially the same. Therefore, the height of the first epitaxial layer formed on the exposed side of the first buffer layer within the channel hole is also essentially the same, enabling the bottoms of different channel holes to be essentially flush.

[0185] In this embodiment, after forming a first epitaxial layer at the location corresponding to the first buffer layer within the channel hole, the first epitaxial layer forms the bottom of the channel hole, thereby sealing the bottom of the channel hole. It should be noted that after forming the first epitaxial layer, the bottom of each channel hole is substantially flush in the direction perpendicular to the first substrate, thus improving the consistency of the bottom of each channel hole, i.e., improving the depth uniformity of each channel hole. Furthermore, the manufacturing method provided in this embodiment eliminates the need to control the flush bottom of the hole structure through etching processes, greatly reducing the difficulty of the etching process.

[0186] In other embodiments of this application, the method further includes:

[0187] The support layer is etched to form a seventh lower hole structure that exposes the side of the first oxide layer, the seventh lower hole structure being connected to the second upper hole structure to form the hole structure.

[0188] In some other embodiments of this application, the first epitaxial layer is formed on the exposed side of the first buffer layer within the seventh lower hole structure.

[0189] Here, the support layer is etched to form a seventh lower channel hole that exposes the sides of the first buffer layer and the first oxide layer. The seventh lower channel hole is connected to the second upper channel hole to form a channel hole. Thus, the sides of the first buffer layer and the first oxide layer are simultaneously exposed within the channel hole. Compared to the above scheme where only the sides of the first buffer layer are exposed, this scheme removes more support layer material through etching, resulting in a deeper seventh lower channel hole than the sixth lower channel hole. Therefore, a first epitaxial layer can be epitaxially grown on the exposed sides of the first buffer layer within the channel hole. In this embodiment, the height of the first epitaxial layer formed on the exposed sides of the first buffer layer within the channel hole is substantially the same, thereby achieving substantially flush bottoms for different channel holes. For example, the first epitaxial layer may include polysilicon.

[0190] In other embodiments of this application, the method further includes:

[0191] The support layer is etched to form an eighth lower hole structure that exposes the side of the second buffer layer. The eighth lower hole structure communicates with the second upper hole structure to form the hole structure.

[0192] In some other embodiments of this application, a third epitaxial layer is formed on the side exposed by the second buffer layer within the eighth lower hole structure.

[0193] Here, the support layer is etched to form an eighth lower channel hole that exposes the sides of the first buffer layer, the first oxide layer, and the second buffer layer. The eighth lower channel hole and the second upper channel hole are connected to form a channel hole. Thus, the sides of the first buffer layer, the first oxide layer, and the second buffer layer are simultaneously exposed within the channel hole. Compared to the above scheme where the sides of the first buffer layer and the first oxide layer are exposed, this scheme removes more support layer material through etching, resulting in a deeper eighth lower channel hole than the seventh lower channel hole. Therefore, a first epitaxial layer can be epitaxially grown on the exposed sides of the first buffer layer within the channel hole, and a third epitaxial layer can be epitaxially grown on the exposed sides of the second buffer layer within the channel hole. In this embodiment, the height of the first epitaxial layer formed on the exposed sides of the first buffer layer within the channel hole is substantially the same, thereby achieving substantially flush bottoms for different channel holes. Furthermore, the third epitaxial layer is located directly below the first epitaxial layer, providing support for the first epitaxial layer. For example, the first epitaxial layer may include polysilicon, and the third epitaxial layer may also include polysilicon.

[0194] Figure 4F A cross-sectional structural diagram of the stepped region along the X direction and the core region along the Y direction of the storage device is shown. In the embodiments of this application, the X and Y directions can be perpendicular to each other, and both the X and Y directions are parallel to the first substrate. The following... Figures 4F to 4NBoth diagrams show cross-sectional structural schematics of the stepped region along the X-direction and the core region along the Y-direction of the storage device, which will not be described again hereafter. Figure 4F As shown, the vertical memory cell string of the memory device is formed by a channel structure. The channel structure 421 may have a columnar shape extending in a direction perpendicular to the first substrate, i.e., the channel structure 421 extends along a third direction. The channel structure 421 may include a memory film 415 and a channel layer 419. The memory film 415 includes a three-layer structure, namely, a barrier layer 416, a memory layer 417, and a tunneling layer 418. The barrier layer is located as the outermost layer of the three-layer structure, the tunneling layer is located as the innermost layer of the three-layer structure, and the memory layer is located between the barrier layer and the tunneling layer. The barrier layer 416, the memory layer 417, the tunneling layer 418, the channel layer 419, and the insulating layer 420 are sequentially formed within the channel hole, and an air gap may also be formed within the insulating layer 420.

[0195] Still referencing Figure 4F The stacked structure may include a stepped region and a core region, wherein the core region is used to form array memory cell strings, which are multiple interconnected memory cells formed perpendicular to the substrate direction; the stepped region is used to form stepped contacts to draw out electrical signals therefrom.

[0196] In some embodiments of this application, multi-level steps can be formed at the edges of alternately stacked gate sacrificial layers and interlayer insulating layers. For example, multi-level steps can be formed in the step region by performing repeated etch-trimming processes on the stacked structure using a patterned mask layer. The patterned mask layer may include a photoresist or a carbon-based polymer material and can be removed after the multi-level steps have been formed.

[0197] In some embodiments of this application, a medium layer is formed above each step in the step region, that is, a medium layer covering the stacked structure is formed, and the medium layer provides a flat upper surface for the stacked structure.

[0198] Still referencing Figure 4F A virtual channel hole is formed in the stepped region, penetrating the stacked structure and extending to the second buffer layer 404. The virtual channel hole is filled to form a virtual channel structure 422, that is, the virtual channel structure 422 extends in a direction perpendicular to the first substrate, i.e., in a third direction. In addition, an air gap can also be formed within the virtual channel structure.

[0199] Still referencing Figure 4F A gate line slot 423 is formed that penetrates the stacked structure. The gate sacrificial layer in the stacked structure is removed through the gate line slot 423 to form a gap, thereby forming a void between each pair of adjacent interlayer insulating layers. Then, conductive material is filled into each void to form each gate layer 425. Here, the alternately stacked gate layers and interlayer insulating layers constitute a gate stacked structure.

[0200] Still referencing Figure 4F After forming an isolation material layer on the sidewall of the gate slot 423, polysilicon is filled into the gate slot to form a polysilicon layer 424.

[0201] Still referencing Figure 4F The etching process forms step contact holes that penetrate the dielectric layer and extend to the gate layer 425 of each step. Specifically, the step contact holes are connected to the gate layer of each step. Conductive material can be filled into the step contact holes to form step contacts 426. The step contacts in the step region are used to extract electrical signals.

[0202] Still referencing Figure 4F It can also form an outer contact 427, which can extend vertically into the first buffer layer 402.

[0203] like Figure 4G As shown, a first bonding layer 428 is formed on the stacked structure. The stacked first substrate 400, second oxide layer 403, second buffer layer 404, first oxide layer 401, first buffer layer 402, the stacked structure, and the first bonding layer 428 constitute the first semiconductor structure. A peripheral circuit is formed on the second substrate 429, and a second bonding layer 430 is formed on the peripheral circuit. The stacked second substrate 429, peripheral circuit, and second bonding layer 430 constitute the second semiconductor structure. The first semiconductor structure and the second semiconductor structure are bonded together in a face-to-face manner.

[0204] like Figure 4H As shown, the first substrate is removed to expose the upper surface of the second oxide layer 403.

[0205] like Figure 4I As shown, the second oxide layer and the second buffer layer are removed to expose the first oxide layer 401 and the first epitaxial layer 414.

[0206] like Figure 4J As shown, the first epitaxial layer is removed to expose the end of the channel structure.

[0207] like Figure 4K As shown, the storage membrane at the end of the channel structure is removed to expose the channel layer 419 at the end of the channel structure.

[0208] Still referencing Figure 4K Remove the first oxide layer to expose the upper surface of the first buffer layer 402.

[0209] like Figure 4L As shown, ion implantation is performed on the exposed channel layer to form a doped channel layer 432 (e.g., Figure 4L(As shown in the dashed box). The doped channel layer is partially located in the stacked structure. In the ion implantation process, dopant ions are implanted into the channel layer in the form of an ion beam. The high-energy ions lose energy due to collisions with electrons and atomic nuclei in the channel layer and eventually stop at a certain depth within the crystal lattice.

[0210] Still referencing Figure 4L Furthermore, ion implantation can be performed on the exposed first buffer layer to form a doped buffer layer 431. As mentioned earlier, the material of the first buffer layer can be polycrystalline silicon, and therefore the doped buffer layer can be doped polycrystalline silicon.

[0211] Still referencing Figure 4L Furthermore, ion implantation can be performed on the polysilicon layer within the exposed gate trenches to form a doped polysilicon layer 433.

[0212] like Figure 4M As shown, a semiconductor layer 434 is formed, which covers a doped buffer layer 431, a doped channel layer 432, and a doped polysilicon layer 333. The semiconductor layer 434 includes a portion that contacts the doped polysilicon layer 433, a portion that extends into the bottom of the channel structure and contacts the doped channel layer 432, and a portion that extends into the doped buffer layer 431.

[0213] like Figure 4N As shown, a transition layer 435 is formed, and the transition layer 435 is etched to form a source contact opening. The source contact opening is filled with conductive material to form a source contact 437.

[0214] Still referencing Figure 4N While forming the source contact 437, the transition layer 435 and the semiconductor layer 434 can be etched to form a peripheral contact opening. The peripheral contact opening is filled with conductive material to form a peripheral contact 438, wherein the peripheral contact 438 contacts the end of the peripheral contact 427.

[0215] In this embodiment, the peripheral contacts are connected to the peripheral contact elements, enabling the transmission of electrical signals with the peripheral circuit of the second semiconductor structure; the source contacts can be connected to the doped channel layer through the semiconductor layer.

[0216] Still referencing Figure 4N Furthermore, an interconnect layer 436 can be formed above the source contact 437 and the peripheral contact 438, and electrically connected to the source contact 437 and the peripheral contact 438, to enable pad take-out. For example, it can transmit electrical signals between the first semiconductor structure and the second semiconductor structure.

[0217] refer to Figure 5A and Figure 5B , Figure 5A and Figure 5BThese are schematic diagrams illustrating two optional cross-sectional structures of the storage device provided in embodiments of this application. For example... Figure 5A and Figure 5B As shown, the first semiconductor structure includes a semiconductor layer 534, a doped buffer layer 531, a stacked structure, and a channel structure extending through the stacked structure; the semiconductor layer 534 includes a portion extending into the bottom of the channel structure and contacting the doped channel layer 532; the first semiconductor structure also includes a first bonding layer 528. The second semiconductor structure includes a second substrate 529, peripheral circuitry, and a second bonding layer 530 located on the peripheral circuitry. Bonding is achieved through the first bonding layer of the first semiconductor structure and the second bonding layer of the second semiconductor structure.

[0218] Still referencing Figure 5A and Figure 5B A transition layer 535 is formed on the semiconductor layer 534. Source contacts 537 and peripheral contacts 538 are formed within the transition layer 535. An interconnect layer 536 can also be formed above the source contacts 537 and peripheral contacts 538 and electrically connected to them to facilitate pad lead-out. In this embodiment, the peripheral contacts 538 are connected to the peripheral contact 527, enabling the transmission of electrical signals with the peripheral circuitry of the second semiconductor structure. The source contacts 537 can be connected to the doped channel layer 532 through the semiconductor layer 534.

[0219] Still referencing Figure 5A Along the radial direction of the channel structure, the width W1 of the portion where the semiconductor layer 534 contacts the doped channel layer 532 is equal to the width of the channel structure. (Still referring to...) Figure 5B Along the radial direction of the channel structure, the width W2 of the portion where the semiconductor layer 534 contacts the doped channel layer 532 is greater than the width of the channel structure. That is, during the process of etching away the storage film at the end of the channel structure to expose the channel layer at the end of the channel structure, the width of the opening can be enlarged along the radial direction of the channel structure before filling to form the semiconductor layer.

[0220] refer to Figures 6A to 6G , Figures 6A to 6G This is a partial cross-sectional structural diagram illustrating seven optional relative positional relationships between the memory layer and the semiconductor layer provided in embodiments of this application. (See attached diagram.) Figures 6A to 6G As shown, the semiconductor layer 634 includes a portion extending into the bottom of the channel structure and contacting the doped channel layer, and a portion extending into the doped buffer layer 631; along the axial direction of the channel structure, the thickness of the portion of the semiconductor layer 634 in contact with the storage film 615 is greater than or equal to the thickness of the portion of the semiconductor layer 634 in contact with the channel layer 619. After forming the channel via, a barrier layer 616, a storage layer 617, and a tunneling layer 618 are formed sequentially.

[0221] like Figure 6A , Figure 6C and Figure 6E As shown in the dashed box, the direct contact surface between the semiconductor layer 634 and the memory film 615 is planar; that is, the thickness of the portion where the semiconductor layer 634 contacts the barrier layer 616 is the same as the thickness of the portion where the semiconductor layer 634 contacts the tunneling layer 618. Figure 6B and Figure 6F As shown, the direct contact surface between the semiconductor layer 634 and the memory film 615 is a stepped surface. That is, the thickness of the portion where the semiconductor layer 634 contacts the barrier layer 616 is different from the thickness of the portion where the semiconductor layer 634 contacts the tunneling layer 618. More specifically, the thickness of the portion where the semiconductor layer 634 contacts the barrier layer 616 is less than the thickness of the portion where the semiconductor layer 634 contacts the tunneling layer 618. Figure 6D and Figure 6G As shown, the direct contact surface between the semiconductor layer 634 and the storage film 615 is a stepped surface. That is, the thickness of the contact portion between the semiconductor layer 634 and the barrier layer 616 is different from the thickness of the contact portion between the semiconductor layer 634 and the tunneling layer 618. More specifically, the thickness of the contact portion between the semiconductor layer 634 and the barrier layer 616 is greater than the thickness of the contact portion between the semiconductor layer 634 and the tunneling layer 618.

[0222] Still referencing Figure 6A The memory layer 617 can be in direct contact with the semiconductor layer 634. (Refer to...) Figure 6B , Figure 6C and Figure 6D The memory layer 617 can also extend into the semiconductor layer 634. (See also...) Figure 6E , Figure 6F and Figure 6G The semiconductor layer 634 can also extend into the memory layer 617.

[0223] refer to Figure 7A and Figure 7B , Figure 7A A partial top view of the die structure provided in this application embodiment is shown in Figure 1. Figure 7B This is a second partial top view of the die structure provided in an embodiment of this application. It should be noted that... Figure 7A Let's take a die, which consists of eight memory planes, as an example for explanation. Figure 7B Let's take a die, which consists of four memory planes, as an example for illustration. Figure 7A and Figure 7BAs shown in the embodiments of this application, the die includes at least a circuit region (second semiconductor structure) and a memory region (first semiconductor structure). The circuit region is used to form driving circuits, read / write circuits, and control circuits, etc., and the memory region forms a memory array of memory cell strings. The memory region, i.e., the first semiconductor structure, may include one or more memory planes 739, each memory plane 739 may include one or more memory blocks 740, and each memory block 740 may include one or more finger memory regions 741. Typically, in order to increase the capacity of the chip, multiple memory planes are designed in the memory region of the chip, and each memory plane has a substantially the same capacity, that is, it has a substantially the same number of memory cells.

[0224] This application embodiment also provides a storage device, the storage device comprising:

[0225] A first semiconductor structure, the first semiconductor structure including a semiconductor layer, a doped buffer layer and a gate stack structure and a channel structure extending through the gate stack structure, the gate stack structure including alternately stacked interlayer insulating layers and gate layers;

[0226] The semiconductor layer covers the ends of the channel structure and the gate stack structure.

[0227] In some embodiments of this application, the bottoms of the different channel structures are substantially flush.

[0228] In some embodiments of this application, the material of the doped buffer layer includes doped polycrystalline silicon.

[0229] In some embodiments of this application, the storage device further includes:

[0230] A second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure including peripheral circuitry.

[0231] In some embodiments of this application, the storage device further includes:

[0232] The source contact and peripheral contact are located on the semiconductor layer; wherein the peripheral contact is in contact with the end of the peripheral contact element.

[0233] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the channel layer includes a doped channel layer that is in contact with the semiconductor layer.

[0234] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the semiconductor layer includes a portion extending into the bottom of the channel structure and contacting the channel layer; along the radial direction of the channel structure, the width of the portion of the semiconductor layer in contact with the channel layer is greater than the width of the channel structure.

[0235] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the semiconductor layer includes a portion extending into the bottom of the channel structure and contacting the channel layer; along the radial direction of the channel structure, the width of the portion of the semiconductor layer in contact with the channel layer is equal to the width of the channel structure.

[0236] In some embodiments of this application, the channel structure includes a storage film and a channel layer; the semiconductor layer extends into the bottom of the channel structure and contacts the storage film and the channel layer; along the axial direction of the channel structure, the thickness of the portion of the semiconductor layer that contacts the storage film is greater than or equal to the thickness of the portion of the semiconductor layer that contacts the channel layer.

[0237] In some embodiments of this application, the storage film includes a barrier layer, a storage layer, and a tunneling layer in sequence along the radially inward direction of the channel structure; the thickness of the portion of the semiconductor layer in contact with the barrier layer is the same as or different from the thickness of the portion of the semiconductor layer in contact with the contact layer.

[0238] In some embodiments of this application, the storage film includes, in a radially inward direction along the channel structure, a barrier layer, a storage layer, and a tunneling layer in sequence; the storage layer extends into the semiconductor layer, or the semiconductor layer extends into the storage layer.

[0239] In some embodiments of this application, the first semiconductor structure includes at least one memory plane, each memory plane includes at least one memory block, and each memory block includes at least one pointer memory region.

[0240] This application provides a memory device and a method for manufacturing the same. The method includes: providing a substrate structure, the substrate structure including a first substrate and a first oxide layer, a first buffer layer, and a stacked structure located on the first substrate, the stacked structure including alternately stacked interlayer insulating layers and gate sacrificial layers; forming a via structure that sequentially penetrates the stacked structure and the first buffer layer; and epitaxially forming a first epitaxial layer on the exposed side of the first buffer layer within the via structure. In the method for manufacturing the memory device provided in this application, after etching to form the via structure, the first epitaxial layer is epitaxially formed on the exposed side of the first buffer layer within the via structure, and the first epitaxial layer forms the bottom of the via structure. This ensures that the bottoms of different via structures are substantially flush in the direction perpendicular to the first substrate without needing to control the flushness of the bottom of the via structure through an etching process. This not only greatly reduces the difficulty of the etching process but also improves the consistency of the via structure.

[0241] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0242] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for manufacturing a storage device, characterized in that, The method includes: A substrate structure is provided, the substrate structure comprising: a first substrate and a first oxide layer, a first buffer layer and a stacked structure located on the first substrate, the stacked structure comprising alternately stacked interlayer insulating layers and gate sacrificial layers; A plurality of pore structures are formed that sequentially penetrate the stacked structure and the first buffer layer; Within the plurality of hole structures, a first epitaxial layer is formed on the exposed side of the first buffer layer. Remove the first substrate and the first epitaxial layer to expose the surface of the first oxide layer and the ends of the plurality of hole structures.

2. The manufacturing method as described in claim 1, characterized in that, The formation of the pore structure that sequentially penetrates the stacked structure and the first buffer layer includes: Forming a lower layered structure; A first lower hole structure is formed, which sequentially penetrates the lower stacked structure, the first buffer layer, and the first oxide layer and extends into the first substrate; a support layer is formed within the first lower hole structure. An upper stacked structure is formed on the lower stacked structure; A first upper hole structure is formed that penetrates the upper stacked structure; wherein the first upper hole structure is connected to the first lower hole structure.

3. The manufacturing method as described in claim 2, characterized in that, The method further includes: The support layer is etched to form a second lower hole structure that exposes the side of the first buffer layer. The second lower hole structure communicates with the first upper hole structure to form the hole structure.

4. The manufacturing method as described in claim 3, characterized in that, The first epitaxial layer is formed on the exposed side of the first buffer layer within the second lower hole structure.

5. The manufacturing method as described in claim 2, characterized in that, The method further includes: The support layer is etched to form a third lower hole structure that exposes the side of the first oxide layer, the third lower hole structure being connected to the first upper hole structure to form the hole structure.

6. The manufacturing method as described in claim 5, characterized in that, The first epitaxial layer is formed on the exposed side of the first buffer layer within the third lower hole structure.

7. The manufacturing method as described in claim 2, characterized in that, The method further includes: The support layer is etched to form a fourth lower hole structure that exposes the side surface of the first substrate. The fourth lower hole structure communicates with the first upper hole structure to form the hole structure.

8. The manufacturing method as described in claim 7, characterized in that, A second epitaxial layer is formed on the exposed side of the first substrate within the fourth lower hole structure.

9. The manufacturing method as described in claim 1, characterized in that, The hole structure includes channel holes, virtual channel holes, and / or grid line slots.

10. The manufacturing method as described in claim 1, characterized in that, After the first epitaxial layer is formed in a direction perpendicular to the first substrate, the bottoms of the different hole structures are substantially flush.

11. The manufacturing method as described in claim 1, characterized in that, The formation of the pore structure that sequentially penetrates the stacked structure and the first buffer layer includes: A pore structure is formed that sequentially penetrates the stacked structure, the first buffer layer, and the first oxide layer, and extends into the first substrate.

12. The manufacturing method as described in claim 1, characterized in that, The substrate structure further includes: a second oxide layer and a second buffer layer located sequentially between the first substrate and the first oxide layer; A hole structure is formed that sequentially penetrates the stacked structure and the first buffer layer.

13. The manufacturing method as described in claim 12, characterized in that, The formation of the pore structure that sequentially penetrates the stacked structure and the first buffer layer includes: Forming a lower layered structure; A fifth lower hole structure is formed, which sequentially penetrates the lower stacked structure, the first buffer layer, and the first oxide layer and extends into the second buffer layer; a support layer is formed within the fifth lower hole structure. An upper stacked structure is formed on the lower stacked structure; A second upper hole structure is formed that penetrates the upper stacked structure; wherein the second upper hole structure is connected to the fifth lower hole structure.

14. The manufacturing method as described in claim 13, characterized in that, The method further includes: The support layer is etched to form a sixth lower hole structure that exposes the side of the first buffer layer. The sixth lower hole structure communicates with the second upper hole structure to form the hole structure.

15. The manufacturing method as described in claim 14, characterized in that, The first epitaxial layer is formed on the exposed side of the first buffer layer within the sixth lower hole structure.

16. The manufacturing method as described in claim 13, characterized in that, The method further includes: The support layer is etched to form a seventh lower hole structure that exposes the side of the first oxide layer, the seventh lower hole structure being connected to the second upper hole structure to form the hole structure.

17. The manufacturing method as described in claim 16, characterized in that, The first epitaxial layer is formed on the exposed side of the first buffer layer within the seventh lower hole structure.

18. The manufacturing method as described in claim 13, characterized in that, The method further includes: The support layer is etched to form an eighth lower hole structure that exposes the side of the second buffer layer. The eighth lower hole structure communicates with the second upper hole structure to form the hole structure.

19. The manufacturing method as described in claim 18, characterized in that, A third epitaxial layer is formed on the exposed side of the second buffer layer within the eighth lower hole structure.

20. The manufacturing method according to claim 1, characterized in that, The material of the first buffer layer includes polycrystalline silicon.

21. The manufacturing method as described in claim 1, characterized in that, When the hole structure is a channel hole, the method further includes: A storage film and a channel layer are sequentially formed within the pore structure to form the channel structure.

22. The manufacturing method as described in claim 21, characterized in that, The method further includes: A first bonding layer is formed on the stacked structure; A second substrate is provided, on which a peripheral circuit is formed and a second bonding layer is formed on the peripheral circuit; The first bonding layer and the second bonding layer are bonded together.

23. The manufacturing method as described in claim 22, characterized in that, The method further includes: Remove the first substrate and the first epitaxial layer to expose the first oxide layer and the end of the channel structure; Remove the storage membrane at the end of the channel structure to expose the channel layer.

24. The manufacturing method as described in claim 23, characterized in that, The method further includes: Remove the first oxide layer to expose the first buffer layer; Ion implantation is performed on the exposed channel layer to form a doped channel layer.

25. The manufacturing method as described in claim 24, characterized in that, The method further includes: A semiconductor layer is formed, the semiconductor layer covering the first buffer layer and the doped channel layer; Peripheral contacts and source contacts are formed on the semiconductor layer; wherein the peripheral contacts are in contact with the ends of the peripheral contacts.

26. A storage device, characterized in that, The storage device is manufactured by the manufacturing method as described in any one of claims 1 to 25; the storage device comprises: A first semiconductor structure includes a semiconductor layer, a doped buffer layer, a gate stack structure, and a channel structure extending through the gate stack structure. The gate stack structure includes alternately stacked interlayer insulating layers and gate layers. The channel structure is located in a via structure. The channel structure includes a storage film and a channel layer. The channel layer covers the bottom of the via structure. In different via structures, the portion of the channel layer covering the bottom of the via structure is substantially flush with the bottom of the via structure. The semiconductor layer covers the end of the channel structure and the gate stack structure. The semiconductor layer includes a first portion covering the surface of the doped buffer layer away from the gate stack structure, a second portion extending from the opening of the doped buffer layer into the bottom of the channel structure and covering a portion of the bottom of the via structure that contacts the channel layer, and a third portion extending from the opening of the doped buffer layer into the bottom of the channel structure and contacting the storage film. Along the axial direction of the channel structure, the thickness of the first portion is less than the thickness of the second portion, and the thickness of the second portion is less than or equal to the thickness of the third portion.

27. The storage device as claimed in claim 26, characterized in that, The bottoms of the different channel structures are basically flush.

28. The storage device as claimed in claim 26, characterized in that, The material of the doped buffer layer includes doped polycrystalline silicon.

29. The storage device as claimed in claim 26, characterized in that, The storage device further includes: A second semiconductor structure bonded to the first semiconductor structure, the second semiconductor structure including peripheral circuitry.

30. The storage device as claimed in claim 26, characterized in that, The storage device further includes: The source contact and peripheral contact are located on the semiconductor layer; wherein the peripheral contact is in contact with the end of the peripheral contact element.

31. The storage device as claimed in claim 26, characterized in that, The channel structure includes a storage film and a channel layer; the channel layer includes a doped channel layer, which is in contact with the semiconductor layer.

32. The storage device as claimed in claim 26, characterized in that, Along the radial direction of the channel structure, the width of the portion of the semiconductor layer that contacts the channel layer is greater than the width of the channel structure.

33. The storage device as claimed in claim 26, characterized in that, Along the radial direction of the channel structure, the width of the portion of the semiconductor layer that contacts the channel layer is equal to the width of the channel structure.

34. The storage device as claimed in claim 26, characterized in that, The storage film includes a barrier layer, a storage layer, and a tunneling layer in sequence along the radial direction inward from the channel structure; the thickness of the portion of the semiconductor layer in contact with the barrier layer and the thickness of the portion of the semiconductor layer in contact with the tunneling layer may be the same or different.

35. The storage device as claimed in claim 26, characterized in that, The storage film includes, in a radially inward direction along the channel structure, a barrier layer, a storage layer, and a tunneling layer; the storage layer extends into the semiconductor layer, or the semiconductor layer extends into the storage layer.

36. The storage device as claimed in claim 26, characterized in that, The first semiconductor structure includes at least one memory plane, each memory plane includes at least one memory block, and each memory block includes at least one pointer memory area.

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