Method for manufacturing semiconductor device, semiconductor device, and three-dimensional memory

Abstract

The application provides a semiconductor device manufacturing method, a semiconductor device and a three-dimensional memory. The method comprises the following steps: sequentially forming a stacked structure and a first dielectric layer on a substrate, the stacked structure comprising a body structure and an etching stop portion in the body structure, the body structure comprising first insulating layers and sacrificial layers which are alternately stacked in a direction away from the substrate; removing part of the first dielectric layer, part of the body structure and the etching stop portion to form a first opening in the first dielectric layer and in the stacked structure; forming a filling portion in the first opening to obtain a storage array structure; sequentially removing the substrate of the storage array structure and part of the stacked structure to form a second opening in the stacked structure, the second opening penetrating to the filling portion; removing the filling portion to obtain a gate line slit. The application better alleviates the problem that the etching of the GL is difficult when the number of layers of the 3D NAND is large.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory, and a memory system. Background Technology

[0002] As the number of layers in 3D NAND continues to increase, controlling the etching shape of GL (Gate Line) becomes increasingly difficult. The higher the number of layers, the more likely problems such as GL sharpness, mouse bite, GL shift, and small bottom CD (small bottom size) will occur. Furthermore, the higher the number of layers, the faster the SiN at the bottom is removed, and the slower the SiN at the top is removed. The greater the etching load effect caused by the inconsistent removal speed between the top and bottom layers.

[0003] Therefore, there is an urgent need for a method to solve the problem of the difficulty in forming GL when there are many layers in 3D NAND in the existing technology.

[0004] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] The main objective of this application is to provide a method for fabricating a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system, in order to solve the problem that it is difficult to form GL when 3D NAND has a large number of layers in the prior art.

[0006] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: sequentially forming a stacked structure and a first dielectric layer on a substrate, the stacked structure including a body structure and an etch stop portion located in the body structure, the body structure including alternatingly stacked first insulating layers and sacrificial layers; removing a portion of the first dielectric layer, a portion of the body structure, and the etch stop portion to form a first opening located in the first dielectric layer and the stacked structure; forming a fill portion in the first opening to obtain a memory array structure; sequentially removing the substrate of the memory array structure and a portion of the stacked structure to form a second opening in the stacked structure, the second opening extending to the fill portion; and removing the fill portion to obtain a gate line slit.

[0007] Optionally, removing a portion of the first dielectric layer, a portion of the body structure, and the etch stop portion to form a first opening located in the first dielectric layer and the stacked structure includes: removing a portion of the first dielectric layer and a portion of the body structure to expose the etch stop portion; removing the etch stop portion to form a first groove; and removing portions of each of the sacrificial layers on the sidewall of the first groove to form a plurality of second grooves on the sidewall of the first groove to obtain the first opening.

[0008] Optionally, after forming a filling portion in the first opening to obtain a memory array structure, and before sequentially removing the substrate of the memory array structure and a portion of the stacked structure, and before forming a second opening in the stacked structure, the method further includes: providing a CMOS structure; and bonding the CMOS structure and the memory array structure to obtain a bonded structure.

[0009] Optionally, sequentially removing the substrate of the memory array structure and a portion of the stacked structure to form a second opening in the stacked structure includes: removing the substrate of the bonding structure to expose the stacked structure; removing the partially exposed stacked structure to form a third groove in the stacked structure, the third groove exposing the filler portion; and removing portions of each of the sacrificial layers on the sidewalls of the third groove to form a plurality of fourth grooves on the sidewalls of the third groove, thereby obtaining the second opening.

[0010] Optionally, after removing the filler portion to obtain the gate line slit, the method further includes: removing each of the sacrificial layers through the gate line slit to obtain a plurality of fifth grooves; filling each of the fifth grooves with metal material to form a plurality of metal layers, the remaining gate line slit forming a third opening; forming a second insulating layer on the surface of the stacked structure away from the first dielectric layer and within the third opening; forming a second dielectric layer within the remaining third opening to obtain a gate line.

[0011] Optionally, a stacked structure and a first dielectric layer are sequentially formed on a substrate, comprising: providing a substrate; forming an alternately stacked first insulating layer and a sacrificial layer on the surface of the substrate; removing a portion of the sacrificial layer and a portion of the first insulating layer to form a sixth groove located in the sacrificial layer and the first insulating layer; filling the sixth groove with sacrificial material to form the etching stop portion, thereby obtaining a preliminary stacked structure; forming an alternately stacked first insulating layer and a sacrificial layer on the surface of the preliminary stacked structure away from the substrate to form the stacked structure; and forming the first dielectric layer on the surface of the stacked structure away from the substrate.

[0012] Optionally, after forming the alternating first insulating layer and the sacrificial layer on the surface of the pre-stacked structure away from the substrate, and before forming the first dielectric layer on the surface of the stacked structure away from the substrate, the method further includes: removing a portion of the stacked structure, forming a channel hole in the stacked structure, the channel hole extending to the substrate, the channel hole having a high-K dielectric layer, a charge blocking layer, an electron trapping layer, a tunneling layer, and a channel layer sequentially disposed along the sidewalls away from the channel hole.

[0013] Optionally, one end of the stacked structure has a stepped region. Before the stacked structure and the first dielectric layer are sequentially formed on the substrate, and before removing a portion of the first dielectric layer, a portion of the body structure, and the etch stop portion to form a first opening located in the first dielectric layer and the stacked structure, the method further includes: removing a portion of the first dielectric layer and a portion of the stepped region to form a plurality of virtual channel vias located in the first dielectric layer and the stepped region, and forming a filling portion in the first opening to obtain a memory array structure, including: forming a filling portion in the first opening; removing a portion of the first dielectric layer and a portion of the stepped region to form a plurality of contact holes located in the first dielectric layer and the stepped region on one side of the filling portion to obtain the memory array structure, wherein the contact holes and the virtual channel vias are alternately arranged, and the gate line slit is located on one side of the contact holes.

[0014] Optionally, the material of the etching stop portion includes carbon, and the material of the filling portion includes carbon.

[0015] According to another aspect of the present invention, a semiconductor device is also provided, which is manufactured using any of the semiconductor device manufacturing methods described above.

[0016] According to another aspect of the present invention, a three-dimensional memory is also provided, including the aforementioned semiconductor device.

[0017] According to another aspect of the present invention, a storage system is also provided, including a storage controller and the three-dimensional memory, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0018] Using the technical solution of this application, in the method for fabricating the semiconductor device, firstly, a stacked structure including a body structure and an etch stop portion and a first dielectric layer are sequentially stacked on a substrate; then, a portion of the first dielectric layer, a portion of the body structure and the etch stop portion are removed from the front side of the structure to form a first opening; then, a filling portion is formed in the first opening; subsequently, the substrate and a portion of the stacked structure are removed from the back side of the structure, and a second opening penetrating to the filling portion is formed in the stacked structure; finally, the filling portion is removed through the second opening to obtain a gate line slit. Compared to existing technologies where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as gate line sharpness, mouse bite, gate line shift, and small bottom CD, the method described in this application forms a first opening by etching from the front side and a filling portion within the first opening. Then, it etches from the back side to the filling portion to form a second opening. Finally, it removes the filling portion to obtain the gate line slit. This method simplifies the fabrication process of gate line slits when there are many 3D NAND layers, ensures good morphology of the obtained gate line slits and the gate lines subsequently formed by filling the gate line slits, and effectively alleviates the problem of the difficulty in forming gate lines when there are many 3D NAND layers in existing technologies. This can effectively improve the manufacturing yield of semiconductor devices. Furthermore, the method described in this application forms gate line slits through front-side etching plus back-side etching, which alleviates the etching load effect of SiN when there are more 3D NAND layers in existing technologies, and improves the process stability of semiconductor devices. Attached Figure Description

[0019] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0021] Figures 2 to 14 The diagrams show the structural schematics obtained after each process step of the method for fabricating a semiconductor device according to an embodiment of this application.

[0022] Figure 15 A schematic diagram of an electronic device according to an embodiment of this application is shown.

[0023] The above figures include the following reference numerals:

[0024] 10. Memory array structure; 20. CMOS structure; 18. Memory; 21. Mobile phone; 100. Substrate; 101. First dielectric layer; 102. Etching stop portion; 103. First insulating layer; 104. Sacrificial layer; 105. Metal layer; 200. First opening; 201. Fill portion; 202. Second opening; 203. Gate line slit; 204. First groove; 205. Second groove; 206. Third groove; 207. Fourth groove; 208. Third opening; 209. Second insulating layer; 210. Second dielectric layer; 211. Gate line; 212. Fifth groove; 300. Channel hole; 301. Virtual channel hole; 302. Contact hole; 303. Alignment mark; 400. Step region. Detailed Implementation

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0029] As mentioned in the background section, existing 3D NAND flash memory has a large number of layers, making it difficult to form GL during etch. To solve the above problems, in a typical embodiment of this application, a method for fabricating a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system are provided.

[0030] According to an embodiment of this application, a method for fabricating a semiconductor device is provided.

[0031] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 1 As shown, the method includes the following steps:

[0032] Step S101, as follows Figure 3 As shown, a stacked structure and a first dielectric layer 101 are sequentially formed on a substrate 100. The stacked structure includes a body structure and an etch stop portion 102 located in the body structure. The body structure includes an alternately stacked first insulating layer 103 and a sacrificial layer 104.

[0033] Step S102: Remove a portion of the first dielectric layer 101, a portion of the body structure, and the etching stop portion 102 to form a structure as described above. Figure 5 The first opening 200 is shown in the first dielectric layer 101 and the stacked structure described above;

[0034] Step S103: A filling portion 201 is formed in the first opening 200, resulting in... Figure 7 The storage array structure 10 shown is shown.

[0035] Step S104, as follows Figure 11 As shown, the substrate 100 and part of the stacked structure of the memory array structure 10 are removed in sequence, and a second opening 202 is formed in the stacked structure. The second opening 202 extends through the filling portion 201.

[0036] Step S105, as follows Figure 12 As shown, the gate line slit 203 is obtained by removing the filling portion 201.

[0037] In the above-described method for fabricating a semiconductor device, a stacked structure including a body structure and an etch stop portion, and a first dielectric layer are firstly stacked on a substrate; then, a portion of the first dielectric layer, a portion of the body structure, and the etch stop portion are removed from the front side of the structure to form a first opening; a filling portion is then formed in the first opening; subsequently, the substrate and a portion of the stacked structure are removed from the back side of the structure to form a second opening extending through the filling portion in the stacked structure; finally, the filling portion is removed through the second opening to obtain a gate line slit. Compared to existing technologies where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mouse bite, GL shift, and small bottom CD, the method described in this application forms a first opening by etching from the front side and a filling portion within the first opening. Then, it etches from the back side to the filling portion to form a second opening. Finally, it removes the filling portion to obtain the gate line slit. This method simplifies the fabrication process of gate line slits when there are many 3D NAND layers, and ensures good morphology of the obtained gate line slits and the gate lines subsequently formed by filling the gate line slits. It effectively alleviates the problem of the difficulty in forming GL when there are many 3D NAND layers in existing technologies, and can effectively improve the manufacturing yield of semiconductor devices. Furthermore, the method described in this application forms gate line slits by etching from the front side and the back side, which alleviates the etching load effect of SiN when there are many 3D NAND layers in existing technologies, and improves the process stability of semiconductor devices.

[0038] In one specific embodiment, the central axis of the first opening coincides with the central axis of the second opening, and the central axis is parallel to the thickness direction of the substrate.

[0039] To further alleviate the problem of increased difficulty in forming GL with higher layer counts, according to a specific embodiment of this application, a portion of the aforementioned first dielectric layer, a portion of the aforementioned body structure, and the aforementioned etching stop portion are removed to form a first opening located in the aforementioned first dielectric layer and the aforementioned stacked structure, including: Figure 3 , Figure 4 as well as Figure 5As shown, a portion of the first dielectric layer 101 and a portion of the body structure are removed, exposing the etching stop portion 102. The etching stop portion 102 is then removed to form a first groove 204. A portion of each of the sacrificial layers 104 on the sidewalls of the first groove 204 is removed to form a plurality of second grooves 205 on the sidewalls of the first groove 204, resulting in the first opening 200. By first forming the first groove and then etching away portions of the sacrificial layers on the sidewalls of the first groove, a larger process window for the first opening is ensured, facilitating the subsequent formation of the second openings, thereby further ensuring that the final formation of the GL is less difficult.

[0040] According to another specific embodiment of this application, after forming a filling portion in the first opening to obtain a memory array structure, before sequentially removing the substrate and a portion of the stacked structure of the memory array structure and forming a second opening in the stacked structure, the method further includes: providing a CMOS structure 20; bonding the CMOS structure 20 and the memory array structure 10 to obtain... Figure 8 The bonding structure is shown. Specifically, the memory array structure and the CMOS structure are bonded using a predetermined surface as the bonding interface. The predetermined surface is the surface away from the substrate.

[0041] To further facilitate the subsequent removal of the sacrificial layer, in another specific embodiment of this application, the substrate of the aforementioned memory array structure and a portion of the aforementioned stacked structure are removed sequentially, forming a second opening in the aforementioned stacked structure, including: Figures 9 to 11 As shown, the substrate 100 of the aforementioned bonding structure is removed to expose the aforementioned stacked structure; the partially exposed stacked structure is removed, and a structure as shown is formed in the aforementioned stacked structure. Figure 10 The third groove 206 shown exposes the filling portion 201. A portion of each of the sacrificial layers 104 on the sidewall of the third groove 206 is removed to form a plurality of fourth grooves 207 on the sidewall of the third groove 206, resulting in the second opening 202. It is understood that in some specific embodiments, the material of the filling portion 201 is different from the material in the body structure, and the filling portion 201 can serve as an etching stop layer when the third groove 206 is formed by etching.

[0042] In some specific embodiments, after removing the filling portion to obtain the gate line slit, the method further includes: as follows: Figure 12 As shown, by removing each of the aforementioned sacrificial layers through the gate line slits, a plurality of fifth grooves 212 are obtained; as Figure 13As shown, metal material is filled into each of the aforementioned fifth grooves 212 to form a plurality of metal layers 105, and the remaining gate line slits form a third opening 208; a second insulating layer 209 is formed on the surface of the aforementioned stacked structure away from the aforementioned first dielectric layer 101 and within the aforementioned third opening 208; a second dielectric layer 210 is formed within the remaining aforementioned third opening 208, resulting in the following... Figure 14 Gate line 211 is shown.

[0043] In one specific embodiment, metal material is filled into each of the aforementioned fifth grooves to form multiple metal layers, and the remaining gate line slits form a third opening, including: sequentially forming a titanium nitride layer and a tungsten layer in each of the fifth grooves and the gate line slits to form a metal layer in the fifth grooves; removing the metal material on the sidewalls of the gate line slits to expose the first insulating layer on the sidewalls of the gate line slits, thereby obtaining the third opening.

[0044] According to another specific embodiment of this application, a stacked structure and a first dielectric layer are sequentially formed on a substrate, including: as shown in the figure. Figure 3 As shown, a substrate 100 is provided; alternating layers of the first insulating layer 103 and the sacrificial layer 104 are formed on the surface of the substrate 100; a portion of the sacrificial layer 104 and a portion of the first insulating layer 103 are removed to form a sixth groove located in the sacrificial layer 104 and the first insulating layer 103; the sixth groove is filled with sacrificial material to form the etching stop portion 102, thereby obtaining a pre-stacked structure; alternating layers of the first insulating layer 103 and the sacrificial layer 104 are formed on the surface of the pre-stacked structure away from the substrate 100 to form the stacked structure; and a first dielectric layer 101 is formed on the surface of the stacked structure away from the substrate 100.

[0045] It should be noted that each step in the above-described substrate formation embodiments can be implemented using feasible methods in the prior art. The substrate in the above-described substrate can be selected according to the actual needs of the device, and may include a silicon substrate, a germanium substrate, a silicon-germanium composite, an SOI (Silicon on Insulator) substrate, or a GOI (Germanium on Insulator) substrate. In other embodiments, the substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, and may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as SGOI (Sorganium on Silicon). Of course, it may also be other substrates feasible in the prior art.

[0046] In another specific embodiment of this application, a substrate is provided, comprising: providing a pre-substrate; removing a portion of the pre-substrate to form a seventh groove located in the pre-substrate; and filling the seventh groove with a predetermined material to form a... Figure 2 The alignment mark 303 shown is aligned with the central axis of the second opening, and this line is parallel to the thickness direction of the substrate, thus obtaining the substrate. The substrate of the memory array structure and a portion of the stacked structure are sequentially removed, including: as shown... Figures 9 to 11 As shown, the pre-substrate of the aforementioned memory array structure is removed, exposing the alignment marks; the alignment marks and a portion of the aforementioned stacked structure are then removed sequentially to form the second opening. This further simplifies the fabrication process of the second opening.

[0047] Specifically, the sixth groove can pass through one insulating dielectric layer and one sacrificial layer, or it can pass through multiple insulating dielectric layers and multiple sacrificial layers. In order to ensure that the formed first groove can stop more accurately at the position of the etching stop portion, and thus further ensure process stability, those skilled in the art can set the sixth groove to pass through multiple insulating dielectric layers and multiple sacrificial layers.

[0048] According to another specific embodiment of this application, after forming the alternating stacked first insulating layer and the sacrificial layer on the surface of the pre-stacked structure away from the substrate, and before forming the first dielectric layer on the surface of the stacked structure away from the substrate, the method further includes: Figure 2 As shown, a portion of the aforementioned stacked structure is removed, forming a channel hole 300 within the stacked structure. The channel hole 300 extends into the substrate 100. Within the channel hole 300, a high-k dielectric layer, a charge-blocking layer, an electron-trapping layer, a tunneling layer, and a channel layer are sequentially disposed along the sidewalls away from the channel hole. This method forms the channel hole including the high-k dielectric layer through front-side etching, avoiding the impact of high-k dielectric layer formation at high temperatures on the bonding structure and further ensuring better stability of the bonding structure.

[0049] The charge blocking layer, electron trapping layer, tunneling layer and channel layer constitute an ONOP stacked structure, namely an oxide-nitride-oxide-polysilicon stacked structure.

[0050] In practical applications, those skilled in the art can choose any feasible method from the prior art to form the aforementioned channel holes. In one specific embodiment, after forming the alternatingly stacked first insulating layer and the sacrificial layer on the surface of the substrate, before removing a portion of the sacrificial layer and a portion of the first insulating layer to form a sixth groove located in the sacrificial layer and the first insulating layer, the method further includes: removing a portion of the sacrificial layer and a portion of the first insulating layer to form a plurality of first channel hole openings located in the sacrificial layer and the first insulating layer and penetrating into the substrate, wherein the sixth groove is located between two adjacent first channel hole openings; filling each of the first channel hole openings with a filler material to form a pre-channel hole; and forming the alternatingly stacked first insulating layer and the sacrificial layer on the exposed surface of the pre-channel hole and the exposed surface of the sacrificial layer. Removing a portion of the aforementioned stacked structure and forming a channel hole in the aforementioned stacked structure includes: etching the aforementioned stacked structure to form a second channel hole opening extending to the aforementioned pre-prepared channel hole; removing the aforementioned filler material through the aforementioned second channel hole opening to obtain a channel hole opening; and sequentially forming the aforementioned high-K dielectric layer, the aforementioned charge blocking layer, the aforementioned electron trapping layer, the aforementioned tunneling layer, and the aforementioned channel layer in the aforementioned channel hole opening to obtain the aforementioned channel hole.

[0051] In another specific embodiment of this application, such as Figure 3 As shown, one end of the aforementioned stacked structure has a stepped region 400. A stacked structure and a first dielectric layer are sequentially formed on the substrate. A portion of the first dielectric layer, a portion of the body structure, and the etching stop portion are removed to form a first opening located in the first dielectric layer and the stacked structure. The method further includes: Figure 5 As shown, by removing a portion of the first dielectric layer 101 and a portion of the stepped region, a plurality of virtual channel holes 301 are formed in the first dielectric layer 101 and the stepped region. A filling portion is formed in the first opening to obtain a memory array structure, including: Figure 5 and Figure 6 As shown, a filling portion 201 is formed in the first opening 200; as Figure 7 As shown, a portion of the first dielectric layer 101 and a portion of the stepped region are removed to form a plurality of contact holes 302 located in the first dielectric layer 101 and the stepped region on one side of the filling portion 201, thereby obtaining the aforementioned memory array structure, as shown. Figure 12 As shown, the contact hole 302 and the virtual channel hole 301 are alternately arranged, and the gate line slit 203 is located on one side of the contact hole 302. The virtual channel hole provides support for the stepped area, avoiding problems such as tilting of the stepped area during the formation of the contact hole.

[0052] In the above embodiments, in order to ensure that the contact hole stops on the corresponding step in the step area more easily, the thickness of the sacrificial layer is greater than the thickness of the first insulating dielectric layer.

[0053] The materials of the aforementioned structural layers can be any suitable materials available in the prior art, and those skilled in the art can flexibly configure them according to actual conditions. In practical applications, the material of the etching stop portion includes carbon, the material of the filling portion includes carbon, the metal material includes titanium nitride and tungsten, the material of the second insulating layer includes silicon oxide, the material of the first dielectric layer includes silicon oxide, the material of the second dielectric layer includes polycrystalline silicon, the material of the first insulating layer includes silicon oxide, and the material of the sacrificial layer includes silicon nitride. In one embodiment of this application, the material of the etching stop portion is carbon, the material of the filling portion is carbon, the metal material is titanium nitride and tungsten, the material of the second insulating layer is silicon oxide, the material of the first dielectric layer is silicon oxide, the material of the second dielectric layer is polycrystalline silicon, the material of the first insulating layer is silicon oxide, and the material of the sacrificial layer is silicon nitride.

[0054] According to another specific embodiment of this application, removing the substrate of the bonding structure to expose the stacked structure includes: removing a portion of the substrate to expose the alignment mark, the stacked structure, a portion of the channel hole, and a portion of the virtual channel hole, and removing the remaining substrate.

[0055] After removing the substrate of the aforementioned bonding structure to expose the aforementioned stacked structure, and before removing the partially exposed stacked structure and forming a third groove in the stacked structure, the method further includes: removing the high-k dielectric layer exposed by the aforementioned channel hole to expose a portion of the charge blocking layer; removing the exposed charge blocking layer to expose a portion of the aforementioned electron trapping layer; removing the exposed electron trapping layer to expose a portion of the aforementioned tunneling layer; removing the exposed tunneling layer to expose a portion of the aforementioned channel layer; depositing polysilicon material on the surfaces of the exposed channel layer, the exposed stacked structure, and the exposed virtual channel hole; planarizing the deposited polysilicon material to obtain a second substrate; etching the second substrate to expose the aforementioned alignment marks, wherein the distance between the exposed surface of the alignment marks and the aforementioned CMOS structure is greater than the remaining The distance between the exposed surface of the second substrate and the CMOS structure, i.e., the exposed surface of the alignment mark protrudes beyond the exposed surface of the remaining second substrate; a hard mask layer and a first protective layer are sequentially formed on the exposed alignment mark and the remaining second substrate. The material of the first protective layer can be silicon oxynitride. Since the exposed surface of the alignment mark protrudes beyond the exposed surface of the remaining second substrate, after the hard mask layer and the first protective layer are formed, the hard mask layer and the first protective layer on the alignment mark also protrude beyond the hard mask layer and the first protective layer on the remaining second substrate; the first protective layer and the hard mask layer are planarized to remove the protruding portion, thus exposing part of the hard mask layer; a second protective layer is deposited on the planarized hard mask layer to obtain an intermediate structure. The material of the second protective layer can also be silicon oxynitride.

[0056] It should be noted that the material filling the aforementioned channel holes is not limited to the aforementioned high-k dielectric layer, charge-blocking layer, electron-trapping layer, tunneling layer, and channel layer. The material filling the channel holes may also include only the aforementioned charge-blocking layer, electron-trapping layer, tunneling layer, and channel layer. To further ensure better structural stability of the semiconductor device, the material filling the channel holes may also include an insulating material. This insulating material is located on the surface of the channel layer away from the tunneling layer, and it completely fills the channel holes to provide support. When the aforementioned high-k dielectric layer is absent from the channel holes, after removing a portion of the substrate, the exposed portion of the charge-blocking layer is simply a portion of the channel hole. Subsequently, only the exposed charge-blocking layer, the exposed electron-trapping layer, and the exposed tunneling layer need to be removed sequentially.

[0057] The process of removing a portion of the exposed stacked structure and forming a third groove in the stacked structure includes: performing photolithography on the intermediate structure to sequentially remove a portion of the second protective layer, a portion of the hard mask layer, the alignment mark, and a portion of the stacked structure to form the third groove.

[0058] Compared to the fabrication process of forming gate lines on the front side and then removing most of the F (fluorine) ions from the tungsten in the gate lines through a high-temperature degassing process, which can cause wafer deformation and affect the subsequent bonding alignment between the array wafer and the CMOS wafer, the method described in this application forms the gate lines after bonding, i.e., the high-temperature degassing process is performed after bonding. Since the structure is already bonded at this point, the high temperature will not affect the bonding effect. In addition, compared to forming gate lines on the front side, which involves other high-temperature processes after gate line formation, causing residual F ions in the tungsten in the gate lines to move erratically, thus damaging the metal material and affecting device performance, the method described in this application forms the gate line slits and gate lines after bonding. That is, the high-temperature processes are basically completed before the gate line slits are formed, thus avoiding the influence of these high-temperature processes on the tungsten material filled in the gate lines.

[0059] These structural layers can be formed via one or more of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), and / or other known crystal growth processes.

[0060] According to another typical embodiment of this application, a semiconductor device is also provided, which is manufactured using any of the above-described semiconductor device manufacturing methods.

[0061] The aforementioned semiconductor devices are fabricated using any of the methods described above. Compared to existing technologies where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mousebite, GL shift, and small bottom CD, the aforementioned method forms a first opening through front-side etching and a filling portion within the first opening. Then, it etches from the back side to the filling portion to form a second opening, and finally removes the filling portion to obtain the gate line slit. This ensures that the fabrication process of the gate line slit is simpler when there are many 3D NAND layers, and ensures that the obtained gate line slit and the gate lines subsequently formed by filling the gate line slit have good morphology. This effectively alleviates the problem of the difficulty in forming GL when there are many 3D NAND layers in existing technologies, and can effectively improve the fabrication yield of semiconductor devices. Furthermore, the method of this application forms the gate line slit through front-side etching plus back-side etching, which alleviates the etching load effect of SiN when there are many 3D NAND layers in existing technologies, and improves the process stability of semiconductor devices.

[0062] According to another typical embodiment of this application, a three-dimensional memory including the semiconductor device described above is also provided.

[0063] The aforementioned three-dimensional memory, including the aforementioned semiconductor device, is fabricated using any of the methods described above. Compared to existing technologies where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mouse bite, GL shift, and small bottom CD, the aforementioned method ensures a simpler fabrication process for gate line slits when there are many 3D NAND layers. It also ensures better morphology of the obtained gate line slits and the gate lines subsequently formed by filling these slits. This effectively alleviates the problem of the difficulty in forming GL when there are many 3D NAND layers in existing technologies, and can effectively improve the fabrication yield of semiconductor devices. Furthermore, the method of this application forms gate line slits through front-side etching plus back-side etching, which alleviates the etching load effect of SiN when there are more 3D NAND layers in existing technologies, improves the process stability of semiconductor devices, and thus ensures better performance of the three-dimensional memory.

[0064] According to another typical embodiment of this application, a storage system is also provided, including a storage controller and the aforementioned three-dimensional memory, wherein the three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0065] The aforementioned storage system includes a storage controller and a three-dimensional memory. The three-dimensional memory includes the aforementioned semiconductor device, which is fabricated using any of the methods described above. Compared to existing technologies where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mousebite, GL shift, and small bottom CD, the aforementioned method ensures a simpler fabrication process for gate line slits when there are many 3D NAND layers. It also ensures better morphology of the obtained gate line slits and the gate lines subsequently filled by these slits. This effectively alleviates the problem of the difficulty in forming GL when there are many 3D NAND layers in existing technologies, and can effectively improve the fabrication yield of semiconductor devices. Furthermore, the method of this application forms gate line slits through front-side etching and back-side etching, alleviating the etching load effect of SiN when there are more 3D NAND layers in existing technologies, improving the process stability of semiconductor devices, and thus ensuring better performance of the storage system.

[0066] This application also provides an electronic device, including the above-described three-dimensional memory.

[0067] The aforementioned electronic device includes the aforementioned three-dimensional memory, which includes the aforementioned semiconductor device. This semiconductor device is fabricated using any of the aforementioned methods. Compared to the prior art where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mouse bite, GL shift, and small bottom CD, the aforementioned method ensures a simpler fabrication process for gate line slits when there are many 3D NAND layers. It also ensures better morphology of the obtained gate line slits and the gate lines subsequently filled by these slits. This effectively alleviates the problem of the difficulty in forming GLs when there are many 3D NAND layers in the prior art, and can effectively improve the fabrication yield of semiconductor devices. Furthermore, the method of this application forms gate line slits through front-side etching plus back-side etching, alleviating the etching load effect of SiN when there are more 3D NAND layers in the prior art, improving the process stability of semiconductor devices, and thus ensuring better performance of electronic devices.

[0068] In the embodiments of this application, the aforementioned electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, and power bank. In this embodiment, the memory employing the semiconductor structure of this application can be used in any electronic device because the semiconductor structure of this application experiences breakdown later, thus further improving the performance of electronic devices using this semiconductor structure. Figure 15 A schematic diagram of the structure of a mobile phone according to an embodiment of this application is shown, such as... Figure 15 As shown, the mobile phone 21 includes a memory 18 employing the semiconductor structure of this application.

[0069] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0070] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units described above can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0071] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0072] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0073] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0074] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0075] 1) In the semiconductor device fabrication method described above in this application, a stacked structure including a body structure and an etch stop portion and a first dielectric layer are firstly stacked on a substrate; then, a portion of the first dielectric layer, a portion of the body structure and the etch stop portion are removed from the front side of the structure to form a first opening; then, a filling portion is formed in the first opening; then, the substrate and a portion of the stacked structure are removed from the back side of the structure to form a second opening penetrating to the filling portion in the stacked structure; finally, the filling portion is removed through the second opening to obtain a gate line slit. Compared to existing technologies where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as gate line sharpness, mouse bite, gate line shift, and small bottom CD, the method described in this application forms a first opening by etching from the front side and a filling portion within the first opening. Then, it etches from the back side to the filling portion to form a second opening. Finally, it removes the filling portion to obtain the gate line slit. This method simplifies the fabrication process of gate line slits when there are many 3D NAND layers, ensures good morphology of the obtained gate line slits and the gate lines subsequently formed by filling the gate line slits, and effectively alleviates the difficulty of forming gate lines (GLs) when there are many 3D NAND layers in existing technologies. This significantly improves the manufacturing yield of semiconductor devices. Furthermore, the method of this application forms gate line slits through front-side etching followed by back-side etching, mitigating the etching load effect of SiN when there are many 3D NAND layers in existing technologies, and improving the process stability of semiconductor devices.

[0076] 2) The semiconductor device described in this application is fabricated using any of the methods described above. Compared to the prior art where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mouse bite, GL shift, and small bottom CD, the above method forms a first opening by etching from the front side and a filling portion within the first opening. Then, it etches from the back side to the filling portion to form a second opening. Finally, it removes the filling portion to obtain the gate line slit. This ensures that the fabrication process of the gate line slit is simpler when there are many 3D NAND layers, and ensures that the obtained gate line slit and the gate lines obtained by filling the gate line slit have good morphology. This effectively alleviates the problem of the difficulty in forming GL when there are many 3D NAND layers in the prior art, and can effectively improve the fabrication yield of semiconductor devices. Furthermore, the above method of this application forms the gate line slit by etching from the front side and the back side, which alleviates the etching load effect of SiN when there are more 3D NAND layers in the prior art, and improves the process stability of semiconductor devices.

[0077] 3) The three-dimensional memory described in this application includes the aforementioned semiconductor device, which is fabricated using any of the methods described above. Compared to the prior art where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mouse bite, GL shift, and small bottom CD, the above method ensures that the fabrication process of gate line slits is simpler when there are many 3D NAND layers. It also ensures that the obtained gate line slits and the gate lines obtained by filling the gate line slits have better morphology, effectively alleviating the problem of the difficulty in forming GL when there are many 3D NAND layers in the prior art, and effectively improving the fabrication yield of semiconductor devices. Furthermore, the above method of this application forms gate line slits through front-side etching and back-side etching, which alleviates the etching load effect of SiN when there are more 3D NAND layers in the prior art, improves the process stability of semiconductor devices, and thus ensures better performance of the three-dimensional memory.

[0078] 4) The memory system described in this application includes a memory controller and a three-dimensional memory. The three-dimensional memory includes the semiconductor device described above, which is fabricated using any of the methods described above. Compared to the prior art where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, problems such as GL sharpness, mouse bite, GL shift, and small bottom CD are prone to occur. The above method ensures that the fabrication process of gate line slits is simpler when there are many 3D NAND layers, and ensures that the obtained gate line slits and the gate lines obtained by filling the gate line slits have better morphology. It effectively alleviates the problem of the difficulty in forming GL when there are many 3D NAND layers in the prior art, and can effectively improve the fabrication yield of semiconductor devices. Furthermore, the above method of this application forms gate line slits by etching from the front side and the back side, which alleviates the etching load effect of SiN when there are more 3D NAND layers in the prior art, improves the process stability of semiconductor devices, and thus ensures better performance of the memory system.

[0079] 5) The electronic device described in this application includes the aforementioned three-dimensional memory, which includes the aforementioned semiconductor device. This semiconductor device is fabricated using any of the aforementioned methods. Compared to the prior art where gate line slits are etched from the front side to form gate lines when there are many 3D NAND layers, which easily leads to problems such as GL sharpness, mouse bite, GL shift, and small bottom CD, the aforementioned method ensures a simpler fabrication process for gate line slits when there are many 3D NAND layers. It also ensures better morphology of the obtained gate line slits and the gate lines subsequently filled by these slits. This effectively alleviates the problem of the difficulty in forming GLs when there are many 3D NAND layers in the prior art, and can effectively improve the fabrication yield of semiconductor devices. Furthermore, the aforementioned method of this application forms gate line slits through front-side etching plus back-side etching, alleviating the etching load effect of SiN when there are more 3D NAND layers in the prior art, improving the process stability of semiconductor devices, and thus ensuring better performance of electronic devices.

[0080] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A stacked structure and a first dielectric layer are sequentially formed on a substrate. The stacked structure includes a body structure and an etch stop portion located in the body structure. The body structure includes an alternately stacked first insulating layer and a sacrificial layer. A portion of the first dielectric layer, a portion of the body structure, and the etching stop portion are removed to form a first opening located in the first dielectric layer and the stacked structure, wherein the first opening includes a first groove and a plurality of second grooves formed by removing portions of each of the sacrificial layers of the first groove sidewalls; A filling portion is formed in the first opening to obtain a storage array structure; The substrate and a portion of the stacked structure of the memory array structure are removed sequentially, forming a second opening in the stacked structure. The second opening extends through the filling portion, wherein the second opening includes a third groove and a plurality of fourth grooves formed by removing portions of each of the sacrificial layers of the third groove sidewalls. Remove the filling portion to obtain the gate line slit.

2. The method according to claim 1, characterized in that, Removing a portion of the first dielectric layer, a portion of the body structure, and the etching stop portion to form a first opening located in the first dielectric layer and the stacked structure includes: Remove a portion of the first dielectric layer and a portion of the body structure to expose the etching stop portion; Remove the etching stop portion to form the first groove; A portion of each of the sacrificial layers on the sidewall of the first groove is removed to form a plurality of second grooves on the sidewall of the first groove, thereby obtaining the first opening.

3. The method according to claim 1, characterized in that, After forming a filling portion in the first opening to obtain a memory array structure, and before sequentially removing the substrate and a portion of the stacked structure of the memory array structure, and before forming a second opening in the stacked structure, the method further includes: Provides CMOS structure; The CMOS structure and the memory array structure are bonded together to obtain a bonded structure.

4. The method according to claim 3, characterized in that, Sequentially removing the substrate and a portion of the stacked structure of the memory array structure, forming a second opening in the stacked structure, including: Remove the substrate of the bonding structure to expose the stacked structure; The partially exposed stacked structure is removed, and the third groove is formed in the stacked structure, the third groove exposing the filling portion; A portion of each of the sacrificial layers on the sidewall of the third groove is removed to form a plurality of the fourth grooves on the sidewall of the third groove, thereby obtaining the second opening.

5. The method according to claim 1, characterized in that, After removing the filling portion to obtain the gate line slit, the method further includes: By removing each of the sacrificial layers through the gate line slits, a plurality of fifth grooves are obtained; Each of the fifth grooves is filled with metal material to form multiple metal layers, and the remaining gate line slits form a third opening; A second insulating layer is formed on the surface of the stacked structure away from the first dielectric layer and within the third opening; A second dielectric layer is formed within the remaining third opening to obtain a gate line.

6. The method according to claim 1, characterized in that, A stacked structure and a first dielectric layer are sequentially formed on a substrate, including: Provide substrate; Alternating layers of the first insulating layer and the sacrificial layer are formed on the surface of the substrate; A portion of the sacrificial layer and a portion of the first insulating layer are removed to form a sixth groove located in the sacrificial layer and the first insulating layer; The sixth groove is filled with sacrificial material to form the etching stop portion, thus obtaining the pre-stacked structure; The first insulating layer and the sacrificial layer are alternately stacked on the surface of the pre-stacked structure away from the substrate to form the stacked structure; The first dielectric layer is formed on the surface of the stacked structure away from the substrate.

7. The method according to claim 6, characterized in that, After forming alternately stacked first insulating layers and sacrificial layers on the surface of the pre-stacked structure away from the substrate, and before forming the first dielectric layer on the surface of the stacked structure away from the substrate, the method further includes: The stacked structure is partially removed, and a channel hole is formed in the stacked structure, the channel hole extending to the substrate, and the channel hole has a high-k dielectric layer, a charge blocking layer, an electron trapping layer, a tunneling layer and a channel layer arranged sequentially along the sidewall away from the channel hole.

8. The method according to claim 1, characterized in that, One end of the stacked structure has a stepped area. Before sequentially forming a stacked structure and a first dielectric layer on a substrate, and before removing a portion of the first dielectric layer, a portion of the body structure, and the etch stop portion to form a first opening located in the first dielectric layer and the stacked structure, the method further includes: A portion of the first dielectric layer and a portion of the stepped region are removed to form a plurality of virtual channel holes located in the first dielectric layer and the stepped region. A filling portion is formed in the first opening to obtain a storage array structure, including: A filling portion is formed in the first opening; A portion of the first dielectric layer and a portion of the stepped region are removed to form a plurality of contact holes located in the first dielectric layer and the stepped region on one side of the filling portion, thereby obtaining the memory array structure. The contact holes and the virtual channel holes are alternately arranged, and the gate line slit is located on one side of the contact holes.

9. The method according to any one of claims 1 to 8, characterized in that, The material of the etching stop portion includes carbon, and the material of the filling portion includes carbon.

10. A semiconductor device, characterized in that, The semiconductor device is manufactured using the semiconductor device manufacturing method according to any one of claims 1 to 9.

11. A three-dimensional memory, characterized in that, Includes the semiconductor device of claim 10.

12. A storage system, characterized in that, The device includes a storage controller and the three-dimensional memory of claim 11, the three-dimensional memory being configured to store data, and the storage controller being coupled to the three-dimensional memory and configured to control the three-dimensional memory.

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