Three-dimensional memory and manufacturing method thereof, storage system and electronic device

Abstract

The application relates to a three-dimensional memory, a manufacturing method thereof, a storage system and an electronic device. A stack structure is formed on a substrate; a channel hole is formed, the channel hole penetrates through the stack structure and extends into the substrate; a blocking layer is formed at the bottom of the channel hole; and a channel structure is formed on the blocking layer in the channel hole, so that the formed channel structure can be located on the substrate and does not extend into the interior of the substrate, thereby avoiding the reaction liquid (such as a grinding reaction liquid) from entering the interior of the channel structure through the gap or gap in the interior of the channel structure in the process of removing the substrate, and the storage unit in the channel structure is damaged, the yield and stability of the three-dimensional memory are improved.

Description

[Technical Field] This invention relates to the field of semiconductor technology, specifically to a three-dimensional memory, its fabrication method, storage system, and electronic device. [Background Technology] With the development of technology, the semiconductor industry is constantly seeking new production methods to enable each memory die in memory devices to have a greater number of memory cells. Among them, 3D NAND (three-dimensional) memory has become a cutting-edge and highly promising memory technology due to its advantages such as high storage density and low cost.

[0001] However, how to achieve a good electrical connection between the channel structure and the bottom source layer in a three-dimensional memory is a rather troublesome problem in current memory technology, and new methods to solve this problem are urgently needed. [Summary of the Invention] This invention provides a three-dimensional memory and its fabrication method, storage system, and electronic device to achieve good electrical connection between the channel structure and the bottom source layer in the three-dimensional memory, and to improve the yield and stability of the three-dimensional memory.

[0002] To at least partially solve the above problems, the present invention provides a method for fabricating a three-dimensional memory, the method comprising: forming a stacked structure on a substrate; forming a channel hole that penetrates the stacked structure and extends into the substrate; forming a barrier layer at the bottom of the channel hole; and forming a channel structure located on the barrier layer in the channel hole.

[0003] Specifically, forming a barrier layer at the bottom of the channel hole includes growing a barrier layer on the substrate surface exposed at the bottom of the channel hole.

[0004] Specifically, forming a barrier layer at the bottom of the channel hole includes: oxidizing the substrate surface exposed at the bottom of the channel hole to form an oxide, and the oxide extending from the unoxidized remaining substrate in the substrate toward the bottom of the channel hole to form a barrier layer.

[0005] Specifically, forming a stacked structure on the substrate includes: forming a sacrificial layer on the substrate; and forming a stacked structure on the sacrificial layer.

[0006] The height of the barrier layer relative to the bottom surface of the channel hole is no greater than the height of the sacrificial layer relative to the bottom surface of the channel hole.

[0007] Specifically, forming a channel structure on a barrier layer in a channel hole includes: forming a channel structure including a channel layer on the sidewall of the channel hole and the surface of the barrier layer; and after forming the channel structure on the barrier layer in the channel hole, further includes: removing the substrate and the barrier layer to expose the end of the channel layer; and forming a common source layer that covers and connects the end of the channel layer.

[0008] The channel structure further includes a storage function layer, which is formed sequentially on the sidewall of the channel hole and the surface of the barrier layer. The substrate and barrier layer are removed to expose the end of the channel layer. Specifically, this includes: removing the substrate and barrier layer to expose the sacrificial layer and the end of the channel structure; and removing the sacrificial layer and the storage function layer in the end of the channel structure to expose the end of the channel layer.

[0009] Before forming the stacked structure on the sacrificial layer, the process further includes: forming a stop layer on the sacrificial layer, with the stacked structure located on the stop layer and the channel via penetrating the stop layer; removing the storage function layer in the sacrificial layer and the end of the channel structure to expose the end of the channel layer, specifically including: using the stop layer as the etching stop layer, selectively etching away the storage function layer in the sacrificial layer and the end of the channel structure relative to the channel layer to expose the end of the stop layer and the channel layer.

[0010] The process of forming a stacked structure on a substrate specifically includes: forming a first stacked structure on the substrate; forming a first channel via penetrating the first stacked structure and extending into the substrate; forming a sacrificial material layer in the first channel via; forming a second stacked structure on the first stacked structure and the sacrificial material layer to obtain a stacked structure including the first stacked structure and the second stacked structure; and forming a channel via in the stacked structure specifically includes: forming a second channel via penetrating the second stacked structure, the second channel via exposing the sacrificial material layer; and removing the sacrificial material layer through the second channel via to obtain a channel via including the first channel via and the second channel via.

[0011] To at least partially solve the above problems, embodiments of the present invention also provide a three-dimensional memory, which further includes: a common source layer and a stacked structure; a channel structure extending through the stacked structure and into the common source layer, the channel structure including a channel layer and a storage function layer, the storage function layer being disposed around the sidewall of the channel layer, the end of the channel layer extending into the common source layer and connected to the common source layer; and a stop layer located between the common source layer and the stacked structure, the channel structure penetrating the stop layer, and the storage function layer being in contact with the stop layer.

[0012] The three-dimensional memory includes gaps that are sealed within a channel structure.

[0013] The stacked structure includes a first stack structure and a second stack structure arranged sequentially in the direction away from the common source layer, and the gap is located in a partial channel structure arranged in parallel with the first stack structure and the stop layer.

[0014] The end of the channel layer is located on the side of the stop layer away from the stacked structure.

[0015] To at least partially solve the above problems, embodiments of the present invention also provide a three-dimensional memory, which is manufactured using any of the three-dimensional memory manufacturing methods described above.

[0016] To at least partially solve the above problems, embodiments of the present invention also provide a storage system, which includes a controller and a three-dimensional memory as described above, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

[0017] To at least partially solve the above problems, embodiments of the present invention also provide an electronic device that includes the above-described storage system.

[0018] The electronic devices include at least one of the following: mobile phones, desktop computers, tablet computers, laptops, servers, in-vehicle equipment, wearable devices, and power banks.

[0019] The beneficial effects of the embodiments of the present invention are as follows: Unlike the prior art, the three-dimensional memory and its fabrication method, storage system and electronic device provided by the embodiments of the present invention form a stacked structure on a substrate, and then form a channel hole. The channel hole penetrates the stacked structure and extends into the substrate. Then, a barrier layer is formed at the bottom of the channel hole, and a channel structure is formed in the channel hole on the barrier layer. This allows the formed channel structure to be located on the substrate and not extend into the interior of the substrate. In the subsequent substrate removal process, the problem of the reaction liquid entering the interior of the channel structure through the gas cavity gap inside the channel structure and affecting the performance of the storage cells in the channel structure can be avoided or reduced, thereby improving the yield and stability of the three-dimensional memory. [Attached Image Description] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the method for fabricating a three-dimensional memory provided in an embodiment of the present invention; Figure 2 This is a cross-sectional structural diagram after step S111 is completed according to an embodiment of the present invention; Figure 3 This is a cross-sectional structural diagram after step S112 is completed according to an embodiment of the present invention; Figure 4 This is a cross-sectional structural diagram after step S12 is completed according to an embodiment of the present invention; Figure 5This is a cross-sectional structural diagram after step S13 is completed according to an embodiment of the present invention; Figure 6 This is another cross-sectional structural diagram after step S13 is completed, as provided in the embodiment of the present invention; Figure 7 This is a cross-sectional structural diagram after step S14 is completed according to an embodiment of the present invention; Figure 8 This is another cross-sectional structural diagram after step S14 is completed, as provided in the embodiment of the present invention; Figure 9 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the channel structure, provided in another embodiment; Figure 10 This is a cross-sectional view of the semiconductor structure obtained after bonding the peripheral circuit chip to the first interconnect layer, as provided in an embodiment of the present invention. Figure 11 This is a cross-sectional structural diagram after step S151 is completed according to an embodiment of the present invention; Figure 12 This is a cross-sectional structural diagram after step S152 is completed according to an embodiment of the present invention; Figure 13 This is another cross-sectional structural diagram after step S16 is completed, as provided in the embodiment of the present invention; Figure 14 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the second interconnect layer, provided in an embodiment of the present invention. Figure 15 This is a schematic diagram of the structure of the storage system provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0021] Furthermore, the directional terms mentioned in the embodiments of this invention, such as [up], [down], [front], [back], [left], [right], [inner], [outer], and [side], are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the embodiments of this invention, and not for limiting the embodiments of this invention. In the various drawings, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0022] The embodiments of the present invention may be presented in various forms, and some examples will be described below.

[0023] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention. The specific process of the method for fabricating the three-dimensional memory is as follows: Step S11: Form a stacked structure on the substrate.

[0024] Specifically, step S11 can include: Step S111: Form a sacrificial layer on the substrate.

[0025] The cross-sectional structure diagram after step S111 is shown below. Figure 2 As shown.

[0026] The substrate 10 is used to support the device structure thereon and may include semiconductor materials such as silicon, germanium or silicon-on-insulator (SOI).

[0027] Specifically, a sacrificial layer 11 can be formed on the substrate 10 using a thin film deposition process (e.g., chemical vapor deposition). The material of the sacrificial layer 11 can be, but is not limited to, an insulating material such as silicon oxide, and the sacrificial layer 11 can be used to protect the substrate 10 from damage in subsequent process steps.

[0028] Step S112: Form a stacked structure on the sacrificial layer.

[0029] The cross-sectional structure diagram after step S112 is shown below. Figure 3 As shown.

[0030] The stacked structure 13 may include a plurality of gate sacrificial layers 131 and interlayer insulating layers 132 alternately stacked in a longitudinal direction Z perpendicular to the substrate 10. Specifically, methods such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, and laser-assisted deposition can be used to form the gate sacrificial layer 131 and interlayer insulating layer 132 of the stacked structure 13 on the stop layer 12. The gate sacrificial layer 131 may be, but is not limited to, silicon nitride, and the interlayer insulating layer 132 may be, but is not limited to, silicon oxide, thereby forming a silicon nitride / silicon oxide stacked structure 13. Furthermore, in subsequent process steps, the gate sacrificial layer 131 may be replaced by a replacement process, and a conductive material (e.g., tungsten) may be filled at the same location to form a gate layer.

[0031] In a three-dimensional memory, the number of layers in the stacked structure 13 determines the number of memory cells it contains in the vertical direction (that is, the longitudinal direction Z perpendicular to the substrate 10). For example, the stacked structure 13 can have 32, 64, 96, or 128 layers, and the more layers the stacked structure 13 has, the higher the integration density of the corresponding three-dimensional memory.

[0032] In some embodiments, such as Figure 3 As shown, prior to step S112, the fabrication method of the three-dimensional memory may further include forming a stop layer 12 on the sacrificial layer 11. Specifically, a thin-film deposition process (e.g., chemical vapor deposition) can be used to form the stop layer 12 on the sacrificial layer 11. The material of the stop layer 12 may be, but is not limited to, polysilicon. Correspondingly, the stacked structure 13 may be located on the stop layer 12. That is, the stacked structure 13 may be formed on the side of the stop layer 12 facing away from the sacrificial layer 11.

[0033] Step S12: Form a channel hole that penetrates the stacked structure and extends into the substrate.

[0034] The cross-sectional structure diagram after step S12 is shown below. Figure 4 As shown.

[0035] Specifically, an anisotropic etching process (e.g., dry etching) can be used to etch the aforementioned stacked structure 13, stop layer 12, sacrificial layer 11, and substrate 10 sequentially from top to bottom, forming a channel hole 14 that penetrates the stacked structure 13, stop layer 12, sacrificial layer 11, and part of the substrate 10 from top to bottom. The bottom of the channel hole 14 exposes the substrate 10, and the channel hole 14 extends into the interior of the substrate 10, forming a groove 111A on the substrate 10.

[0036] Step S13: Form a barrier layer at the bottom of the channel hole.

[0037] The cross-sectional structure diagram after step S13 is shown below. Figure 5 As shown.

[0038] The barrier layer 15 can extend from the bottom surface of the channel hole 14 in a direction away from the substrate 10 to the bottom of the channel hole 14. The height H1 of the barrier layer 15 relative to the bottom surface of the channel hole 14 can be no greater than the height H2 of the sacrificial layer 11 relative to the bottom surface of the channel hole 14. This ensures that after the barrier layer 15 is removed in subsequent process steps, a certain thickness of residual sacrificial layer still covers the bottom surface of the stacked structure 13, protecting the stacked structure 13 from damage by the reaction solution used to remove the barrier layer 15.

[0039] In one specific embodiment, the height H1 of the barrier layer 15 relative to the bottom surface of the channel hole 14 can be equal to or less than the height H3 of the top surface of the substrate 10 relative to the bottom surface of the channel hole 14. That is, the barrier layer 15 can be formed only in the bottom section 111A of the channel hole 14 that passes through the substrate 10 (that is, the groove 111A), and the barrier layer 15 can either completely fill the bottom section 111A of the channel hole or not completely fill it.

[0040] In another specific embodiment, the height H1 of the barrier layer 15 relative to the bottom surface of the channel hole 14 can be greater than the height H3 of the top surface of the substrate 10 relative to the bottom surface of the channel hole 14, but not greater than the height of the top surface of the stop layer 12 relative to the bottom surface of the channel hole 14.

[0041] In one possible embodiment, such as Figure 5 As shown, the barrier layer 15 can completely fill the bottom section 111A of the channel hole 14 that penetrates the substrate 10. That is, the height H1 of the barrier layer 15 relative to the bottom surface of the channel hole 14 can be equal to the height H3 of the top surface of the substrate 10 relative to the bottom surface of the channel hole 14. Furthermore, step S13 can specifically include: growing the barrier layer 15 on the surface of the substrate 10 exposed at the bottom of the channel hole 14. The barrier layer 15 can extend from the surface of the substrate 10 into the bottom of the channel hole 14 and be connected as a single unit to completely fill the bottom section 111A of the channel hole 14 that penetrates the substrate 10. The material of the barrier layer 15 can be, but is not limited to, polycrystalline silicon or monocrystalline silicon, and the material of the barrier layer 15 can be the same as or different from the material of the substrate 10.

[0042] Specifically, the barrier layer 15 can be epitaxially grown on the surface of the substrate 10 exposed at the bottom of the channel hole 14 using a selective epitaxial growth (SEG) process.

[0043] In some alternative embodiments, such as Figure 6As shown, step S13 can specifically include: oxidizing the surface of the substrate 10 exposed at the bottom of the channel hole 14, so that the portion of the substrate 10 exposed through the bottom of the channel hole 14 (or the inner wall of the groove 111A) is oxidized into oxide 16. The oxide 16 can extend from the unoxidized remaining substrate in the substrate 10 into the channel hole and connect as a single unit to fill the bottom section 111A of the channel hole 14 through the substrate 10, thereby obtaining the barrier layer 15. The barrier layer 15 can be the portion of the oxide 16 extending into the bottom section 111A of the channel hole. Specifically, the substrate 10 can be made of monocrystalline silicon, and the oxide 16 can be made of silicon oxide.

[0044] It should be noted that the substrate 10 (e.g., a single-crystal silicon layer) expands after oxidation. That is, after the portion of the substrate exposed at the bottom of the channel hole 14 is oxidized into oxide 16, the volume of oxide 16 will be larger than the volume of the oxidized portion of the substrate. Furthermore, since the oxidation direction is from the bottom inner wall of the channel hole 14 towards the interior of the substrate 10, the substrate material closer to the bottom inner wall of the channel hole 14 is oxidized earlier than the substrate material farther from the bottom inner wall of the channel hole 14. Therefore, the oxidized substrate material expands from the interior of the substrate 10 towards the interior of the channel hole 14, entering the bottom of the channel hole 14. Moreover, when the oxidized substrate material reaches a certain amount, it fills and compacts the bottom section 111A of the channel hole 14, resulting in the aforementioned barrier layer 15 composed of the oxidized substrate material.

[0045] Furthermore, in specific implementation, a thermal oxidation process (e.g., a wet oxidation process) can be used to oxidize the material of the substrate 10 exposed through the inner wall of the bottom section 111A of the channel hole to form the oxide 16.

[0046] It is worth noting that, compared to the scheme of oxidizing the surface of the substrate 10 exposed through the bottom of the channel hole 14 to form the barrier layer 15, the scheme of epitaxially growing the barrier layer 15 on the surface of the substrate 10 exposed through the bottom of the channel hole 14 is more conducive to reducing the process difficulty of removing the substrate 10 by chemical mechanical polishing in subsequent process steps.

[0047] Step S14: Form a channel structure on the barrier layer in the channel hole.

[0048] The cross-sectional structure diagram after step S14 is shown below. Figure 7 As shown.

[0049] The channel structure 18 may include a storage function layer 181 and a channel layer 182 sequentially formed on the sidewall of the channel hole 14 and the surface of the barrier layer 15.

[0050] Specifically, a storage function layer 181 and a channel layer 182 can be sequentially formed on the sidewall of the channel hole 14 and the surface of the barrier layer 15. Then, a dielectric material (e.g., silicon oxide) is filled into the channel hole 14 where the storage function layer 181 and the channel layer 182 are formed to form an insulating filling layer 183 to fill the remaining space in the channel hole 14, thereby obtaining the channel structure 18.

[0051] The channel structure 18 includes an insulating filler layer 183, a channel layer 182, and a storage function layer 181. Furthermore, due to the different deposition rates of dielectric materials on different material surfaces, air gaps 18A may be formed inside the insulating filler layer 183 (i.e., inside the channel structure 18).

[0052] It should be noted that although the aforementioned air cavity gaps 18A may be formed inside the channel structures 18 formed in each channel hole 14, in practice, only some of the channel structures 18 in the channel holes 14 may have the aforementioned air cavity gaps 18A formed, or all the channel structures 18 in the channel holes 14 may have the aforementioned air cavity gaps 18A formed, or none of the channel structures 18 in the channel holes 14 may have the aforementioned air cavity gaps 18A formed (that is, each channel hole 14 may be completely filled by its corresponding channel structure 18, so that the aforementioned air cavity gaps 18A are not formed). Furthermore, it is understood that the aforementioned air cavity gaps 18A are not expected to be formed within the channel structures 18.

[0053] The aforementioned storage functional layer 181 may include a charge blocking layer, a charge trapping layer, and a tunneling layer sequentially formed on the sidewalls of the channel via 14 and the surface of the barrier layer 15. Specifically, the materials of the charge blocking layer, charge trapping layer, tunneling layer, and the aforementioned channel layer 182 may be silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively, corresponding to the aforementioned channel structure 18 as an "ONOP" structure. Furthermore, it is understood that although the storage functional layer exemplified here is an ONO structure composed of an oxide layer, a nitride layer, and another oxide layer, other possible structures are also possible.

[0054] In the above embodiments, in order to increase the storage density of the three-dimensional memory by increasing the number of layers of the stacked structure 13 without increasing the difficulty of the etching process for forming the above-mentioned channel hole 14, the stacked structure 13 may include multiple stacked structures stacked in the longitudinal Z direction, and the channel hole 14 through the stacked structure 13 can be formed by multiple etching processes.

[0055] Specifically, such as Figure 8 As shown, the aforementioned stacked structure 13 may include a first stacked structure 13A and a second stacked structure 13B stacked in the longitudinal direction Z. Accordingly, step S11 may specifically include: forming the first stacked structure 13A on the substrate 10; forming a first channel hole 14A, the first channel hole 14A penetrating the first stacked structure 13A and extending into the substrate 10; forming a sacrificial material layer in the first channel hole 14A; and forming a second stacked structure 13B on the first stacked structure 13A and the sacrificial material layer to obtain a stacked structure 13 including the first stacked structure 13A and the second stacked structure 13B. Step S13 may specifically include: forming a second channel hole 14B penetrating the second stacked structure 13B, the second channel hole 14B exposing the sacrificial material layer; and removing the sacrificial material layer through the second channel hole 14B to obtain a channel hole 14 including the first channel hole 14A and the second channel hole 14B.

[0056] The first stack structure 13A and the second stack structure 13B in the stacked structure 13 can both include multiple layers of gate sacrificial layer 131 and interlayer insulating layer 132 alternately stacked in the longitudinal direction Z perpendicular to the substrate 10. Furthermore, the number of layers in the second stack structure 13B can be the same as or different from the number of layers in the first stack structure 13A.

[0057] The first channel hole 14A can penetrate the first stack structure 13A, the stop layer 12, and the sacrificial layer 11 in a longitudinal direction Z perpendicular to the substrate 10, and extend into the interior of the substrate 10 to form a groove 111A on the substrate 10. The second channel hole 14B can penetrate the second stack structure 13B in a longitudinal direction Z perpendicular to the substrate 10, and the bottom of the second channel hole 14B exposes the top surface of the sacrificial material layer in the first channel hole 14A.

[0058] The aforementioned sacrificial material layer can be formed by depositing and filling the sacrificial material in the first channel hole 14A using a chemical vapor deposition process, and then removing the sacrificial material located outside the first channel hole 14A using chemical mechanical planarization. The sacrificial material can be any one of polycrystalline silicon, carbon, and tungsten.

[0059] The aforementioned via 14 includes a first via 14A and a second via 14B that are interconnected. After the second via 14B is formed, a selective etchant can be used to selectively etch and remove the sacrificial material layer relative to the first stack structure 13A and the second stack structure 13B through the second via 14B to obtain the aforementioned via 14. A barrier layer 15 can then be formed at the bottom of the via 14. Finally, a channel structure 18 located on the barrier layer 15 is formed in the via 14.

[0060] like Figure 9As shown, according to another method for fabricating a three-dimensional memory, after forming the via 24, a channel structure 28 is formed throughout the via 24. The channel structure 28 penetrates the stacked structure 23, the stop layer 22, and the sacrificial layer 21, and extends into the interior of the substrate 10. Since the via 24, in which the storage functional layer 281 and the channel layer 282 are formed, is filled with a dielectric material (e.g., silicon oxide), an air cavity gap 28A is formed inside the resulting insulating filling layer 283. This air cavity gap 28A extends from the stacked structure 23 toward the substrate 20 to the side of the sacrificial layer 21 away from the stacked structure 23. Therefore, when the substrate 20 is removed in subsequent process steps, the reaction solution used to remove the substrate 20 (e.g., a polishing reaction solution used to remove the substrate 20 by chemical mechanical polishing) will enter the interior of the channel structure 28 along the air cavity gap 28A from the side of the sacrificial layer 21 away from the stacked structure 23, leading to defects in the memory cells within the channel structure 28.

[0061] The inventors also discovered that, as Figure 9 As shown, when the stacked structure 23 includes a first stacked structure 23A and a second stacked structure 23B stacked in the longitudinal direction Z, the small aperture of the channel holes at the connection between the first stacked structure 23A and the second stacked structure 23B will cause the lower channel hole 24A in the stacked structure (i.e., the first stacked structure 23A) near the substrate 20 to be sealed in advance when the channel hole 24 (including the lower channel hole 24A and the upper channel hole 24B) where the storage functional layer 281 and the channel layer 282 are formed to form an insulating filling layer 283. This will result in the formation of large voids 28A inside the channel structure segment of the channel structure 28 adjacent to the first stacked structure 23A. The presence of these voids 28A will cause the reaction liquid to enter the interior of the channel structure 28 during the subsequent removal of the substrate 20, which will seriously affect the performance of the memory cells in the channel structure 28.

[0062] Furthermore, compared to the scheme of forming the channel structure 28 in the entire channel hole 24 and extending the channel structure 28 into the substrate 20, this embodiment forms a barrier layer 15 at the bottom of the channel hole 14, which allows the channel structure formed in subsequent process steps to be located on the substrate and not extend into the interior of the substrate. Thus, when the substrate 10 is removed in subsequent process steps, the air cavity gap 18A inside the channel structure 18 can be prevented from being exposed from the substrate 10, which would cause the reaction liquid (e.g., polishing reaction liquid) to enter the interior of the channel structure 18 through the air cavity gap 18A exposed from the substrate 10, thereby affecting the quality of the memory cells in the channel structure 18.

[0063] In some specific embodiments, such as Figure 10As shown, after forming the aforementioned channel structure 18, the fabrication method of the aforementioned three-dimensional memory may further include: forming a gate line gap that penetrates the stacked structure 13 and extends to the substrate 10; removing the gate sacrificial layer 131 in the aforementioned stacked structure 13 through the gate line gap to form a sacrificial gap; forming a gate layer 131 within the sacrificial gap (in this case, the gate layer and the gate sacrificial layer are represented by the same reference numerals); and filling the gate line gap with an insulating material (e.g., oxide) and / or a conductive material (e.g., titanium, polysilicon, and / or tungsten) to form a gate line gap structure 19.

[0064] In some embodiments, such as Figure 10 As shown, the width of each gate layer 131 at at least one end of the above-mentioned stacked structure 13 can be successively reduced in the direction away from the substrate 10 to form a stepped structure 13C. Furthermore, after forming the above-mentioned gate gap structure 19, the above-mentioned method for fabricating the three-dimensional memory may further include: forming a plurality of word line contacts 32A, which are electrically connected to the gate layer 131 at the positions of the stepped structure 13C.

[0065] Specifically, the aforementioned plurality of word line contacts 32A may be perpendicular to the substrate 10 and may extend in the longitudinal direction Z to the multiple steps of the stepped structure 13C. In one embodiment, as Figure 10 As shown, while forming the multiple word line contacts 32A, peripheral pad contacts 32B can also be formed around the periphery of the stacked structure 13. The peripheral pad contacts 32B are used for electrical connection with peripheral circuits, and their number and arrangement can be prepared according to actual needs. The materials of the word line contacts 32A and the peripheral pad contacts 32B can be conductive materials, such as tungsten.

[0066] In some specific embodiments, such as Figure 10 As shown, after forming the word line contact 32A and the peripheral pad contact 32B, the fabrication method of the three-dimensional memory may further include: forming a first interlayer dielectric layer 33 on the stacked structure 13; forming a plurality of first conductive contacts 34 penetrating the first interlayer dielectric layer 33; and forming a first interconnect layer 35 on the first interlayer dielectric layer 33. The first interlayer dielectric layer 33 may be made of an insulating material such as silicon oxide. The first interconnect layer 35 may be made of a conductive material such as tungsten.

[0067] Specifically, the plurality of first conductive contacts 34 may include bit line contacts, which may extend in a direction Z perpendicular to the substrate 10, with one end electrically connected to the channel structure 18 and the other end electrically connected to a corresponding conductive trace in the first interconnect layer 35. In some embodiments, the plurality of first conductive contacts 34 may further include peripheral circuit contacts, which may extend in a direction Z perpendicular to the substrate 10, with one end electrically connected to a corresponding peripheral circuit contact 32B and the other end electrically connected to a corresponding conductive trace in the first interconnect layer 35.

[0068] In some specific embodiments, such as Figure 10 As shown, after forming the first interconnect layer 35, the fabrication method of the three-dimensional memory may further include: providing a peripheral circuit chip 36 and bonding the peripheral circuit chip 36 to the first interconnect layer 35 using a bonding structure. Furthermore, the peripheral circuit chip 36 and the bonding structure can be found in specific embodiments of peripheral circuit chips and bonding structures in the prior art, and therefore will not be described in detail here.

[0069] In the above embodiments, after step S14, the following may also be included: Step S15: Remove the substrate and barrier layer to expose the end of the trench layer.

[0070] Specifically, step S15 can include: Step S151: Remove the substrate and barrier layer to expose the sacrificial layer and the ends of the channel structure.

[0071] The cross-sectional structure diagram after step S151 can be as follows: Figure 11 As shown.

[0072] Specifically, the semiconductor structure obtained after the preceding steps can be flipped 180°, and then the substrate 10 can be polished using the sacrificial layer 11 as the polishing stop layer until the end 18B of the sacrificial layer 11 and the channel structure 18 is exposed. The end 18B extends into the sacrificial layer 11. In one specific embodiment, the end 18B can be flush with the sacrificial layer 11. That is, the end face of the end 18B can be in the same horizontal plane as the surface of the sacrificial layer 11 facing away from the stacked structure 13.

[0073] Step S152: Remove the sacrificial layer and the storage function layer at the end of the channel structure to expose the end of the channel layer.

[0074] The cross-sectional structure diagram after step S152 can be as follows: Figure 12 As shown.

[0075] Specifically, a selective etchant can be used to selectively etch away the sacrificial layer 11 and the storage function layer 181 in the end 18B of the channel structure 18 that contacts the sacrificial layer 11, so as to expose the end 182A of the channel layer 182 in the end 18B of the channel structure 18.

[0076] In one specific embodiment, a stop layer 12 may be formed between the sacrificial layer 11 and the stacked structure 13, and the above step S152 may specifically include: using the stop layer 12 as an etching stop layer, selectively etching away the storage function layer 181 in the end 18B of the sacrificial layer 11 and the channel structure 18 relative to the channel layer 182, until the end 182A of the stop layer 12 and the channel layer 182 located in the end 18B of the channel structure 18 is exposed.

[0077] Step S16: Form a common source electrode layer that covers and connects the ends of the channel layer.

[0078] The cross-sectional structure diagram after step S16 is completed can be shown as follows: Figure 13 As shown.

[0079] Specifically, a common source layer 30 covering the end 182A of the channel layer 182 can be formed on the side of the stop layer 12 opposite to the stacked structure 13. The common source layer 30 may include polysilicon. For example, the common source layer 30 may include P-type doped polysilicon. Specifically, the common source layer 30 may also cover the end 181A of the memory functional layer 181.

[0080] In some embodiments, such as Figure 14 As shown, after step S16, the fabrication method of the three-dimensional memory may further include: forming a second interlayer dielectric layer 31 on the side of the common source layer 30 away from the stacked structure 13; forming a plurality of second conductive contacts 37 penetrating the second interlayer dielectric layer 31; and forming a second interconnect layer 38 on the side of the second interlayer dielectric layer 31 away from the common source layer 30.

[0081] Specifically, the plurality of second conductive contacts 37 may include source contacts that extend longitudinally in the Z direction, with one end electrically connected to the common source layer 30 and the other end electrically connected to the second interconnect layer 38. In some embodiments, the plurality of second conductive contacts 37 may further include peripheral circuit contacts that extend longitudinally in the Z direction, with one end electrically connected to the peripheral circuit contact 32B and the other end electrically connected to the second interconnect layer 38.

[0082] The fabrication method of the three-dimensional memory in this embodiment involves forming a stacked structure on a substrate, then forming a channel hole that penetrates the stacked structure and extends into the substrate. A barrier layer is then formed at the bottom of the channel hole, and a channel structure is formed on the barrier layer within the channel hole. This ensures that the formed channel structure is located on the substrate and does not extend into the interior of the substrate. Consequently, when the substrate is removed in subsequent process steps, the air gaps inside the channel structure are prevented from being exposed from the substrate, thus avoiding the problem of reaction liquid (e.g., polishing reaction liquid) entering the interior of the channel structure through the exposed air gaps and affecting the performance of the memory cells in the channel structure. This improves the yield and stability of the three-dimensional memory.

[0083] The three-dimensional memory fabricated according to the above method embodiments of the present invention is as follows: Figure 14 As shown, the three-dimensional memory may include: The three-dimensional memory fabricated according to the above method embodiments of the present invention is as follows: Figure 14 As shown, the three-dimensional memory may include: a stacked common source layer 30 and a stacked structure 13, and a channel structure 18 that penetrates the stacked structure 13 and extends into the common source layer 30. The channel structure 18 includes a channel layer 182, and an end 182A of the channel layer 182 extends into the common source layer 30 and is connected to the common source layer 30.

[0084] In one embodiment, the channel structure 18 may further include a storage function layer 181, which may be disposed around the sidewall of the channel layer 182. Furthermore, the three-dimensional memory may also include a stop layer 12 located between the common source layer 30 and the stacked structure 13. The channel structure 18 extends through the stop layer 12, and the storage function layer 181 is in contact with the stop layer 12.

[0085] Specifically, the sidewall of the aforementioned channel layer 182 extends away from the aforementioned common source layer 30, and the aforementioned channel layer 182 may also have a bottom wall facing the aforementioned common source layer 30, and the channel layer 182 can contact the aforementioned common source layer 30 through its bottom wall. It should be noted that, unlike the channel layer 182 which has a bottom wall facing the aforementioned common source layer 30, the aforementioned storage function layer 181 may not have a bottom wall facing the aforementioned common source layer 30, and the aforementioned storage function layer 181 may have a sidewall extending away from the aforementioned common source layer 30, and the sidewall of the storage function layer 181 is disposed around the sidewall of the channel layer 182, and the storage function layer 181 can contact the aforementioned stop layer 30 through its sidewall, thereby ensuring that the bottom wall of the channel layer 182 located inside the storage function layer 181 can be exposed, and at the same time, the stop layer 12 can be isolated from the channel layer 182.

[0086] In one embodiment, the aforementioned three-dimensional memory may further include a gap 18A, which is sealed within the channel structure 18. This avoids the problem in existing three-dimensional memories where a gap is formed inside the channel structure during its formation, and this gap is exposed from the back side of the substrate during substrate removal. Consequently, the reaction solution used to remove the substrate can enter the channel structure through this exposed gap, leading to defects in the memory cells within the channel structure. In other words, even if a gap 18A is formed inside the channel structure 18 during its formation, in this embodiment, because the channel structure 18 is formed only on the substrate and does not extend into the substrate, the gap 18A is always sealed within the channel structure 18 during substrate removal and is not exposed. This prevents the reaction solution used to remove the substrate from entering the channel structure 18 through the gap 18A and affecting the quality of the memory cells within the channel structure 18.

[0087] In one specific embodiment, the aforementioned stacked structure 13 may include a first stacked structure (such as...) arranged sequentially in a direction away from the common source layer 30. Figure 8 The first stack structure 13A shown) and the second stack structure (as shown) Figure 8 The second stack structure 13B shown above, and the aforementioned gap 18A may be located in a partial channel structure 18 arranged alongside the first stack structure and the stop layer 12.

[0088] In one specific embodiment, the end 182A of the aforementioned channel layer 182 may be located on the side of the stop layer 12 away from the stacked structure 13. Specifically, the end 182A of the channel layer 182 is the end of the channel layer 182 that contacts the aforementioned common source layer 30.

[0089] It should be noted that the various structures of the three-dimensional memory in this embodiment can refer to the specific implementation methods described in the above method embodiments, so they will not be repeated here.

[0090] The three-dimensional memory provided in this embodiment forms a barrier layer at the bottom of the channel hole. This barrier layer can prevent the channel structure from entering the bottom of the channel hole when the channel structure is formed. This makes it difficult for the air cavity gap inside the channel structure to extend from the stacked structure towards the substrate to the side of the sacrificial layer away from the stacked structure. As a result, in the subsequent substrate removal process, it can avoid or reduce the problem of the reaction liquid entering the inside of the channel structure through the air cavity gap inside the channel structure, thus affecting the performance of the memory cells in the channel structure.

[0091] Accordingly, such as Figure 15As shown, this embodiment of the invention also provides a storage system 40, which includes a controller 41 and a three-dimensional memory 42. The controller 41 is coupled to the three-dimensional memory 42 and is used to control the three-dimensional memory 42 to store data.

[0092] The three-dimensional memory 42 may be the same as the three-dimensional memory described in any of the embodiments above, and therefore will not be repeated here. The controller 41 controls the three-dimensional memory 42 via channel CH, and the three-dimensional memory 42 can perform operations based on the control of the controller 41 in response to requests from the host 50. The three-dimensional memory 42 receives commands CMD and addresses ADDR from the controller 41 via channel CH and accesses the region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 42 can perform internal operations corresponding to commands on the region selected by the address.

[0093] In some implementations, the storage system 40 may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC and Micro MMC, a Secure Digital Card in the form of SD, Mini SD and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card or Memory Stick, etc.

[0094] Specifically, the aforementioned storage system 40 can be used in terminal products such as computers, televisions, set-top boxes, and in-vehicle systems.

[0095] The storage system provided in this embodiment forms a barrier layer at the bottom of the channel hole. This barrier layer can prevent the channel structure from entering the interior of the substrate when the channel structure is formed. In subsequent process steps, when the substrate is removed, the air cavity gap inside the channel structure can be prevented from being exposed from the substrate. This would prevent the reaction liquid (e.g., polishing reaction liquid) from entering the interior of the channel structure through the air cavity gap exposed from the substrate, thereby affecting the performance of the storage cells in the channel structure. This improves the yield and stability of the three-dimensional memory.

[0096] Accordingly, such as Figure 16 As shown, this embodiment of the invention also provides an electronic device 60, which includes the storage system 61 provided in this embodiment of the invention. Specifically, the electronic device 60 can be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted device, wearable device, or power bank.

[0097] An electronic device provided in this embodiment of the invention has the same beneficial effects as the storage system described above due to the inclusion of the storage system provided in this embodiment of the invention.

[0098] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A multilayer structure is formed on the substrate; A channel hole is formed, which penetrates the stacked structure and extends into the substrate; A barrier layer is formed at the bottom of the channel hole; A channel structure including a channel layer is formed on the sidewall of the channel hole and on the surface of the barrier layer; Remove the substrate and the barrier layer to expose the end of the trench layer; A common source electrode layer is formed that covers and connects the ends of the channel layer.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of a barrier layer at the bottom of the channel hole specifically includes: A barrier layer is grown on the substrate surface exposed at the bottom of the channel hole.

3. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of a barrier layer at the bottom of the channel hole specifically includes: The substrate surface exposed at the bottom of the channel hole is oxidized to form an oxide, which extends from the unoxidized remaining substrate in the substrate toward the bottom of the channel hole to form the barrier layer.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of the stacked structure on the substrate specifically includes: A sacrificial layer is formed on the substrate; A stacked structure is formed on the sacrificial layer.

5. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that, The height of the barrier layer relative to the bottom surface of the channel hole is no greater than the height of the sacrificial layer relative to the bottom surface of the channel hole.

6. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that, The channel structure further includes a storage functional layer, wherein the storage functional layer and the channel layer are sequentially formed on the sidewall of the channel aperture and the surface of the barrier layer, and the removal of the substrate and the barrier layer to expose the end of the channel layer specifically includes: Remove the substrate and the barrier layer to expose the sacrificial layer and the end of the channel structure; Remove the sacrificial layer and the storage function layer at the end of the channel structure to expose the end of the channel layer.

7. The method for manufacturing a three-dimensional memory according to claim 6, characterized in that, Before forming the laminated structure on the sacrificial layer, the method further includes: A stop layer is formed on the sacrificial layer, the stacked structure is located on the stop layer, and the channel hole penetrates the stop layer; Removing the sacrificial layer and the storage function layer at the end of the channel structure to expose the end of the channel layer specifically includes: Using the stop layer as the etching stop layer, the storage function layer in the end of the sacrificial layer and the channel structure is selectively etched away relative to the channel layer to expose the stop layer and the end of the channel layer.

8. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, The formation of the stacked structure on the substrate specifically includes: A first stack structure is formed on the substrate; A first channel hole is formed, which penetrates the first stack structure and extends into the substrate; A sacrificial material layer is formed in the first channel hole; A second stack structure is formed on the first stack structure and the sacrificial material layer to obtain a stacked structure including the first stack structure and the second stack structure; The formation of the channel hole specifically includes: A second channel hole is formed through the second stack structure, the second channel hole exposing the sacrificial material layer; The sacrificial material layer is removed via the second channel hole to obtain a channel hole including the first channel hole and the second channel hole.

9. A three-dimensional memory, characterized in that, include: Stacked common source electrode layer and stacked structure; A channel structure that penetrates the stacked structure and extends along a first direction into the common source layer, the channel structure including a channel layer and a storage function layer, the storage function layer being disposed around the sidewall of the channel layer, and the end of the channel layer extending into the common source layer and connected to the common source layer; A stop layer is located between the common source layer and the stacked structure, the channel structure penetrates the stop layer, and the storage function layer is located between the stop layer and the channel layer and is in contact with the stop layer; A gate line gap structure extends through the stacked structure and the stop layer. The first end of the gate line gap structure in the first direction contacts the common source layer. The first end of the gate line gap structure is coplanar with the side of the stop layer opposite to the stacked structure.

10. The three-dimensional memory according to claim 9, characterized in that, The three-dimensional memory includes a gap that is sealed within the channel structure.

11. The three-dimensional memory according to claim 10, characterized in that, The stacked structure includes a first stack structure and a second stack structure arranged sequentially in a direction away from the common source layer, and the gap is located in a portion of the channel structure arranged parallel to the first stack structure and the stop layer.

12. The three-dimensional memory according to claim 9, characterized in that, The end of the channel layer is located on the side of the stop layer opposite to the stacked structure.

13. A three-dimensional memory, characterized in that, The three-dimensional memory is manufactured using the method described in any one of claims 1 to 8.

14. A storage system, characterized in that, The storage system includes a controller and a three-dimensional memory as described in any one of claims 9 to 13, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

15. An electronic device, characterized in that, Includes the storage system described in claim 14.

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