Image sensor and method of forming the same

Abstract

Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive component is disposed above a frontside of the semiconductor substrate. A through-substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive component. The through-substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed below the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through-substrate via. Embodiments of the present application provide an image sensor and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to image sensors and methods of forming the same. Background Technology

[0002] Integrated circuits (ICs) with image sensors are widely used in modern electronic devices such as cameras and mobile phones. Complementary metal-oxide-semiconductor (CMOS) devices have become popular IC image sensors. Compared with charge-coupled devices (CCDs), CMOS image sensors are increasingly favored due to their low power consumption, small size, fast data processing speed, direct data output, and low manufacturing cost. As IC sizes shrink, small pixel sizes in CMOS devices are desirable. For smaller pixel sizes, crosstalk between pixels can become a problem, and unique solutions can improve the performance of small CMOS pixel sizes. Summary of the Invention

[0003] Some embodiments relate to an image sensor. The image sensor includes: a semiconductor substrate including a pixel region and a peripheral region. A back-side isolation structure extends into the back side of the semiconductor substrate and laterally surrounds the pixel region. The back-side isolation structure includes a metal core, and a dielectric pad separates the metal core from the semiconductor substrate. A conductive component is disposed above the front side of the semiconductor substrate. A through-substrate via extends from the back side of the semiconductor substrate through the peripheral region to contact the conductive component. The through-substrate via is laterally offset from the back-side isolation structure. A conductive bridge is disposed below the back side of the semiconductor substrate and electrically couples the metal core of the back-side isolation structure to the through-substrate via.

[0004] An image sensor includes: a semiconductor substrate including pixel regions laterally offset from the peripheral region. A back-side isolation structure extends into the back side of the semiconductor substrate and laterally surrounds the pixel regions. A through-substrate via extends through the semiconductor substrate in the peripheral region and is electrically coupled to the back-side isolation structure via a conductive bridge disposed below the back side of the semiconductor substrate. A conductive member is disposed above the front side of the semiconductor substrate and is electrically coupled to the through-substrate via. A negative bias circuit is configured to apply a first bias state and a second bias state across the back-side isolation structure and the semiconductor substrate at different times via the conductive member.

[0005] A method of forming an image sensor includes: forming conductive components on the front side of a semiconductor substrate; patterning the semiconductor substrate to form back isolation trenches and back connection trenches in a pixel region such that the back isolation trenches intersect the back connection trenches; patterning through-holes extending through the semiconductor substrate in a peripheral region laterally offset from the pixel region; providing a conductive material to form back isolation structures in the back isolation trenches, back connection structures in the back connection trenches, and through-substrate vias in the through-holes to contact the conductive components; and forming conductive bridges over the back surface of the through-substrate vias and the back surface of the back connection structures.

[0006] Embodiments of this application also relate to stacked structures of CMOS image sensors. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A cross-sectional view of some embodiments of an image sensor is shown, including a negative bias circuit coupled to a peripheral region configured to negatively bias a pixel array region.

[0009] Figure 2 Show Figure 1 Top views of some embodiments of the image sensor, such as Figure 1 and Figure 2 The cutting lines A-A' and B-B' are shown in the diagram.

[0010] Figure 3 Show Figure 1 Top views of some embodiments of the image sensor, such as Figure 1 and Figure 3 The cutting lines C-C' and D-D' are shown in the diagram.

[0011] Figure 4A Cross-sectional views of some embodiments of an image sensor including offset back-side conductive traces are shown.

[0012] Figure 4B Cross-sectional views of some embodiments of an image sensor including an irregular dielectric layer are shown.

[0013] Figure 4C Cross-sectional views of some embodiments of an image sensor including offset back-side conductive traces and an irregular dielectric layer are shown.

[0014] Figure 5 Show Figure 4A Top views of some embodiments of the image sensor, such as Figure 4A and Figure 5 The cutting lines C-C' and D-D' are shown.

[0015] Figure 6A Cross-sectional views of some embodiments of an image sensor including a separation layer are shown.

[0016] Figure 6B Cross-sectional views of some embodiments of an image sensor including a separation layer and a back separation trace are shown.

[0017] Figure 7 Show Figure 6A Top views of some embodiments of the image sensor, such as Figure 6A and Figure 7 The cutting lines C-C' and D-D' are shown.

[0018] Figure 8 and Figure 9 Show Figure 1 , Figure 5 and Figures 6A-6B A top view of an alternative embodiment of the image sensor, wherein, Figure 1 , Figure 5 and Figures 6A-6B This illustrates the different possible offsets of the back conductive traces relative to the metal core.

[0019] Figure 10 Cross-sectional views of some embodiments of the image sensor are shown, including a detailed view of the photodetector.

[0020] Figures 11 to 29 Cross-sectional and top views of some embodiments of a method for forming an image sensor with a negative bias circuit coupled to a peripheral region configured to negatively bias a pixel array region are shown.

[0021] Figure 30 A flowchart illustrating some embodiments of a method for forming an image sensor including a negative bias circuit coupled to a peripheral region configured to negatively bias a pixel array region is shown. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0024] Some image sensors include a semiconductor substrate with a photodetector array and a back-side isolation structure disposed within the semiconductor substrate. The back-side isolation structure forms an isolation grid composed of square or ring-shaped grid segments, the outer edges of which are adjacent to each other to form the isolation grid. Each grid segment laterally surrounds one or more photodetectors in the photodetector array and reduces crosstalk between one or more photodetectors and their adjacent photodetectors. Therefore, the back-side isolation structure reduces crosstalk by preventing photons directed towards a first photodetector in the photodetector array from traveling to a second photodetector in the photodetector array and being absorbed / sensed by it. However, as the size of the associated photodetectors and isolation grid decreases, crosstalk between photodetectors increases and the quantum efficiency of the photodetectors decreases.

[0025] One method for improving the performance of an image sensor with a reduced isolation grid size is to negatively bias a back-side isolation structure in a pixel array region. In some embodiments, the image sensor may form a pixel array region including a photodetector and a back-side isolation structure, and a peripheral region including a negative bias circuit coupled to the back-side isolation structure. Therefore, the image sensor includes a through-substrate via that is laterally offset from the back-side isolation structure and extends through the back side of a semiconductor substrate in the peripheral region. A conductive component is disposed above the front side of the semiconductor substrate contacting the through-substrate via. A back-side connection structure disposed within the semiconductor substrate extends across both the pixel array region and the peripheral region and is electrically coupled to the back-side isolation structure. A conductive bridge disposed below the back side of the semiconductor substrate electrically couples the back-side isolation structure to the through-substrate via. The negative bias circuit is coupled to the conductive component and the semiconductor substrate and is configured to apply a negative bias to the back-side isolation structure through the conductive component.

[0026] When a negative bias is applied to the back-side isolation structure, the number of electron-hole pairs adjacent to the back-side isolation structure in the semiconductor substrate decreases compared to the unbiased configuration. Therefore, for the negative bias configuration, the conductivity of the semiconductor substrate on the opposite side of the back-side isolation structure decreases compared to the unbiased configuration. This decrease in conductivity reduces crosstalk between photodetectors and improves the quantum efficiency of the photodetectors. The sensing performance of the image sensor is improved, and the reliability and / or accuracy of the images generated by the image sensor are enhanced.

[0027] Figure 1 A cross-sectional view of some embodiments of an image sensor 100 is shown, the image sensor including a negative bias circuit 134 coupled to a peripheral region 138 of the image sensor. The negative bias circuit 134 is configured to negatively bias a pixel array region 135 of the image sensor.

[0028] Image sensor 100 includes a semiconductor substrate 110, which includes a pixel array region 135, comprising at least one pixel region 136 and a peripheral region 138 laterally offset from the pixel array region 135. In some embodiments, the semiconductor substrate 110 includes any type of semiconductor body (e.g., single-crystal silicon / CMOS bulk, silicon-germanium (SeGe), silicon-on-insulator (SOI), etc.) and / or has a first doping type (e.g., p-type doping). A first dielectric layer 102 is disposed over the front side of the semiconductor substrate 110. A second dielectric layer 106 separates the first dielectric layer 102 from the semiconductor substrate 110. A third dielectric layer 116 is disposed over the back side of the semiconductor substrate 110. The first dielectric layer 102, the second dielectric layer 106, and the third dielectric layer 116 may be, for example, or comprise oxides, such as silicon dioxide, tantalum oxide, dielectrics, low-k dielectrics, or another suitable oxide or dielectric.

[0029] A photodetector 112 is disposed in a semiconductor substrate 110 between a second dielectric layer 106 and a third dielectric layer 116. The photodetector 112 is configured to convert electromagnetic radiation (e.g., photons) into electrical signals. For example, the photodetector 112 may generate electron-hole pairs from the electromagnetic radiation. The photodetector 112 includes a second doping type (e.g., n-type doping) opposite to the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa.

[0030] A back-side isolation structure 115 extends to the back side of the semiconductor substrate 110 and laterally surrounds the pixel array region 135 and the individual pixel regions within the pixel array region 135. The back-side isolation structure 115 includes a first dielectric pad 114, a metal core 124, and a second dielectric pad 118 separating the first dielectric pad 114 from the metal core 124. The first dielectric pad 114 contacts the sidewall of the semiconductor substrate 110. The metal core 124 and the second dielectric pad 118 further extend through a third dielectric layer 116. The second dielectric pad 118 extends along the sidewall and front surface of the metal core 124 and further extends through the back side of the semiconductor substrate 110 to the back surface of the third dielectric layer 116. The first dielectric pad 114 extends along the sidewall and front surface of the second dielectric pad 118 and further extends through the semiconductor substrate 110 to the back surface of the semiconductor substrate 110. The first dielectric pad 114 and the second dielectric pad 118 may be, for example, oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, low-k dielectrics, etc.

[0031] The top surface of the back isolation structure 115 is separated from the front surface of the semiconductor substrate by a shallow trench isolation (STI) structure 108. The STI structure 108 extends across the top surface of the first dielectric pad 114 and continues along the opposite sidewalls of the first dielectric pad 114. The STI structure 108 may be, for example, or include a dielectric material (e.g., silicon dioxide), a low-k dielectric, etc.

[0032] A semiconductor device 104 is disposed in the second dielectric layer 106, protruding into the front side of the semiconductor substrate 110 and coupled to the photodetector 112. In some embodiments, the semiconductor device 104 may be, for example, a transfer transistor. A gate electrode 152 is disposed above the front side of the semiconductor substrate 110, and a gate dielectric 150 separates the gate electrode 152 from the semiconductor substrate 110. The semiconductor device 104 may selectively form a conductive channel between the photodetector 112 and a source / drain region 151 corresponding to a floating diffusion node to transfer accumulated charge (e.g., by absorbing incident radiation) from the photodetector 112 to the source / drain 151. In some embodiments, the gate electrode 152 may include, for example, polysilicon, aluminum, copper, etc. In further embodiments, the gate dielectric 150 may include, for example, oxide, high-k dielectric, etc.

[0033] A color filter layer 120 is disposed on the back side of the second dielectric pad 118, and a fourth dielectric layer 122 is disposed on the back side of the color filter layer 120. A plurality of microlenses 144 are disposed on the back side of the fourth dielectric layer 122. For example, the fourth dielectric layer 122 may be a dielectric material, such as a low-k dielectric or silicon dioxide. The plurality of microlenses may be, for example, a microlens material, such as glass.

[0034] Through-substrate via 130 is laterally offset from the backside isolation structure 115 within the peripheral region 138 and extends through the backside of the third dielectric layer 116, the second dielectric pad 118, the first dielectric pad 114, the semiconductor substrate 110, the second dielectric layer 106, and into the first dielectric layer 102. Shallow trench isolation (STI) structure 148 extends from the backside surface of the second dielectric layer 106 into the semiconductor substrate 110 and laterally surrounds the through-substrate via 130. Through-dielectric pad 132 extends along the outer sidewall of the through-substrate via from below the backside of the third dielectric layer 116 through the semiconductor substrate 110 into the via STI structure 148. Conductive component 126 is disposed within the first dielectric layer 102 and above the frontside of the second dielectric layer 106. Conductive component 126 further contacts the through-substrate via 130. The through-dielectric pad 132 may be, for example, or include oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, low-k dielectrics, etc.

[0035] Through-substrate via 130 is electrically coupled to metal core 124 via connecting metal core 128 and conductive bridge 142. Therefore, conductive component 126 is electrically coupled to metal core 124 via through-substrate via 130. (Brief reference) Figure 2 (It shows) Figure 1 (Top view of the image sensor), the connecting metal core 128 extends from the metal core 124 of the pixel array region 135 to the peripheral region 138. Therefore, the connecting metal core 128 is electrically coupled to the metal core 124. Furthermore, the connecting metal core 128, the first dielectric pad 114, and the second dielectric pad disposed in the peripheral region can be referred to as the back-side connection structure 117 coupled to the back-side isolation structure 115. The conductive bridge 142 is disposed along the back-side surface of the connecting metal core 128 and the back-side surface of the through-substrate via 130. The through-substrate via 130, the metal core 124, the conductive component 126, the back-side conductive trace 140, and the conductive bridge 142 may be, for example, or include aluminum, copper, aluminum-copper, tungsten, etc. As seen in top view 200, the photodetector 112 is disposed within the semiconductor substrate 110 and between the sidewalls of the metal core 124 to create an isolation unit 202. Therefore, the metal core 124 is arranged as an isolation grid, wherein grid segments surround the respective photodetectors 112. An isolation grid consists of square or ring-shaped grid segments whose outer edges are adjacent to each other to form an isolation grid.

[0036] Refer again Figure 1 The negative bias circuit 134 is electrically coupled to the conductive component 126 and the semiconductor substrate 110. The negative bias circuit 134 is configured to apply a negative bias to the metal core 124 through the conductive component 126, the through-substrate via 130, the conductive bridge 142, and the connecting metal core 128. In some embodiments, the negative bias ranges from about -0.01V to -10V.

[0037] A plurality of electron holes 146 are disposed within the semiconductor substrate 110 adjacent to the back isolation structure 115. In some embodiments, the image sensor 100 can switch between different bias states between exposure cycles. Therefore, the image sensor 100 can be configured to apply one or more different bias states at different times, including an unbiased state and a negative bias state. When a negative bias is applied, the negative bias state results in a first number of electron holes 146 that is less than the second number of electron holes resulting from applying the unbiased state. The reduction in the number of electron holes 146 due to the negative bias state, relative to the unbiased state, reduces the conductivity of the semiconductor substrate on the opposite side of the back isolation structure within the semiconductor substrate 110. Similarly, the resistance between the photodetectors 112 increases relative to the unbiased state for the negative bias state.

[0038] Because the negative bias circuit 134 is configured to apply a negative bias to the metal core 124, crosstalk between adjacent photodetectors 112 is reduced, and the quantum efficiency of the photodetectors 112 is increased. Therefore, the sensing performance of the image sensor 100 is improved, and the reliability and / or accuracy of the images generated by the image sensor 100 are enhanced.

[0039] Figure 3 Show Figure 1 A top view 300 of some embodiments of an image sensor, such as Figure 1 and Figure 3 The cutting lines A-A' and C-C' are shown in the diagram. As seen in top view 300, the back conductive trace 140 is arranged as a back metal grid within the color filter layer 120. The back metal grid is composed of square or annular grid segments whose outer edges are adjacent to each other to form the back metal grid. The color filter layer 120 is configured to block electromagnetic radiation in a first frequency range while transmitting electromagnetic radiation in a second frequency range to the photodetector 112 below. The color filter layer 120 may, for example, comprise a dye-based or pigment-based polymer or resin for filtering incident radiation corresponding to specific wavelengths of a color spectrum (e.g., red, green, blue), or comprise a material that allows the transmission of electromagnetic radiation in a specific frequency range while blocking the transmission of electromagnetic radiation at frequencies outside the specific frequency range. The back conductive trace 140 is disposed along the back side of the metal core 124 (see [reference]). Figure 1 And the center of the back conductive trace 140 is aligned with the center of the metal core 124 (see...). Figure 1 ).

[0040] Figure 4A Cross-sectional views of some embodiments of an image sensor 400a including an offset back-side conductive trace 140 are shown. The image sensor 400a illustrates an alternative embodiment with respect to the offset of the back-side conductive trace 140 relative to the metal core 124 (see offset 401). Thus, as shown in offset 401, Figure 4A The sidewall of the middle metal core 124 is offset from the sidewall of the back conductive trace 140, while the conductive trace 140 and the metal core 124 are... Figure 1 Center alignment. In addition to the back conductive trace 140, the image sensor 400a is for… Figure 1 All embodiments described herein share the same description. For ease of explanation, Figure 4A omitted in Figure 1 Some components.

[0041] In the image sensor 400a, a back conductive trace 140 is disposed within the color filter layer 120 and along the back surface of the metal core 124 and offset aligned with the metal core 124. The back conductive trace 140 overlaps with the back surface of the second dielectric pad 118, wherein the surface of the back conductive trace 140 continuously extends from the second dielectric pad 118 to the metal core 124.

[0042] Figure 4B Cross-sectional views of some embodiments of an image sensor 400b, including an irregular dielectric layer 402, are shown. An alternative embodiment of the image sensor 400b is shown with respect to the irregular dielectric layer 402 protruding into the outer wall of the back conductive trace 140. In addition to the back conductive trace 140 and the irregular dielectric layer 402, the image sensor 400b is... Figure 1 All embodiments described herein share the same description. For ease of explanation, Figure 4B omitted in Figure 1 Some components.

[0043] In the image sensor 400b, a back-side conductive trace 140 is disposed within the color filter layer 120 and along the back surface of the metal core 124, aligned with the metal core 124. An irregular dielectric layer 402 is disposed along the back side of the second dielectric pad 118 and protrudes into the opposing sidewall of the back-side conductive trace 140. The portion of the irregular dielectric layer 402 protruding into the back-side conductive trace 140 includes irregular sidewalls having a series of curved shapes 404. Furthermore, a portion of the irregular dielectric layer 402 extends toward the back side of the back-side conductive trace 140, wherein a first region of the irregular dielectric layer 402 defined by the conductive trace 140 has a first thickness that is thicker than a second region of the irregular dielectric layer 402 adjacent to the back-side conductive trace 140. The irregular dielectric layer 402 may be, for example, or include oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, etc. The irregular dielectric layer 402 may, for example, have... to The thickness range.

[0044] Figure 4C Cross-sectional views of some embodiments of an image sensor 400c, including an offset back-side conductive trace 140 and an irregular dielectric layer 402, are shown. The image sensor 400c is shown in an alternative embodiment with respect to the offset back-side conductive trace 140 disposed on the back surface of the irregular dielectric layer 402. In addition to the back-side conductive trace 140, the metal core 124, and the irregular dielectric layer 402, the image sensor 400c... Figure 1 All embodiments described herein share the same description. For ease of explanation, Figure 4C omitted in Figure 1 Some components.

[0045] In the image sensor 400c, an irregular dielectric layer 402 is disposed along the back surface of a second dielectric pad 118 and the back surface of a metal core 124. The metal core 124 extends from a first back surface of the dielectric pad 118 to below a second back surface of the dielectric pad 118. The metal core 124 protrudes into the irregular dielectric layer 402, such that the front surface of the irregular dielectric layer 402 includes an irregular surface having a series of curved shapes. Figure 4CAn irregular dielectric layer 402 separates the metal core 124 from the back conductive trace 140. A color filter layer 120 is disposed along the back surface of the irregular dielectric layer 402. The back conductive trace 140 is disposed within the color filter layer 120 and along the back surface of the irregular dielectric layer 402. The back conductive trace 140 is offset-aligned with the metal core 124. The back conductive trace 140 overlaps with the back surface of the second dielectric pad 118, wherein the surface of the back conductive trace 140 continuously extends from the second dielectric pad 118 to the metal core 124. The irregular dielectric layer 402 may be, for example, or include oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, etc. The irregular dielectric layer 402 may, for example, have... to The thickness range.

[0046] Figure 5 Show Figure 4A Top view 500 of some embodiments of the image sensor 400a, such as Figure 4A and Figure 5 The cutting lines C-C' and D-D' are shown.

[0047] As seen in top view 500, the metal core 124 is arranged as an isolation grid and the back conductive trace 140 is arranged as a back metal grid. For ease of illustration, Figure 4A The color filter layer 120 is omitted to show the offset alignment of the back conductive trace 140 relative to the metal core 124. The vertical members of the back metal grid are offset to the left of the vertical members of the isolation grid. The horizontal members of the back metal grid are offset below the horizontal members of the isolation grid.

[0048] Figure 6A Cross-sectional views of some embodiments of an image sensor 600a including a separation layer 602 are shown. The image sensor 600a illustrates an alternative embodiment with respect to the separation layer 602 separating the back conductive trace 140 from the metal core 124. In addition to the back conductive trace 140, color filter layer 120, separation layer 602, and conductive bridge 142, the image sensor 600a... Figure 1 All embodiments described herein share the same description. For ease of explanation, Figure 6A omitted in Figure 1 Some components.

[0049] In the image sensor 600a, a separation layer 602 is disposed along the back surface of the metal core 124 and along the back surface of the second dielectric pad 118 in the pixel array region 135. Furthermore, the separation layer 602 is disposed along the second dielectric pad 118, along the back surface connecting the metal core 128, along the back surface penetrating the dielectric pad 132, and along the back surface of the through-substrate via 130 in the peripheral region 138. The separation layer 602 may be, for example, an oxide, a metal oxide, aluminum oxide, hafnium oxide, a high-k dielectric, a low-k dielectric, etc. A color filter layer 120 is disposed along the back surface of the separation layer 602 in the pixel region. A conductive bridge 142 is disposed along the back surface of the separation layer 602 in the peripheral region 138. A back conductive trace 140 is disposed within the color filter layer 120 and along the back surface of the separation layer 602. In some embodiments, the center of the back conductive trace 140 is offset from the center of the metal core 124. In other embodiments (not shown), the center of the back conductive trace 140 is aligned with the center of the metal core 124, for example, as... Figure 1 As shown, the back conductive trace 140 is aligned with the metal core 124. In some embodiments, the back conductive trace 140 is electrically coupled to the metal core 124, but in other embodiments, the back conductive trace 140 is electrically isolated from the metal core 124.

[0050] Figure 6B Cross-sectional views of some embodiments of an image sensor 600b are shown, including a separation layer 602 and a back separation trace 604. Image sensor 600a shows alternative embodiments with respect to the separation layer 602 separating the back conductive trace 140 from the metal core 124 and the back separation trace 604 separating the back conductive trace 140 from the metal core 124. In addition to the semiconductor substrate 110, first dielectric pad 114, third dielectric layer 116, second dielectric pad 118, back conductive trace 140, color filter layer 120, separation layer 602, and back separation trace 604, image sensor 600b also includes... Figure 1 All embodiments described herein share the same description. For ease of explanation, Figure 6B omitted in Figure 1 Some components.

[0051] In image sensor 600b, a third dielectric layer protrudes into semiconductor substrate 110 and separates second dielectric pad 118 from first dielectric pad 114 in both pixel array region 135 and peripheral region 138. A separation layer 602 is disposed in pixel array region 135 along the back surface of metal core 124 and along the back surface of second dielectric pad 118. Separation layer 602 may be, for example, or include oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, low-k dielectrics, etc. Color filter layer 120 is disposed along the back surface of separation layer 602 in pixel region. Back surface conductive trace 140 is disposed within color filter layer 120 aligned with metal core 124. Back surface separation trace 604 is disposed along the back surface of separation layer 602 and separates back surface conductive trace 140 from separation layer 602. Back surface separation trace 604 may be, for example, or include aluminum, copper, aluminum-copper, tungsten, titanium nitride, etc. In some embodiments, the metal core 124, the back separation trace 604, and the back conductive trace 140 comprise the same material. In other embodiments, the metal core 124, the back separation trace 604, and the back conductive trace 140 comprise different materials. For example, the metal core 124 is aluminum copper, the back separation trace 604 is titanium nitride, and the back conductive trace 140 is tungsten.

[0052] Figure 7 Show Figure 6A A top view 700 of some embodiments of the image sensor 600a, such as... Figure 6A and Figure 7 The cutting lines C-C' and D-D' are shown.

[0053] As seen in top view 700, the metal core 124 is arranged as an isolation grid and the back conductive trace 140 is arranged as a back metal grid. For ease of illustration, Figure 6A The color filter layer 120 is omitted to show the separation layer 602 disposed along the front surface of the back metal grid.

[0054] Figure 8 and Figure 9 Show respectively Figure 1 , Figures 4A to 4C , Figure 6A and Figure 6B Top views 800 and 900 of optional embodiments of image sensors 100, 400a-400c, 600a and 600b respectively show different possible offsets of the back conductive trace 140 relative to the metal core 124.

[0055] As seen in top views 800 and 900, the metal core 124 is arranged as an isolation grid and the back conductive trace 140 is arranged as a back metal grid. For ease of illustration, Figure 4A Color filter layer 120 and Figure 6AThe separation layer 602 is omitted to show the offset alignment of the back conductive trace 140 relative to the metal core 124. In the top view 800, the vertical members of the back metal grid are offset to the left of the vertical members of the isolation grid, wherein a first gap exists between the sidewalls of the vertical members of the back metal grid and the sidewalls of the vertical members of the isolation grid. The horizontal members of the back metal grid are offset above the horizontal members of the isolation grid, wherein a second gap exists between the sidewalls of the horizontal members of the back metal grid and the sidewalls of the horizontal members of the isolation grid.

[0056] In top view 900, the vertical members of the back metal grid are offset to the right of the vertical members of the isolation grid, and the horizontal members of the back metal grid are offset below the vertical members of the isolation grid. The sidewalls of the horizontal and vertical members of the back metal grid overlap with the sidewalls of the horizontal and vertical members of the isolation grid.

[0057] Top views 800 and 900 do not limit the offset between the back metal grid and the isolation grid. In alternative embodiments (not shown), the back metal grid may be offset relative to the isolation grid in other ways. For example, the vertical members of the back metal grid may be offset to the right or left of the vertical members of the isolation grid. Furthermore, the horizontal members of the back metal grid may be offset above or below the horizontal members of the isolation grid. The back metal grid may be aligned, overlapped, or separated from the isolation grid by a certain gap. Furthermore, the relationship between the vertical and horizontal members and the offset of the back metal grid relative to the isolation grid may depend on the spatial position between the back metal grid and the isolation grid. For example, a first offset may occur at the center of the back metal grid and the isolation grid, and a second offset may occur at the periphery of the back metal grid and the isolation grid. The first offset may be... Figure 1 The scenario depicted shows the back metal grid and isolation grid aligned. The second offset could be... Figure 8 The scenario depicted shows that the sidewalls of the back metal grid and the sidewalls of the isolation grid are separated by a certain gap. Furthermore, different areas of the back metal grid and the isolation grid may include additional offset scenes or combinations of offset scenes. Figure 8 and Figure 9 Optional embodiments may arise due to registration differences during manufacturing.

[0058] Figure 10 Cross-sectional views of some embodiments of the image sensor 1000 are shown, including a detailed view of the photodetector 112. In addition to optional embodiments concerning the photodetector 112, the metal core 124, and the STI structure 108, the image sensor 1000... Figure 1 All embodiments described herein share the same description.

[0059] In the image sensor 1000, a photodetector 112 is disposed below the back surface of the second dielectric layer 106. The photodetector 112 may be configured as a single-photon avalanche diode (SPAD). A SPAD can detect incident radiation of very low intensity (e.g., single photons). In some embodiments, a SPAD may be used, for example, in near-infrared (NIR) direct time-of-flight (D-TOF) applications.

[0060] The SPAD may include a first p-type doped region 1004 disposed on the back side of the second dielectric layer 106. A metal core extends to the back side of the semiconductor substrate. Figure 1 The P-type implant 1002 laterally surrounds the first P-type doped region 1004. The P-type implant 1002 separates the metal core 124 from the second dielectric layer 106. The P-type implant 1002 restores the photosensing function that may have been lost due to the manufacturing process of forming the metal core 124. The STI structure 108 laterally surrounds a portion of the P-type implant 1002 and the metal core 124 and extends from the back side of the second dielectric layer 106.

[0061] The SPAD also includes a first N-type doped region 1010, a second N-type doped region 1014, a third N-type doped region 1008, a fourth N-type doped region 1006, and a second P-type doped region 1012. Doped regions 1010, 1014, 1008, 1006, and 1012 are disposed below the back surface of the second dielectric layer 106 and within the first P-type doped region 1004. The second N-type doped region 1014 surrounds the lateral sidewalls and back surface of the first N-type doped region 1010. The second P-type doped region 1012 is disposed below the back surface of the second N-type doped region 1014. The third N-type doped region 1008 surrounds the lateral sidewalls of the second N-type doped region 1014 and the second P-type doped region 1012. The fourth N-type doped region 1006 surrounds the lateral sidewalls of the third N-type doped region 1008.

[0062] N-type doped regions 1010, 1014, 1008, and 1006 may include different doping concentrations. For example, the doping concentration of the first N-type doped region 1010 is higher than that of the second N-type doped region 1014.

[0063] The doping concentration of the second N-type doped region 1014 is higher than that of the third N-type doped region 1008.

[0064] The doping concentration of the third N-type doped region 1008 is higher than that of the fourth N-type doped region 1006. The N-type doped regions 1010, 1014, 1008, and 1006 may, for example, include regions ranging from 10... 10 Up to 10 18 atoms / cm 3The doping concentration of the second P-type doped region 1012 can be higher than that of the first P-type doped region 1004. The P-type doped regions 1004 and 1012 can, for example, include regions ranging from 10... 10 Up to 10 15 atoms / cm 3 The doping concentration.

[0065] Figures 11 to 29 Cross-sectional and top views of some embodiments of a method for forming an image sensor having a negative bias circuit 134 coupled to a peripheral region 138 configured to negatively bias a pixel array region 135 are shown. Although Figures 11 to 29 The cross-sectional views 1100-2900 shown are described with reference to one method, but it should be understood that... Figures 11 to 29 The structure shown is not limited to this method, but can be used independently of it. Furthermore, although Figures 11 to 29 The actions are described as a series of actions, but it should be understood that these actions are not limited to other embodiments where the order of the actions may be changed, and the disclosed method is also applicable to other structures. In other embodiments, some actions illustrated and / or described may be omitted in whole or in part. Furthermore, Figures 1 to 10 The alternative embodiments depicted are available as alternatives. Figures 11 to 29 Examples are shown, although they may not be shown.

[0066] like Figure 11 As shown in cross-sectional view 1100, a photodetector 112 is formed within the pixel array region 135 of the semiconductor substrate 110. A second dielectric layer 106 is formed above the top side of the semiconductor substrate 110. A semiconductor device 104 is formed within the second dielectric layer 106 and protrudes into the front side of the semiconductor substrate 110, and is coupled to the photodetector 112. In some embodiments, the semiconductor substrate 110 includes any type of semiconductor body (e.g., single-crystal silicon / CMOS bulk, silicon-germanium (SeGe), silicon-on-insulator (SOI), etc.) and / or has a first doping type (e.g., p-type doping).

[0067] In some embodiments, the semiconductor device 104 may be, for example, a transfer transistor. A gate electrode 152 is disposed above the front side of the semiconductor substrate 110, and a gate dielectric 150 separates the gate electrode 152 from the semiconductor substrate 110. The semiconductor device 104 may selectively form a conductive channel between the photodetector 112 and the source / drain region 151 corresponding to the floating diffusion node to transfer accumulated charge (e.g., by absorbing incident radiation) from the photodetector 112 to the source / drain 151. In some embodiments, the gate electrode 152 may include, for example, polysilicon, aluminum, copper, etc. In further embodiments, the gate dielectric 150 may include, for example, oxides, high-k dielectrics, etc.

[0068] STI structure 108 is formed along the back side of the second dielectric layer 106 within the pixel array region 135 of the semiconductor substrate 110. STI structure 108 laterally surrounds the photodetector 112. Through-hole STI structure 148 is formed along the back side of the second dielectric layer 106 and within a peripheral region 138 of the semiconductor substrate 110, which is laterally offset from the pixel array region 135. STI structure 108 and through-hole STI structure 148 may be, for example, or include a dielectric material (e.g., silicon dioxide), a high-k dielectric, etc.

[0069] like Figure 12 As shown in cross-sectional view 1200, the first dielectric layer 102 is deposited above the front side of the second dielectric layer 106. For ease of illustration, Figure 12 omitted in Figure 11 Some components. In some embodiments, the first dielectric layer 102 may be deposited, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) processes, or other suitable growth or deposition processes. The first dielectric layer 102 is patterned to define a conductive component opening (not shown) within the first dielectric layer 102 above the top surface of the via STI structure 148. A conductive material (e.g., by PVD, CVD, ALD, etc.) is deposited within the conductive component opening forming the conductive component 126. The conductive component 126 may be, for example, aluminum, copper, aluminum-copper, tungsten, etc.

[0070] A hard mask layer 1202 is deposited on the back side of the semiconductor substrate 110. In some embodiments, the hard mask layer 1202 may be deposited, for example, by a PVD, CVD, or ALD process and may be or comprise a silicon-based material, such as silicon nitride.

[0071] like Figure 13 As shown in cross-sectional view 1300, a first patterning process is performed on the hard mask layer 1202 and the semiconductor substrate 110 to form a cavity opening 1302 in the pixel array region 135 and a cavity opening 1304 in the peripheral region 138. The cavity opening 1302 laterally surrounds the photodetector 112 and exposes the sidewalls of the semiconductor substrate 110, the back surface of the STI structure 108, and the sidewalls of the vertical portion of the STI structure 108. The width 1306 of the cavity opening 1302 can be, for example, about 0.12 micrometers (μm), in the range of about 0.1 μm to about 0.14 μm, or other suitable values. The cavity opening 1304 is formed to be laterally offset from the via STI structure 148.

[0072] For example, patterning may include either photolithography or etching. In some embodiments (not shown), photoresist is formed on a hard mask layer ( Figure 12Above 1202. The photoresist is patterned using an acceptable photolithography technique to develop the exposed photoresist. With the exposed photoresist in place, etching is performed to transfer the pattern from the exposed photoresist to underlying layers, such as the semiconductor substrate 110 and the hard mask layer 1202, to define cavity openings 1302, 1304. The etching process may include a wet etching process, a dry etching process, or some other suitable etching process.

[0073] like Figure 14 As shown in the cross-sectional diagram 1400, the hard mask layer ( Figure 13 The 1202 layer was removed. The hard mask layer ( Figure 13 The 1202) can be removed, for example, by chemical cleaning, etching, planarization, ashing, or other suitable removal processes. The first dielectric pad 114 runs along the back surface of the semiconductor substrate 110, with openings in the cavity ( Figure 13 The first dielectric pad 114 is disposed on the sidewalls of the exposed semiconductor substrate 110 (1302, 1304), the sidewalls of the vertical portion of the STI structure 108, and the back surface of the STI structure 108. A third dielectric layer 116 is deposited over the back surface and sidewalls of the first dielectric pad 114. The first dielectric pad 114 may be, for example, or include oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, low-k dielectrics, etc. In some embodiments, the first dielectric pad 114 may be deposited, for example, by PVD, CVD, ALD, plasma-enhanced CVD (PECVD), plasma-enhanced ALD (PEALD) processes, or other suitable processes. to The thickness of the first dielectric layer 102, the second dielectric layer 106, and the third dielectric layer 116 may be, for example, or include oxides, such as silicon dioxide, tantalum oxide, dielectrics, low-k dielectrics, high-k dielectrics, or another suitable oxide or dielectric. In some embodiments, the third dielectric layer 116 may be deposited, for example, by PVD, CVD, ALD processes or other suitable processes.

[0074] like Figure 15As shown in cross-sectional view 1500, a second etching process is performed on the third dielectric layer 116 to form a cavity opening 1502 in the pixel array region 135 and a cavity opening 1504 in the peripheral region 138. The cavity openings 1502 and 1504 expose the bottom surface of the first dielectric pad 114, the sidewalls of the first dielectric pad 114, and the sidewalls of the third dielectric layer 116 in the pixel array region 135 and the peripheral region 138. In some embodiments, the second etching process may include: 1) forming a hard mask (not shown) over the third dielectric layer 116; 2) exposing the unmasked area of ​​the third dielectric layer 116 to one or more etchants until the back surface of the first dielectric pad 114 is reached; and 3) performing a removal process to remove the mask layer. In some embodiments, etching may include a wet etching process, a dry etching process, or other suitable etching processes. In some embodiments, the opening cavities 1502 and 1504 in the third dielectric layer 116 may be wider than the inner sidewall of the first dielectric pad 114, as shown by line 1506, such that there is a transverse “step” between the inner sidewall of the first dielectric pad 114 and the inner sidewall of the third dielectric layer 116.

[0075] like Figure 16 As shown in cross-sectional view 1600, the second dielectric pad 118 is deposited along the sidewall of the third dielectric layer 116, along the sidewall of the first dielectric pad 114, and along the back surface of the first dielectric pad 114 in both the pixel array region 135 and the peripheral region 138 above the back surface of the third dielectric layer 116. The second dielectric pad 118 is deposited in the cavity opening ( Figure 15 In (1502, 1504), a back isolation trench 1602 is formed in the pixel array region 135, and a back connection trench 1604 is formed in the peripheral region 138 defined by the sidewalls of the second dielectric pad 118. The back isolation trench 1602 and the back connection trench 1604 extend through the third dielectric layer 116 and into the semiconductor substrate 110. The second dielectric pad 118 may be, for example, or include oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, low-k dielectrics, etc. In some embodiments, the second dielectric pad 118 may be deposited, for example, by PVD, CVD, ALD, PECVD, PEALD processes or other suitable processes, with a thickness of approximately In Approximate to Within the range, or for other suitable values.

[0076] Figure 17 Show Figure 16 Top view 1700 of some embodiments of the cross-sectional view 1600, such as Figure 16 and Figure 17 The cutting lines A-A' and B-B' are shown in the diagram. For ease of explanation, Figure 17 omitted in Figure 16 Some components.

[0077] As seen in top view 1700, the back isolation trench 1602 is arranged as a back isolation trench grid 1602 such that the back isolation trench 1602 intersects with the back connection trench 1604. A photodetector 112 is disposed within the semiconductor substrate 110 and between the sidewalls of the semiconductor substrate 110. The photodetector 112 is configured to convert electromagnetic radiation (e.g., photons) into electrical signals. For example, the photodetector 112 may generate electron-hole pairs from the electromagnetic radiation. The photodetector 112 includes a second doping type (e.g., n-type doping) opposite to the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa.

[0078] like Figure 18 As shown in the cross-sectional view 1800, the back isolation trench is filled. Figure 16 and Figure 17 1602) and back connection groove ( Figure 16 and Figure 17 (1604) to form metal core 124 and connecting metal core 128. Forming metal core 124 and connecting metal core 128 may, for example, include: 1) depositing a first conductive layer (not shown) covering the back surface of the second dielectric pad 118, and filling the back isolation trench ( Figure 16 and Figure 17 1602) and back connection groove ( Figure 16 and Figure 17 The first dielectric pad 114, the second dielectric pad 118 (not shown), and the second dielectric pad 118 are: 1) a portion of the first conductive layer (not shown) flush with the back surface of the second dielectric pad 118; and 2) a portion of the first conductive layer (not shown) to which the first conductive layer (not shown) is removed. The portion of the first conductive layer (not shown) to be removed can be, for example, by a chemical cleaning process, an etching process, a planarization process, or other suitable removal process. The metal core 124 and the connecting metal core 128 can be, for example, aluminum, copper, aluminum-copper, tungsten, etc. The first dielectric pad 114, the metal core 124, and the second dielectric pad 118 form a back isolation structure 115 extending to the back surface of the semiconductor substrate 110 and laterally surrounding the pixel array region 135. The first dielectric pad 114, the second dielectric pad 118, and the connecting metal core 128 form a back connection structure 117 coupled to the back isolation structure 115 and extending from the pixel array region 135 to the peripheral region 138.

[0079] Figure 19 Show Figure 18 Top view 1900 of some embodiments of the cross-sectional view 1800, such as Figure 18 and Figure 19 The cutting lines A-A' and B-B' are shown in the diagram.

[0080] As seen in top view 1900, the metal core 124 is arranged as an isolation grid. The isolation grid is composed of square or annular grid segments whose outer edges are adjacent to each other to form the isolation grid. A photodetector 112 is disposed within the semiconductor substrate 110 (see...). Figure 18 The metal core 128 is connected between the metal core 124 forming the isolation unit 202 and the sidewall of the metal core 124. The metal core 128 is formed to extend from the isolation grid in the pixel array area 135 to the peripheral area 138.

[0081] like Figure 20 As shown in cross-sectional view 2000, a third etching process is performed on the second dielectric pad 118, the third dielectric layer 116, the first dielectric pad 114, the semiconductor substrate 110, and the via STI structure 148 to form a via cavity opening 2002. In some embodiments, the third etching process may include: 1) forming a hard mask (not shown) above the back surface of the second dielectric pad 118 and the back surfaces of both the metal core 124 and the connecting metal core 128; 2) exposing the unmasked areas of the second dielectric pad 118 and the underlying layer to one or more etchants until the one or more etchants etch into the via STI structure 148 and reach the back surface of the via STI structure 148; 3) performing a removal process to remove the mask layer. In some embodiments, the third etching may include a wet etching process, a dry etching process, or other suitable etching processes.

[0082] The through-dielectric pad 132 is deposited along the back surface of the second dielectric pad 118 and the back surface of the metal core 124 and the connecting metal core. The through-dielectric pad 132 is further deposited along the sidewalls of the via STI structure 148 in the second dielectric pad 118, the third dielectric layer 116, the first dielectric pad 114, the semiconductor substrate 110, and the via cavity opening 2002. The through-dielectric pad 132 is also deposited along the back surface of the via STI structure 148. The through-dielectric pad 132 may be, for example, or include oxides, metal oxides, aluminum oxide, hafnium oxide, high-k dielectrics, low-k dielectrics, etc.

[0083] like Figure 21 As shown in cross-sectional view 2100, a fourth etching is performed to remove a portion of the dielectric pad 132 through the back surface of the second dielectric pad 118, and to etch through the dielectric pad 132, the via STI structure 148, the second dielectric layer 106, and into the conductive component 126, thereby exposing the back surface of the conductive component 126. In some embodiments, the fourth etching may include: 1) opening the via cavity ( Figure 201) A first hard mask (not shown) is formed above the sidewall of the through dielectric pad 132 in 2002); 2) The unmasked area of ​​the through dielectric pad 132 is exposed to one or more etchants until the back surface of the second dielectric pad 118, the metal core 124, and the connecting metal core 128 is reached; and the via STI structure is reached; 3) A second hard mask (not shown) is formed above the back surface of the second dielectric pad 118, the metal core 124, and the connecting metal core 128 to expose the back surface of the via STI structure 148; 4) The unmasked area of ​​the back surface of the via STI structure 148 and the underlying layer are exposed to one or more etchants until the back surface of the conductive component 126 is reached; 5) A removal process is performed to remove the first mask layer (not shown) and the second mask layer (not shown).

[0084] After the fourth etching is completed, a second conductive layer 2102 is deposited above the back surface of the second dielectric pad 118, the metal core 124, and the connecting metal core 128. The second conductive layer 2102 is further deposited to fill the via cavity opening. Figure 20 The second conductive layer 2102 covers the sidewalls of the dielectric pad 132, the via STI structure 148, the second dielectric layer 106, and the conductive component 126, and also covers the back surface of the conductive component 126. In some embodiments, the second conductive layer 2102 may be deposited, for example, by PVD, CVD, ALD processes or other suitable processes. The second conductive layer 2102 may be, for example, aluminum, copper, aluminum-copper, tungsten, etc. In some embodiments, the second conductive layer 2102 is substantially composed of aluminum. In other embodiments, the second conductive layer 2102 is substantially composed of tungsten. Furthermore, the second conductive layer 2102 is located at the opening of the via cavity ( Figure 20 In the 2002), a through-substrate via 130 is formed and a conductive bridge 142 is formed in the peripheral region 138 above the back surface of the second dielectric pad 118 and the connecting metal core 128, wherein the conductive bridge 142 electrically couples the connecting metal core 128 to the through-substrate via 130.

[0085] like Figure 22 As shown in cross-sectional view 2200, a fifth etching process is performed to form a back conductive trace 140 in the pixel array region 135, wherein the back conductive trace 140 extends above the back surface of the metal core 124 and between the sidewalls of the metal core 124. In some embodiments, the fifth etching process includes: 1) forming a mask layer (not shown) over the second conductive layer 2102, wherein the sidewalls of the unmasked area are aligned with the sidewalls of the metal core 124 in the pixel array region 135, and forming a mask layer (not shown) over the conductive bridge 142 in the peripheral region 138; 2) exposing the unmasked area of ​​the second conductive layer 2102 to one or more etchants until the back surface of the second dielectric pad 118 is reached;

[0086] 3) A removal process is performed to remove the mask layer. In some embodiments, the fifth etching process may include performing wet etching, dry etching, or other suitable etching processes. Upon completion of the fifth etching process, the center of the back conductive trace 140 is aligned with the center of the metal core 124.

[0087] Figure 23 Show Figure 22 Top view 2300 of some embodiments of cross-sectional view 2200, such as Figure 22 and Figure 23 The cutting lines A-A' and B-B' are shown in the diagram. As seen in top view 2300, a conductive bridge 142 is formed above the back side of the through-substrate via 130, above the back side of the connecting metal core, and extends vertically from the conductive member 126. A plurality of through-substrate vias 130 are formed to electrically couple to the metal core 124 via the connecting metal core 128 and the conductive bridge 142. Furthermore, a plurality of through-substrate vias 130 are formed to electrically couple to the conductive member 126.

[0088] Figure 24 The cross-sectional view 2400 shows Figure 22 In an optional embodiment of cross-sectional view 2200, an optional offset is formed between the metal core 124 and the connecting metal core 128. In the method... Figure 24 exist Figure 21 Before.

[0089] like Figure 24 As shown in cross-sectional view 2400, a fifth etching process is performed to form a back conductive trace 140 in the pixel array region 135, wherein the back conductive trace 140 extends above the back surface of the metal core 124 and the back surface of the second dielectric pad 118, such that the center of the back conductive trace 140 is offset from the center of the metal core 124. In some embodiments, the fifth etching process includes: 1) forming a mask layer (not shown) over the second conductive layer 2102, wherein the sidewalls of the unmasked area are located above the metal core 124 and the second dielectric pad 118 in the pixel array region 135; forming a mask layer (not shown) over a second portion of the conductive bridge 142 in the peripheral region 138; 2) exposing the unmasked area of ​​the second conductive layer 2102 to one or more etchants until the back surfaces of the second dielectric pad 118 and the metal core 124 are reached; 3) performing a removal process to remove the mask layer. In some embodiments, the fifth etching process may include performing wet etching, dry etching, or other suitable etching processes. When the fifth etching process is completed, the center of the back conductive trace 140 is laterally offset from the center of the metal core 124, and the conductive bridge 142 exists in the peripheral region 138.

[0090] Figure 25 Show Figure 24Top view 2500 of some embodiments of cross-sectional view 2400, such as Figure 24 and 25 The cutting lines C-C' and D-D' are shown in the diagram.

[0091] As seen in top view 2500, the metal core 124 is formed as an isolation grid and the back conductive trace 140 is formed as a back metal grid. The vertical members of the back metal grid are offset to the left of the vertical members of the isolation grid. The horizontal members of the back metal grid are offset below the horizontal members of the isolation grid.

[0092] Figure 26 The cross-sectional view 2600 shows Figure 21 An alternative embodiment of cross-sectional view 2100 shows a separation layer 602 formed above the back surface of the second dielectric pad 118. In the method Figure 26 exist Figure 20 Before.

[0093] like Figure 26 As shown in cross-sectional view 2600, a fourth etching is performed to remove a portion of the dielectric pad 132 through the back surface of the second dielectric pad 118, and to etch through the dielectric pad 132, the via STI structure 148, the second dielectric layer 106, and into the conductive component 126, thereby exposing the back surface of the conductive component 126. The fourth etching includes... Figure 21 The same fourth etching step described in [the text]. After completing the fourth etching, through-substrate via 130 is deposited to fill the via cavity opening ( Figure 20 The through-substrate via 130 (2002) covers the sidewalls of the through-substrate dielectric pad 132, the via STI structure 148, and the conductive component 126, and also covers the back surface of the conductive component 126. The through-substrate via 130 may be, for example, aluminum, copper, aluminum-copper, tungsten, etc. In some embodiments, the through-substrate via 130 may be deposited, for example, by PVD, CVD, ALD processes or other suitable processes.

[0094] A separation layer 602 is deposited above the back surface of the second dielectric pad 118, the metal core 124, the connecting metal core 128, the through dielectric pad 132, and the through substrate via 130. The separation layer 602 may be, for example, an oxide, a metal oxide, alumina, hafnium oxide, a high-k dielectric, a low-k dielectric, etc. In some embodiments, the separation layer 602 may be deposited, for example, by PVD, CVD, ALD processes or other suitable processes. to The thickness is specified. The conductive trace layer 2602 is deposited on the back surface of the separation layer 602 in both the pixel array region 135 and the peripheral region 138. The conductive trace layer 2602 can be, for example, aluminum, copper, aluminum-copper, tungsten, etc. In some embodiments, the conductive trace layer 2602 is substantially composed of aluminum. In other embodiments, the conductive trace layer 2602 is substantially composed of tungsten.

[0095] Figure 27 The cross-sectional view 2700 shows Figure 22 and Figure 24 In alternative embodiments of cross-sectional views 2200 and 2400, an offset is formed between the metal core 124 and the connecting metal core 128 separated from the second dielectric pad 118 by a separation layer. In the method flow, Figure 27 exist Figure 26 Before.

[0096] like Figure 27 As shown in cross-sectional view 2700, a fifth etching process is performed to form a back conductive trace 140 in the pixel array region 135, wherein the back conductive trace 140 extends over the metal core 124 and the second dielectric pad 118 such that the center of the back conductive trace 140 is offset from the center of the metal core 124. In some embodiments, the fifth etching process includes: 1) a conductive trace layer in the pixel array region 135 and the peripheral region 138 ( Figure 26 A mask layer (not shown) is formed above the first portion of 2602), wherein the sidewalls of the unmasked area are below the metal core 124 and the second dielectric pad 118; 2) a conductive trace layer ( Figure 26 The unmasked area of ​​the 2602) is exposed to one or more etchants until the back surface of the release layer 602 is reached; 3) a removal process is performed to remove the mask layer. In some embodiments, the fifth etching process may include performing wet etching, dry etching or other suitable etching processes. Upon completion of the fifth etching process, the center of the back conductive trace 140 is laterally offset from the center of the metal core 124 and the conductive bridge 142 is formed along the back surface of the release layer 602 in the peripheral region 138.

[0097] Figure 28 Show Figure 27 Top view 2800 of some embodiments of cross-sectional view 2700, such as Figure 27 and 28 The cutting lines C-C' and D-D' are shown. As seen in top view 2800, the metal core 124 is arranged as an isolation grid and the back conductive trace 140 is arranged as a back metal grid. The vertical members of the back metal grid are formed to be offset to the left of the vertical members of the isolation grid. The horizontal members of the back metal grid are offset above the horizontal members of the isolation grid.

[0098] Figures 24 to 28The alternative embodiments do not limit the offset between the back metal grid and the isolation grid. The back metal grid and the isolation grid can be formed to reflect... Figures 4A to 9 The components discussed herein. In an alternative embodiment (not shown), the back metal grid may be formed to be offset relative to the isolation grid in other ways. For example, the vertical members of the back metal grid may be formed to be offset to the right or left of the vertical members of the isolation grid. Furthermore, the horizontal members of the back metal grid may be formed to be offset above or below the horizontal members of the isolation grid. The back metal grid may be formed to be aligned, overlapped, or separated from the isolation grid by a certain gap. Furthermore, the relationship between the vertical and horizontal members and the offset of the back metal grid relative to the isolation grid may depend on the spatial position between the back metal grid and the isolation grid. For example, a first offset may occur at the center of the back metal grid and the isolation grid, and a second offset may occur at the periphery of the back metal grid and the isolation grid. The first offset may be... Figure 22 The scenario depicted shows the back metal grid and isolation grid aligned. The second offset could be... Figures 8 to 9 , Figure 24 or Figure 27 The offset depicted in any of them. In addition, different areas of the back metal grid and isolation grid may include additional offset scenes or combinations of offset scenes. Figures 24 to 28 Optional embodiments may arise due to registration differences during manufacturing.

[0099] Figure 29 Cross-sectional view 2900 in Figure 22 Before cross-sectional view 2200, cross-sectional view 2900 shows the formation of a color filter layer 120, a fourth dielectric layer 122, and multiple microlenses 144, as well as a negative bias circuit 134, in pixel array region 135.

[0100] like Figure 29As shown in cross-sectional view 2900, a color filter layer 120 is deposited on the back surface of the back conductive trace 140 and the second dielectric pad, and above the sidewalls of the back conductive trace 140 in the pixel array region 135. The color filter layer 120 may, for example, comprise a dye-based or pigment-based polymer or resin for filtering incident radiation corresponding to specific wavelengths of a color spectrum (e.g., red, green, blue), or comprise a material that allows the transmission of electromagnetic radiation having a specific frequency range while transmitting electromagnetic radiation at frequencies outside that specific frequency range. A fourth dielectric layer 122 is deposited above the back surface of the color filter layer 120, and a plurality of microlenses 144 are formed on the back surface of the fourth dielectric layer 122. Thus, the plurality of microlenses 144 and the underlying structure form a pixel array region 135 including at least one pixel region 136. The fourth dielectric layer 122 may, for example, be a bulk substrate (e.g., a bulk silicon substrate), an SOI substrate, or some other suitable substrate. The plurality of microlenses may, for example, be a microlens material. The color filter layer 120, the fourth dielectric layer 122, and the multiple microlenses 144 can be formed by a combination of deposition and etching processes.

[0101] A negative bias circuit 134 is electrically coupled to a conductive component 126 and a semiconductor substrate 110. The negative bias circuit is configured to apply a negative bias to the metal core 124 through the conductive component 126, a through-substrate via 130, and a connecting metal core 128. A plurality of electron holes 146 may be disposed within the semiconductor substrate 110 adjacent to a backside isolation structure 115. The negative bias circuit 134 is configured to apply a negative bias to the metal core 124 during a negative bias state to reduce the number of electron holes 146 relative to an unbiased state. Because the negative bias circuit 134 is configured to apply a negative bias to the metal core 124, crosstalk between adjacent photodetectors 112 is reduced, and the quantum efficiency of the photodetectors 112 is increased. Therefore, the sensing performance of the image sensor 100 is improved, and the reliability and / or accuracy of the images generated by the image sensor 100 are enhanced.

[0102] Figure 30 A flowchart illustrating some embodiments of a method 3000 for forming an image sensor including a negative bias circuit coupled to a peripheral region configured to negatively bias a pixel region is shown.

[0103] At operation 3002, a photodetector is formed within the pixel region of the semiconductor substrate. A second dielectric layer is formed above the top surface of the semiconductor substrate. An STI structure is formed along the back side of the second dielectric layer that laterally surrounds the photodetector 112. Conductive components are formed within the second dielectric layer surrounding the image sensor. Figure 11 Cross-sectional view 1100 shows some embodiments corresponding to action 3002.

[0104] At action 3004, a first etching is performed on the semiconductor substrate to expose openings in the pixel region and peripheral region of the semiconductor substrate. The etching exposes the back surface of the STI structure in the pixel region. Figure 12 and Figure 13 Cross-sectional views 1200 and 1300 are shown, respectively, corresponding to some embodiments of action 3004.

[0105] At action 3006, a first dielectric pad is deposited along the exposed surfaces of the semiconductor substrate and the STI structure. A third dielectric layer is deposited above the back surface of the first dielectric pad and fills the opening created by the first etching. A second etching is performed to expose the third dielectric layer and the sidewalls of the first dielectric pad within the semiconductor substrate. Figure 14 and Figure 15 Cross-sectional views 1400 and 1500 are shown, respectively, corresponding to some embodiments of action 3006.

[0106] At action 3008, a second dielectric pad is deposited along the surface of the third dielectric layer, and a first dielectric pad is deposited in the opening created by the second etching. Metal cores and connection metal cores are deposited within the sidewalls of the second dielectric pads in the pixel region and the peripheral region. A third and fourth etching are performed in the peripheral region to form through-substrate vias coupled to conductive components in the peripheral region. Conductive trace layers are deposited on the back surfaces of the metal cores, the second dielectric layer, the connection metal cores, and the through-substrate vias. Figures 16 to 21 Cross-sectional views 1600 and 2100 are shown, respectively, of some embodiments corresponding to action 3008.

[0107] At action 3010, a conductive trace layer is etched to form a conductive bridge in the peripheral region that electrically couples the connecting metal core to a through-hole in the substrate, and conductive traces aligned or offset from the metal core are formed in the pixel region above the back surface of the metal core. Figures 22 to 28 Cross-sectional views 2200 to 2800 are shown, each corresponding to one of the embodiments of action 3010.

[0108] At action 3012, a color filter layer and multiple microlenses are formed above the conductive trace. A negative bias circuit is formed, coupled to the through-hole in the substrate and the semiconductor substrate. Figure 29 Cross-sectional view 2900 shows some embodiments corresponding to action 3012.

[0109] Although method 3000 is shown and / or described as a series of actions or events, it should be understood that method 3000 is not limited to the shown order or actions. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or actions may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0110] Some embodiments relate to an image sensor. The image sensor includes: a semiconductor substrate including a pixel region and a peripheral region. A back-side isolation structure extends into the back side of the semiconductor substrate and laterally surrounds the pixel region. The back-side isolation structure includes a metal core, and a dielectric pad separates the metal core from the semiconductor substrate. A conductive component is disposed above the front side of the semiconductor substrate. A through-substrate via extends from the back side of the semiconductor substrate through the peripheral region to contact the conductive component. The through-substrate via is laterally offset from the back-side isolation structure. A conductive bridge is disposed below the back side of the semiconductor substrate and electrically couples the metal core of the back-side isolation structure to the through-substrate via.

[0111] In some embodiments, the image sensor further includes: a back-side connection structure extending across both the pixel region and the peripheral region and in direct contact with both the conductive bridge and the metal core of the back-side isolation structure. In some embodiments, the image sensor further includes: a back-side conductive trace located directly beneath and aligned with the metal core of the back-side isolation structure. In some embodiments, the image sensor further includes: a separation layer comprising a dielectric material disposed between the back-side conductive trace and the metal core of the back-side isolation structure. In some embodiments, the back-side conductive trace comprises aluminum or tungsten. In some embodiments, the image sensor further includes: a back-side conductive trace located directly beneath and laterally offset from the metal core of the back-side isolation structure. In some embodiments, the image sensor further includes: an additional through-substrate via extending from the back side of the semiconductor substrate through the peripheral region and laterally spaced from the through-substrate via, the additional through-substrate via being electrically coupled to the pixel region and in direct contact with the conductive component. In some embodiments, the image sensor further includes: a negative bias circuit coupled to the conductive component and configured to apply a negative bias to the metal core through the conductive component. In some embodiments, the image sensor further includes an additional pixel region adjacent to the pixel region, wherein the negative bias increases the resistance between the pixel region and the additional pixel region.

[0112] An image sensor includes: a semiconductor substrate including pixel regions laterally offset from the peripheral region. A back-side isolation structure extends into the back side of the semiconductor substrate and laterally surrounds the pixel regions. A through-substrate via extends through the semiconductor substrate in the peripheral region and is electrically coupled to the back-side isolation structure via a conductive bridge disposed below the back side of the semiconductor substrate. A conductive member is disposed above the front side of the semiconductor substrate and is electrically coupled to the through-substrate via. A negative bias circuit is configured to apply a first bias state and a second bias state across the back-side isolation structure and the semiconductor substrate at different times via the conductive member.

[0113] In some embodiments, the first bias state is a negative bias that reduces the number of electron-hole pairs adjacent to the backside isolation structure within the semiconductor substrate relative to the second bias state. In some embodiments, the first bias state reduces the conductivity of the semiconductor substrate on the opposite side of the backside isolation structure relative to the second bias state. In some embodiments, the image sensor further includes: an isolation dielectric layer separating the conductive component from the semiconductor substrate. In some embodiments, the image sensor further includes: a through-dielectric pad disposed above the backside of the semiconductor substrate and separating the through-substrate via from the semiconductor substrate. In some embodiments, the backside isolation structure includes a metal core extending into the backside of the semiconductor substrate, and the image sensor further includes: a backside conductive trace located below the metal core, wherein the center of the backside conductive trace is offset from the center of the metal core. In some embodiments, the backside isolation structure includes a metal core extending into the backside of the semiconductor substrate, and the image sensor further includes: a separation layer including a dielectric material disposed between the backside conductive trace and the backside isolation structure, wherein the backside conductive trace extends through the separation layer to be electrically coupled to the metal core. In some embodiments, the back-side isolation structure includes a metal core extending into the back side of the semiconductor substrate in the trench, and the image sensor further includes: a first dielectric pad disposed along the inner sidewall of the trench; a second dielectric pad disposed along the inner sidewall of the first dielectric layer and separating the metal core from the first dielectric pad; and a dielectric layer that vertically separates the bottom surface of the first dielectric pad from the second dielectric pad.

[0114] A method of forming an image sensor includes: forming conductive components on the front side of a semiconductor substrate; patterning the semiconductor substrate to form back isolation trenches and back connection trenches in a pixel region such that the back isolation trenches intersect the back connection trenches; patterning through-holes extending through the semiconductor substrate in a peripheral region laterally offset from the pixel region; providing a conductive material to form back isolation structures in the back isolation trenches, back connection structures in the back connection trenches, and through-substrate vias in the through-holes to contact the conductive components; and forming conductive bridges over the back surface of the through-substrate vias and the back surface of the back connection structures.

[0115] In some embodiments, the method further includes forming a dielectric pad along the sidewalls of the back isolation trench, the back connection trench, and the through hole before providing the conductive material. In some embodiments, the method further includes forming a metal layer covering the back isolation structure over the pixel region; and patterning the metal layer to form an isolation grid aligned with the back isolation structure.

[0116] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An image sensor, comprising: Semiconductor substrate, including pixel area and peripheral area; A back-side isolation structure extends to the back side of the semiconductor substrate and laterally surrounds the pixel region. The back-side isolation structure includes a metal core, a first dielectric pad, and a second dielectric pad. The metal core extends into a trench on the back side of the semiconductor substrate. The first dielectric pad is disposed along the inner sidewall of the trench. The second dielectric pad is disposed along the inner sidewall of the first dielectric pad and separates the metal core from the first dielectric pad. A dielectric layer is disposed on the back side of the semiconductor substrate, wherein a first dielectric pad extends from the trench to the back side of the semiconductor substrate, and a second dielectric pad extends from the trench to the back side of the dielectric layer away from the semiconductor substrate; A conductive component is disposed above the front side of the semiconductor substrate; A through-substrate via extends from the back side of the semiconductor substrate through the peripheral region to contact the conductive component, the through-substrate via being laterally offset from the back side isolation structure; as well as A conductive bridge is disposed below the back side of the semiconductor substrate and electrically couples the metal core of the back side isolation structure to the through-substrate via.

2. The image sensor according to claim 1, further comprising: The back-side connection structure extends across both the pixel area and the peripheral area and is in direct contact with both the conductive bridge and the metal core of the back-side isolation structure.

3. The image sensor according to claim 1, further comprising: The back conductive trace is located directly below the metal core of the back isolation structure and aligned with the metal core of the back isolation structure.

4. The image sensor according to claim 3, further comprising: The separation layer includes a dielectric material disposed between the metal core of the back conductive trace and the back isolation structure.

5. The image sensor according to claim 4, wherein, The conductive traces on the back side include aluminum or tungsten.

6. The image sensor according to claim 1, further comprising: The back conductive trace is located directly below the metal core of the back isolation structure and is laterally offset from the metal core of the back isolation structure.

7. The image sensor according to claim 1, further comprising: An additional through-substrate via extends from the back side of the semiconductor substrate through the peripheral region and is laterally spaced from the through-substrate via. The additional through-substrate via is electrically coupled to the pixel region and is in direct contact with the conductive component.

8. The image sensor according to claim 1, further comprising: A negative bias circuit is coupled to the conductive component and configured to apply a negative bias to the metal core through the conductive component.

9. The image sensor according to claim 8, further comprising: An additional pixel region is adjacent to the pixel region, wherein the negative bias increases the resistance between the pixel region and the additional pixel region.

10. An image sensor, comprising: A semiconductor substrate, including a pixel region laterally offset from the peripheral region; A back-side isolation structure extends into the back side of the semiconductor substrate and laterally surrounds the pixel region. The back-side isolation structure includes a metal core, a first dielectric pad, and a second dielectric pad. The metal core extends into a trench on the back side of the semiconductor substrate. The first dielectric pad is disposed along the inner sidewall of the trench. The second dielectric pad is disposed along the inner sidewall of the first dielectric pad and separates the metal core from the first dielectric pad. A dielectric layer is disposed on the back side of the semiconductor substrate, wherein a first dielectric pad extends from the trench to the back side of the semiconductor substrate, and a second dielectric pad extends from the trench to the back side of the dielectric layer away from the semiconductor substrate; Through-substrate vias extend through the semiconductor substrate in the peripheral region and are electrically coupled to the back isolation structure via conductive bridges disposed below the back side of the semiconductor substrate; A conductive component is disposed above the front side of the semiconductor substrate and electrically coupled to the through-substrate via; as well as A negative bias circuit is configured to apply a first bias state and a second bias state at different times through the conductive component across the back isolation structure and the semiconductor substrate.

11. The image sensor according to claim 10, wherein, The first bias state is a negative bias, which reduces the number of electron-hole pairs adjacent to the back-side isolation structure within the semiconductor substrate relative to the second bias state.

12. The image sensor according to claim 10, wherein, The first bias state reduces the conductivity of the semiconductor substrate on the opposite side of the back isolation structure relative to the second bias state.

13. The image sensor according to claim 10, further comprising: An isolation dielectric layer separates the conductive component from the semiconductor substrate.

14. The image sensor of claim 10, further comprising: A through-substrate via is disposed above the back side of the semiconductor substrate and separates the through-substrate via from the semiconductor substrate.

15. The image sensor according to claim 10, wherein, The back-side isolation structure includes a metal core extending into the back side of the semiconductor substrate, and further includes: A back conductive trace is located below the metal core, wherein the center of the back conductive trace is offset from the center of the metal core.

16. The image sensor according to claim 10, wherein, The back-side isolation structure includes a metal core extending into the back side of the semiconductor substrate, and further includes: The separation layer includes a dielectric material disposed between the back conductive trace and the back isolation structure, wherein the back conductive trace extends through the separation layer to be electrically coupled to the metal core.

17. The image sensor according to claim 10, wherein, The dielectric layer vertically separates the bottom surface of the first dielectric pad from the second dielectric pad.

18. A method for forming an image sensor, comprising: Conductive components are formed on the front side of a semiconductor substrate; The semiconductor substrate is patterned to form back isolation trenches and back connection trenches in the pixel area, such that the back isolation trenches intersect with the back connection trenches; Patterning is performed on the through-holes extending through the semiconductor substrate in a peripheral region laterally offset from the pixel region; A conductive material is provided to form a back isolation structure in the back isolation trench, a back connection structure in the back connection trench, and a through-substrate via in the through-hole for contact with the conductive component. Forming the back isolation structure includes: forming a first dielectric pad of the back isolation structure in the back isolation trench and on the back side of the semiconductor substrate; forming a dielectric layer on the first dielectric pad on the back side of the semiconductor substrate; forming a second dielectric pad of the back isolation structure extending along the inner sidewall of the first dielectric pad to the back side of the dielectric layer; and forming a metal core of the back isolation structure on the second dielectric pad. A conductive bridge is formed on the back surface of the through-substrate via and above the back surface of the back connection structure.

19. The method according to claim 18, wherein, The metal core is arranged as an isolation grid.

20. The method of claim 18, further comprising: A metal layer covering the back isolation structure is formed above the pixel area; as well as The metal layer is patterned to form an isolation grid aligned with the back isolation structure.

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