Transparent display device

Abstract

A transparent display device. The transparent display device minimizes coupling between signal lines and applies repair structures to scan lines. The transparent display device includes: a substrate having a light-transmitting area and a plurality of sub-pixels disposed between the light-transmitting area; a first anode electrode and a second anode electrode disposed in each of the plurality of sub-pixels; a first connecting electrode connecting the first anode electrode and the second anode electrode; a driving transistor disposed in each of the plurality of sub-pixels; and a second connecting electrode disposed below the driving transistor, electrically connecting the driving transistor to the first connecting electrode.

Description

Technical Field

[0001] This disclosure relates to a transparent display device. Background Technology

[0002] With the advancement of the information society, the demand for display devices for displaying images has increased in various forms. Recently, various types of display devices, such as liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diode (OLED) displays, and quantum dot light-emitting diode (QLED) displays, have been widely used.

[0003] Recently, research has been actively conducted on transparent display devices, which allow users to view objects or images arranged on the opposite side of the display device.

[0004] A transparent display device includes a display area and a non-display area for displaying images, wherein the display area may include a light-transmitting area and a non-light-transmitting area that allow external light to pass through. The transparent display device can achieve high light transmittance within the display area through the light-transmitting area.

[0005] In transparent display devices, short circuits can occur between the anode and cathode due to particles. This can lead to black spots. Because transparent display devices have a smaller light-emitting area than conventional display devices, the light loss rate caused by black spots may be increased. Summary of the Invention

[0006] This disclosure was made in view of the above problems, and the purpose of this disclosure is to provide a transparent display device that can reduce or minimize the light loss rate due to the presence of dark spots.

[0007] Another technical advantage of this disclosure is that it provides a transparent display device that can reduce or minimize the degradation of transparency caused by repair lines.

[0008] In addition to the technical advantages of this disclosure described above, those skilled in the art will clearly understand additional technical advantages and features of this disclosure from the following description.

[0009] According to one aspect of this disclosure, the above and other technical advantages can be achieved by providing a transparent display device, the transparent display device comprising: a substrate having a light-transmitting area and a plurality of sub-pixels disposed between the light-transmitting area; a first anode electrode and a second anode electrode disposed in each of the plurality of sub-pixels; a first connecting electrode connecting the first anode electrode and the second anode electrode; a driving transistor disposed in each of the plurality of sub-pixels; and a second connecting electrode disposed below the driving transistor and electrically connected to the driving transistor and the first connecting electrode.

[0010] According to another aspect of this disclosure, the above and other technical advantages can be achieved by providing a transparent display device, which includes: a substrate having a light-transmitting area and a plurality of sub-pixels disposed between the light-transmitting area; a first anode electrode and a second anode electrode disposed in each of the plurality of sub-pixels; a first connecting electrode connecting the first anode electrode and the second anode electrode; a driving transistor disposed in each of the plurality of sub-pixels; and a second connecting electrode disposed outside the first connecting electrode, electrically connecting the driving transistor to the first connecting electrode. Attached Figure Description

[0011] The above and other objects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure;

[0013] Figure 2 This is a schematic plan view illustrating a transparent display panel according to one embodiment of the present disclosure;

[0014] Figure 3 This is an example Figure 2 A magnified view of region A;

[0015] Figure 4 This is an example Figure 3 A magnified view of region B;

[0016] Figure 5 It is along Figure 4 A cross-sectional view taken from line II′;

[0017] Figure 6 It is along Figure 4 A cross-sectional view taken from line II-II′;

[0018] Figure 7 This is a diagram illustrating an example of a setup with multiple signal lines and multiple drive transistors;

[0019] Figure 8 It is along Figure 7 A cross-sectional view taken from line III-III′;

[0020] Figure 9 It is along Figure 7 A cross-sectional view taken from line IV-IV′;

[0021] Figure 10 This is a diagram illustrating an example of how reference lines and scan lines are set in the intersection area;

[0022] Figure 11This is another example illustrating a setup with multiple signal lines and multiple drive transistors; and

[0023] Figure 12 This is another example illustrating the setting of reference lines and scan lines in the intersection area. Detailed Implementation

[0024] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following description of embodiments in conjunction with the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0025] The shapes, dimensions, scales, angles, and quantities disclosed in the drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. Throughout the specification, similar reference numerals refer to similar elements. In the following description, detailed descriptions of relevant known functions or constructions will be omitted where it is determined that they unnecessarily obscure the essential points of this disclosure. Where the terms “comprising,” “having,” and “including” are used as described in this specification, an additional part may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0026] When interpreting components, although there is no explicit description, the components are interpreted as including a range of error.

[0027] When describing positional relationships, for example, when the positional relationship is described as "on top of," "above," "below," and "below," one or more parts may be arranged between the two parts unless "only" or "directly" is used.

[0028] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0029] In describing the elements of this disclosure, the terms “first,” “second,” etc., may be used. These terms are intended to identify the corresponding elements from other elements, and the basis, order, or number of the corresponding elements is not limited by these terms. Unless specifically mentioned, the expression “connected” or “linked” to another element should be understood as meaning that the element can be directly connected or linked to another element, or that a third element can be inserted between the corresponding elements.

[0030] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure can be partially or entirely linked or combined with each other, and can be interoperable and technically driven in various ways. Embodiments of this disclosure can be implemented independently of each other or together in an interdependent relationship.

[0031] In the following description, examples of transparent display devices according to this disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0032] Figure 1 This is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure.

[0033] In the following text, the X-axis represents the line parallel to the scan line, the Y-axis represents the line parallel to the data line, and the Z-axis represents the height direction of the transparent display device 100.

[0034] Although the specification has been described based on an embodiment of the transparent display device 100 according to this disclosure as an organic light-emitting display device, the transparent display device 100 may be implemented as a liquid crystal display device, a plasma display panel (PDP), a quantum dot light-emitting display (QLED), or an electrophoretic display device.

[0035] Reference Figure 1 According to one embodiment of the present disclosure, a transparent display device 100 includes a transparent display panel 110, a source driver integrated circuit (IC) 210, a flexible film 220, a circuit board 230, and a timing controller 240.

[0036] The transparent display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be an encapsulation substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using semiconductor processes. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 111 and the second substrate 112 may be made of transparent materials.

[0037] The scan driver can be disposed on one side of the display area of ​​the transparent display panel 110 using a gate-in-panel (GIP) method, or in the non-display areas on both peripheral sides of the transparent display panel 110. Alternatively, the scan driver can be fabricated in a driver chip, mounted on a flexible film, and attached to one or both peripheral sides of the display area of ​​the transparent display panel 110 using a tape-on-board (TAB) method.

[0038] If the source driver IC 210 is manufactured in the driver chip, the source driver IC 210 can be mounted on the flexible film 220 by the chip-on-film (COF) method or the chip-on-plastic (COP) method.

[0039] Pads such as power pads and data pads can be formed in the pad area PA of the transparent display panel 110. Lines connecting the pads to the source driver IC 210 and lines connecting the circuit board 230 to the pads can be formed in the flexible film 220. The flexible film 220 can be attached to the pads using an anisotropic conductive film, thereby allowing the pads to connect to the lines on the flexible film 220.

[0040] Figure 2 This is a schematic plan view of a transparent display panel according to one embodiment of the present disclosure. Figure 3 This is an example Figure 2 A magnified view of region A. Figure 4 This is an example Figure 3 A magnified view of region B. Figure 5 It is along Figure 4 The cross-sectional view taken from line II′, and Figure 6 It is along Figure 4 The cross-sectional view taken from line II-II′.

[0041] Reference Figure 2 and Figure 6 The transparent display panel 110 may include a display area DA with pixels P for displaying images and a non-display area NDA for not displaying images.

[0042] The non-display area NDA can be configured with a pad area PA and at least one scan driver 205, and pads PAD are configured in the pad area PA.

[0043] Scan driver 205 is connected to scan line SL and provides scan signals to scan line SL. Scan driver 205 can be disposed in the non-display area NDA on one side of the display area DA of the transparent display panel 110 or on the two peripheral sides of the transparent display panel 110 using an in-panel gate driver (GIP) method. For example, as... Figure 2 As shown, the scan driver 205 can be formed on both sides of the display area DA of the transparent display panel 110, but these scan drivers are not limited to this. The scan driver 205 can also be formed only on one side of the display area DA of the transparent display panel 110.

[0044] The display area DA includes a light-transmitting area TA and a light-blocking area NTA. The light-transmitting area TA is the region through which most external incident light passes, while the light-blocking area NTA is the region through which most external incident light cannot pass. For example, the light-transmitting area TA can be an area with a transmittance greater than α% (e.g., about 90%), and the light-blocking area NTA can be an area with a transmittance less than or less than β% (e.g., about 50%). In this case, α is greater than β. Due to the light-transmitting area TA, the user can view objects or backgrounds arranged on the rear surface of the transparent display panel 110.

[0045] The non-transparent area NTA can be provided with multiple pixels P and multiple first signal lines SL1 and multiple second signal lines SL2 for providing signals to each of the multiple pixels P.

[0046] Multiple first signal lines SL1 may extend in a first direction (e.g., the Y-axis direction). Multiple second signal lines SL2 may extend in a second direction (e.g., the X-axis direction). The multiple second signal lines SL2 may intersect or overlap with the multiple first signal lines SL1.

[0047] The light-transmitting area TA can be positioned between adjacent first signal lines SL1. The light-transmitting area TA can also be positioned between adjacent second signal lines SL2. That is, the light-transmitting area TA can be surrounded by two first signal lines SL1 and two second signal lines SL2.

[0048] Pixel P can be configured to overlap with at least one of the first signal line SL1 and the second signal line SL2, thereby emitting predetermined light to display an image. The light-emitting area EA can correspond to the area in pixel P that emits light.

[0049] Each pixel P may include at least one of a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. The first sub-pixel P1 may include a first emitting region EA1 that emits green light. The second sub-pixel P2 may include a second emitting region EA2 that emits red light. The third sub-pixel P3 may include a third emitting region EA3 that emits blue light. The fourth sub-pixel P4 may include a fourth emitting region EA4 that emits white light. However, the emitting regions are not limited to this example. Each pixel P may also include sub-pixels that emit light of colors other than red, green, blue, and white. Furthermore, the arrangement order of sub-pixels P1, P2, and P3 can be varied in various ways.

[0050] Meanwhile, the light-emitting areas EA1, EA2, EA3, and EA4, respectively located in multiple sub-pixels P1, P2, P3, and P4, can include light-emitting areas divided into multiple regions. Specifically, the first light-emitting area EA1 located in the first sub-pixel P1 can include two segmented regions, namely, a first segmented light-emitting area EA1-1 and a second segmented light-emitting area EA1-2. The second light-emitting area EA2 located in the second sub-pixel P2 can include two segmented regions, namely, a first segmented light-emitting area EA2-1 and a second segmented light-emitting area EA2-2. The third light-emitting area EA3 located in the third sub-pixel P3 can include two segmented regions, namely, a first segmented light-emitting area EA3-1 and a second segmented light-emitting area EA3-2. The fourth light-emitting area EA4 located in the fourth sub-pixel P4 can include two segmented regions, namely, a first segmented light-emitting area EA4-1 and a second segmented light-emitting area EA4-2.

[0051] In the following text, for ease of description, the first sub-pixel P1 is a green sub-pixel that emits green light, the second sub-pixel P2 is a red sub-pixel that emits red light, the third sub-pixel P3 is a blue sub-pixel that emits blue light, and the fourth sub-pixel P4 is a white sub-pixel that emits white light.

[0052] The first sub-pixel P1 and the second sub-pixel P2 can be configured to overlap with at least a portion of the first signal line SL1 and be arranged alternately along the first signal line SL1.

[0053] The third sub-pixel P3 and the fourth sub-pixel P4 can be configured to overlap with at least a portion of the second signal line SL2 and be arranged alternately along the second signal line SL2.

[0054] The third sub-pixel P3 and the fourth sub-pixel P4 can be set in the area where the first signal line SL1 and the second signal line SL2 intersect or overlap, such as Figure 3 As shown, but not limited to.

[0055] In another embodiment, the first sub-pixel P1 and the second sub-pixel P2 can be located in the area where the first signal line SL1 and the second signal line SL2 intersect or overlap. In this case, the third sub-pixel P3 and the fourth sub-pixel P4 can be spaced apart from each other, and the first sub-pixel P1 and the second sub-pixel P2 are interposed between them in the area where the first signal line SL1 and the second signal line SL2 intersect or overlap.

[0056] Circuit elements including capacitors, thin-film transistors, and light-emitting diodes can be disposed in each of the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4. The thin-film transistors may include switching transistors, sensing transistors, and driving transistors TR.

[0057] The switching transistor switches on and off according to the scan signal provided to the scan line, so as to supply the data voltage provided from the data line to the driving transistor TR.

[0058] The sensing transistor is used to sense the threshold voltage deviation of the driving transistor TR, which causes image quality degradation.

[0059] The driving transistor TR switches according to the data voltage supplied from the switching thin-film transistor to generate a data current from the power supply provided by the pixel power line, thereby supplying the generated data current to the anode electrode 120 of the sub-pixel. The driving transistor TR includes an active layer ACT, a gate GE, a source SE, and a drain DE.

[0060] The capacitor Cst is used to hold the data voltage supplied to the driving transistor TR for one frame. The capacitor Cst may include two capacitor electrodes, but is not limited to this. In one embodiment, the capacitor Cst may include three capacitor electrodes.

[0061] Specifically, the active layer ACT can be disposed on the first substrate 111. The active layer ACT can be formed of silicon-based semiconductor material or oxide-based semiconductor material.

[0062] A light-shielding layer LS, used to block external light from entering the active layer ACT and the first capacitor electrode CE1, can be disposed between the active layer ACT and the first substrate 111, such as... Figure 5 and Figure 6 As shown. The light-shielding layer LS and the first capacitor electrode CE1 can be integrally formed and can be made of a conductive material. For example, the light-shielding layer LS can be formed as a single layer or multiple layers of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or alloys thereof. In this case, a buffer film BF can be provided between the light-shielding layer LS and the active layer ACT.

[0063] The gate insulating film GI can be disposed on the active layer ACT. The gate insulating film GI can be formed as an inorganic film, such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film of SiOx and SiNx.

[0064] The gate electrode GE and the second capacitor electrode CE2 can be disposed on the gate insulating film GI. The gate electrode GE and the second capacitor electrode CE2 can be formed as a single layer or multiple layers of any one of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu or alloys thereof.

[0065] The interlayer insulating layer (ILD) can be disposed above the gate electrode GE and the second capacitor electrode CE2. The ILD can be formed as an inorganic layer, such as a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a multilayer of SiOx and SiNx.

[0066] The source (SE), drain (DE), and third capacitor electrode (CE3) can be disposed on the interlayer insulating layer (ILD). One of the source (SE) and drain (DE) can be connected to the active layer (ACT) through a contact hole passing through the gate insulating film (GI) and the interlayer insulating layer (ILD).

[0067] The source electrode SE, drain electrode DE, and third capacitor electrode CE3 can be formed from a single layer or multiple layers of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or their alloys.

[0068] A passivation layer PAS can be provided above the source (SE), drain (DE), and third capacitor electrode (CE3) to protect the drive transistor (TR). A planarization layer PLN can be disposed above the passivation layer PAS to planarize the step difference caused by the drive transistor TR. The planarization layer PLN can be formed of an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0069] A light-emitting diode composed of an anode electrode 120, an organic light-emitting layer 130, and a cathode electrode 140, and a dam 125 are disposed on the planarization layer PLN.

[0070] The anode electrode 120 can be disposed on the planarization layer PLN and connected to the driving transistor TR. Specifically, the anode electrode 120 can be connected to the source SE or drain DE of the driving transistor TR through a contact hole, and the anode electrode 120 can be electrically connected to the driving transistor TR.

[0071] An anode electrode 120 can be provided for each of sub-pixels P1, P2, P3, and P4. One anode electrode 120 can be provided in the first sub-pixel P1, another anode electrode 120 can be provided in the second sub-pixel P2, another anode electrode 120 can be provided in the third sub-pixel P3, and another anode electrode 120 can be provided in the fourth sub-pixel P4. The anode electrodes 120 are not provided in the light-transmitting area TA.

[0072] The anode electrode 120 can be formed from highly reflective metallic materials such as aluminum and titanium deposition structures (Ti / Al / Ti), aluminum and ITO deposition structures (ITO / Al / ITO), Ag alloys, and Ag alloy and ITO deposition structures (ITO / Ag alloy / ITO), MoTi alloys, and MoTi alloy and ITO deposition structures (ITO / MoTi alloy / ITO). The Ag alloy can be an alloy of silver (Ag), palladium (Pb), and copper (Cu). The MoTi alloy can be an alloy of molybdenum (Mo) and titanium (Ti).

[0073] Multiple anode electrodes 120 may be disposed in each of the multiple sub-pixels P1, P2, P3 and P4. For example, the anode electrode 120 disposed in each of the multiple sub-pixels P1, P2, P3 and P4 may include a first anode electrode 121, a second anode electrode 122 and a first connecting electrode ACE.

[0074] The first anode electrode 121 can be disposed in the first segmented light-emitting regions EA1-1, EA2-1, EA3-1 and EA4-1, and the second anode electrode 122 can be disposed in the second segmented light-emitting regions EA1-2, EA2-2, EA3-2 and EA4-2. The first anode electrode 121 and the second anode electrode 122 can be spaced apart from each other in the same layer.

[0075] The first connecting electrode ACE can connect the first anode electrode 121 to the second anode electrode 122. Specifically, the first connecting electrode ACE may include a first anode connecting portion ACE1, a second anode connecting portion ACE2, and a third anode connecting portion ACE3, such as... Figure 4 As shown.

[0076] The first anode connection portion ACE1 can extend a predetermined length from the first anode electrode 121 toward the light-transmitting area TA. The second anode connection portion ACE2 can extend a predetermined length from the second anode electrode 122 toward the light-transmitting area TA. In this case, the second anode connection portion ACE2 can be disposed on a first side of the first anode connection portion ACE1 to be adjacent to the first anode connection portion ACE1. The third anode connection portion ACE3 can connect one end of the first anode connection portion ACE1 to one end of the second anode connection portion ACE2. Therefore, the first anode electrode 121 can be electrically connected to the second anode electrode 122 through the first connecting electrode ACE.

[0077] The first anode connection portion ACE1, the second anode connection portion ACE2, and the third anode connection portion ACE3 can be integrally formed in the same layer with the first anode electrode 121 and the second anode electrode 122. The area formed by the first anode connection portion ACE1, the second anode connection portion ACE2, and the third anode connection portion ACE3 can be a non-transparent area NTA. The transparent area TA can be disposed between the first anode connection portion ACE1 and the second anode connection portion ACE2.

[0078] The anode electrode 120 can be electrically connected to the driving transistor TR via the second connection electrode TCE. Specifically, the second connection electrode TCE may include a first transistor connection portion TCE1 and a second transistor connection portion TCE2.

[0079] The first transistor connection portion TCE1 can be disposed on the second side of the first anode connection portion ACE1 to be adjacent to the first anode connection portion ACE1. The first transistor connection portion TCE1 can extend a predetermined length from the light-shielding layer LS in the direction of the light-transmitting region TA. At this time, the light-shielding layer LS can be electrically connected to the source SE or drain DE of the driving transistor TR through the first contact hole CH1, such as... Figure 5 As shown. Therefore, the first transistor connection part TCE1 can also be electrically connected to the source SE or drain DE of the driving transistor TR.

[0080] The second transistor connection portion TCE2 can be bent from the first transistor connection portion TCE1 toward the first connection electrode ACE and extend a predetermined length in the direction of the first connection electrode ACE. At this time, at least a portion of the second transistor connection portion TCE2 can overlap with the third anode connection portion ACE3. The second transistor connection portion TCE2 can be electrically connected to the third anode connection portion ACE3 in the area where it overlaps with the third anode connection portion ACE3 through a contact hole.

[0081] To connect the second transistor connection portion TCE2 to the third anode connection portion ACE3, an intermediate connection electrode ICE can also be provided between the second transistor connection portion TCE2 and the third anode connection portion ACE3, such as... Figure 5 As shown. In this case, the intermediate connecting electrode ICE can be electrically connected to the second transistor connecting part TCE2 through the second contact hole CH2, and can be electrically connected to the third anode connecting part ACE3 through the third contact hole CH3.

[0082] Although Figure 6 The second transistor connection portion TCE2 is shown to be connected to the third anode connection portion ACE3 via an intermediate connection electrode ICE, but this disclosure is not limited thereto. In another embodiment, the second transistor connection portion TCE2 may be directly connected to the third anode connection portion ACE3.

[0083] In a transparent display panel 110 according to one embodiment of the present disclosure, a first transistor connection portion TCE1 is connected to the source SE or drain DE of a driving transistor TR, and a second transistor connection portion TCE2 extending from the first transistor connection portion TCE1 is electrically connected to a third anode connection portion ACE3. As a result, the anode electrode 120 can be electrically connected to the source SE or drain DE of the driving transistor TR through the first connection electrode ACE and the second connection electrode TCE.

[0084] The first transistor connection portion TCE1 and the second transistor connection portion TCE2 can be integrally formed in the same layer as the light-shielding layer LS. Therefore, the area where the first transistor connection portion TCE1 and the second transistor connection portion TCE2 are formed can be a non-transparent region NTA. The transparent region TA can be disposed between the first transistor connection portion TCE1 and the first anode connection portion ACE1.

[0085] When a transparent display panel 110 according to one embodiment of the present disclosure malfunctions by driving transistor TR, the transparent display panel 110 can be repaired by laser cutting the second connection electrode TCE along the first laser cutting line LC1.

[0086] In addition, if either the first anode electrode 121 or the second anode electrode 122 malfunctions due to particles that may appear during the process, the transparent display panel 110 can be repaired by laser cutting at least one of the first anode connection portion ACE1 or the second anode connection portion ACE2 of the first connecting electrode ACE.

[0087] For example, when a short circuit occurs between the anode electrode 120 and the cathode electrode 140 due to particles in the area where the first anode electrode 121 is disposed, the transparent display panel 110 according to an embodiment of the present disclosure can be repaired by laser cutting the first anode connection portion ACE1 along the second laser cutting line LC2.

[0088] As another example, when a short circuit occurs between the anode electrode 120 and the cathode electrode 140 due to particles in the area where the second anode electrode 122 is disposed, the transparent display panel 110 according to one embodiment of the present disclosure can be repaired by laser cutting the second anode connection portion ACE2 along the third laser cutting line LC3.

[0089] In a transparent display panel 110 according to one embodiment of the present disclosure, even if black spots appear on the corresponding anode electrodes of the plurality of anode electrodes 121 and 122 due to particles, they can be short-circuited by laser cutting, thereby reducing the light loss rate caused by the appearance of dark spots.

[0090] A transparent display panel 110 according to one embodiment of the present disclosure is characterized in that the second connection electrode TCE and the light-shielding layer LS are formed in the same layer. In the transparent display panel 110 according to one embodiment of the present disclosure, when the second connection electrode TCE is formed in the same layer as the gate GE or source SE of the driving transistor TR, the horizontal spacing between the first connection electrode ACE and the second connection electrode TCE is increased, thereby reducing or minimizing interference during laser cutting.

[0091] In addition, a transparent display panel 110 according to one embodiment of the present disclosure is characterized in that a second connection electrode TCE is disposed outside the first connection electrode ACE.

[0092] As described above, the region where the first connecting electrode ACE and the second connecting electrode TCE are located becomes the non-transparent region NTA. Therefore, as the region where the first connecting electrode ACE and the second connecting electrode TCE are formed increases, the transparent region TA decreases, and the light transmittance can decrease. To prevent the light transmittance from decreasing, it is preferable to minimize the region where the first connecting electrode ACE and the second connecting electrode TCE are formed.

[0093] The first connecting electrode ACE can be formed of the same material as the first anode electrode 121 and the second anode electrode 122 and be in the same layer as the first anode electrode 121 and the second anode electrode 122. That is, the first connecting electrode ACE can be formed of the following metallic materials with high reflectivity: such as a deposition structure of Al and Ti (Ti / Al / Ti), a deposition structure of Al and ITO (ITO / Al / ITO), Ag alloy, and a deposition structure of Ag alloy and ITO (ITO / Ag alloy / ITO).

[0094] The second connecting electrode TCE can be formed of the same material as the light-shielding layer LS and is in the same layer as the light-shielding layer LS. That is, the second connecting electrode TCE can be formed of a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0095] The minimum linewidth of the electrodes can vary depending on the material. Since the first connecting electrode ACE and the second connecting electrode TCE are made of different materials, their minimum widths can differ. Typically, the minimum linewidth of the material constituting the anode electrodes 121 and 122 is greater than the minimum linewidth of the light-shielding layer LS. That is, the width W1 of the second connecting electrode TCE can be less than or narrower than the width W2 of the first connecting electrode ACE.

[0096] In this case, it is preferable to minimize or reduce the area used to form the first connecting electrode ACE, which is made of the same material as the anode electrodes 121 and 122.

[0097] In order to minimize the area used to form the first connection electrode ACE, in a transparent display panel 110 according to one embodiment of the present disclosure, the second connection electrode TCE may be disposed outside the first connection electrode ACE (i.e., on the outside).

[0098] When the second connecting electrode TCE is disposed inside the first connecting electrode ACE (i.e., between the first anode connecting portion ACE1 and the second anode connecting portion ACE2), the second connecting electrode TCE can be formed as a straight line. That is, only the first transistor connecting portion TCE1 can be provided, and the second transistor connecting portion TCE2, which extends by bending from the first transistor connecting portion TCE1, can be omitted.

[0099] On the other hand, in the first connecting electrode ACE, the length of the third anode connecting portion ACE3, which connects the first anode connecting portion ACE1 and the second anode connecting portion ACE2, has no choice but to be increased. This requires ensuring a minimum distance between components so as not to affect other components during laser cutting. To this end, the first anode connecting portion ACE1 should be spaced at a minimum distance from the first transistor connecting portion TCE1 of the second connecting electrode TCE, and the second anode connecting portion ACE2 should also be spaced at a minimum distance from the first transistor connecting portion TCE1 of the second connecting electrode TCE. Therefore, due to the increased distance between the first anode connecting portion ACE1 and the second anode connecting portion ACE2, the length of the third anode connecting portion ACE3 is increased.

[0100] Meanwhile, when the second connection electrode TCE is disposed outside the first connection electrode ACE, the second connection electrode TCE can be formed to reach the first transistor connection portion TCE1 and extend through a second transistor connection portion TCE2 that bends from the first transistor connection portion TCE1. That is, compared with the case where the second connection electrode TCE is disposed inside the first connection electrode ACE, the area in which the second connection electrode TCE is formed is larger.

[0101] However, the first connecting electrode ACE can reduce or minimize the length of the third anode connecting portion ACE3, which connects the first anode connecting portion ACE1 and the second anode connecting portion ACE2. Since no other elements are disposed between the first anode connecting portion ACE1 and the second anode connecting portion ACE2, the first anode connecting portion ACE1 and the second anode connecting portion ACE2 can be spaced apart by a minimum distance. Because the third anode connecting portion ACE3 has a minimum length, the area forming the first connecting electrode ACE is smaller compared to the case where the second connecting electrode TCE is disposed inside the first connecting electrode ACE.

[0102] In a transparent display panel 110 according to one embodiment of the present disclosure, a second connecting electrode TCE is disposed outside the first connecting electrode ACE, thereby reducing or minimizing the area where the first connecting electrode ACE with a relatively large width W2 is formed. As a result, the transparent display panel 110 according to one embodiment of the present disclosure can minimize or reduce the area where the first connecting electrode ACE and the second connecting electrode TCE are formed, and can improve light transmittance.

[0103] A dam 125 can be provided on top of the planarization layer PLN. Additionally, a dam 125 can be provided between the anode electrodes 120. The dam 125 can be formed to cover or at least partially cover the edge of each anode electrode 120 and expose a portion of each anode electrode 120. Therefore, the dam 125 can prevent luminous efficiency degradation caused by current concentrated at the ends of each anode electrode 120.

[0104] The embankment 125 may define light-emitting regions EA1-1, EA1-2, EA2-1, EA2-2, EA3-1, EA3-2, EA4-1, and EA4-2 for each sub-pixel P1, P2, P3, and P4. The light-emitting regions EA1-1, EA1-2, EA2-1, EA2-2, EA3-1, EA3-2, EA4-1, and EA4-2 for each sub-pixel P1, P2, P3, and P4 represent the regions in which an anode electrode 120, an organic light-emitting layer 130, and a cathode electrode 140 are sequentially deposited, and where holes from the anode electrode 120 and electrons from the cathode electrode 140 combine in the organic light-emitting layer 130 to emit light. In this case, since the area forming the dam 125 does not emit light, this area can be a non-luminous area, while the area where the dam 125 is not formed and the anode electrode 120 is exposed can be luminous areas EA1-1, EA1-2, EA2-1, EA2-2, EA3-1, EA3-2, EA4-1 and EA4-2.

[0105] The embankment 125 can be formed of an organic layer, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0106] An organic light-emitting layer 130 may be disposed on the anode electrode 120. The organic light-emitting layer 130 may include a hole transport layer, a light-emitting layer, and an electron transport layer. In this case, if a voltage is applied to the anode electrode 120 and the cathode electrode 140, holes and electrons move to the light-emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting layer to emit light.

[0107] In one embodiment, the organic light-emitting layer 130 may be a common layer formed together for sub-pixels P1, P2, P3, and P4. For example, the organic light-emitting layer 130 may be a white light-emitting layer that emits white light.

[0108] In another embodiment, the organic light-emitting layer 130 may include a light-emitting layer formed in each sub-pixel P1, P2, P3, and P4. For example, a green light-emitting layer emitting green light may be formed in the first sub-pixel P1, a red light-emitting layer emitting red light may be formed in the second sub-pixel P2, a blue light-emitting layer emitting blue light may be formed in the third sub-pixel P3, and a white light-emitting layer emitting white light may be formed in the fourth sub-pixel P4. In this case, the light-emitting layers of the organic light-emitting layer 130 are not formed in the light-transmitting region TA.

[0109] The cathode electrode 140 can be disposed on the organic light-emitting layer 130 and the embankment 125. The cathode electrode 140 can be disposed in the light-transmitting region TA and the opaque region NTA including the light-emitting region EA, but is not limited thereto. The cathode electrode 140 can be disposed only in the opaque region NTA including the light-emitting region EA, but can be disposed outside the light-transmitting region TA to improve light transmittance.

[0110] The cathode electrode 140 may be a common layer formed together in sub-pixels P1, P2, and P3 to apply the same voltage. The cathode electrode 140 may be formed of a light-transmitting conductive material. For example, the cathode electrode 140 may be formed of a low-resistance metallic material, such as Ag, or an alloy of Mg and Ag.

[0111] An encapsulation layer 150 may be provided on top of the light-emitting diode. The encapsulation layer 150 may be formed on top of the cathode electrode 140 to cover the cathode electrode 140. The encapsulation layer 150 is used to prevent oxygen or water from penetrating into the organic light-emitting layer 130 and the cathode electrode 140. For this purpose, the encapsulation layer 150 may include at least one inorganic layer and at least one organic layer.

[0112] At the same time, despite Figure 5 and Figure 6 It is not shown, but a cover layer may be additionally formed between the cathode electrode 140 and the encapsulation layer 150.

[0113] The color filter CF can be disposed on the encapsulation layer 150. The color filter CF can be disposed on a surface of the second substrate 112 facing the first substrate 111. In this case, the first substrate 111 with the encapsulation layer 150 and the second substrate 112 with the color filter CF can be bonded to each other by the adhesive layer 160. At this time, the adhesive layer 160 can be an optically transparent resin (OCR) layer or an optically transparent adhesive (OCA) film.

[0114] The color filter CF can be patterned for each sub-pixel P1, P2, P3, and P4. Specifically, the color filter CF can include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1 can be set to the light-emitting area EA1 corresponding to the first sub-pixel P1, and can be a green color filter that transmits green light. The second color filter CF2 can be set to the light-emitting area EA2 corresponding to the second sub-pixel P2, and can be a red color filter that transmits red light. The third color filter CF3 can be set to the light-emitting area EA3 corresponding to the third sub-pixel P3, and can be a blue color filter that transmits blue light.

[0115] In a transparent display panel 110 according to one embodiment of the present disclosure, no polarizer is used, and a color filter CF is formed in a second substrate 112. When a polarizer is attached to the transparent display panel 110, the transmittance of the transparent display panel 110 is reduced by the polarizer. When the polarizer is not attached to the transparent display panel 110, there is a problem that external incident light is reflected in the electrodes.

[0116] The transparent display panel 110 according to one embodiment of the present disclosure can prevent a decrease in light transmittance because it does not have an attached polarizer. Furthermore, in the transparent display panel 110 according to one embodiment of the present disclosure, a color filter CF can be formed in the second substrate 112 to partially absorb external incident light, thereby preventing the incident light from being reflected in the electrodes. In other words, the transparent display panel 110 according to one embodiment of the present disclosure can reduce external light reflectivity without reducing light transmittance.

[0117] Simultaneously, a black matrix BM can be set between color filters CF1, CF2, and CF3. The black matrix BM can be set between sub-pixels P1, P2, and P3 to prevent color mixing between adjacent sub-pixels P1, P2, and P3.

[0118] Black matrix (BM) can include light-absorbing materials, such as black dyes that completely absorb light in the visible light wavelength range.

[0119] Figure 7 This diagram illustrates an example of setting up multiple signal lines and multiple driving transistors. Figure 8 It is along Figure 7 The cross-sectional view taken from line III-III′, and Figure 9 It is along Figure 7 The cross-sectional view taken from line IV-IV′. Figure 10 This is a diagram illustrating an example of how reference lines and scan lines are set in an intersection or overlap area.

[0120] In the following text, reference will be made to Figures 7 to 9A detailed example of setting up the first signal line SL1, the second signal line SL2, and the driving transistor TR.

[0121] As described above, the display area DA includes a light-transmitting area TA and a light-transmitting area NTA. The light-transmitting area NTA includes a first light-transmitting area NTA1 extending between adjacent light-transmitting areas TA along a first direction (e.g., the Y-axis direction) and a second light-transmitting area NTA2 extending between adjacent light-transmitting areas TA along a second direction (e.g., the X-axis direction).

[0122] The first signal line SL1 and the driving transistors TR1 and TR2, which are configured to overlap with the first signal line SL1, can be disposed in the first opaque area NTA1. For example, the first sub-pixel P1 and the second sub-pixel P2 can be configured to overlap with at least a portion of the first signal line SL1, and can be alternately disposed along the first signal line SL1. The first signal line SL1, the first driving transistor TR1 of the first sub-pixel P1, and the second driving transistor TR2 of the second sub-pixel P2 can be disposed in the first opaque area NTA1.

[0123] The first signal line SL1 may be disposed in the first non-transparent area NTA1 and extend in a first direction (e.g., the Y-axis direction). The first signal line SL1 may include multiple signal lines, and may include, for example, a first data line DL1, a reference line REFL, and a second data line DL2.

[0124] Specifically, the reference line REFL can be disposed in the first non-transparent area NTA1 and extend in a first direction (e.g., the Y-axis direction). The reference line REFL can provide a reference voltage (or initialization voltage, sensing voltage) to the driving transistor TR of each sub-pixel P1, P2, P3 and P4 disposed in the display area DA.

[0125] The first data line DL1 can be disposed in the first non-transparent area NTA1, disposed on the first side of the reference line REFL and extending in a first direction (e.g., the Y-axis direction). The first data line DL1 can provide data voltage to at least a portion of the sub-pixels P1, P2, P3 and P4 disposed in the display area DA.

[0126] For example, the first data line DL1 can provide a first data voltage to the second driving transistor TR2 of the second sub-pixel P2 and the third driving transistor TR3 of the third sub-pixel P3, which are located on the first side of the reference line REFL.

[0127] The second data line DL2 can be disposed in the first non-transparent area NTA1, located on the second side of the reference line REFL, and extending in a first direction (e.g., the Y-axis direction). In this case, the second side of the reference line REFL can be the side facing the first side. For example, when the first side is the left side of the reference line REFL, the second side can be the right side of the reference line REFL. The second data line DL2 can provide data voltage to the sub-pixels P1, P2, P3, and P4 disposed in the display area DA, excluding the sub-pixels connected to the first data line DL1.

[0128] For example, the second data line DL2 can provide a second data voltage to the first driving transistor TR1 of the first sub-pixel P1 and the fourth driving transistor TR4 of the fourth sub-pixel P4, which are located on the second side of the reference line REFL.

[0129] The first signal line SL1 may also include a first power line and a second power line.

[0130] The first power line can be located in the first non-transparent area NTA1, between the reference line REFL and the first data line DL1, and extends in a first direction (e.g., the Y-axis direction).

[0131] The second power line can be located in the first non-transparent area NTA1, between the reference line REFL and the second data line DL2, and extends in a first direction (e.g., the Y-axis direction).

[0132] In one embodiment, one of the first power line and the second power line may be a pixel power line VDDL for providing a first power supply to the anode electrode 120 of each sub-pixel P1, P2, P3, and P4. In one embodiment, one of the first power line and the second power line may be a common power line VSSL for providing a second power supply to the cathode electrode 140 of each sub-pixel P1, P2, P3, and P4.

[0133] A transparent display panel 110 according to one embodiment of the present disclosure is characterized in that the reference line REFL is not configured to be adjacent to the first data line DL1 and the second data line DL2.

[0134] A voltage can be applied to the reference line REFL, while data voltages can be applied to the data lines DL1 and DL2 in pulse form. When the reference line REFL is positioned adjacent to the data lines DL1 and DL2, crosstalk caused by capacitive coupling may occur between the reference line REFL and the data lines DL1 and DL2 when voltage changes occur in the data lines DL1 and DL2. In this case, the voltage of the reference line REFL may change, and furthermore, the brightness of sub-pixels P1, P2, P3, and P4 may change. As a result, dark or bright lines may appear.

[0135] The transparent display panel 110 can have a wide light-transmitting area TA to ensure light transmittance, and a relatively narrow light-blocking area NTA. Since multiple signal lines are not light-transmitting, they can be placed within the light-blocking area NTA. However, compared to a conventional display panel, the spacing between the signal lines cannot be reduced because the multiple signal lines are placed in the narrow light-blocking area NTA. Consequently, in the transparent display panel 110, the parasitic capacitance between the reference line REFL and the data lines DL1 and DL2 increases, and crosstalk caused by coupling may occur more severely.

[0136] In a transparent display panel 110 according to one embodiment of the present disclosure, in order to minimize or reduce the parasitic capacitance between the reference line REFL and the data lines DL1 and DL2 within a limited space, the reference line REFL and the data lines DL1 and DL2 may not be set to be adjacent to each other.

[0137] Specifically, in a transparent display panel 110 according to one embodiment of the present disclosure, the pixel power line VDDL or the common power line VSSL can be disposed between the reference line REFL and the first data line DL1, thereby the reference line REFL and the first data line DL1 can be disposed not adjacent to each other. Additionally, in a transparent display panel 110 according to one embodiment of the present disclosure, the pixel power line VDDL or the common power line VSSL can be disposed between the reference line REFL and the second data line DL2, thereby the reference line REFL and the second data line DL2 can be disposed not adjacent to each other. Since a specific power supply voltage that is not a pulse type is applied to the pixel power line VDDL or the common power line VSSL, the reference line REFL is almost unaffected by the pixel power line VDDL or the common power line.

[0138] In other words, in the transparent display panel 110 according to one embodiment of the present disclosure, different signal lines are provided between the reference line REFL and the data lines DL1 and DL2, thereby increasing the spacing between the reference line REFL and the data lines DL1 and DL2. Therefore, the transparent display panel 110 according to one embodiment of the present disclosure can reduce the parasitic capacitance between the reference line REFL and the data lines DL1 and DL2.

[0139] In a transparent display panel 110 according to one embodiment of the present disclosure, reference lines REFL and data lines DL1 and DL2 can be disposed in their respective layers, which are different from each other. Specifically, reference lines REFL can be disposed in a first layer, and data lines DL1 and DL2 can be disposed in a second layer, which is different from the first layer.

[0140] In one implementation, the reference line REFL may be disposed in the same layer as one of the elements constituting the driving transistor TR. Specifically, the reference line REFL may be disposed in the same layer as any one of the active layer ACT, gate GE, source SE, and drain DE of the driving transistor TR. For example, the reference line REFL may be disposed in the same layer as the gate GE, such as... Figure 8 As shown.

[0141] In one embodiment, data lines DL1 and DL2 can be disposed between the driving transistor TR and the substrate 111. For example, data lines DL1 and DL2 can be formed in the same layer as the light-shielding layer LS, such as... Figure 5 As shown.

[0142] In a transparent display panel 110 according to one embodiment of the present disclosure, reference lines REFL and data lines DL1 and DL2 are disposed in their respective layers, which maximizes the vertical spacing between reference lines REFL and data lines DL1 and DL2 within a limited space. Therefore, the transparent display panel 110 according to one embodiment of the present disclosure can minimize or reduce the parasitic capacitance between reference lines REFL and data lines DL1 and DL2.

[0143] Simultaneously, the first driving transistor TR1 and the second driving transistor TR2 can be configured in a zigzag pattern instead of being arranged in a straight line. More specifically, as... Figure 7 As shown, the first driving transistor TR1 can be disposed on one side of the first center line CL1 in the first non-transparent area NTA1, which is parallel to the first direction (e.g., the Y-axis direction), and the second driving transistor TR2 can be disposed on the other side of the first center line CL1.

[0144] In other words, the first driving transistor TR1 can be located on the second side of the reference line REFL, and can be located between the second data line DL2 and the light-transmitting area TA. The second driving transistor TR2 can be located on the first side of the reference line REFL, and can be located between the first data line DL1 and the light-transmitting area TA.

[0145] A transparent display panel 110 according to one embodiment of the present disclosure is characterized in that the first driving transistor TR1 and the second driving transistor TR2 are arranged in a Z-shaped pattern.

[0146] For example, suppose the first driving transistor TR1 and the second driving transistor TR2 are positioned on a straight line on the first side of the reference line REFL.

[0147] The first driving transistor TR1 can be connected to the first data line DL1, and the second driving transistor TR2 can be connected to the second data line DL2. In this case, the connection line for connecting the second driving transistor TR2 and the second data line DL2 should cross or overlap with the first data line DL1, the pixel power line VDDL, the reference line REFL, and the common power line VSSL. Therefore, the connection line for connecting the second driving transistor TR2 and the second data line DL2 can have a longer length, and resistance may cause losses in the data voltage.

[0148] In addition, since the length of the connecting line between the first driving transistor TR1 and the first data line DL1 is different from the length of the connecting line between the second driving transistor TR2 and the second data line DL2, a deviation may occur in the data voltage.

[0149] In a transparent display panel 110 according to one embodiment of the present disclosure, the first driving transistor TR1 and the second driving transistor TR2 can be arranged in a Z-shaped pattern, such that the length of the connecting line for connecting the first driving transistor TR1 and the first signal line SL1 can be the same as or similar to the length of the connecting line for connecting the second driving transistor TR2 and the second signal line SL2.

[0150] Therefore, the transparent display panel 110 according to one embodiment of the present disclosure can prevent deviation of the signal voltage applied to each of the first driving transistor TR1 and the second driving transistor TR2.

[0151] Furthermore, the transparent display panel 110 according to one embodiment of this disclosure can reduce or minimize the length of the connection line used to connect the first signal line SL1 to the first driving transistor TR1 and the second driving transistor TR2. The transparent display panel 110 according to one embodiment of this disclosure can prevent signal voltage loss, such as data voltage loss.

[0152] The second signal line SL2 and the driving transistors TR3 and TR4 of the sub-pixels P3 and P4 that overlap with the second signal line SL2 can be disposed in the second opaque area NTA2. For example, the third sub-pixel P3 and the fourth sub-pixel P4 can be disposed to overlap with at least a portion of the second signal line SL2, and can be arranged alternately along the second signal line SL2. The second signal line SL2, the third driving transistor TR3 of the third sub-pixel P3, and the fourth driving transistor TR4 of the fourth sub-pixel P4 can be disposed in the second opaque area NTA2.

[0153] The second signal line SL2 can be disposed in the second non-transparent area NTA2 and then extend in a second direction (e.g., the X-axis direction). The second signal line SL2 may include multiple signal lines, and may include, for example, at least one scan line SCANL1 and SCANL2.

[0154] The following description is based on the provision of two scan lines, SCANL1 and SCANL2, in the second opaque area NTA2, but this disclosure is not limited thereto. Only one scan line may be provided in the second opaque area NTA2.

[0155] Specifically, the first scan line SCANL1 can be disposed in the second non-transparent area NTA2 and then extend in a second direction (e.g., the X-axis direction). The first scan line SCANL1 can provide scan signals to at least a portion of the sub-pixels P1, P2, P3 and P4 disposed in the display area DA.

[0156] For example, the first scan line SCANL1 can provide a first scan signal to the first driving transistor TR1 of the first sub-pixel P1 and the third driving transistor TR3 of the third sub-pixel P3.

[0157] The second scan line SCANL2 can be disposed in the second non-transparent area NTA2 and then extend in a second direction (e.g., the X-axis direction). The second scan line SCANL2 can provide scan signals to the sub-pixels of sub-pixels P1, P2, P3 and P4 disposed in the display area DA, excluding the sub-pixels connected to the first scan line SCANL1.

[0158] For example, the second scan line SCANL2 can provide a second scan signal to the second driving transistor TR2 of the second sub-pixel P2 and the fourth driving transistor TR4 of the fourth sub-pixel P4.

[0159] The first scan line SCANL1 and the second scan line SCANL2 can be formed in different layers from the first signal line SL1. Specifically, the first scan line SCANL1 and the second scan line SCANL2 can be formed in different layers from the first data line DL1, the reference line REFL, and the second data line DL2.

[0160] In one embodiment, the first scan line SCANL1 and the second scan line SCANL2 may be disposed in the same layer as one of the elements constituting the driving transistor TR. Specifically, the first scan line SCANL1 and the second scan line SCANL2 may be disposed in the same layer as any one of the active layer ACT, gate GE, source SE, and drain DE of the driving transistor TR. For example, as... Figure 9As shown, the first scan line SCANL1 and the second scan line SCANL2 can be placed in the same layer as the source SE and drain DE, as... Figure 9 As shown.

[0161] The first signal line SL1 and the second signal line SL2 may cross or overlap in a cross or overlapping area IA where the first opaque area NTA1 and the second opaque area NTA2 intersect or overlap. A short circuit may occur between the first signal line SL1 and the second signal line SL2 in the cross or overlapping area IA.

[0162] Specifically, signal lines formed in the same layer as the gate (GE) and signal lines formed in the same layer as the source (SE) and drain (DE) are likely to short-circuit due to particles.

[0163] According to one embodiment, when the reference line REFL is formed in the same layer as the gate GE of the driving transistor TR and the scan lines SCANL1 and SCANL2 are formed in the same layer as the source SE and drain DE of the driving transistor TR, the reference line REFL and the scan lines SCANL1 and SCANL2 may be short-circuited due to particles.

[0164] In a transparent display panel 110 according to one embodiment of the present disclosure, when a short circuit occurs between the reference line REFL and the scan lines SCANL1 and SCANL2, a repair structure is applied to the scan lines SCANL1 and SCANL2.

[0165] In the following text, reference will be made to Figure 7 and Figure 10 Describe an example of setting the reference line REFL and scan lines SCANL1 and SCANL2 in the cross or overlap area IA.

[0166] The reference line REFL may include a first line section RL1, a second line section RL2, and a curved section RL3.

[0167] The first line portion RL1 can be disposed on the first side of the first center line CL1 in the first non-transparent area NTA1, which is parallel to the first direction (e.g., the Y-axis direction), and the second line portion RL2 can be disposed on the second side of the first center line CL1.

[0168] The curved portion RL3 can be bent in the intersection or overlapping area IA where the first opaque area NTA1 and the second opaque area NTA2 intersect or overlap, thereby connecting the first line portion RL1 and the second line portion RL2. For example... Figure 7 and Figure 10 As shown, the curved portion RL3 can be formed to be inclined in the second non-transparent area NTA2 relative to the second centerline CL2 which is parallel to the second direction (e.g., the X-axis direction).

[0169] Each scan line SCANL1 and SCANL2 may include a first line section SCL1, a second line section SCL2, and a connecting line section SCL3.

[0170] The first line section SCL1 can be set on the first side of the reference line REFL, and the second line section SCL2 can be set on the second side of the reference line REFL.

[0171] The connecting line portion SCL3 can be disposed in the intersection or overlapping area IA where the first opaque area NTA1 and the second opaque area NTA2 intersect or overlap, and can connect the first line portion SCL1 and the second line portion SCL2. For example... Figure 7 and Figure 10 As shown, the connecting line SCL3 may include multiple branch lines SCL3-2.

[0172] In detail, the connecting line SCL3 can be provided with multiple branch lines SCL3-2 in the area where it intersects with the bend RL3 of the reference line REFL. Each of the multiple branch lines (divergence lines) SCL3-2 can have a first length L1 and at least a portion thereof can overlap with the bend RL3 of the reference line REFL. The multiple branch lines SCL3-2 can be spaced apart from each other.

[0173] Although Figure 10 The diagram shows two branch lines SCL3-2, but this disclosure is not limited to this. More than two branch lines SCL3-2 can be formed.

[0174] The connecting section SCL3 may further include multiple sub-connecting sections SCL3-1, SCL3-3, and SCL3-4 for connecting the first section SCL1 to multiple branch lines SCL3-2 or for connecting the second section SCL2 to multiple branch lines SCL3-2. For example... Figure 7 and Figure 10 As shown, multiple sub-connecting lines SCL3-1, SCL3-3 and SCL3-4 can be formed to be inclined or parallel to the second center line CL2.

[0175] According to one embodiment of the present disclosure, scan lines SCANL1 and SCANL2 are formed by multiple branch lines SCL3-2 in the region where they intersect with the bend RL3 of reference line REFL. In a transparent display panel 110 according to one embodiment of the present disclosure, when any of the multiple branch lines SCL3-2 is short-circuited with the bend RL3 of reference line REFL, the corresponding branch line SCL3-2 can be laser-cut to separate it from the multiple sub-connecting lines SCL3-1, SCL3-3, and SCL3-4, and then repaired.

[0176] exist Figure 7and Figure 10 In this configuration, the curved portion RL3 of the reference line REFL is inclined relative to the second center line CL2, but is not limited to this. The curved portion RL3 of the reference line REFL can also be set to be parallel to the second center line CL2.

[0177] Figure 11 This is another example illustrating the setup of multiple signal lines and multiple drive transistors, and Figure 12 This is another example illustrating the setting of reference lines and scan lines in the intersection or overlap area.

[0178] In the following text, repeated descriptions will be omitted, and the reference line REFL and scan lines SCANL1 and SCANL2 will be described primarily.

[0179] Reference Figure 11 and Figure 12 The reference line REFL may include a first line section RL1, a second line section RL2, and a curved section RL3.

[0180] The first line portion RL1 can be disposed on the first side of the first center line CL1 in the first non-transparent area NTA1, which is parallel to the first direction (e.g., the Y-axis direction), and the second line portion RL2 can be disposed on the second side of the first center line CL1.

[0181] The bending portion RL3 can be bent from the intersection or overlap area IA where the first opaque area NTA1 and the second opaque area NTA2 intersect or overlap, thereby connecting the first line portion RL1 and the second line portion RL2. The bending portion RL3 can connect one end of the first line portion RL1 to one end of the second line portion RL2.

[0182] The curved portion RL3 can be formed parallel to the second centerline CL2, such as... Figure 11 and Figure 12 As shown. In this case, the first line segment RL1 and the second line segment RL2 can extend to the intersection or overlapping area IA. One end of the first line segment RL1 and one end of the second line segment RL2 can be equal to each other in terms of distance from the second center line CL2.

[0183] Each scan line SCANL1 and SCANL2 may include a first line section SCL1, a second line section SCL2, and a connecting line section SCL3.

[0184] The first line section SCL1 can be set on the first side of the reference line REFL, and the second line section SCL2 can be set on the second side of the reference line REFL.

[0185] The connecting line part SCL3 can be set in the intersection or overlapping area IA where the first opaque area NTA1 and the second opaque area NTA2 intersect or overlap, and can connect the first line part SCL1 and the second line part SCL2.

[0186] Reference Figure 11 and Figure 12 The connecting line section SCL3 may include multiple branch lines SCL3-2.

[0187] In detail, each of the multiple branch lines SCL3-2 may intersect or overlap with either the first line portion RL1 or the second line portion RL2 of the reference line REFL. For example, when there are two branch lines SCL3-2, one branch line SCL3-2 may have a second length L2, and at least a portion of it may overlap with the first line portion RL1. The other branch line SCL3-2 may be spaced apart from the first branch line SCL3-2, may have a second length L2, and at least a portion of it may overlap with the second line portion RL2.

[0188] exist Figure 12 In this diagram, multiple branch lines SCL3-2 are shown as two, but are not limited to this. Multiple branch lines SCL3-2 can be formed as more than two.

[0189] The connecting line section SCL3 may further include multiple sub-connecting line sections SCL3-1, SCL3-3, and SCL3-4 for connecting the first line section SCL1 to multiple branch lines SCL3-2 or for connecting the second line section SCL2 to multiple branch lines SCL3-2. The multiple sub-connecting line sections SCL3-1, SCL3-3, and SCL3-4 may be formed to be inclined or parallel to the second center line CL2, such as... Figure 11 and Figure 12 As shown.

[0190] According to another embodiment of the present disclosure, scan lines SCANL1 and SCANL2 form multiple branch lines SCL3-2 in the region where they intersect with the bend RL3 of reference line REFL. In a transparent display panel 110 according to one embodiment of the present disclosure, when any of the multiple branch lines SCL3-2 is short-circuited with the bend RL3 of reference line REFL, the corresponding branch line SCL3-2 can be laser-cut to separate it from the sub-connecting lines SCL3-1, SCL3-3, and SCL3-4, and then repaired.

[0191] Meanwhile, according to another embodiment of the present disclosure, the curved portion RL3 of the reference line REFL can be formed parallel to the second center line CL2, thereby reducing or minimizing the length of the branch lines SCL3-2 of the scan lines SCANL1 and SCANL2.

[0192] In detail, when a short circuit occurs, the minimum margin width M required from the reference line REFL is required for laser cutting relative to branch line SCL3-2.

[0193] Figure 10 The scan lines SCANL1 and SCANL2 shown have a branch line SCL3-2 that needs to ensure a minimum margin width M on one side (e.g., the left side) of the reference line REFL, and another branch line SCL3-2 that needs to ensure a minimum margin width M on the other side (e.g., the right side) of the reference line REFL.

[0194] because Figure 10 The curved portion RL3 of the reference line REFL shown is inclined relative to the second center line CL2, so the width W2 between the minimum margin width M on the left and the minimum margin width M on the right is greater than the width W1 of the reference line REFL.

[0195] at the same time, Figure 12 The curved portion RL3 of the reference line REFL shown is parallel to the second center line CL2, and the branch lines SCL3-2 of scan lines SCANL1 and SCANL2 intersect or overlap with the first line portion RL1 or the second line portion RL2, which is set perpendicular to the second center line CL2. In this case, the width between the minimum margin width M on the left and the minimum margin width M on the right can be equal to the width W1 of the reference line REFL.

[0196] result, Figure 12 The length L2 of the branch line SCL3-2 of the scan lines SCANL1 and SCANL2 shown can be shorter than Figure 10 The length L1 of the branch line SCL3-2 of the scan lines SCANL1 and SCANL2 shown is given. According to another embodiment of this disclosure, the scan lines SCANL1 and SCANL2 can be used to easily apply the repair structure to a limited space and increase the degree of design freedom by minimizing the length of the branch line SCL3-2.

[0197] The following beneficial effects can be obtained from this disclosure.

[0198] Even if dark spots appear due to particles, this disclosure can reduce the light loss caused by dark spots by laser cutting to short-circuit only the corresponding anode electrode among multiple anode electrodes.

[0199] Furthermore, since the second connection electrode used for connecting to the driving transistor is formed in the same layer as the light-shielding layer, the spacing between the first and second connection electrodes can be increased. Therefore, this disclosure can minimize or reduce interference between components during laser cutting.

[0200] Furthermore, the second connecting electrode is disposed outside the first connecting electrode, thereby reducing or minimizing the area where the first and second connecting electrodes are formed. As a result, this disclosure can improve light transmittance.

[0201] Because different signal lines are used between the reference line and the data line, the spacing between them can be increased. Therefore, the parasitic capacitance between the reference line and the data line can be reduced.

[0202] Furthermore, in this disclosure, the scan line can form multiple branch lines in the region where it intersects with the reference line. Therefore, when a short circuit occurs between any of the multiple branch lines and the reference line, the corresponding branch line can be cut and repaired by laser.

[0203] Furthermore, in this disclosure, the curved portion of the reference line can be formed parallel to the second center line, thereby reducing or minimizing the length of multiple branch lines provided in the scan line. Therefore, in this disclosure, the scan line repair structure can be easily applied to limited spaces and increases design flexibility.

[0204] It will be apparent to those skilled in the art that this disclosure is not limited to the above-described embodiments and drawings, and that various substitutions, modifications, and variations can be made to this disclosure without departing from its spirit or scope. Therefore, the scope of this disclosure is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this disclosure.

Claims

1. A transparent display device, the transparent display device comprising: A substrate having multiple light-transmitting areas and multiple sub-pixels disposed between the light-transmitting areas; A first anode electrode and a second anode electrode are disposed in each of the plurality of sub-pixels; A first connecting electrode connects the first anode electrode and the second anode electrode; A driving transistor is disposed in each of the plurality of sub-pixels; as well as A second connection electrode is disposed below the driving transistor, which electrically connects the driving transistor to the first connection electrode.

2. The transparent display device according to claim 1, further comprising a light-shielding layer disposed between the substrate and the driving transistor, wherein the second connection electrode is made of the same material as the light-shielding layer, and the second connection electrode and the light-shielding layer are in the same layer.

3. The transparent display device according to claim 2, wherein, The light-shielding layer is electrically connected to the driving transistor through a first contact hole, wherein the second connection electrode is electrically connected to the first connection electrode through a second contact hole.

4. The transparent display device according to claim 3, further comprising an intermediate connecting electrode disposed between the first connecting electrode and the second connecting electrode, wherein, The intermediate connecting electrode is electrically connected to the second connecting electrode through the second contact hole, and is connected to the first connecting electrode through the third contact hole.

5. The transparent display device according to claim 4, wherein, The first connecting electrode includes a first anode connecting portion extending from the first anode electrode toward the light-transmitting area, a second anode connecting portion extending from the second anode electrode toward the light-transmitting area, and a third anode connecting portion connecting one end of the first anode connecting portion and one end of the second anode connecting portion. The intermediate connecting electrode is electrically connected to the third anode connecting portion through the third contact hole.

6. The transparent display device according to claim 1, wherein, The second connection electrode includes a first transistor connection portion and a second transistor connection portion. The first transistor connection portion extends from a light-shielding layer disposed between the driving transistor and the substrate toward the light-transmitting area. The second transistor connection portion bends from the first transistor connection portion toward the first connection electrode and has at least a portion overlapping the first connection electrode.

7. The transparent display device according to claim 6, wherein, The first connecting electrode includes a first anode connecting portion extending from the first anode electrode toward the light-transmitting area, a second anode connecting portion extending from the second anode electrode toward the light-transmitting area, and a third anode connecting portion connecting one end of the first anode connecting portion and one end of the second anode connecting portion. The first transistor connection portion is connected to the driving transistor, and the second transistor connection portion is electrically connected to the third anode connection portion.

8. The transparent display device according to claim 1, further comprising: A reference line extending along a first direction from a non-transparent area disposed between the light-transmitting areas; A first data line is disposed on a first side of the reference line; A second data line is disposed on a second side of the reference line; A first power line is disposed between the reference line and the first data line; as well as A second power line is disposed between the reference line and the second data line. The first data line and the second data line are disposed in the same layer as the second connection electrode.

9. The transparent display device according to claim 8, wherein, The reference line is located on a different layer than the first data line and the second data line.

10. The transparent display device according to claim 8, wherein, The opaque area includes a first opaque area extending in the first direction between the light-transmitting areas and a second opaque area extending in the second direction between the light-transmitting areas, and the reference line includes a curved portion that bends from the intersection of the first opaque area and the second opaque area where they overlap.

11. The transparent display device according to claim 10, wherein, The curved portion is configured to be parallel to the second opaque area.

12. A transparent display device, the transparent display device comprising: A substrate having multiple light-transmitting areas and multiple sub-pixels disposed between the light-transmitting areas; A first anode electrode and a second anode electrode are disposed in each of the plurality of sub-pixels; A first connecting electrode connects the first anode electrode and the second anode electrode; A driving transistor is disposed in each of the plurality of sub-pixels; as well as A second connection electrode is disposed outside the first connection electrode, and electrically connects the driving transistor to the first connection electrode. The second connection electrode extends from the driving transistor toward the light-transmitting area.

13. The transparent display device according to claim 12, wherein, The first connecting electrode includes a first anode connecting portion extending from the first anode electrode toward the light-transmitting area, a second anode connecting portion extending from the second anode electrode toward the light-transmitting area, and a third anode connecting portion connecting one end of the first anode connecting portion and one end of the second anode connecting portion.

14. The transparent display device according to claim 13, wherein, The second anode connection portion is disposed on the first side of the first anode connection portion to be adjacent to the first anode connection portion.

15. The transparent display device according to claim 14, wherein, The second connecting electrode is disposed on the second side of the first anode connecting portion so as to be adjacent to the first anode connecting portion.

16. The transparent display device according to claim 13, wherein, The second connection electrode includes a first transistor connection portion and a second transistor connection portion. The first transistor connection portion extends from a light-shielding layer disposed between the substrate and the driving transistor toward the light-transmitting area. The second transistor connection portion bends from the first transistor connection portion toward the first connection electrode and has at least a portion overlapping with the third anode connection portion.

17. The transparent display device according to claim 12, wherein, The width of the second connecting electrode is smaller than the width of the first connecting electrode.

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