A negative capacitance tunneling field effect transistor based on antiferromagnetic layer

Abstract

The application discloses a negative capacitance tunneling field effect transistor based on a antiferromagnetic layer, and belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large scale integration (ULSI). The application adds an antiferromagnetic layer in a TFET control gate to bring a negative capacitance effect, and when a dynamic polarization matching condition is met, a gate voltage amplification coefficient is greater than 1, and a subthreshold slope can be improved. In the negative capacitance effect, the gate voltage amplification coefficient first increases and then decreases, and the polarization-voltage relationship of the antiferromagnetic layer makes the negative capacitance effect start from the subthreshold region of the TFET connected in series below, so that the rising section of the gate voltage amplification coefficient in the negative capacitance effect delays the problem of the degradation of the subthreshold slope of the TFET, reduces the average subthreshold slope, improves the on-state current when operating at a low voltage, and shows great application prospects of ultra-low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of field-effect transistor logic devices and circuits in CMOS ultra-large integrated circuits (ULSI), specifically relating to a negative capacitance tunneling field-effect transistor (NCTFET). Background Technology

[0002] As device feature sizes continue to shrink, the negative impact of short-channel effects intensifies. Drain-induced barrier reduction (DIBL) and band-to-band tunneling effects cause the off-state leakage current to increase continuously. Furthermore, the subthreshold slope (SS) of traditional MOSFET devices is limited by thermoelectric potential and cannot decrease synchronously with device size reduction, meaning that power consumption cannot be continuously reduced by lowering the operating voltage.

[0003] Currently, tunneling field-effect transistors (TFETs) and negative capacitance transistors (NCFETs) have broken through the theoretical limit of 60mV / dec for the subthreshold slope of conventional MOSFETs through band-to-band tunneling conduction mechanism and negative capacitance (NC) effect, respectively, showing great promise for ultra-low power applications. However, TFETs suffer from the degradation problem of subthreshold slope SS, which gradually increases with increasing gate voltage, resulting in a larger average subthreshold slope (SS). avg This is unfavorable for low-power applications. Current methods to alleviate the subthreshold slope degradation problem of TFETs include introducing heterojunctions in the substrate, but this increases cost and process complexity. If ferroelectricity is used to introduce a negative capacitance effect in the TFET to create an FE-NCTFET, the minimum subthreshold slope of the TFET can be further reduced and the on-state current increased, but this suffers from a more severe subthreshold slope (SS) degradation problem. In the NC effect, the gate voltage amplification factor (A...)... V The capacitance will initially increase and then decrease. Taking the turn-on process of an N-type FE-NCTFET as an example, when the ferroelectric polarization increases rapidly and meets the dynamic polarization matching condition, the negative capacitance effect begins to occur. (Refer to...) Figure 1a The relationship between ferroelectric polarization and voltage is shown, where the ferroelectric voltage is close to the coercive voltage +V. C The ferroelectric polarization is negative. When the gate voltage continues to rise, the ferroelectric polarization becomes positive when the lower series-connected TFET operates in the subthreshold region, and the ferroelectric voltage exceeds +V. C A V The decline in the subthreshold slope (SS) of the TFET will exacerbate the degradation problem. Summary of the Invention

[0004] The purpose of this invention is to propose a negative capacitance tunneling field-effect transistor (AFE-NCTFET) based on an antiferroelectric layer. In the gate stack structure of the NCTFET, an antiferroelectric layer is used instead of a ferroelectric layer to generate a negative capacitance effect. This invention can optimize the subthreshold slope (SS) of the TFET while ensuring that the device operates in the subthreshold region when the negative capacitance effect occurs. It also slows down the degradation of the subthreshold slope (SS) during the rise of the gate voltage amplification factor, increases the operating current range where the subthreshold slope (SS) is below 60 mV / dec, and achieves higher on-state current during low-voltage operation. Furthermore, it is compatible with existing CMOS processes and is expected to be adopted in low-power applications, demonstrating high practical value.

[0005] The technical solution of the present invention is as follows:

[0006] A negative capacitance tunneling field-effect transistor includes a semiconductor substrate, a highly doped source region, a highly doped drain region, a gate dielectric layer, and a gate stack. The gate stack is composed of a metal equipotential layer, an antiferroelectric layer, and a gate electrode layer, or the gate stack is composed of an antiferroelectric layer and a gate electrode layer. The polarization charge of the antiferroelectric layer changes per unit time... The charge increment (C) caused by the entire gate voltage falling onto the tunneling field-effect transistor is greater than the total charge increment (C) P dV G When the gate voltage is at a certain value, the negative capacitance tunneling field-effect transistor exhibits a negative capacitance effect, and the gate voltage amplification factor is greater than 1.

[0007] The antiferroelectric material of this invention has a different polarization and voltage relationship than ferroelectric materials, such as... Figure 1b As shown, taking the turn-on process of an N-type AFE-NCTFET as an example, the negative capacitance effect also occurs when the antiferroelectric voltage approaches the coercive voltage +V. C 1 When the antiferroelectric polarization is positive, the TFET connected in series below it can operate in the subthreshold region when the negative capacitance effect begins.

[0008] The antiferroelectric layer can be obtained by adjusting the ratio of doped hafnium oxide to hafnium in a ferroelectric material.

[0009] The antiferroelectric layer can be made of antiferroelectric materials such as zirconium oxide (ZrO2).

[0010] The gate stack structure can employ a short-gate design, meaning the gate stack structure partially covers the channel region, leaving an uncovered region with a certain spacing between the gate and drain. This effectively suppresses tunneling at the drain junction, i.e., the bipolar conduction effect in TFETs. The highly doped source region and highly doped drain region contain impurities of different doping types. For N-type (or P-type) devices, the highly doped source region is composed of P... + (or P) - Doped regions and N + (or N)- The doped region consists of two parts. Specifically, for an N-type transistor, the highly doped drain region consists of N... - (concentration approximately 1×10) 17 ~1×10 19 cm -3 The doped region is composed of P-doped regions, and the highly doped source region is composed of P-doped regions. + (concentration approximately 1×10) 20 ~1×10 21 cm -3 The highly doped drain region is composed of P-type transistors. - (concentration approximately 1×10) 17 ~1×10 19 cm -3 The doped region is composed of N, and the highly doped source region is composed of N + (concentration approximately 1×10) 20 ~1×10 21 cm -3 It consists of doped regions.

[0011] The technical effects of this invention are as follows:

[0012] 1. Using an antiferroelectric layer to generate a negative capacitance effect, if the change in polarization charge of the antiferroelectric layer per unit time during gate voltage changes... The charge increment (C) caused by the entire applied gate voltage falling onto the tunneling field-effect transistor exceeds the applied gate voltage. P dV G When the dynamic polarization matching condition is met, the gate voltage amplification factor is greater than 1, which can improve the subthreshold slope.

[0013] II. When the negative capacitance effect occurs With C P dV G The difference between them first increases and then decreases, corresponding to the gate voltage amplification factor first increasing and then decreasing.

[0014] Third, the negative capacitance effect also occurs when the antiferroelectric voltage is close to the coercive voltage +V. C 1 At this time, the antiferroelectric polarization becomes positive, which allows the TFET connected in series below it to operate in the subthreshold region when the negative capacitance effect begins. V An increase in SS can slow down SS degradation, resulting in a lower SS. avg It has higher on-state current in low-voltage applications and shows great potential in low-power applications. Attached Figure Description

[0015] Figure 1a This is a schematic diagram showing the polarization and voltage relationship of a typical ferroelectric material;

[0016] Figure 1bThis is a schematic diagram illustrating the polarization and voltage relationship of a typical antiferroelectric material.

[0017] Figure 2a This invention relates to the MFIS structure of a negative capacitance tunneling field-effect transistor based on an antiferroelectric layer.

[0018] Figure 2b This invention relates to the MFMIS structure of a negative capacitance tunneling field-effect transistor based on an antiferroelectric layer.

[0019] Figure 3a To prepare a substrate after fabricating a gate stack structure on a substrate;

[0020] Figure 3b The substrate after photolithography of the active region;

[0021] Figure 3c Injecting process technology into the active region of the source region;

[0022] Figure 3d The implantation process for the highly doped drain region and active region;

[0023] Figure 3e This is a diagram of a negative capacitance tunneling field-effect transistor based on an antiferroelectric layer after the source-drain junction has been formed.

[0024] Figure 4 This is a schematic diagram of the structure of the negative capacitance tunneling field-effect transistor based on the antiferroelectric layer of the present invention.

[0025] In the picture:

[0026] 1 — Semiconductor substrate 2 — Highly doped source region

[0027] 3—Highly doped drain region; 4—Gate dielectric layer

[0028] 5 – Metallic equipotential layer; 6 – Antiferroelectric layer

[0029] 7—Gate electrode layer; 8—Photoresist Detailed Implementation

[0030] The present invention will be further illustrated below through examples. It should be noted that the examples are provided to aid in further understanding of the invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the invention and the appended claims. Therefore, the invention should not be limited to the content disclosed in the embodiments, and the scope of protection claimed by the invention is determined by the claims.

[0031] Corresponding to the device structure of MFIS, such as Figure 2aAs shown, the control gate stack of the present invention consists of an antiferroelectric layer and a gate electrode layer; the control gate stack consists of a metal equipotential layer, an antiferroelectric layer, and a gate electrode layer, forming the device structure of the MFMIS, as shown. Figure 2b As shown.

[0032] Taking the MFMIS device structure as an example, this invention can introduce an antiferroelectric layer into the gate stack structure for fabrication based on the conventional TFET process.

[0033] The specific implementation steps are shown in the figure:

[0034] (1) An HfO2 insulating medium with a thickness of 1 nm-10 nm was grown on substrate 1 by atomic layer deposition (ALD).

[0035] (2) Prepare a metal equipotential layer with a thickness of 10nm-50nm on the insulating medium grown in step (1) by physical vapor deposition (PVD);

[0036] (3) An antiferroelectric layer of ZrO2 with a thickness of 1nm-20nm is grown on the surface of the metal equipotential layer prepared in step (2) by atomic layer deposition (ALD).

[0037] (4) A gate electrode with a thickness of 10 nm-50 nm is prepared on the surface of the antiferroelectric layer grown in step (3) by physical vapor deposition (PVD). Figure 3a As shown;

[0038] (5) Define the grating pattern through photolithography, such as Figure 3b As shown. Photoresist is applied to the drain region, and the source region is implanted using the photoresist as a mask. Then the photoresist is removed, as... Figure 3c As shown;

[0039] (6) Apply photoresist to the source and gate regions, use the photoresist as a mask for active and drain region implantation, and then remove the photoresist. Figure 3d As shown;

[0040] (7) Rapid thermal annealing (RTA) activates source and drain impurities, forming source and drain regions and causing the material to exhibit antiferroelectricity, such as Figure 3e As shown.

[0041] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for mitigating subthreshold slope degradation of a tunneling field-effect transistor, the tunneling field-effect transistor comprising a semiconductor substrate, a highly doped source region, a highly doped drain region, a gate dielectric layer, and a control gate stack, characterized in that, The control gate stack consists of an antiferroelectric layer and a gate electrode layer, or it consists of a metal equipotential layer, an antiferroelectric layer, and a gate electrode layer. The antiferroelectric layer is made of doped hafnium oxide or zirconium oxide antiferroelectric material. The control gate stack partially covers the channel region, and there is an uncovered region with a certain distance between it and the highly doped drain region. The highly doped source region and the highly doped drain region contain impurities of different doping types. When the polarization charge of the antiferroelectric layer changes by a certain amount per unit time (∂P)... AFE / ∂t) is greater than the charge increment (C) caused by the entire gate voltage dropping onto the tunneling field-effect transistor. P dV G When the gate voltage is increased, the tunneling field-effect transistor (TFTE) exhibits a negative capacitance effect, resulting in a gate voltage amplification factor greater than 1. Simultaneously, the TFTE operates in the subthreshold region during the negative capacitance effect, thereby mitigating the subthreshold slope degradation of the TFTE.

2. The method for mitigating subthreshold slope degradation of tunneling field-effect transistors as described in claim 1, characterized in that, The highly doped source region and highly doped drain region contain impurities of different doping types. For an N-type transistor, the highly doped drain region consists of N... - The doped region is composed of a doping concentration of 1×10⁻⁶. 17 ~1×10 19 cm -3 The highly doped source region is composed of P + The doped region is composed of a doping concentration of 1×10⁻⁶. 20 ~1×10 21 cm -3 ; For a P-type transistor, the highly doped drain region is composed of P... - The doped region is composed of a doping concentration of 1×10⁻⁶. 17 ~1×10 19 cm -3 The highly doped source region consists of N + The doped region is composed of a doping concentration of 1×10⁻⁶. 20 ~1×10 21 cm -3 .

3. The method for mitigating subthreshold slope degradation of tunneling field-effect transistors as described in claim 1, characterized in that, The thickness of the metal equipotential layer ranges from 10 nm to 50 nm.

4. The method for mitigating subthreshold slope degradation of tunneling field-effect transistors as described in claim 1, characterized in that, The thickness of the antiferroelectric layer ranges from 1 nm to 20 nm.

5. The method for mitigating subthreshold slope degradation of a tunneling field-effect transistor as described in claim 1, characterized in that, The thickness of the gate electrode ranges from 10 nm to 50 nm.

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