Logic and memory function reconfigurable ferroelectric transistor device and method of making the same

Abstract

The application provides a ferroelectric transistor device with reconfigurable logic and storage functions, which comprises a control transistor and a ferroelectric transistor, and the control transistor and the ferroelectric transistor are connected; by adjusting the control transistor, the reconfiguration of the logic function and the storage function of the ferroelectric transistor is realized. The ferroelectric transistor device with reconfigurable logic and storage functions can realize the reconfiguration of the output state between an or gate and an inverter by setting the gate state and the storage state of the ferroelectric transistor.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit device technology, and more specifically, to a ferroelectric transistor device with reconfigurable logic and storage functions and its fabrication method. Background Technology

[0002] Integrated circuits have revolutionized modern information technology. For decades, their development has followed Moore's Law. However, as devices are integrated to the nanoscale, the performance of traditional devices is gradually approaching physical limits, and the era of Moore's Law is coming to an end. The post-Moore's Law era urgently needs new micro- and nano-electronic device technologies characterized by new materials, new structures, and new principles to provide new ideas and pathways for the continued development of integrated circuits. Currently, collaborative innovation in the following four areas is the mainstream and focus of electronic device technology in the post-Moore's Law era: 1) transistor device technology that transcends the Boltzmann limitation; 2) information storage materials and device technologies that surpass SRAM and DRAM; 3) three-dimensional integration technology for logic, storage, and other devices; and 4) high-performance heterogeneous integration technology. Several new transistor concepts have been proposed to break through the Boltzmann limitation, including negative capacitance transistors based on ferroelectric materials, tunneling transistors based on PN junctions, and phase-change transistors based on metal-insulator phase-change materials. Several memory devices based on new materials have also been proposed to achieve high-density non-volatile memory, including resistive random access memory (RRAM), phase-change memory (PCM), spintronic memory (SRAM), ferroelectric memory (FRAM), and ferroelectric transistors.

[0003] Ferroelectric transistors have demonstrated potential applications in both computing and storage technologies in the post-Moore's Law era. The concept of ferroelectric transistors has been around for over fifty years. In 2008, the negative capacitance transistor, with a similar structure, was proposed, expanding its functionality from high-performance storage to high-energy-efficiency computing. The discovery of the ferroelectric properties of HfO2, a high-k dielectric material already maturely used in CMOS processes in 2011, fundamentally solved key challenges limiting the application of this device structure (such as compatibility with CMOS processes, integrability, and toxicity). Furthermore, both ferroelectric transistors and negative capacitance transistors offer significant advantages over other device concepts in their respective application areas: for example, negative capacitance transistors can not only overcome the Boltzmann limit but also increase the on-state current, thereby achieving high-performance, low-power logic operations, which is difficult to achieve with other device concepts such as tunneling transistors; and ferroelectric transistors can achieve non-volatile storage and are field-controlled devices with only a 1T structure, offering higher integration density, lower energy consumption, and non-destructive readout compared to other 1T1C or 1T1R ferroelectric memory devices. Based on these advantages, both technologies hold enormous application potential in the fields of high-efficiency CMOS technology and high-density non-volatile memory technology.

[0004] However, there has been no exploration or research into the three-dimensional integration technology of ferroelectric transistors in logic, memory and other devices, as well as high-performance heterogeneous integration technology. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the purpose of this invention is to provide a ferroelectric transistor with reconfigurable logic and storage functions and a method for its fabrication.

[0006] According to one aspect of the present invention, a ferroelectric transistor device with reconfigurable logic and storage functions is provided, comprising a control transistor and a ferroelectric transistor connected together; the logic and storage functions of the ferroelectric transistor are reconfigured by adjusting the control transistor.

[0007] Preferably, the ferroelectric transistor is a dual-gate ferroelectric transistor with internal electrodes, wherein the portion below the internal first gate is a transistor comprising metal, an insulating layer, and a semiconductor, and the portion above the internal first gate comprises an insulating layer and an external second gate; the source and drain electrodes of the control transistor are respectively connected to the internal first gate and the external second gate of the ferroelectric transistor.

[0008] Preferably, the source electrode of the control transistor is connected to the external second gate of the dual-gate ferroelectric transistor, and the drain electrode is connected to the internal first gate. When the external second gate of the control transistor is low, it is in the off state, the drain electrode and the source electrode are disconnected, the internal first gate is high, and the dual-gate ferroelectric transistor is a logic transistor, realizing logic functions. When the external second gate of the control transistor is high, the drain electrode and the source electrode are connected, the internal first gate is high, the internal gate floats, and the dual-gate ferroelectric transistor is a ferroelectric storage transistor, realizing storage functions.

[0009] Preferably, the ferroelectric transistor is a dual-gate ferroelectric transistor with internal electrodes, wherein the portion below the internal first gate is a transistor comprising a metal, a ferroelectric layer, an insulating layer, and a semiconductor, and the portion above the internal first gate comprises an insulating layer and an external second gate; the source and drain electrodes of the control transistor are respectively connected to the internal first gate and the external second gate of the ferroelectric transistor.

[0010] Preferably, the source electrode of the control transistor is connected to the internal first gate, and the drain electrode of the control transistor is connected to the external second gate;

[0011] When the control transistor is in the off state, the internal first gate is at a high level and the external second gate is open at a low level, it is a ferroelectric transistor, which realizes the storage function;

[0012] The control transistor is in the off state, the external electrode of the ferroelectric transistor is at a high level, the internal electrode floats, and it is a negative capacitance transistor, thus realizing the storage function.

[0013] Preferably, the ferroelectric transistor is a dual-gate ferroelectric transistor containing a channel layer with gates on both sides. One side of the channel layer is a transistor comprising a metal, a ferroelectric layer, an insulating layer, and a semiconductor, and the other side is a control transistor comprising a metal, an insulating layer, and a semiconductor.

[0014] Preferably, the control transistor is in the off state, and the ferroelectric transistor performs the storage function;

[0015] The control transistor is in the ON state, and the hysteresis window of the ferroelectric transistor moves to realize the logic function.

[0016] Preferably, the control transistor and the ferroelectric transistor are linked through three-dimensional integration, and the source electrode and the drain electrode are connected to the gate through three-dimensional vias; the three-dimensional integration includes atomic layer deposition, magnetron sputtering, chemical vapor deposition and two-dimensional material transfer.

[0017] Preferably, the control transistor and the ferroelectric transistor are connected by a wire.

[0018] According to a second aspect of the present invention, a method for fabricating a ferroelectric transistor device with reconfigurable logic and storage functions is provided, comprising:

[0019] Semiconductor layers are fabricated on insulating substrates using silicon-on-insulator (SiO2) processes.

[0020] Source and drain regions were fabricated using photolithography and ion implantation processes;

[0021] Internal source electrodes and internal drain electrodes were fabricated using photolithography and magnetron sputtering metal deposition processes.

[0022] A dielectric layer is prepared on the semiconductor layer using an atomic layer deposition process;

[0023] The internal first gate was fabricated using photolithography and magnetron sputtering metal deposition processes;

[0024] A ferroelectric layer is fabricated on the internal gate;

[0025] An external second gate was fabricated using photolithography and magnetron sputtering metal deposition processes;

[0026] Ferroelectricity is achieved through a hot annealing process.

[0027] A first insulating layer is deposited on the prepared ferroelectric transistor having an internal first gate and an external second gate using a chemical vapor deposition method.

[0028] Three-dimensional via 1 and three-dimensional via 2 were fabricated using photolithography and dry etching processes;

[0029] Semiconductor layers were fabricated using magnetron sputtering and atomic layer deposition processes;

[0030] External source electrodes and external drain electrodes are fabricated using photolithography and magnetron sputtering metal deposition processes;

[0031] A second insulating layer is prepared on the semiconductor layer using an atomic layer deposition process;

[0032] The control gate was fabricated using photolithography and magnetron sputtering metal deposition processes.

[0033] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a ferroelectric transistor with reconfigurable logic and storage functions, which can realize the reconfiguration of the output state between NOR gates and inverters by setting the gate state and storage state of the output ferroelectric transistor. Attached Figure Description

[0034] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0035] Figure 1 This is a structural diagram of a reconfigurable ferroelectric transistor device according to the first structure of the embodiment provided by the present invention;

[0036] Figure 2 Is with Figure 1 The corresponding working principle diagram of the reconfigurable ferroelectric transistor device;

[0037] Figure 1 In the middle: 1-substrate, 2-semiconductor layer, 3-source region, 4-drain region, 5-internal source electrode, 6-internal drain electrode, 7-dielectric layer, 8-internal first gate, 9-ferroelectric layer, 10-external second gate, 11-first insulating layer, 12-three-dimensional via one, 13-three-dimensional via two, 14-thin film semiconductor, 15-external drain electrode, 16-external source electrode, 17-second insulating layer, 18-control gate;

[0038] Figure 3 This is a structural diagram of a reconfigurable ferroelectric transistor device according to the second structure of the embodiment provided by the present invention;

[0039] Figure 4 Is with Figure 3 The corresponding working principle diagram of the reconfigurable ferroelectric transistor device;

[0040] Figure 3In the middle: 20-Left semiconductor layer, 21-Left source region, 22-Left drain region, 23-Left source electrode, 24-Left drain electrode, 25-First dielectric layer, 26-Ferroelectric layer, 27-Inner first gate, 28-Second dielectric layer, 29-Outer second gate, 30-Wire 1, 31-Wire 2, 32-Right semiconductor, 33-Dielectric layer, 34-Right source region, 35-Right drain region, 36-Right source electrode, 37-Right drain electrode, 38-Insulating layer, 39-Control gate;

[0041] Figure 5 This is a structural diagram of a reconfigurable ferroelectric transistor device according to the third structure of the embodiments provided by the present invention;

[0042] Figure 6 Is with Figure 5 The corresponding working principle diagram of the reconfigurable ferroelectric transistor device;

[0043] Figure 5 In the middle: 40-substrate, 41-gate, 42-dielectric layer, 43-channel layer, 44-insulating layer, 45-source region, 46-drain region, 47-source electrode, 48-drain electrode, 49-dielectric layer, 52-ferroelectric layer, 51-external gate;

[0044] Figure 7 This is a schematic diagram illustrating the application principle of a reconfigurable ferroelectric transistor according to a preferred embodiment of the present invention. Detailed Implementation

[0045] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0046] The present invention provides an embodiment of a ferroelectric transistor device with reconfigurable logic and storage functions, comprising a control transistor and a ferroelectric transistor connected together; the logic and storage functions of the ferroelectric transistor can be reconfigured by adjusting the control transistor.

[0047] To better perform function switching and reconfiguration, the present invention provides three structures as three preferred embodiments.

[0048] This invention provides a preferred embodiment of a first structure for constructing a ferroelectric transistor device with reconfigurable logic and storage functions. The first structure is a dual-gate ferroelectric transistor structure with internal electrodes. The portion below the internal first gate is similar to a conventional metal-insulator-semiconductor transistor, while the portion above the internal first gate is composed of an insulating layer and an external second gate. The source and drain electrodes of the control transistor are connected to the two gates respectively. Specifically, as shown... Figure 1 As shown:

[0049] The first structure of the reconfigurable ferroelectric transistor includes a conventional gate-insulator-semiconductor transistor structure, which includes an insulating substrate 1, a semiconductor layer 2, a source region 3, a drain region 4, an internal source electrode 5, an internal drain electrode 6, a dielectric layer 7, an internal first gate 8, a ferroelectric layer 9 on the internal first gate 8, and an external second gate 10. The above components constitute a dual-gate ferroelectric transistor structure.

[0050] The control gate 18, the second insulating layer 17, the external drain electrode 15 and the external source electrode 16 of the thin film semiconductor 14 transistor structure are connected to the internal first gate 8 and the external second gate 10 through three-dimensional through-hole 12 and three-dimensional through-hole 2 13 respectively. The above components serve as control transistors.

[0051] Furthermore, in this embodiment, the dual-gate ferroelectric transistor is specifically configured as follows: an edge substrate 1 is located at the bottom; a semiconductor layer 2 is located on the upper surface of the edge substrate; a source region 3 is located at one end of the upper surface of the edge substrate 1; a drain region 4 is located at the other end of the upper surface of the edge substrate 1; an inner edge electrode 5 is located on the upper surface of the source region 3; an inner drain electrode 6 is located on the upper surface of the drain region 4; a dielectric layer 7 is located on the upper surface of the semiconductor layer 2; an inner first gate is located on the upper surface of the dielectric layer 7; a ferroelectric layer 9 is located above the inner first gate 8; and an outer second gate 10 is located above the ferroelectric layer 9.

[0052] The control transistor is specifically configured as follows: a control gate 18 is located at the top; a second insulating layer 17 is located below the control gate 18; a thin-film semiconductor 14 is located below the second insulating layer 17; an external electrode 16 is located at one end of the thin-film semiconductor 14; and an external drain electrode 15 is located at the other end of the thin-film semiconductor 14. The external electrode 16 is connected to the internal first gate 8 and the external second gate 10 through three-dimensional via 12 and three-dimensional via 13, respectively. The control transistor and the dual-gate ferroelectric transistor are separated by the first insulating layer 11.

[0053] The working principle of this embodiment is as follows: Figure 2 As shown, when the control gate 18 of the control transistor is low, it is in the off state. The external second gate 10 is open, and the internal first gate 8 is high. The dual-gate ferroelectric transistor is equivalent to a traditional logic transistor and realizes logic functions.

[0054] When the control gate 18 of the control transistor is at a high level, the external second gate 10 is at a high level, and the internal first gate 8 floats. The dual-gate ferroelectric transistor is equivalent to a ferroelectric storage transistor, realizing the storage function.

[0055] This invention provides another preferred embodiment of a second structure for constructing a ferroelectric transistor device with reconfigurable logic and storage functions. The second structure is also a dual-gate ferroelectric transistor structure with internal electrodes, but the portion below the internal gate is similar to the conventional metal-ferroelectric layer-insulator-semiconductor transistor structure, while the portion above the internal gate is composed of an insulating layer and an external gate. The source and drain electrodes of the transistor at the control terminal are respectively connected to the two gates. Specifically, as shown... Figure 3 As shown:

[0056] The second structure of the reconfigurable ferroelectric transistor includes an edge substrate 19, a left semiconductor layer 20, a left source region 21, a left drain region 22, a left source electrode 23, a left drain electrode 24, a first dielectric layer 25, a ferroelectric layer 26, an internal first gate 27, a second dielectric layer 28, and an external second gate 29 thereon, the above components forming a dual-gate ferroelectric transistor structure.

[0057] The right semiconductor 32, dielectric layer 33, right source region 34, right drain region 35, and control gate 39 are connected to the right source electrode 36 and right drain electrode 37 of the control transistor via wires 30 and 31, respectively, to the internal first gate 27 and the external second gate 29. The above components serve as control transistors.

[0058] Furthermore, the edge substrate 19 is located at the bottom, and the left semiconductor layer 20 and the right semiconductor layer 32 are respectively mounted above the edge substrate 19. The left source region 34 and the left drain region 22 are distributed on both sides of the left semiconductor layer 20; the left source electrode 23 and the left drain electrode 24 are respectively disposed above the left source region 34 and the left drain region 22. The right source region 34 and the right drain region 35 are distributed on both sides of the right semiconductor layer 32, and the right source electrode 36 and the right drain electrode 37 are respectively disposed above the right source region 34 and the right drain region 35.

[0059] The first dielectric layer 25 is located on the left semiconductor 20. The first dielectric layer 25 consists of, in sequence, a ferroelectric layer 26, an inner first gate 27, a second dielectric layer 28, and an outer second gate 29.

[0060] The insulating layer 38 is located above the right semiconductor layer 32, and the control gate 39 is located above the insulating layer 38. The right source electrode 36 and the right drain electrode 37 are connected to the external second gate 29 and the internal gate 27 through wires 31 and 30, respectively.

[0061] The working principle of this embodiment is as follows: Figure 4As shown, when the control gate 39 of the control transistor is low, it is in the off state; the internal first gate 27 is high; and the external second gate 29 is open and low, equivalent to a traditional ferroelectric transistor, thus realizing the storage function. When the control gate 39 of the control transistor is low, it is in the off state; the external gate 29 of the ferroelectric transistor is high; and the internal first gate 27 floats, equivalent to a negative capacitor transistor, thus realizing the logic function.

[0062] This invention provides a third preferred embodiment for constructing a ferroelectric transistor device with reconfigurable logic and storage functions. The third structure is a dual-gate ferroelectric transistor structure with gates on both sides of the channel layer. One side of the channel layer is a conventional metal-ferroelectric layer-insulator-semiconductor transistor structure, and the other side is a metal-insulator-semiconductor transistor structure serving as a control transistor. When the control transistor is in the off state, the ferroelectric transistor performs the storage function; when the control transistor is in the on state, the movement of the hysteresis window of the ferroelectric transistor enables the logic function. Specifically, as shown... Figure 5 As shown:

[0063] The third structure of the reconfigurable ferroelectric transistor includes a substrate 40, a gate 41, a first dielectric layer 42, a channel layer 43, an insulating layer 44, a source region 45, a drain region 46, a source electrode 47, and a drain electrode 48 forming a back-gate control transistor, and a second dielectric layer 49, a ferroelectric layer 50, and an external gate 51 on top of the channel source and drain to form a ferroelectric transistor. The channel layer 43 has a dual-gate ferroelectric transistor structure with gates on both sides; one side of the channel layer is a conventional metal-ferroelectric layer-insulator-semiconductor transistor structure, and the other side is a metal-insulator-semiconductor transistor structure serving as the control transistor.

[0064] Furthermore, substrate 40 is located at the bottom, internal gate 41 is located above substrate 40, and first dielectric layer 42 and channel layer 43 are sequentially stacked above internal first gate 41; insulating layer 44 is located on both sides of the stacked internal first gate 41 and first dielectric layer 42; source region 45 and drain region 46 are respectively located on both sides of channel layer 43, and source electrode 47 and drain electrode 48 are respectively located above source region 45 and drain region 46. Second dielectric layer 49, ferroelectric layer 50 and external gate 51 are sequentially stacked above channel layer 43 from bottom to top.

[0065] The working principle of this embodiment is as follows: Figure 6 As shown, when the external gate 51 of the control transistor is low, the ferroelectric transistor performs the storage function; when the external gate 51 of the control transistor is high, the ferroelectric transistor performs the logic function.

[0066] In other embodiments of the present invention, the semiconductor material in the first and second structures described above includes all semiconductor materials, including Si, Ge, oxides, organic semiconductors, wide bandgap semiconductors, and two-dimensional semiconductor materials.

[0067] The third structure mentioned above uses any type of thin-film semiconductor material, including oxides, organic materials, two-dimensional materials, etc. The thickness of the semiconductor material is 0.5-10μm, and a gate dielectric stack can be formed on both sides of the channel.

[0068] The insulating layer in the three structures includes any of the insulating layer materials, including oxides, two-dimensional materials, and organic materials, with an insulating layer thickness of 0.5-500 nm.

[0069] The ferroelectric layer in the three structures includes all ferroelectric materials such as oxides, perovskites, two-dimensional materials, and organic materials, with a thickness of 2-1 μm.

[0070] The gate material in the three structures includes any of all conductive materials, such as elemental metals, heavily doped semiconductors, two-dimensional conductive materials, and organic conductive materials, with a gate thickness of 0.5-200 nm.

[0071] The source and drain electrode materials in the three structures include any one of elemental metal materials, alloy materials, and heavily doped semiconductor materials, or a stack of the above materials.

[0072] The control transistors and ferroelectric transistors in the three structures can be linked through three-dimensional integration. Furthermore, the three-dimensional integration method includes any one of atomic layer deposition, magnetron sputtering, chemical vapor deposition, or two-dimensional material transfer.

[0073] Based on the same concept as the above embodiments, in other embodiments of the present invention, a fabrication process method for a first structure of a reconfigurable ferroelectric transistor is also provided, including:

[0074] S1, a semiconductor layer 2 is fabricated on an insulating substrate 1 using processes such as silicon-on-insulator (SOI);

[0075] S2, doped source region 3 and drain region 4 are prepared using photolithography and ion implantation processes;

[0076] S3, the internal source electrode 5 and the internal drain electrode 6 are prepared by metal deposition processes such as photolithography and magnetron sputtering;

[0077] S4, a dielectric layer 7 is prepared on semiconductor layer 2 using an atomic layer deposition process;

[0078] S5, then the internal first gate 8 is prepared by metal deposition processes such as photolithography and magnetron sputtering;

[0079] S6, a ferroelectric layer 9 is prepared on the internal first gate 8, typically a ferroelectric hafnium-based oxide based on atomic layer deposition process;

[0080] S7, then the external second gate 10 is prepared by metal deposition processes such as photolithography and magnetron sputtering;

[0081] S8, then undergoes a hot annealing process to form ferroelectric properties;

[0082] S9, deposit a first insulating layer 11 on the ferroelectric transistor with an internal first gate prepared above by means of chemical vapor deposition or the like;

[0083] S10, using photolithography and dry etching processes to prepare three-dimensional through-hole 12 and three-dimensional through-hole 23;

[0084] S11, then a semiconductor layer 14 is prepared based on processes such as magnetron sputtering and atomic layer deposition. The materials that can be selected include, but are not limited to, oxide semiconductors, low-temperature polycrystalline silicon, amorphous silicon, two-dimensional semiconductors, etc.

[0085] S12, then the external electrode 15 and the external drain electrode 16 are prepared based on metal deposition processes such as photolithography and magnetron sputtering;

[0086] S13, a second insulating layer 17 is prepared on the semiconductor layer 14 using an atomic layer deposition process;

[0087] S14, then use metal deposition processes such as photolithography and magnetron sputtering to prepare the control gate 18.

[0088] Embodiments of the present invention can be controlled via a control terminal (V) C This enables ferroelectric transistors to switch between logic and storage functions, thus allowing for the reconfiguration of logic units such as NOR gates and inverters using a single device. For example... Figure 7 An example of a reconfigurable inverter is given, including its circuit structure. Figure 7 As shown in the middle left figure, the truth table of the reconfigurable inverter is as follows: Figure 7 As shown in the middle right figure, by controlling VC and the ferroelectric polarization state (Q(FE)), the logic function of the reconfigurable inverter can be switched between a normal inverter, open circuit, and short circuit. Reconfigurable NAND, XOR, and other logic can also be achieved through complex circuit design.

[0089] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention. The above preferred features can be used in any combination without conflict.

Claims

1. A ferroelectric transistor device with reconfigurable logic and storage functions, characterized in that, It includes a control transistor and a ferroelectric transistor, which are connected together; by adjusting the control transistor, the logic function and storage function of the ferroelectric transistor can be reconfigured. The ferroelectric transistor is a dual-gate ferroelectric transistor with internal electrodes, including an internal first gate. The portion below the internal first gate is a transistor comprising a metal, a ferroelectric layer, an insulating layer, and a semiconductor. The portion above the internal first gate includes an insulating layer and an external second gate. The source and drain electrodes of the control transistor are respectively connected to the internal first gate and the external second gate of the ferroelectric transistor. The source electrode of the control transistor is connected to the internal first gate, and the drain electrode of the control transistor is connected to the external second gate. When the control transistor is in the off state, the internal first gate is at a high level, and the external second gate is open at a low level, it is a ferroelectric transistor, which realizes the storage function; The control transistor is in the ON state, the external second gate is at a high level, and the internal first gate is floating, which is a negative capacitance transistor, to realize the logic function.

2. The ferroelectric transistor device with reconfigurable logic and storage functions according to claim 1, characterized in that: The control transistor and the ferroelectric transistor are connected by a wire.

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