Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure and a manufacturing method thereof, wherein the chip packaging structure comprises: a substrate, a chip and a transparent cover plate; the substrate comprises a core plate, an insulating layer arranged on the surface of the core plate and at least one metal wiring layer, the surface of the core plate is provided with a groove, the chip is arranged in the groove and is electrically connected to the metal wiring layer; the insulating layer located on the chip side is provided with an opening, and the opening at least exposes a part of the chip; the transparent cover plate is arranged in the opening, and at least a part of the edge area of ​​the transparent cover plate is nested in the insulating layer, and a certain distance is spaced between the transparent cover plate and the chip. There is no need to directly attach the transparent cover plate to the chip, which avoids the influence of the glue layer on the light transmittance of the packaging structure and improves the sensing accuracy of the chip. At the same time, the nested structure increases the fixing effect on the transparent cover plate, strengthens the stability of the transparent cover plate structure, and further improves the stability of the packaging structure.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic packaging, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] Currently, in the chip packaging structure of photosensitive devices, a piece of glass needs to be attached above the chip for protection and light transmission. However, some current solutions directly bond the glass and chip with a glue layer, which will affect the light transmittance. In addition, the adhesion between the chip and the glass is poor, and voids will appear in the glue layer. Other solutions directly use the glass plate as a substrate or a protective cover plate directly suspended on the substrate. In this case, the glass plate is prone to peeling and displacement, causing damage to the device. Summary of the invention

[0003] The object of the present invention is to provide a chip packaging structure and a manufacturing method thereof.

[0004] The present invention provides a chip packaging structure, the chip packaging structure comprising:

[0005] Substrate, chip and transparent cover;

[0006] The substrate comprises a core board, an insulating layer arranged on the surface of the core board and at least one metal wiring layer, the surface of the core board is provided with a groove, the chip is arranged in the groove and is electrically connected to the metal wiring layer;

[0007] The insulating layer located at the chip side is provided with an opening, and the opening at least exposes a portion of the chip;

[0008] The transparent cover plate is arranged in the opening, and at least a part of the edge area of ​​the transparent cover plate is nested in the insulating layer. The transparent cover plate is spaced a certain distance from the chip.

[0009] As a further improvement of the present invention, the insulating layer includes an inner insulating layer located on the upper and lower surfaces of the core board and a solder resist layer located on the surface of the inner insulating layer.

[0010] As a further improvement of the present invention, the edge area of ​​the transparent cover is nested in the inner insulating layer.

[0011] As a further improvement of the present invention, an inner metal wiring layer is arranged between the core board and the inner insulating layer, the chip is electrically connected to the inner metal wiring layer, an outer metal wiring layer is arranged on the surface of the inner insulating layer, and the inner metal wiring layer and the outer metal wiring layer are electrically connected through metal through holes arranged in the core board and the inner insulating layer.

[0012] As a further improvement of the present invention, the transparent cover plate is arranged between the inner insulating layer and the solder resist layer, and the solder resist layer covers the edge area of ​​the transparent cover plate.

[0013] As a further improvement of the present invention, an inner metal wiring layer is arranged in the inner insulating layer, the chip is electrically connected to the inner metal wiring layer, an outer metal wiring layer is arranged on the side surface of the inner insulating layer facing away from the chip, and the inner metal wiring layer and the outer metal wiring layer are electrically connected via metal through holes arranged in the core board and the inner insulating layer.

[0014] The present invention also provides a chip packaging structure manufacturing method, comprising the steps of:

[0015] Providing a core plate, forming a groove on the surface of the core plate and a through hole penetrating the core plate;

[0016] placing a chip in the groove;

[0017] Plating metal on the upper and lower surfaces of the core board and in the through hole, and etching to form an inner metal wiring layer;

[0018] A transparent cover plate is attached to the chip side so that the transparent cover plate covers the chip, and an inner insulating layer is pressed on the upper and lower surfaces of the core board;

[0019] Forming a plated metal on the surface of the inner insulating layer and etching to form an outer metal wiring layer;

[0020] A solder resist layer is formed on the surface of the outer metal wiring layer.

[0021] As a further improvement of the present invention, “bonding a transparent cover plate to the chip side and pressing an inner insulating layer on the upper and lower surfaces of the core plate” specifically includes:

[0022] Firstly attaching a transparent cover plate to the side of the core plate adjacent to the chip;

[0023] Then, an inner insulating layer is pressed on the upper and lower surfaces of the core board.

[0024] As a further improvement of the present invention, “bonding a transparent cover plate to the chip side and pressing an inner insulating layer on the upper and lower surfaces of the core plate” specifically includes:

[0025] Firstly, an inner insulating layer is pressed on the upper and lower surfaces of the core plate;

[0026] A transparent cover plate is then attached to the inner insulating layer adjacent to the chip.

[0027] As a further improvement of the present invention, the groove depth is greater than the chip thickness.

[0028] The beneficial effects of the present invention are as follows: the present invention nests the transparent cover plate inside the insulating layer, thereby eliminating the need to directly attach the transparent cover plate to the chip, thereby avoiding the influence of the adhesive layer on the light transmittance of the packaging structure, and improving the sensing accuracy of the chip. At the same time, the nested structure increases the fixing effect on the transparent cover plate, strengthens the stability of the transparent cover plate structure, and can limit the transparent cover plate in the horizontal direction, thereby avoiding the transparent cover plate from falling off or shifting during use due to the small bonding and fixing area, and further improving the stability of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the packaging structure in Example 1 of the present invention.

[0030] Figure 2 It is a schematic diagram of the packaging structure in Example 2 of the present invention.

[0031] Figure 3 It is a schematic diagram of the manufacturing process of the packaging structure in Example 2 of the present invention.

[0032] Figures 4 to 9 It is a schematic diagram of each step of the manufacturing process of the packaging structure in Example 2 of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in combination with the specific implementation methods of this application and the corresponding drawings. Obviously, the described implementation methods are only part of the implementation methods of this application, not all of the implementation methods. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0035] For ease of explanation, this document uses terms that represent relative positions in space for description, such as "above", "below", "back", "front", etc., to describe the relationship of one unit or feature shown in the drawings relative to another unit or feature. Terms of relative positions in space can include different orientations of the device in use or operation other than the orientation shown in the figure. For example, if the device in the figure is turned over, the unit described as being "below" or "above" other units or features will be located "below" or "above" the other units or features. Therefore, the exemplary term "below" can encompass both the spatial orientations of below and above.

[0036] Example 1

[0037] like Figure 1 As shown, a chip 2 packaging structure suitable for optical devices such as photosensitive devices is provided in Example 1 of the present invention, which includes: a substrate 1, a chip 2 and a transparent cover 3.

[0038] The substrate 1 includes a core board 11 (core layer), an insulating layer 12 arranged on the surface of the core board 11, and at least one metal wiring layer 13. Among them, the core board 11 is a plate-like material made by impregnating glass fiber cloth or other reinforcing materials with resin and hot pressing. It is the main base material of the substrate 1 and can play the role of insulation and support. The insulating layer 12 includes an inner insulating layer 121 located on the upper and lower surfaces of the core board 11 and a solder resist layer 122 located on the surface of the inner insulating layer 121. The inner insulating layer 121 is a PP (prepreg) layer, which is composed of semi-solid resin and glass fiber or other reinforced substrates. It constitutes an impregnation layer and mainly plays the role of filling and bonding the layers in the substrate 1. The solder resist layer 122 is a thin layer formed by a solder resist material covering the surface of the substrate 1, which can prevent the metal wiring layer 13 from being affected by oxidation, moisture, and mechanical stress.

[0039] A groove 111 is provided on the surface of the core board 11 . The shape of the groove 111 is adapted to the chip and is usually square. The groove 111 is used to place the chip 2 . The groove 111 can be formed by laser or other methods.

[0040] Furthermore, the depth of the groove 111 is greater than the thickness of the chip 2, thereby ensuring that a certain distance is maintained between the upper surface of the chip 2 and the upper surface of the core board 11, so as to ensure that there is no direct contact between the transparent cover board 3 placed above the chip 2 and the chip 2. Placing the chip 2 in the groove 111 opened on the substrate 1 is similar to an embedded packaging structure, which can effectively utilize the space of the substrate 1 and reduce the thickness of the chip 2 packaging structure, which is conducive to meeting the miniaturization requirements of the packaging structure.

[0041] The chip 2 is disposed in the groove 111 and electrically connected to the metal wiring layer 13. The chip 2 is fixedly attached to the groove 111 by an adhesive layer. The adhesive layer can be a polymer adhesive material, such as a polymer material such as silicone, epoxy resin, benzocyclobutene, etc. It can be understood that the depth of the groove 111 is also greater than the total thickness of the chip 2 and the adhesive layer.

[0042] The insulating layer 12 located at the chip 2 side is provided with an opening 123 , and the opening 123 at least exposes a portion of the chip 2 for placing the transparent cover plate 3 buried therein.

[0043] Furthermore, the transparent cover plate 3 is arranged in the opening 123, and at least a part of the edge area of ​​the transparent cover plate 3 is nested in the insulating layer 12, and a certain distance is between the transparent cover plate 3 and the chip 2, that is, a cavity is formed between the transparent cover plate 3 and the chip 2. The material of the transparent cover plate 3 can be inorganic glass, organic glass or other light-transmitting materials with a specific strength, which plays a role in protecting the chip 2 and transmitting light. The upper and lower surfaces of the transparent cover plate 3 are both flat and smooth surfaces to avoid scattering, diffuse reflection and other effects on the incident light, thereby affecting the sensing accuracy of the chip 2. The transparent cover plate 3 is nested in the insulating layer 12, and there is no direct contact between the chip 2. There is no need to set an adhesive layer between the chip 2 and the transparent cover plate 3, which avoids the influence of the adhesive layer on the transmittance, thereby making the overall transmittance of the packaging structure higher, which is conducive to improving the sensing accuracy of the chip 2. In addition to being fixed to the insulating layer 12 through the adhesive layer, the transparent cover plate 3 is nested inside the insulating layer 12 to form a snap-fit ​​structure between the two, thereby fixing the transparent tube cover plate 3 and enhancing the stability of the packaging structure. In addition, since the sides of the transparent cover plate 3 are also restricted by the insulating layer 12, the transparent cover plate 3 can be limited in the horizontal direction, thereby avoiding the transparent cover plate 3 from falling off or shifting during use due to the small adhesive fixing area, thereby further improving the stability of the packaging structure.

[0044] Specifically, in Example 1, the edge area of ​​the transparent cover plate 3 is nested in the inner insulating layer 121. An inner metal wiring layer 131 is provided between the core plate 11 and the inner insulating layer 121, and the chip 2 is electrically connected to the inner metal wiring layer 131. An outer metal wiring layer 132 is provided on the surface of the inner insulating layer 121, and the inner metal wiring layer 131 and the outer metal wiring layer 132 are electrically connected through metal through holes 14 provided in the core plate 11 and the inner insulating layer 121. In the manufacturing process, the transparent cover plate 3 is first directly bonded and fixed to the inner metal wiring layer 131 through the adhesive layer, and then the inner insulating layer 121 is pressed, so that the transparent cover plate 3 is nested in the inner insulating layer 121.

[0045] Furthermore, the thickness of the inner metal wiring layer 131 located on the chip 2 side can also be designed as needed. Since the transparent cover 3 is directly attached thereto, controlling the thickness of the inner metal wiring layer 131 can also play a role in controlling the spacing distance between the transparent cover 3 and the chip 2.

[0046] Example 2

[0047] like Figure 2 As shown, a chip 2 packaging structure suitable for optical devices such as photosensitive devices provided by embodiment 2 of the present invention is similar in general structure to embodiment 1, and the difference from embodiment 1 is that:

[0048] The transparent cover plate 3 is disposed between the inner insulating layer 121 and the solder resist layer 122, and the solder resist layer 122 covers the edge area of ​​the transparent cover plate 3. In the manufacturing process, the inner insulating layer 121 is pressed first, and then the transparent cover plate 3 is attached to the inner insulating layer 121, so that the solder resist layer 122, the inner insulating layer 121 and the transparent cover plate 3 form a nested structure to fix the transparent cover plate.

[0049] An inner metal wiring layer 131 is arranged in the inner insulating layer 121, and the chip 2 is electrically connected to the inner metal wiring layer 131. An outer metal wiring layer 132 is arranged on the side surface of the inner insulating layer 121 facing away from the chip 2, and the inner metal wiring layer 131 and the outer metal wiring layer 132 are electrically connected via metal through holes 14 arranged in the core board 11 and the inner insulating layer 121.

[0050] Example 3

[0051] like Figure 3 As shown, Embodiment 3 of the present invention further provides a method for manufacturing a chip 2 packaging structure, comprising the steps of:

[0052] S1: Figure 4 As shown, a core plate 11 is provided, and a groove 111 and a through hole penetrating the core plate 11 are formed on the surface of the core plate 11 .

[0053] Specifically, a groove 111 whose shape matches the chip 2 can be formed on the surface of the core board 11 by laser lithography, and the depth of the groove 111 is greater than the thickness of the chip 2, thereby ensuring that a certain distance is maintained between the upper surface of the chip 2 and the upper surface of the core board 11.

[0054] Before step S1, the method further includes:

[0055] Baking the core board 11 to remove moisture;

[0056] The copper layer originally coated on the front side of the core board 11 is completely etched away, and the copper layer originally coated on the back side of the core board 11 is etched to reduce the thickness, so as to facilitate the subsequent processes.

[0057] S2: Figure 5As shown, the chip 2 is placed in the groove 111 .

[0058] Specifically, the chip 2 is bonded and fixed in the groove 111 by using a polymer material such as silica gel, epoxy resin, benzocyclobutene, etc.

[0059] S3: Metal is plated on the upper and lower surfaces of the core board 11 and in the through holes, and then etched to form an inner metal wiring layer 131 .

[0060] Specifically, step S3 includes:

[0061] like Figure 6a As shown, a protective film is attached to the chip 2 to expose the pad area of ​​the chip 2, and copper is plated on the front side of the core board 11 so that the pad of the chip 2 is electrically connected to the copper layer.

[0062] like Figure 6b As shown, copper plating is further performed and the copper plating thickness is controlled so as to adjust the distance between the transparent cover plate 3 and the chip 2 which are subsequently arranged.

[0063] like Figure 6c As shown, the copper layer is made into an inner metal wiring layer 131 through processes such as exposure, development, and etching.

[0064] S4: attaching the transparent cover plate 3 to the side of the chip 2 so that the transparent cover plate 3 covers the chip 2 , and pressing the inner insulating layer 121 on the upper and lower surfaces of the core board 11 .

[0065] Specifically, in this embodiment, if Figure 7a As shown, the transparent cover plate 3 is first attached to the side of the core plate 11 adjacent to the chip 2, and the transparent cover plate 3 is bonded to the inner metal wiring layer 131 through a polymer material.

[0066] like Figure 7b As shown, the inner insulating layer 121 is then pressed onto the upper and lower surfaces of the core board 11 , so that the transparent cover board 3 is nested in the inner insulating layer 121 .

[0067] S5: Figure 8 As shown, a plated metal is formed on the surface of the inner insulating layer 121 and then etched to form an outer metal wiring layer 132 .

[0068] Step S5 further includes: forming a through hole in the inner insulating layer 121 , and plating metal in the through hole so that the inner metal wiring layer 131 and the outer metal wiring layer 132 are electrically connected.

[0069] S6: Fig. 9 As shown, a solder resist layer 122 is formed on the surface of the outer metal wiring layer 132 .

[0070] Example 4

[0071] Embodiment 4 of the present invention further provides a method for manufacturing a chip 2 packaging structure, which has substantially the same steps as those of embodiment 3, except that step S4 specifically includes:

[0072] First, the inner insulating layer 121 is pressed onto the upper and lower surfaces of the core plate 11;

[0073] The transparent cover plate 3 is then attached to the inner insulating layer 121 adjacent to the chip 2. Then, the inner insulating layer 121 and the transparent cover plate 3 are covered with a solder resist layer 122 so that a nested structure is formed between the transparent cover plate 3 and the inner insulating layer 121 and the solder resist layer 122.

[0074] In summary, the present invention nests the transparent cover plate inside the insulating layer, thereby eliminating the need to directly attach the transparent cover plate to the chip, avoiding the influence of the adhesive layer on the light transmittance of the packaging structure, and improving the sensing accuracy of the chip. At the same time, the nested structure increases the fixing effect on the transparent cover plate, strengthens the stability of the transparent cover plate structure, and can limit the transparent cover plate in the horizontal direction, avoiding the transparent cover plate from falling off or shifting during use due to the small bonding and fixing area, and further improving the stability of the packaging structure.

[0075] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0076] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. All equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: Substrate, chip and transparent cover; The substrate comprises a core board, an insulating layer arranged on the surface of the core board and at least one metal wiring layer, the surface of the core board is provided with a groove, the chip is arranged in the groove and is electrically connected to the metal wiring layer; The insulating layer located at the chip side is provided with an opening, and the opening at least exposes a portion of the chip; The transparent cover is disposed in the opening, and at least a portion of the edge region of the transparent cover is nested in the insulating layer, and a certain distance is spaced between the transparent cover and the chip; The chip packaging structure also includes a through hole passing through the upper and lower surfaces of the core board, and an inner metal wiring layer located on the upper and lower surfaces of the core board and in the through hole. The chip is electrically connected to the inner metal wiring layer, the through hole is spaced apart from the chip, and the insulating layer and the inner metal wiring layer are stacked to form a rewiring layer structure.

2. The chip packaging structure according to claim 1, characterized in that: The insulating layer includes an inner insulating layer located on the upper and lower surfaces of the core board and a solder resist layer located on the surface of the inner insulating layer.

3. The chip packaging structure according to claim 2, characterized in that: The edge area of ​​the transparent cover is nested in the inner insulating layer.

4. The chip packaging structure according to claim 3, characterized in that: An inner metal wiring layer is arranged between the core board and the inner insulating layer, an outer metal wiring layer is arranged on the surface of the inner insulating layer, and the inner metal wiring layer and the outer metal wiring layer are electrically connected through metal through holes arranged in the core board and the inner insulating layer.

5. The chip packaging structure according to claim 2, characterized in that: The transparent cover plate is arranged between the inner insulating layer and the solder resist layer, and the solder resist layer covers the edge area of ​​the transparent cover plate.

6. The chip packaging structure according to claim 5, characterized in that: An inner metal wiring layer is arranged in the inner insulating layer, and an outer metal wiring layer is arranged on the side surface of the inner insulating layer away from the chip. The inner metal wiring layer and the outer metal wiring layer are electrically connected through metal through holes arranged in the core board and the inner insulating layer.

7. A method for manufacturing a chip packaging structure, characterized in that: Includes steps: Providing a core plate, forming a groove on the surface of the core plate and a through hole penetrating the core plate; placing a chip in the groove; Plating metal on the upper and lower surfaces of the core board and in the through hole, and etching to form an inner metal wiring layer, the chip is electrically connected to the inner metal wiring layer, and the through hole is spaced apart from the chip; A transparent cover plate is attached to the chip side so that the transparent cover plate covers the chip, and an inner insulating layer is pressed on the upper and lower surfaces of the core board; Forming a plated metal on the surface of the inner insulating layer and etching to form an outer metal wiring layer; A solder resist layer is formed on the surface of the outer metal wiring layer, and the inner metal wiring layer, the inner insulating layer, the outer metal wiring layer and the solder resist layer are stacked to form a redistribution layer structure.

8. The method for manufacturing a chip packaging structure according to claim 7, characterized in that: "Attaching a transparent cover plate to the chip side and pressing an inner insulating layer on the upper and lower surfaces of the core plate" specifically includes: Firstly attaching a transparent cover plate to the side of the core plate adjacent to the chip; Then, an inner insulating layer is pressed on the upper and lower surfaces of the core board.

9. The method for manufacturing a chip packaging structure according to claim 7, The characteristic is that, "Attaching a transparent cover plate to the chip side and pressing an inner insulating layer on the upper and lower surfaces of the core plate" specifically includes: Firstly, an inner insulating layer is pressed on the upper and lower surfaces of the core plate; A transparent cover plate is then attached to the inner insulating layer adjacent to the chip.

10. The method for manufacturing a chip packaging structure according to claim 7, characterized in that: The groove depth is greater than the chip thickness.

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