Red light micro light emitting diode chip and preparation method thereof

Abstract

The present disclosure provides a red light micro-light emitting diode chip and a preparation method thereof, belonging to the field of optoelectronic manufacturing technology. The chip includes: a substrate, an epitaxial structure, a first passivation layer, a metal reinforcement layer, a first electrode, and a second electrode; the epitaxial structure includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked on the substrate in sequence, the surface of the second semiconductor layer has a groove exposing the first semiconductor layer, the first electrode is located on the surface of the first semiconductor layer, and is located on the bottom surface of the groove, and the second electrode is located on the surface of the second semiconductor layer; the first passivation layer at least covers the surface of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer, and the second electrode, the metal reinforcement layer is located on the first passivation layer, and the orthographic projection of the metal reinforcement layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate. The embodiment of the present disclosure can effectively alleviate the problem of crack failure of the chip caused by stress generated by welding.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a red light micro light emitting diode chip and a preparation method thereof. Background Art

[0002] Micro LED refers to an ultra-small light-emitting diode with a side length of 10μm to 100μm, and a red micro LED is a diode that emits red light. Micro LEDs are small in size and can be arranged more densely to greatly improve resolution. They also have self-luminous properties, high brightness, high contrast, high responsiveness and power saving.

[0003] In the related art, a red light micro-LED chip generally includes a substrate, an epitaxial structure, a first electrode, a second electrode, a passivation layer, a first solder point block and a second solder point block. The epitaxial structure is stacked on the substrate, the first electrode and the second electrode are both arranged on the side of the epitaxial structure away from the substrate, the passivation layer is located on the epitaxial structure and covers the two electrodes. The first solder point block and the second solder point block are located on the passivation layer and are respectively connected to the two electrodes through vias on the passivation layer.

[0004] The two solder joints are usually made on the surface of the passivation layer by laser welding. However, due to the rapid rise and fall of temperature during laser welding, stress will be generated in the chip, which can easily cause cracks in the epitaxial structure of the chip and cause chip failure. Summary of the invention

[0005] The disclosed embodiment provides a red light micro-LED chip and a method for manufacturing the same, which can effectively alleviate the problem of crack failure of the chip caused by stress generated by welding. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a red light micro-LED chip, which includes: a substrate, an epitaxial structure, a first passivation layer, a metal reinforcement layer, a first electrode, and a second electrode; the epitaxial structure includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, the surface of the second semiconductor layer has a groove exposing the first semiconductor layer, the first electrode is located on the surface of the first semiconductor layer and on the bottom of the groove, and the second electrode is located on the surface of the second semiconductor layer; the first passivation layer at least covers the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer, and the second electrode, the metal reinforcement layer is located on the first passivation layer, and the orthographic projection of the metal reinforcement layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate.

[0007] Optionally, the metal reinforcement layer includes a first Ti layer, a first Ni layer, a Pt layer, a second Ni layer and a second Ti layer sequentially stacked on the surface of the first passivation layer, and the thickness of the Pt layer is not less than half of the total thickness of the metal reinforcement layer.

[0008] Optionally, the thickness of the first Ti layer is 400 angstroms to 600 angstroms, the thickness of the first Ni layer is 800 angstroms to 1200 angstroms, the thickness of the Pt layer is 4900 angstroms to 5100 angstroms, the thickness of the second Ni layer is 800 angstroms to 1200 angstroms, and the thickness of the second Ti layer is 400 angstroms to 600 angstroms.

[0009] Optionally, the bottom surface of the groove has a convex structure, and the convex structure is connected to a side wall of the groove close to the second electrode.

[0010] Optionally, the protruding structure includes a plurality of step blocks, which are arranged in sequence in a direction away from the side wall of the groove, and in the direction away from the side wall of the groove, the area of ​​the orthographic projection of the step blocks on the side wall of the groove gradually decreases.

[0011] Optionally, there are a plurality of protrusion structures, and the plurality of protrusion structures are arranged at intervals in a direction parallel to the substrate.

[0012] Optionally, a bottom surface of the protruding structure away from the groove is a stepped surface, and the stepped surface is respectively connected to the surface of the groove and the side wall of the groove.

[0013] Optionally, the red light micro-LED chip further includes a second passivation layer, the second passivation layer is located on the metal reinforcement layer, and the orthographic projection of the second passivation layer on the substrate coincides with the orthographic projection of the first passivation layer on the substrate.

[0014] Optionally, the red light micro-LED chip also includes: a first solder point block and a second solder point block, the first solder point block and the second solder point block are both located on the surface of the second passivation layer; the first solder point block is connected to the first electrode through a first via hole, and the second solder point block is connected to the second electrode through a second via hole, and the first solder point block and the second solder point block are both insulated from the metal reinforcement layer.

[0015] On the other hand, the embodiment of the present disclosure also provides a method for preparing a red light micro-LED chip, the preparation method comprising: providing a substrate; forming an epitaxial structure on the substrate, the epitaxial structure comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, the surface of the second semiconductor layer having a groove exposing the first semiconductor layer; forming a first electrode and a second electrode on the surface of the epitaxial structure, the first electrode being located on the surface of the first semiconductor layer and on the bottom of the groove, and the second electrode being located on the surface of the second semiconductor layer; forming a first passivation layer and a metal reinforcement layer on the epitaxial structure, the first passivation layer at least covering the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer, and the second electrode, the metal reinforcement layer being located on the first passivation layer, and the orthographic projection of the metal reinforcement layer on the substrate being located within the orthographic projection of the first passivation layer on the substrate.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] In the red light micro-LED provided by the embodiment of the present disclosure, an epitaxial structure is provided on the substrate, the second semiconductor layer in the epitaxial structure has a groove exposing the first semiconductor layer, the first electrode is arranged in the groove and connected to the first semiconductor layer, the second electrode is arranged on the second semiconductor layer, and the epitaxial structure is covered with a first passivation layer, the first passivation layer at least covers the surface of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer and the second electrode, and a metal reinforcement layer is also covered outside the first passivation layer, the orthographic projection of the metal reinforcement layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, so as to avoid the metal reinforcement layer being connected to the two electrodes and causing the two electrodes to short-circuit. Since the metal reinforcement layer is arranged on the surface of the epitaxial structure, that is, the metal reinforcement layer can effectively reinforce the strength of the epitaxial structure below, so when the temperature changes drastically due to laser welding and stress is generated in the chip, the metal reinforcement layer can resist the stress and effectively prevent the epitaxial structure in the chip from cracking and failing. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a structural schematic diagram of a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0020] Figure 2is a schematic structural diagram of a metal reinforcement layer provided by an embodiment of the present disclosure;

[0021] Figure 3 is a partial structural schematic diagram of an epitaxial structure provided by an embodiment of the present disclosure;

[0022] Figure 4 is a top view of a transition step provided by an embodiment of the present disclosure;

[0023] Figure 5 is a cross-sectional view of another epitaxial structure provided by an embodiment of the present disclosure;

[0024] Figure 6 is a partial structural schematic diagram of another epitaxial structure provided by an embodiment of the present disclosure;

[0025] Figure 7 is a top view of a micro light emitting diode chip provided by an embodiment of the present disclosure;

[0026] Figure 8 It is a flow chart of a method for preparing a red light micro-light emitting diode chip provided by an embodiment of the present disclosure;

[0027] Fig. 9 It is a schematic diagram of a preparation process of a red light micro-light emitting diode chip provided by an embodiment of the present disclosure;

[0028] Fig.10 It is a schematic diagram of the preparation process of a red light micro-LED chip provided in an embodiment of the present disclosure.

[0029] The descriptions of the marks in the figure are as follows:

[0030] 10. Substrate;

[0031] 20. epitaxial structure; 201. first semiconductor layer; 202. multi-quantum well layer; 203. second semiconductor layer;

[0032] 31. first passivation layer; 32. metal reinforcement layer; 321. first Ti layer; 322. first Ni layer; 323. Pt layer; 324. second Ni layer; 325. second Ti layer; 33. second passivation layer;

[0033] 41. a first electrode; 42. a second electrode;

[0034] 51. groove; 53. protrusion structure; 530. step block; 531. step block; 532. step surface;

[0035] 61. first via hole; 62. second via hole;

[0036] 71. a first welding point block; 72. a second welding point block;

[0037] 80. Protective layer. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0039] Figure 1 Schematic diagram of the structure of a micro light emitting diode chip provided by the embodiment of the present disclosure. Figure 1 As shown, the red light micro-LED chip includes: a substrate 10 , an epitaxial structure 20 , a first passivation layer 31 , a metal reinforcement layer 32 , a first electrode 41 and a second electrode 42 .

[0040] like Figure 1 As shown, the epitaxial structure 20 includes a first semiconductor layer 201, a multi-quantum well layer 202 and a second semiconductor layer 203 stacked in sequence on a substrate 10, the surface of the second semiconductor layer 203 has a groove 51 exposing the first semiconductor layer 201, the first electrode 41 is located on the surface of the first semiconductor layer 201 and on the bottom of the groove 51, and the second electrode 42 is located on the surface of the second semiconductor layer 203.

[0041] like Figure 1 As shown, the first passivation layer 31 at least covers the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203, and the second electrode 42. The metal reinforcement layer 32 is located on the first passivation layer 31, and the orthographic projection of the metal reinforcement layer 32 on the substrate 10 is located within the orthographic projection of the first passivation layer 31 on the substrate 10.

[0042] In the red light micro-LED provided in the embodiment of the present disclosure, an epitaxial structure 20 is provided on the substrate 10, and a groove 51 exposing the first semiconductor layer 201 is provided on the second semiconductor layer 203 in the epitaxial structure 20, and the first electrode 41 is arranged in the groove 51 and connected to the first semiconductor layer 201, and the second electrode 42 is arranged on the second semiconductor layer 203. The epitaxial structure 20 is covered with a first passivation layer 31, and the first passivation layer 31 at least covers the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203 and the second electrode 42, and a metal reinforcement layer 32 is also covered outside the first passivation layer 31, and the orthographic projection of the metal reinforcement layer 32 on the substrate 10 is located within the orthographic projection of the first passivation layer 31 on the substrate 10, thereby preventing the metal reinforcement layer 32 from being connected to the two electrodes, thereby causing the two electrodes to short-circuit. Since the metal reinforcement layer 32 is arranged on the surface of the epitaxial structure 20, the metal reinforcement layer 32 can effectively reinforce the strength of the epitaxial structure 20 below. In this way, when laser welding causes drastic temperature changes and generates stress in the chip, the metal reinforcement layer 32 can resist the stress and effectively prevent the epitaxial structure 20 in the chip from cracking and failing.

[0043] Figure 2 Schematic diagram of the structure of a metal reinforcement layer 32 provided in an embodiment of the present disclosure. Figure 2 As shown, the metal reinforcement layer 32 includes a first Ti layer 321, a first Ni layer 322, a Pt layer 323, a second Ni layer 324 and a second Ti layer 325 which are sequentially stacked on the surface of the first passivation layer 31, and the thickness of the Pt layer 323 is not less than half of the total thickness of the metal reinforcement layer 32.

[0044] Among them, the first Ti layer 321 is used to improve the adhesion between the first passivation layer 31 and the metal reinforcement layer 32; the first Ni layer 322 is used to improve the adhesion between the first Ti layer 321 and the Pt layer 323, and can also increase the toughness of the metal reinforcement layer 32; the Pt layer 323 is used to enhance the strength of the metal reinforcement layer 32, that is, mainly through the Pt layer 323 to resist stress; the second Ni layer 324 is used to improve the adhesion between the second Ti layer 325 and the Pt layer 323, and can also increase the toughness of the metal reinforcement layer 32; the second Ti layer 325 is used to improve the adhesion between the second passivation layer 33 and the metal reinforcement layer 32.

[0045] In the above implementation, the thickness of the Pt layer 323 is not less than half of the total thickness of the metal reinforcement layer 32, that is, the Pt layer 323 accounts for at least half of the total thickness of the metal reinforcement layer 32. Since the Pt layer 323 is used to resist stress, the thickness of the Pt layer 323 is ensured to be large enough to ensure the effect of the metal reinforcement layer 32 in resisting stress.

[0046] Illustratively, the thickness of the first Ti layer 321 is 400 angstroms to 600 angstroms. As an example, the thickness of the first Ti layer 321 is 500 angstroms.

[0047] Illustratively, the thickness of the first Ni layer 322 is 800 angstroms to 1200 angstroms. As an example, the thickness of the first Ni layer 322 is 1000 angstroms.

[0048] Illustratively, the thickness of the Pt layer 323 is 4900 angstroms to 5100 angstroms. As an example, the thickness of the Pt layer 323 is 5000 angstroms.

[0049] Illustratively, the thickness of the second Ni layer 324 is 800 angstroms to 1200 angstroms. As an example, the thickness of the second Ni layer 324 is 1000 angstroms.

[0050] As an example, the thickness of the second Ti layer 325 is 400 angstroms to 600 angstroms. As an example, the thickness of the second Ti layer 325 is 500 angstroms.

[0051] Alternatively, if Figure 1As shown, the bottom surface of the groove 51 has a protruding structure 53 , and the protruding structure 53 is connected to the side wall of the groove 51 close to the second electrode 42 .

[0052] In the above implementation, a protruding structure 53 is formed on the bottom surface of the groove 51. This allows the vertical plane connecting the surface of the second semiconductor and the bottom surface of the groove 51 on the epitaxial structure 20 to form a stepped zigzag surface, which can extend the stress transfer path to release the stress at the location of the vertical plane, and effectively avoid cracks on the surface of the epitaxial structure 20.

[0053] Figure 3 It is a partial structural diagram of an epitaxial structure 20 provided in an embodiment of the present disclosure. Figure 4 FIG. 5 is a top view of a protrusion structure 53 provided in an embodiment of the present disclosure. Figure 3 , 4 As shown, the protruding structure 53 includes a plurality of step blocks 531, which are arranged in sequence in a direction away from the side wall of the groove 51. In the direction away from the side wall of the groove 51, the area of ​​the positive projection of the step blocks 531 on the side wall of the groove 51 gradually decreases.

[0054] In the above implementation, the protruding structure 53 includes a plurality of step blocks 531 arranged in sequence, and the area of ​​each step block 531 arranged in sequence gradually decreases. In this way, the protruding structure 53 obtained by stacking a plurality of step blocks 531 can form a stepped structure, that is, the cross section of the protruding structure 53 in the direction parallel to the substrate 10 is a stepped cross section, which can extend the stress transmission path to release the stress at the position of the vertical plane, and avoid cracks on the surface of the epitaxial structure 20.

[0055] For example, Figure 4 As shown, the protruding structure 53 includes three step blocks 531, which are arranged in sequence along the direction away from the side wall of the groove 51, and each step block 531 is located in the middle of the previous step block 531. In this way, the protruding structure 53 forms a symmetrical step structure and a step-shaped cross section, further extending the stress transfer path to release the stress at the position of the vertical plane, and avoiding cracks on the surface of the epitaxial structure 20.

[0056] Alternatively, if Figure 3 As shown, there are a plurality of protrusion structures 53 , and the plurality of protrusion structures 53 are arranged at intervals in a direction parallel to the substrate 10 .

[0057] By providing a plurality of spaced-apart protrusion structures 53, the cross-section of the protrusion structure 53 in the direction parallel to the substrate 10 is a discontinuously arranged block cross-section. Compared with long and unseparated protrusions, this can extend the stress transfer path to release the stress at the vertical plane position, thereby avoiding cracks on the surface of the epitaxial structure 20.

[0058] As an example, in the embodiments of the present disclosure, Figure 3 As shown, the protruding structure 53 includes two protruding structures 53 arranged at intervals in a direction parallel to the substrate 10 .

[0059] Figure 5 FIG. 2 is a cross-sectional view of another epitaxial structure 20 provided in an embodiment of the present disclosure. Figure 5 As shown, the bottom surface of the protrusion structure 53 away from the groove 51 is a step surface 532 , and the step surface 532 is respectively connected to the surface of the groove 51 and the side wall of the groove 51 .

[0060] By setting the protrusion structure 53 away from the bottom surface of the groove 51 as a stepped surface 532, the vertical plane connecting the surface of the second semiconductor and the bottom surface of the groove 51 on the epitaxial structure 20 can form a more dense stepped tortuous surface, which can extend the stress transfer path to release the stress at the location of the vertical plane, effectively avoiding cracks on the surface of the epitaxial structure 20.

[0061] As an example, Figure 3 As shown, the protrusion structure 53 includes a plurality of step blocks 530, and the structure of each step block 530 can be as follows: Figure 3 The schematic diagram includes a plurality of protruding structures of stepped blocks 531. In this way, the protruding structures 53 can form a stepped tortuous surface in both a direction perpendicular to the substrate 10 and a direction parallel to the substrate 10, so as to extend the stress transmission path and facilitate stress release.

[0062] As an example, Figure 6 FIG. 1 is a partial structural diagram of another epitaxial structure provided by an embodiment of the present disclosure. Figure 6 As shown, the protruding structure 53 includes a plurality of step blocks 530, each of which may be in the shape of a rectangular block, that is, a plurality of step blocks 530 are combined to form a stepped protruding structure 53. This structure is simpler and is easy to process and prepare.

[0063] Alternatively, if Figure 1As shown, the red light micro LED chip further includes a second passivation layer 33, which is located on the metal reinforcement layer 32, and the orthographic projection of the second passivation layer 33 on the substrate 10 coincides with the orthographic projection of the first passivation layer 31 on the substrate 10. In this way, the first passivation layer 31 and the second passivation layer 33 together cover the metal reinforcement layer 32, so as to avoid the problem of the metal reinforcement layer 32 being exposed and connected to the electrode to cause a short circuit.

[0064] Exemplarily, the second passivation layer 33 may be a DBR (Distributed Bragg Reflection) layer, which includes a plurality of periodically alternately stacked SiO2 layers and TiO2 layers. The number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 36.

[0065] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0066] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 202 to the second passivation layer 33 to the substrate 10, thereby improving the light extraction effect.

[0067] Alternatively, if Figure 1 As shown, the red light micro LED chip further includes: a first solder point block 71 and a second solder point block 72 , and the first solder point block 71 and the second solder point block 72 are both located on the surface of the second passivation layer 33 .

[0068] like Figure 1 As shown, the surface of the second passivation layer 33 has a first via 61 exposing the first electrode 41, and the surface of the second passivation layer 33 has a second via 62 exposing the second electrode 42. The first solder block 71 is connected to the first electrode 41 through the first via 61, and the second solder block 72 is connected to the second electrode 42 through the second via 62. The first solder block 71 and the second solder block 72 are both insulated from the metal reinforcement layer 32.

[0069] A first solder joint block 71 connected to the first electrode 41 is provided on the surface of the second passivation layer 33 to facilitate electrical connection of the first electrode 41 ; a second solder joint block 72 connected to the second electrode 42 is provided on the surface of the second passivation layer 33 to facilitate electrical connection of the second electrode 42 .

[0070] Figure 7 FIG. 1 is a top view of a micro light emitting diode chip provided by an embodiment of the present disclosure. Figure 7 As shown, the first soldering point block 71 and the second soldering point block 72 are both rectangular blocks, which increase the area and facilitate conduction. In addition, on the surface of the second passivation layer 33, the first soldering point block 71 and the second soldering point block 72 are distributed at intervals.

[0071] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light emitting diode has good light emitting effect and stability.

[0072] In the embodiment of the present disclosure, one of the first semiconductor layer 201 and the second semiconductor layer 203 is a p-type layer, and the other of the first semiconductor layer 201 and the second semiconductor layer 203 is an n-type layer.

[0073] As an example, the first semiconductor layer 201 is an n-type layer, and the first electrode 41 is an n-type electrode. The second semiconductor layer 203 is a p-type layer, and the second electrode 42 is a p-type electrode.

[0074] Optionally, the first semiconductor layer 201 is an n-type AlGaInP layer. The thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0075] Optionally, the multi-quantum well layer 202 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The multi-quantum well layer 202 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately, and the Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different.

[0076] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 202 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0077] Optionally, the thickness of the multi-quantum well layer 202 may be 150 nm to 200 nm.

[0078] Optionally, the second semiconductor layer 203 is a p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0079] Figure 8 This is a flow chart of a method for preparing a red light micro-LED chip provided in an embodiment of the present disclosure. Figure 1 The red light micro-LED chip shown. Figure 8 As shown, the preparation method comprises:

[0080] S11: providing a substrate 10.

[0081] S12 : forming an epitaxial structure 20 on the substrate 10 .

[0082] The epitaxial structure 20 includes a first semiconductor layer 201 , a multi-quantum well layer 202 , and a second semiconductor layer 203 sequentially stacked on a substrate 10 . The surface of the second semiconductor layer 203 has a groove 51 exposing the first semiconductor layer 201 .

[0083] S13 : forming a first electrode 41 and a second electrode 42 on the surface of the epitaxial structure 20 .

[0084] A first electrode 41 and a second electrode 42 are formed on the surface of the epitaxial structure 20 .

[0085] S14 : forming a first passivation layer 31 and a metal reinforcement layer 32 on the epitaxial structure 20 .

[0086] Among them, the first passivation layer 31 at least covers the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203, and the second electrode 42, the metal reinforcement layer 32 is located on the first passivation layer 31, and the orthographic projection of the metal reinforcement layer 32 on the substrate 10 is located within the orthographic projection of the first passivation layer 31 on the substrate 10.

[0087] In the red light micro-LED provided in the embodiment of the present disclosure, an epitaxial structure 20 is provided on the substrate 10, and a groove 51 exposing the first semiconductor layer 201 is provided on the second semiconductor layer 203 in the epitaxial structure 20, and the first electrode 41 is arranged in the groove 51 and connected to the first semiconductor layer 201, and the second electrode 42 is arranged on the second semiconductor layer 203. The epitaxial structure 20 is covered with a first passivation layer 31, and the first passivation layer 31 at least covers the surfaces of the first semiconductor layer 201, the first electrode 41, the groove 51, the second semiconductor layer 203 and the second electrode 42, and a metal reinforcement layer 32 is also covered outside the first passivation layer 31, and the orthographic projection of the metal reinforcement layer 32 on the substrate 10 is located within the orthographic projection of the first passivation layer 31 on the substrate 10, thereby preventing the metal reinforcement layer 32 from being connected to the two electrodes, thereby causing the two electrodes to short-circuit. Since the metal reinforcement layer 32 is arranged on the surface of the epitaxial structure 20, the metal reinforcement layer 32 can effectively reinforce the strength of the epitaxial structure 20 below. In this way, when laser welding causes drastic temperature changes and generates stress in the chip, the metal reinforcement layer 32 can resist the stress and effectively prevent the epitaxial structure 20 in the chip from cracking and failing.

[0088] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light micro-LED chip has good light-emitting effect and stability.

[0089] like Fig. 9As shown, the epitaxial structure 20 grown in step S12 includes: a first semiconductor layer 201, a multi-quantum well layer 202 and a second semiconductor layer 203. The first semiconductor layer 201, the multi-quantum well layer 202 and the second semiconductor layer 203 are sequentially stacked on the substrate 10, and the surface of the second semiconductor layer 203 has a groove 51 exposing the first semiconductor layer 201.

[0090] The process of growing the epitaxial structure 20 may include: sequentially growing an etching stop layer, a first semiconductor, an AlInP carrier confinement layer, a multi-quantum well layer 202, a second semiconductor layer 203 and a window layer on a GaAs substrate.

[0091] After the epitaxial structure 20 is grown on the GaAs substrate, the epitaxial structure 20 is bonded to the base plate 10 at a bonding temperature of 300° C., and the GaAs substrate is removed.

[0092] like Fig. 9 As shown, after the bonding is completed, the surface of the second semiconductor layer 203 is etched to expose the groove 51 of the first semiconductor layer 201, that is, the process of forming the epitaxial structure 20 on the substrate 10 in step S12 is completed.

[0093] Specifically, it may include: removing a part of the second semiconductor layer 203 by dry etching, and etching until the first semiconductor layer 201 is exposed. The etching depth is 1 μm to 2 μm, for example, etching 1.5 μm.

[0094] Exemplarily, the first semiconductor layer 201 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0095] Exemplarily, the multi-quantum well layer 202 includes an AlGaInP quantum well layer and an AlGaInP quantum barrier layer grown alternately. The multi-quantum well layer 202 may include 3 to 8 periods of AlGaInP quantum well layers and AlGaInP quantum barrier layers stacked alternately, and the Al content in the AlGaInP quantum well layer and the AlGaInP quantum barrier layer is different.

[0096] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 202 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0097] Optionally, the thickness of the multi-quantum well layer 202 may be 150 nm to 200 nm.

[0098] Optionally, the second semiconductor layer 203 is a p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0099] The second semiconductor layer 203 is a p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0100] Exemplarily, the window layer may be a GaP layer, and the thickness of the GaP layer is 2 μm to 5 μm. As an example, the GaP layer is 3 μm.

[0101] Before forming the two electrodes in step S13 , the process may include: etching a transition step groove on the surface of the second semiconductor layer 203 by dry etching to form a protruding structure 53 between the surface of the transition step groove and the surface of the recess 51 .

[0102] The transition step groove extends from the surface of the second semiconductor layer 203 to the first semiconductor layer 201 , and the distance between the transition step groove and the substrate 10 is greater than the distance between the groove 51 and the substrate 10 .

[0103] In step S13, Fig.10 As shown, forming the first electrode 41 and the second electrode 42 may include: processing the first electrode 41 and the second electrode 42 respectively by negative resist stripping.

[0104] like Fig.10 As shown, the second electrode 42 is located on the surface of the second semiconductor layer 203 , and the first electrode 41 is located on the surface of the groove 51 .

[0105] The first electrode 41 is made of gold germanium as the base material, and the evaporation power must be guaranteed when evaporating the gold germanium alloy, and the evaporation time must not exceed 5 seconds to prevent the deviation of the alloy composition, and annealing is performed. The second electrode 42 is made of gold beryllium as the base material.

[0106] like Fig.10 As shown, in step S14, forming the first passivation layer 31 on the epitaxial structure 20 may include: making the first passivation layer 31 on the surfaces of the first semiconductor layer 201, the first electrode 41, the second semiconductor layer 203, the second electrode 42 and the groove 51, and opening a first via 61 exposing the first electrode 41 and a second via 62 exposing the second electrode 42 at a location on the first passivation layer 31 where current needs to be drawn out.

[0107] The thickness of the first passivation layer 31 may be 2000 angstroms to 5000 angstroms. For example, the thickness of the first passivation layer 31 is 3000 angstroms.

[0108] Next, a metal reinforcement layer 32 is formed on the first passivation layer 31 , and no metal reinforcement layer 32 is provided at the positions of the first via hole 61 and the second via hole 62 .

[0109] After step S14, Figure 1 As shown, a second passivation layer 33 may also be included.

[0110] The second passivation layer 33 may be a DBR layer, which includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 36.

[0111] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0112] After making the second passivation layer 33, it can also include: forming a first via 61 and a second via 62 on the second passivation layer 33, and forming a first solder joint block 71 on the surface of the second passivation layer 33 by photolithography, so that the first solder joint block 71 is connected to the first semiconductor layer 201 through the first via 61; then, forming a second solder joint block 72 on the surface of the second passivation layer 33 by photolithography, so that the second solder joint block 72 is connected to the second semiconductor layer 203 through the second via 62.

[0113] Wherein, both solder joint blocks may include a Cr layer, an Al layer, a Ti layer, a Ni layer and an Au layer stacked in sequence.

[0114] Exemplarily, the thickness of the Cr layer is 100 angstroms, the thickness of the Al layer is 3000 angstroms, the thickness of the Ti layer is 500 angstroms, the thickness of the Ni layer is 2000 angstroms, and the thickness of the Au layer is 90000 angstroms.

[0115] like Figure 1 As shown, after the first solder joint block 71 and the second solder joint block 72 are formed, a protective layer 80 may be formed on the surface of the second passivation layer 33 , and the protective layer 80 extends from the surface of the second passivation layer 33 to the substrate 10 .

[0116] For example, in the embodiment of the present disclosure, the protective layer 80 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0117] It should be noted that after the protective layer 80 is grown on the surface of the second passivation layer 33 , a through hole exposing the solder joint block can be etched on the surface of the protective layer 80 using a photolithography technique to facilitate electrical connection.

[0118] Finally, the sapphire substrate 10 is thinned to a final thickness of 80 μm, and then the sapphire is subjected to invisible cutting and cleaving, which can effectively reduce the loss of brightness. Then, the micro light emitting diode chip is obtained by testing.

[0119] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A red light micro-light emitting diode chip, characterized in that: The red light micro-LED chip comprises: a substrate (10), an epitaxial structure (20), a first passivation layer (31), a metal reinforcement layer (32), a first electrode (41) and a second electrode (42); The epitaxial structure (20) comprises a first semiconductor layer (201), a multi-quantum well layer (202) and a second semiconductor layer (203) which are sequentially stacked on the substrate (10); the surface of the second semiconductor layer (203) has a groove (51) exposing the first semiconductor layer (201); the first electrode (41) is located on the surface of the first semiconductor layer (201) and on the bottom surface of the groove (51); and the second electrode (42) is located on the surface of the second semiconductor layer (203); The first passivation layer (31) at least covers the surfaces of the first semiconductor layer (201), the first electrode (41), the groove (51), the second semiconductor layer (203), and the second electrode (42); the metal reinforcement layer (32) is located on the first passivation layer (31); and the orthographic projection of the metal reinforcement layer (32) on the substrate (10) is located within the orthographic projection of the first passivation layer (31) on the substrate (10); The bottom surface of the groove (51) has a protruding structure (53), the protruding structure (53) is connected to the side wall of the groove (51) close to the second electrode (42), and the protruding structure (53) includes a plurality of step blocks (531), and the plurality of step blocks (531) are arranged in sequence along a direction away from the side wall of the groove (51), and in the direction away from the side wall of the groove (51), the area of ​​the orthographic projection of the step blocks (531) on the side wall of the groove (51) gradually decreases.

2. The red light micro-LED chip according to claim 1, characterized in that: The metal reinforcement layer (32) comprises a first Ti layer (321), a first Ni layer (322), a Pt layer (323), a second Ni layer (324) and a second Ti layer (325) which are sequentially stacked on the surface of the first passivation layer (31), and the thickness of the Pt layer (323) is not less than half of the total thickness of the metal reinforcement layer (32).

3. The red light micro-LED chip according to claim 2, characterized in that: The thickness of the first Ti layer (321) is 400 to 600 angstroms, the thickness of the first Ni layer (322) is 800 to 1200 angstroms, the thickness of the Pt layer (323) is 4900 to 5100 angstroms, the thickness of the second Ni layer (324) is 800 to 1200 angstroms, and the thickness of the second Ti layer (325) is 400 to 600 angstroms.

4. The red light micro-LED chip according to claim 1, characterized in that: There are a plurality of the protrusion structures (53), and the plurality of the protrusion structures (53) are arranged at intervals in a direction parallel to the substrate (10).

5. The red light micro-LED chip according to claim 1, characterized in that: The bottom surface of the protruding structure (53) away from the groove (51) is a stepped surface (532), and the stepped surface (532) is respectively connected to the surface of the groove (51) and the side wall of the groove (51).

6. The red light micro-LED chip according to any one of claims 1 to 5, characterized in that: The red light micro-LED chip further comprises a second passivation layer (33), the second passivation layer (33) being located on the metal reinforcement layer (32), and the orthographic projection of the second passivation layer (33) on the substrate (10) coincides with the orthographic projection of the first passivation layer (31) on the substrate (10).

7. The red light micro-LED chip according to claim 6, characterized in that: The red light micro-LED chip further comprises: a first solder point block (71) and a second solder point block (72), wherein the first solder point block (71) and the second solder point block (72) are both located on the surface of the second passivation layer (33); The first soldering point block (71) is connected to the first electrode (41) through a first via hole (61), and the second soldering point block (72) is connected to the second electrode (42) through a second via hole (62). Both the first soldering point block (71) and the second soldering point block (72) are insulated from the metal reinforcement layer (32).

8. A method for preparing a red light micro-light emitting diode chip, characterized in that: The preparation method comprises: providing a substrate; An epitaxial structure is formed on the substrate, the epitaxial structure comprising a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer sequentially stacked on the substrate, the surface of the second semiconductor layer having a groove exposing the first semiconductor layer, the bottom surface of the groove (51) having a convex structure (53), the convex structure (53) comprising a plurality of step blocks (531), the plurality of step blocks (531) being sequentially arranged in a direction away from the side wall of the groove (51), and in a direction away from the side wall of the groove (51), the area of ​​the orthographic projection of the step blocks (531) on the side wall of the groove (51) gradually decreases; A first electrode and a second electrode are formed on the surface of the epitaxial structure, the first electrode is located on the surface of the first semiconductor layer and on the bottom surface of the groove, the second electrode is located on the surface of the second semiconductor layer, and the protruding structure (53) is connected to the side wall of the groove (51) close to the second electrode (42); A first passivation layer and a metal reinforcement layer are formed on the epitaxial structure, wherein the first passivation layer at least covers the surfaces of the first semiconductor layer, the first electrode, the groove, the second semiconductor layer, and the second electrode, and the metal reinforcement layer is located on the first passivation layer, and the orthographic projection of the metal reinforcement layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate.

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