Non-volatile memory device with wire limit

Abstract

The present invention relates to a non-volatile memory device with wire confinement. A memory device and a method of manufacturing the same are provided. The memory device includes a first electrode having a length along a first axis, a second electrode having a length along a second axis perpendicular to the first axis, and a switching layer adjacent to the first electrode. A portion of the switching layer is located between a first electrode edge and a second electrode portion. A cross-section of the first electrode and the second electrode can have a polygonal shape.

Description

Technical Field

[0001] This invention generally relates to integrated circuits and the manufacture of integrated circuits, and more particularly to structures for non-volatile memory devices and methods for manufacturing non-volatile memory devices. Background Technology

[0002] Semiconductor memory devices can generally be divided into volatile memory devices and non-volatile memory devices. Volatile memory devices typically require a continuous power supply to retain the stored information, while non-volatile memory devices retain data even when power is off. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM). Examples of non-volatile memory devices include flash memory, read-only memory (ROM), and non-volatile random access memory such as resistive random access memory (ReRAM or RRAM).

[0003] Resistive random access memory (RAM) stores information through a resistive element between two conductive electrodes. This element has a resistance value that can vary between a high-resistance state and a low-resistance state, corresponding to different logic values ​​used for data storage. For example, to write a logic "1" value, a switching voltage can be applied to form one or more filaments within the resistive element, thereby creating a conductive path across the element to provide a low-resistance state. Conversely, a switching voltage can be applied to destroy these filaments, thereby removing the conductive path to provide a high-resistance state.

[0004] However, due to variations in the filament formation and breakage processes, the resistance values ​​in the high-resistance and low-resistance states can change significantly. Therefore, at least in part due to the resistance variations described above, the switching voltage required to program the memory device to change the information storage state may also vary.

[0005] There is a need for improved structures for non-volatile memory devices and methods for manufacturing such non-volatile memory devices. Summary of the Invention

[0006] According to an embodiment of the present invention, a memory device includes: a first electrode having a length along a first axis; a second electrode having a length along a second axis perpendicular to the first axis; and a switching layer adjacent to the first electrode. A portion of the switching layer is located between an edge of the first electrode and a portion of the second electrode.

[0007] According to another embodiment of the present invention, a memory device includes: a first vertical electrode having a length along a vertical axis; a first horizontal electrode having a length along a horizontal axis; a second horizontal electrode having a length along a horizontal axis and parallel to the first horizontal electrode; and a switching layer adjacent to the first vertical electrode. A first portion of the switching layer is located between the first vertical electrode and the first horizontal electrode, and a second portion of the switching layer is located between the first vertical electrode and the second horizontal electrode. The first portion and the second portion of the switching layer are positioned adjacent to the edge portion of the vertical electrode.

[0008] According to another embodiment of the present invention, a method for manufacturing a memory device is provided. The method includes: providing a first electrode having a first axis; providing a second electrode having a second axis perpendicular to the first axis; and providing a switching layer adjacent to the first electrode. A portion of the switching layer is located between an edge of the first electrode and a portion of the second electrode. Attached Figure Description

[0009] The accompanying drawings illustrate examples of various non-limiting embodiments of the invention and form part of the specification. The drawings, together with the foregoing general description of the invention and the following detailed description of various embodiments, serve to explain examples of non-limiting embodiments of the invention. In the drawings, the same reference numerals generally indicate the same features in the various views.

[0010] Figure 1 A simplified top view of a memory device according to an exemplary embodiment of the present invention is shown.

[0011] Figure 2A and Figure 2B Each of the aspects of the invention is shown. Figure 1 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0012] Figure 2C A simplified top view of an alternative embodiment according to another aspect of the invention is shown.

[0013] Figure 3A and Figure 3B Each of the other aspects of the invention is shown separately. Figure 1 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0014] Figure 4A and Figure 4B Each shows another aspect of the invention. Figure 1 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0015] Figure 5A simplified top view of a memory device according to another exemplary embodiment of the present invention is shown.

[0016] Figure 6A and Figure 6B Each of the aspects of the invention is shown. Figure 5 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0017] Figure 7A and Figure 7B Each of the other aspects of the invention is shown. Figure 5 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0018] Figure 8 A simplified top view of a memory device according to yet another exemplary embodiment of the present invention is shown.

[0019] Figure 9A and Figure 9B Each of the aspects of the invention is shown. Figure 8 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0020] Figure 10 A simplified top view of a memory device according to yet another exemplary embodiment of the present invention is shown.

[0021] Figure 11A and Figure 11B Each of the aspects of the invention is shown. Figure 10 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0022] Figure 12 A simplified top view of a memory device according to yet another exemplary embodiment of the present invention is shown.

[0023] Figure 13A and Figure 13B Each of the aspects of the invention is shown. Figure 12 Simplified cross-sectional and perspective views of exemplary embodiments thereof.

[0024] Figure 14 and Figure 15 It was shown as Figure 12 A simplified top view of an alternative memory device according to other exemplary embodiments of the present invention.

[0025] Figure 16A A simplified perspective view of a memory device with exemplary interconnects according to one aspect of the present invention is shown.

[0026] Figure 16B and Figure 16CA top view of a memory device with exemplary interconnects according to one aspect of the present invention is shown.

[0027] Figures 17A to 17K A simplified cross-sectional view is shown, illustrating exemplary process steps for manufacturing a memory device according to an embodiment of the present invention.

[0028] Figure 18A and Figure 18B A representation according to another embodiment of the invention is shown. Figure 17A A simplified cross-sectional view of an alternative embodiment.

[0029] Figures 19A to 19L A simplified cross-sectional view illustrating exemplary process steps for manufacturing a memory device is shown according to another embodiment of the present invention.

[0030] For the sake of simplicity and clarity, the accompanying drawings illustrate a general construction method, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described device embodiments. Furthermore, elements in the drawings are not necessarily drawn to scale, and the dimensions of some elements may be exaggerated relative to others to aid in understanding the device embodiments. Detailed Implementation

[0031] According to an exemplary embodiment of the present invention, a memory device 10 is disposed in a metallization layer of an interconnect structure fabricated through mid-stage and back-stage processes above a substrate 100. In some embodiments, the memory device 10 may be a resistive memory cell type, such as, for example, random access memory (ReRAM or RRAM) or conductive bridged random access memory (CBRAM). The memory device 10 may be connected to one of the conductive lines within the interconnect structure, such as the M2 metallization layer. The memory device 10 includes a first electrode having a length along a first axis and a second electrode having a length along a second axis perpendicular to the first axis. For example, the first axis may be the Y-axis and the second axis may be the X-axis. The first electrode may be part of a first electrode array comprising one or more rows of at least two electrodes arranged spaced apart and parallel to the first axis. The second electrode may be part of a second electrode array comprising one or more rows of at least two electrodes arranged spaced apart and parallel to the second axis. Reference Figure 1This diagram illustrates an exemplary top view of a memory device 10 according to an embodiment of the present invention. A first electrode array is parallel to the Y-axis and includes a first row of vertical electrodes and a second row of vertical electrodes. The first row of vertical electrodes includes vertical electrodes 102, 104, and 106, and the second row of vertical electrodes includes vertical electrodes 112, 114, and 116. Each of the vertical electrodes 102, 104, 106, 112, 114, and 116 has a length along the Y-axis and each has a side surface and edge along the Y-axis. When viewed along the Y-axis, the vertical electrodes may have a polygonal cross-section, such as a square or rhombus as an example. The second electrode array is parallel to the X-axis (by...). Figure 1 (Represented by the dashed line marked "X") and includes a first row of horizontal electrodes and a second row of horizontal electrodes located below the first row of horizontal electrodes. The first row of horizontal electrodes includes horizontal electrodes 122, 124, and 126, and the second row of horizontal electrodes includes horizontal electrodes 132, 134, and 136. Figure 1 (Not shown in the image). Each of the horizontal electrodes 122, 124, 126, 132, 134, and 136 has a length along the X-axis and has a side surface and edge along the X-axis. The first and second electrode arrays may be staggered such that a first row of vertical electrodes is located between horizontal electrodes 122 and 124. A second row of vertical electrodes is similarly located between horizontal electrodes 124 and 126. The first and second electrode arrays may include conductive materials, such as metals or alloys thereof. The material selection for the vertical electrodes may be based on factors such as oxidation resistance and differences in work function relative to the horizontal electrodes. Non-limiting examples of suitable conductive materials for the electrodes include copper, cobalt, hafnium, platinum, ruthenium, silver, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, or alloys thereof. The first and second electrode arrays may be disposed in a metallization layer of an interconnect structure fabricated by a mid-stage (MOL) or back-end (BEOL) process above a substrate 100 (not shown) and may be arranged in an interlayer dielectric material 160 comprising one or more layers.

[0032] Now for reference Figure 2A The same reference numerals indicate Figure 1 The same features in, and it shows along Figure 1An exemplary cross-sectional view of the memory device 10, taken by the dashed line A-A', is shown. The first vertical electrode 104 includes sides 104a and 104b, and the second vertical electrode 114 includes sides 114a and 114b. Similarly, the first horizontal electrode 122 includes sides 122a and 122b, and the second horizontal electrode 124 includes sides 124a and 124b. It will be understood that each of the vertical and horizontal electrodes includes the sides as described above and does not require further detailed description. The first horizontal electrode is positioned adjacent to a first side of the first vertical electrode 104 such that a first portion of side 104b faces and is close to a first portion of side 122b. The second horizontal electrode 124 is positioned adjacent to a second side of the first vertical electrode 104 such that a first portion of side 104a faces and is close to a portion of side 124a. A third horizontal electrode 132, having sides 132a and 132b, is located below the first horizontal electrode 122, such that a second portion of side 104b faces and approaches a portion of side 132b on the third horizontal electrode 132. A second vertical electrode 114, having sides 114a and 114b, is located on a side of the second horizontal electrode 124 different from the side adjacent to the first vertical electrode 104, such that a first portion of side 114b faces and approaches a portion of side 124b, and a second portion of side 114b faces and approaches (proximal to) a portion of side 134b on the fourth horizontal electrode 134 located below the second horizontal electrode 124.

[0033] For each of the vertical electrodes 102, 104, 106, 112, 114, and 116, the switching layer 150 may be positioned adjacent to that vertical electrode such that a portion of the switching layer 150 lies between at least one of the horizontal electrodes 132, 134, and 136 and the vertical electrode. In another embodiment, the switching layer may alternatively be positioned adjacent to a horizontal electrode, such as a second electrode. In one aspect of the invention, the switching layer 150 may directly contact at least one of the horizontal and vertical electrodes. The switching layer may be conformally deposited on one or more side surfaces of the vertical or horizontal electrode with a nominally uniform thickness. Suitable materials for the switching layer include metal oxides, such as magnesium oxide, tantalum oxide, hafnium oxide, titanium oxide, aluminum oxide, or silicon dioxide. The switching layer may not need to cover the entire or all side surfaces of the electrode, as long as a portion of the switching layer lies between the first electrode (which may be a vertical electrode) and the second electrode (which may be a horizontal electrode). In a preferred embodiment, a first portion of the switching layer is located between a first electrode portion (e.g., a first electrode edge) on the first electrode and a second electrode portion on the second electrode. For example, Figure 2AA switching layer 150 is positioned adjacent to the first vertical electrode 104, such that a first portion of the switching layer 150 lies between a first electrode portion on the first vertical electrode 104 and a second electrode portion on the first horizontal electrode 122. In one embodiment, the first electrode portion may be a first side portion, such as a portion of side 104b, and the second electrode portion may be a second side portion, such as a portion of side 122b. In another example, the first electrode portion may be a portion of side 104a of the first vertical electrode 104, and the second electrode portion may be a portion of side 124a on the second horizontal electrode 124. In another preferred embodiment, a second portion of the switching layer lies between a second electrode portion on the first electrode and a third electrode portion on the third electrode. For example, the second electrode portion on the first electrode may be a portion of side 104b on the first vertical electrode 104, and the third electrode portion may be a portion of side 132b on the third horizontal electrode 132. In another example, the second electrode portion on the first electrode may be another portion of side 104a on the first vertical electrode 104, and the third electrode portion may be a portion of side 134a on the fourth horizontal electrode 134. In a preferred embodiment, the switching layer contacts at least a portion of the electrode edge. For example, a portion of the switching layer contacts at least a portion of the edge on the horizontal electrode of the memory device 10. In another example, a portion of the switching layer contacts at least a portion of the edge on the vertical electrode of the memory device 10.

[0034] refer to Figure 2B The same reference numerals indicate Figure 1 and Figure 2A The same features are provided in an exemplary simplified perspective view of a memory device 10 according to an embodiment of the present invention. A first electrode array may include a first row of vertical electrodes 102, 104, and 106 and a second row of vertical electrodes 112, 114, and 116, the first and second rows of vertical electrodes being parallel to each other and laterally shifted relative to each other. A second electrode array may include a first row of horizontal electrodes 122, 124, and 126 and a second row of horizontal electrodes 132, 134, and 136, the first and second rows of vertical electrodes being parallel to each other and vertically shifted relative to each other. The switching layer and interlayer dielectric material of each of the aforementioned adjacent vertical electrodes are not shown here to avoid obscuring the relative configuration of the electrodes.

[0035] Figure 2C A top view of memory device 12 is shown, wherein the same reference numerals indicate Figure 1 The same features in, and Figure 2C This is an alternative exemplary embodiment of the present invention, as Figure 1Alternative electrode configurations. As shown in the figure, the first row of vertical electrodes 102, 104, and 106 can be staggered with the second row of vertical electrodes 117 and 119.

[0036] In use, the vertical and horizontal electrodes can be connected to other interconnect structures, such as vias and conductive lines, for sending or receiving electrical input from other electronic components in the memory device (e.g., transistors or diodes, as non-limiting examples). The interconnect structures can include metallic materials, such as copper, cobalt, aluminum, or alloys thereof. The conductive lines can be source lines, bit lines, or word lines, and each conductive line can be connected to more than one vertical or horizontal electrode, depending on the device's design requirements. In use, voltage can be applied to the vertical and horizontal electrodes via the conductive lines to perform read, write, or erase operations on the memory device. For example, memory device 10 may have a first bit line connected to a first horizontal electrode 122 and a second bit line connected to a second horizontal electrode 124. Word lines can be connected to a first vertical electrode 102. When a desired voltage is applied to the horizontal and vertical electrodes according to the operational needs of the memory device, one or more conductive filaments can be formed in a portion of a switching layer located between the first and second electrodes to form a conductive path between the first and second electrodes. The switching layer can be configured to switch between a low resistance state (LRS) and a high resistance state (HRS) by the formation and disruption of conductive filaments. Intentionally confining the conductive filaments to a specific region of the switching layer allows for faster switching behavior between the high resistance state (HRS) and the low resistance state (LRS), as opposed to randomly forming conductive filaments within the switching layer in an unpredictable manner. Therefore, according to one aspect of the invention, a portion of the switching layer is located between a first electrode and a second electrode perpendicular to the first electrode, such that the conductive filaments can be confined to a specific region. For example, referring to the memory device 10 according to an embodiment of the invention, the conductive filaments are confined to a specific portion of the switching layer 150 located between the edge portions of the first vertical electrode 102 and the edge portions of the first horizontal electrode 122. Confining the conductive filaments to a specific region allows for faster switching behavior and translates to faster read, write, and erase operations in the memory device. Furthermore, due to the staggered structure of the vertical and horizontal electrodes, two or more memory cells can share a common electrode but can provide independent memory outputs. For example, the first vertical electrode 102 is a common electrode and forms a memory cell with horizontal electrodes 122, 124, 132 and 134, all of which can be connected to individual bit lines.

[0037] refer to Figure 3A The same reference numerals indicate Figure 2A The same features as those in the alternative embodiment provide a memory device 20 having the same characteristics as those in the alternative embodiment. Figure 1A top view similar to that of a memory device. Similarly, along... Figure 1 The dashed line A-A' represents an exemplary cross-section of memory device 20. Memory device 20 may include features similar to those of memory device 10, including vertical electrodes 102, 104, 106, 112, 114, and 116, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. Memory device 20 may have a first row of horizontal electrodes 222, 224, and 226 and a second row of horizontal electrodes 232, 234, and 236 in place of horizontal electrodes 122, 124, 126, 132, 134, and 136. When viewed along the X-axis, the horizontal electrodes of memory device 20 may each have a substantially semi-circular cross-section and include curved side surfaces, a substantially flat surface, and edges along the X-axis. For example, the first horizontal electrode 222 includes a curved side surface 222c, a substantially flat surface 222d, and edges 222a and 222b along the X-axis. It is understood that each of the horizontal electrodes includes side surfaces and edges similar to those of the first horizontal electrode 222 described above, and does not require further detailed description. The horizontal electrodes in memory device 20 are positioned relative to the switching layer and vertical electrodes in a configuration similar to that of the horizontal electrodes in memory device 10, such that the positions of the electrode portions on the horizontal electrodes relative to the switching layer 150 and the electrode portions on the vertical electrodes are similar to those already described for memory device 10, to achieve confinement of the conductive wire to a specific region. For example, referring to memory device 20, the conductive wire is confined within a portion of the switching layer 150 located between the edge portions of the first vertical electrode 102 and the edge portions of the first horizontal electrode 222. In another example, the wire confinement may be implemented in a first portion of the switching layer 150 located between a portion of the edge 104b of the first vertical electrode 104 facing and close to a portion of the edge 222b of the first horizontal electrode 222. The wire constraint can also be implemented in a second portion of the switching layer, which is located between another portion of the edge 104b of the first vertical electrode 104 facing and close to a portion of the edge 232b on the second horizontal electrode 232. In another example, the second portion of the switching layer may be located between a portion of the edge 104a of the first vertical electrode facing and close to a portion of the edge 234a on the third horizontal electrode 234, and the wire constraint may occur therein. In a preferred embodiment, the switching layer is in contact with at least one of the electrode portions. For example, a portion of the switching layer is in contact with at least a portion of the edge on the horizontal electrode of the memory device 20. In another example, a portion of the switching layer is in contact with at least a portion of the edge on the vertical electrode of the memory device 20.

[0038] Figure 3B It shows having with Figure 2B An exemplary simplified perspective view of a memory device 20 with a similar configuration, but horizontal electrodes 122, 124, 126, 132, 134, and 136 are replaced by horizontal electrodes 222, 224, 226, 232, 234, and 236, each having a substantially semi-circular cross-section. Switching layers and interlayer dielectric materials are not present. Figure 3B The relative arrangement of the electrodes is shown in the diagram to avoid obscuring the view.

[0039] refer to Figure 4A The same reference numerals indicate Figure 2A The same features as those in the alternative embodiment provide a memory device 30 having the same characteristics as those in the alternative embodiment. Figure 1 A top view similar to that of a memory device. Similarly, along... Figure 1The dashed line A-A' denotes an exemplary cross-section of memory device 30. Memory device 30 may include features similar to those of memory device 10, including vertical electrodes 102, 104, 106, 112, 114, and 116, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. Memory device 30 may have a first row of horizontal electrodes 322, 324, and 326 and a second row of horizontal electrodes 332, 334, and 336 in place of horizontal electrodes 122, 124, 126, 132, 134, and 136. In one aspect of the embodiment, when viewed along the X-axis, the horizontal electrodes of memory device 30 may have a substantially rectangular, square, or trapezoidal cross-section. In another aspect of the embodiment, the horizontal electrodes have a substantially flat bottom surface and substantially vertical side surfaces along the X-axis. In yet another aspect of the embodiment, due to manufacturing constraints, the horizontal electrodes may have a non-flat bottom surface and sloping sidewalls, as well as one or more rounded edges. For example, a first horizontal electrode 322 having side surfaces 322a and 322b is positioned adjacent to a first side of a first vertical electrode 104 having edges 104a and 104b, such that a first portion of edge 104b faces and is close to a portion of side surface 322b. A second horizontal electrode 324 having side surfaces 324a and 324b is positioned adjacent to a second side of the first vertical electrode 104, such that a first portion of edge 104a faces and is close to a portion of side surface 324a. A third horizontal electrode 332 having side surfaces 332a and 332b is located below the first horizontal electrode 322, such that a second portion of edge 104b faces and is close to a portion of side surface 332b on the third horizontal electrode 332. It is understood that some or all of the horizontal electrodes similarly include the first and second side surfaces described above, and further detailed description is not required. The horizontal electrodes in memory device 30 are positioned relative to the switching layer and vertical electrodes in a configuration similar to that of the horizontal electrodes in memory device 10, such that the positions of electrode portions on the horizontal electrodes relative to the switching layer 150 and the electrode portions on the vertical electrodes are similar to those already described for memory device 10, thereby confining the conductive wire to a specific region. For example, referring to memory device 30, the conductive wire is confined to a portion of the switching layer 150 located between an edge portion of the first vertical electrode 104 and a side surface portion of the first horizontal electrode 322. In another example, wire confinement may be achieved in a first portion of the switching layer located between a portion of the edge 104b of the first vertical electrode 104 facing and close to a portion of the side surface 322b of the first horizontal electrode 322.Filament restriction can also be implemented in a second portion of the switching layer, which is located between another portion of the edge 104b of the first vertical electrode 104 facing and close to a portion of the side surface 332b on the second horizontal electrode 332. In another example, the second portion of the switching layer may be located between a portion of the edge 104a of the first vertical electrode facing and close to a portion of the side surface 334a on the third horizontal electrode 334, and filament restriction may occur therein. In a preferred embodiment, the switching layer is in contact with at least one of the electrode portions. For example, a portion of the switching layer is in contact with at least the side surface of the horizontal electrode of the memory device 30. In another example, a portion of the switching layer is in contact with at least a portion of the edge on the vertical electrode of the memory device 30.

[0040] Figure 4B It shows having with Figure 2B An exemplary simplified perspective view of a memory device 30 with a similar configuration, but horizontal electrodes 122, 124, 126, 132, 134, and 136 are replaced by horizontal electrodes 322, 324, 326, 332, 334, and 336, each having a substantially rectangular or square cross-section. Switching layers and interlayer dielectric materials are not present. Figure 4B The relative arrangement of the electrodes is shown in the diagram to avoid obscuring the view.

[0041] refer to Figure 5 The same reference numerals indicate Figure 1 The same features as those in the memory device 10 provide a memory device 40 according to an alternative embodiment. The memory device 40 may include features similar to those in the memory device 10, including horizontal electrodes 122, 124, 126, 132, 134, and 136, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. The memory device 40 may have a first row of vertical electrodes 202, 204, 206 and a second row of vertical electrodes 212, 214, and 216, in place of the vertical electrodes 102, 104, 106, 112, 114, and 116 of the memory device 10. Each of the vertical electrodes may have a polygonal cross-section when viewed along the Y-axis. In another aspect of the embodiment, the vertical electrodes have substantially curved side surfaces and a length extending along the Y-axis. For example, the polygonal cross-section may be circular. In other examples, the polygonal cross-section may be elliptical or oval.

[0042] Now for reference Figure 6A The same reference numerals indicate Figure 5 The same features are shown along the same path. Figure 5An exemplary cross-sectional view of the memory device 40, taken by the dashed line B-B', is shown. A first horizontal electrode 122 having sides 122a and 122b is positioned adjacent to a first side of a first vertical electrode 204 having side surfaces 204a and 204b, such that a first portion of side surface 204b faces and is close to a portion of side 122b. A second horizontal electrode 124 having sides 124a and 124b is positioned adjacent to a second side of the first vertical electrode 204, such that a first portion of side 204a faces and is close to a portion of side 124a. A third horizontal electrode 132 having sides 132a and 132b is located below the first horizontal electrode 122, such that a second portion of side surface 204b faces and is close to a portion of side 132b. It is understood that each of the vertical electrodes includes a side surface similar to that described above and does not require further detailed description. The horizontal electrodes in memory device 40 are positioned relative to the switching layer and vertical electrodes in a similar configuration to those in memory device 10, such that the positions of electrode portions on the horizontal electrodes relative to the switching layer 150 and the electrode portions on the vertical electrodes are similar to those already described for memory device 10, to confine the conductive wire to a specific region. For example, referring to memory device 40, the conductive wire is confined to a portion of the switching layer 150 located between an edge portion of the first vertical electrode 204 and a side surface portion of the first horizontal electrode 122. In another example, the wire confinement may be implemented in a first portion of the switching layer located between a portion of the side surface 204b of the first vertical electrode 204 facing and close to a portion of the edge 122b of the first horizontal electrode 122. The wire confinement may also be implemented in a second portion of the switching layer located between another portion of the side surface 204b of the first vertical electrode 204 facing and close to a portion of the edge 132b of the second horizontal electrode 132. In another example, a second portion of the switching layer may be located between a portion of the side surface 204a of the first vertical electrode facing and close to a portion of the edge 134a on the third horizontal electrode 134, and wire confinement may occur therein. In a preferred embodiment, the switching layer contacts at least one of the electrode portions. For example, a portion of the switching layer contacts at least a portion of the side surface of the vertical electrode of the memory device 40. In another example, a portion of the switching layer contacts at least a portion of the edge on the horizontal electrode of the memory device 40.

[0043] Figure 6B It shows having with Figure 2BAn exemplary simplified perspective view of a memory device 40 with a similar configuration, but with vertical electrodes 102, 104, 106, 112, 114, and 116 replaced by vertical electrodes 202, 204, 206, 212, 214, and 216, each having a substantially circular cross-section. Switching layers and interlayer dielectric materials are not present. Figure 6B The relative arrangement of the electrodes is shown in the diagram to avoid obscuring the view.

[0044] refer to Figure 7A The same reference numerals indicate Figure 6A The same features as those in the above provide a memory device 50 according to an alternative embodiment, the memory device 50 having the same... Figure 5 A top view similar to that of a memory device. Similarly, along... Figure 5 The dashed line B-B' represents an exemplary cross-section of memory device 50. Memory device 50 may include features similar to those of memory device 40, including vertical electrodes 202, 204, 206, 212, 214, and 216, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. Memory device 50 may have a first row of horizontal electrodes 222, 224, and 226 and a second row of horizontal electrodes 232, 234, and 236 in place of horizontal electrodes 122, 124, 126, 132, 134, and 136. The horizontal electrodes of memory device 50 are similar to... Figure 3A and Figure 3B The horizontal electrodes of the memory device 20 shown, and when viewed along the X-axis, each of the horizontal electrodes of the memory device 50 may have a substantially semi-circular cross-section, and along the X-axis include curved side surfaces, a substantially flat surface, and edges. The horizontal electrodes in the memory device 50 are in accordance with the previously described... Figure 6A and Figure 6BThe horizontal electrodes of the memory device 40 are configured similarly relative to the switching layer and the vertical electrodes, such that the positions of the electrode portions on the horizontal electrodes relative to the switching layer 150 and the electrode portions on the vertical electrodes are similar to those already described for the memory device 40, in order to confine the conductive wire to a specific region. For example, referring to the memory device 50, the conductive wire is confined to a portion of the switching layer 150, which is located between a side surface portion of the first vertical electrode 204 and an edge portion of the first horizontal electrode 222. In another example, the wire confinement may be implemented in a first portion of the switching layer 150, which is located between a portion of the side surface 204b of the first vertical electrode 204 facing and close to a portion of the edge 222b of the first horizontal electrode 222. The wire confinement may also be implemented in a second portion of the switching layer, which is located between another portion of the side surface 204b of the first vertical electrode 204 facing and close to a portion of the edge 232b of the second horizontal electrode 232. In another example, the second portion of the switching layer may be located between a portion of the side surface 204a on the first vertical electrode facing and close to a portion of the edge 234a on the third horizontal electrode 234, and wire confinement may occur therein. In a preferred embodiment, the switching layer contacts at least one of the electrode portions. For example, a portion of the switching layer contacts at least a portion of the edge of the horizontal electrode of the memory device 50. In another example, a portion of the switching layer contacts at least a portion of the edge on the vertical electrode of the memory device 50.

[0045] Figure 7B It shows having with Figure 6B An exemplary simplified perspective view of a memory device 50 with a similar configuration, but horizontal electrodes 122, 124, 126, 132, 134, and 136 are replaced by horizontal electrodes 222, 224, 226, 232, 234, and 236, each having a substantially semi-circular cross-section. Switching layers and interlayer dielectric materials are not present. Figure 7B The relative arrangement of the electrodes is shown in the diagram to avoid obscuring the view.

[0046] refer to Figure 8 The same reference numerals indicate Figure 1The same features as those in the memory device 10 provide a memory device 60 according to an alternative embodiment. The memory device 60 may include features similar to those in the memory device 10, including horizontal electrodes 122, 124, 126, 132, 134, and 136, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. The memory device 60 may have a first row of vertical electrodes 302, 304, and 306 and a second row of vertical electrodes 312, 314, and 316, in place of the vertical electrodes 102, 104, 106, 112, 114, and 116 of the memory device 10. Each of the vertical electrodes may have at least three side surfaces and three edges along the Y-axis, and may have a polygonal cross-section when viewed along the Y-axis. For example, the polygonal cross-section may be triangular in shape.

[0047] Now for reference Figure 9A The same reference numerals indicate Figure 8 The same features in, which show along Figure 8The exemplary cross-sectional view of memory device 60 is shown by the dashed line C-C'. Each of the vertical electrodes includes meeting side surfaces to form an edge along the Y-axis. For example, the first vertical electrode 304 has three side surfaces and three edges, including edges 304a and 304b. The vertical electrodes in memory device 60 are positioned relative to the switching layer and horizontal electrodes in a similar configuration to the vertical electrodes of memory device 10, such that the relative positions of the electrode portions on the horizontal electrode with respect to the switching layer 150 and the electrode portions on the vertical electrode are similar to those already described for memory device 10, to achieve confinement of the conductive wire to a specific region. In an exemplary embodiment, a first portion of the switching layer may be located between a first electrode portion on the first electrode and a second electrode portion on the second electrode. For example, referring to memory device 60, the conductive wire is confined to a portion of the switching layer 150, which is located between an edge portion of the first vertical electrode 304 and a side surface portion of the first horizontal electrode 122. In another example, wire restraint may be implemented in a first portion of switching layer 150, which is located between portions of the edges 304b of the first vertical electrode 304 facing and close to a portion of the edge 122b of the first horizontal electrode 122. Wire restraint may also be implemented in a second portion of switching layer 150, which is located between other portions of the edges 304b of the first vertical electrode 304 facing and close to a portion of the edge 132b of the second horizontal electrode 132. In another example, the second portion of switching layer 150 may be located between portions of the edges 304a of the first vertical electrode 304 facing and close to a portion of the edge 134a of the third horizontal electrode 134, and wire restraint may occur therein. In a preferred embodiment, the switching layer contacts at least one of the electrode portions. For example, a portion of switching layer 150 contacts at least a portion of the edge of the vertical electrode of memory device 60. In another example, a portion of switching layer contacts at least a portion of the edge of the horizontal electrode of memory device 60.

[0048] Figure 9B It shows having with Figure 2B An exemplary simplified perspective view of a memory device 60 with a similar configuration, but with vertical electrodes 102, 104, 106, 112, 114, and 116 replaced by vertical electrodes 302, 304, 306, 312, 314, and 316, each with a triangular cross-section. Switching layers and interlayer dielectric materials are not present. Figure 9B The relative arrangement of the electrodes is shown in the diagram to avoid obscuring the view.

[0049] refer to Figure 10 The same reference numerals indicate Figure 1The same features as those in the memory device 10 provide a memory device 70 according to an alternative embodiment. The memory device 70 may include features similar to those in the memory device 10, including horizontal electrodes 122, 124, 126, 132, 134, and 136, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. The memory device 70 may have a first row of vertical electrodes 402, 404, and 406 and a second row of vertical electrodes 412, 414, and 416, in place of the vertical electrodes 102, 104, 106, 112, 114, and 116 of the memory device 10. Each of the vertical electrodes may have at least two substantially parallel side surfaces along the Y-axis and may have a polygonal cross-section when viewed along the Y-axis. For example, the polygonal cross-section may be rectangular or square in shape.

[0050] Now for reference Figure 11A The same reference numerals indicate Figure 10 The same features in, which show along Figure 10The dashed line D-D' in the figure shows an exemplary cross-sectional view of the memory device 70. Each of the vertical electrodes includes substantially parallel side surfaces and polygonal cross-sections, which may have a rectangular shape. In another embodiment, the cross-section may have a square shape. For example, the first vertical electrode 404 has substantially parallel side surfaces 404a and 404b. The vertical electrodes in the memory device 70 are positioned relative to the switching layer and horizontal electrodes in a configuration similar to that of the vertical electrodes in the memory device 40, such that the electrode portions on the horizontal electrodes are positioned relative to the switching layer 150 and the electrode portions on the vertical electrodes in a manner similar to that already described for the memory device 40, to achieve confinement of the conductive wire to a specific region. For example, referring to the memory device 70, the conductive wire is confined to a portion of the switching layer 150, which is located between a side surface portion of the first vertical electrode 404 and a side surface portion of the first horizontal electrode 122. In another example, filament constraint may be implemented in a first portion of the switching layer 150, located between portions of the side surfaces 404b of the first vertical electrode 404 facing and close to a portion of the edge 122b of the first horizontal electrode 122. Filament constraint may also be implemented in a second portion of the switching layer 150, located between other portions of the side surfaces 404b of the first vertical electrode 404 facing and close to a portion of the edge 132b of the second horizontal electrode 132. In another example, the second portion of the switching layer 150 may be located between portions of the side surfaces 404a of the first vertical electrode 404 facing and close to a portion of the edge 134a of the third horizontal electrode 134, and filament constraint may occur therein. In a preferred embodiment, the switching layer contacts at least one of the electrode portions. For example, a portion of the switching layer contacts at least a portion of the side surface of the vertical electrode of the memory device 70. In another example, a portion of the switching layer contacts at least a portion of the edge of the horizontal electrode of the memory device 70.

[0051] Figure 11B It shows having with Figure 2B An exemplary simplified perspective view of a memory device 70 with a similar configuration, but with vertical electrodes 102, 104, 106, 112, 114, and 116 replaced by vertical electrodes 402, 404, 406, 412, 414, and 416, each with a rectangular cross-section. Switching layers and interlayer dielectric materials are not present. Figure 11B The relative arrangement of the electrodes is shown in the diagram to avoid obscuring the view.

[0052] refer to Figure 12 The same reference numerals indicate Figure 1The same features are provided in the memory device 80 according to an alternative embodiment. The memory device 80 may include features similar to those of the memory device 10, including vertical electrodes 102, 104, 106, 112, 114, and 116, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. In other embodiments, the vertical electrodes may be replaced by electrodes having a polygonal cross-section (e.g., a circular cross-section). For example, the vertical electrodes may be similar to those of the memory device 40. The memory device 80 may have a first row of horizontal electrodes 422, 424, 426 and a second row of horizontal electrodes 432, 434, and 436 in place of the horizontal electrodes 122, 124, 126, 132, 134, and 136 of the memory device 10. In one aspect of the embodiment, the horizontal electrodes may have two laterally spaced sidewall surfaces, each sidewall surface may further include one or more portions protruding from the sidewall surface. The protruding portions may include edge portions or surface portions. In a non-limiting example, the first horizontal electrode 422 may have protrusions including side portions 422a and 422b, and the second horizontal electrode 424 may have protrusions including side portions 424a and 424b. Although each pair of protruding side portions (e.g., 422a and 422b) is shown directly opposite each other, it will be understood that the protruding side portions may also be formed in an interleaved configuration based on an alternative mask design. Some or all of the other horizontal electrodes 426, 432, 434, 436 may have protruding side portions similar to those of the aforementioned horizontal electrodes 422 and 424.

[0053] Now for reference Figure 13A The same reference numerals indicate Figure 12 The same features in, and it shows along Figure 12An exemplary cross-sectional view of memory device 80 is shown by the dashed line E-E'. When viewed along the X-axis, the horizontal electrode may have a polygonal cross-section. In one aspect of the embodiment, when viewed along the X-axis, the horizontal electrode may have a cross-sectional shape that is substantially rectangular, square, or trapezoidal. The horizontal electrodes in memory device 80 are positioned relative to the switching layer and vertical electrodes in a configuration similar to that of the horizontal electrodes in memory device 10, such that the positions of electrode portions on the horizontal electrodes relative to the switching layer 150 and the electrode portions on the vertical electrodes are similar to those already described for memory device 10, to achieve confinement of the conductive wire to a specific area. For example, referring to memory device 80, the conductive wire is confined to a portion of the switching layer 150, which is located between a side portion of the first vertical electrode 102 and a protruding side portion of the first horizontal electrode 222. In another example, wire confinement may be achieved in a first portion of the switching layer 150, which is located between a portion of the side 104b of the first vertical electrode 104 facing and close to a portion of the protruding side 422b of the first horizontal electrode 422. Filament restriction can also be implemented in a second portion of the switching layer 150, which is located between another portion of the edge 104b of the first vertical electrode 104 facing and close to a portion of the protruding edge 432b on the second horizontal electrode 432. In another example, the second portion of the switching layer 150 may be located between a portion of the edge 104a on the first vertical electrode 104 facing and close to a portion of the protruding edge 434a on the third horizontal electrode 434, and filament restriction may occur therein. In a preferred embodiment, the switching layer contacts at least one of the electrode portions. For example, a portion of the switching layer 150 contacts at least the edge portion of the vertical electrode of the memory device 80. In another example, a portion of the switching layer 150 contacts both the edge portion of the vertical electrode and the edge portion of the protruding portion of the horizontal electrode.

[0054] Figure 13B It shows having with Figure 2B An exemplary simplified perspective view of a memory device 80 with a similar configuration, but horizontal electrodes 122, 124, 126, 132, 134, and 136 are replaced by horizontal electrodes 422, 424, 426, 432, 434, and 436, one or more of the horizontal electrodes may have two laterally spaced sidewall surfaces, and the sidewall surfaces may further include one or more portions protruding from the sidewall surfaces. Switching layers and interlayer dielectric materials are not present. Figure 13B The relative arrangement of the electrodes is shown in the diagram to avoid obscuring the view.

[0055] refer to Figure 14 The same reference numerals indicate Figure 12The same features are provided in the memory device 80A according to an alternative embodiment. The memory device 80A may include features similar to those of the memory device 80, including vertical electrodes 102, 104, 106, 112, 114, and 116, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. The memory device 80A may have a first row of horizontal electrodes 522, 524, and 526 and a second row of horizontal electrodes 532, 534, and 536, in place of the horizontal electrodes 422, 424, 426, 432, 434, and 436 of the memory device 80. In one aspect of the embodiment, the horizontal electrodes may have two laterally spaced sidewall surfaces, each sidewall surface may further include one or more portions protruding from the sidewall surface. The protruding portions may include asymmetrical edge portions, which may be formed when a sidewall surface portion having a larger surface area intersects with another sidewall surface portion having a smaller surface area. In a non-limiting example, the first horizontal electrode 522 may have protrusions including asymmetrical protruding edge portions 522a and 522b, and the second horizontal electrode 524 may have protrusions including asymmetrical protruding edge portions 524a and 524b. On one hand, each pair of asymmetrical protruding edge portions (e.g., 522a and 522b) may be directly opposite each other. On the other hand, the asymmetrical protruding edge portions may also be formed in an interleaved configuration based on an alternative mask design. Some or all of the other horizontal electrodes 526, 532, 534, 536 may have asymmetrical protruding edge portions similar to those of the aforementioned horizontal electrodes 522 and 524. The horizontal electrodes in memory device 80A are positioned relative to the switching layer and vertical electrodes in a configuration similar to that in memory device 80, such that the relative positions of the electrode portions on the horizontal electrodes with respect to the switching layer 150 and the electrode portions on the vertical electrodes are similar to those already described for memory device 80, to achieve confinement of the conductive wire to a specific region. For example, referring to memory device 80A, a conductive filament is confined within a portion of a switching layer 150, which lies between an edge portion of the first vertical electrode 102 and an asymmetrical protruding edge portion of the first horizontal electrode 522. In another example, the filament confinement may be implemented in a first portion of the switching layer 150, which lies between a portion of the edge 104b of the first vertical electrode 104 facing and close to the asymmetrical protruding edge portion 522b of the first horizontal electrode 522. The filament confinement may also be implemented in a second portion of the switching layer 150, which lies between another portion of the edge 104b of the first vertical electrode 104 facing and close to the asymmetrical protruding edge portion 532b of the second horizontal electrode 532.In another example, a second portion of the switching layer 150 may be located between a portion of the edge 104a on the first vertical electrode 104 facing and close to the asymmetrical protruding edge portion 534a on the third horizontal electrode 534, and wire confinement may occur therein. In a preferred embodiment, the switching layer contacts at least one of the electrode portions. For example, a portion of the switching layer 150 contacts at least the asymmetrical protruding edge portion of the horizontal electrode of the memory device 80A. In another example, a portion of the switching layer 150 contacts both the edge portions of the vertical electrode and the asymmetrical protruding edge portions of the horizontal electrode.

[0056] refer to Figure 15 The same reference numerals indicate Figure 12The same features are provided in an alternative embodiment of memory device 80B. Memory device 80B may include features similar to those of memory device 80, including vertical electrodes 102, 104, 106, 112, 114, and 116, a switching layer 150, and an interlayer dielectric material 160, which have already been described and need not be repeated here. Memory device 80B may have a first row of horizontal electrodes 622, 624, and 626 and a second row of horizontal electrodes 632, 634, and 636, in place of the horizontal electrodes 422, 424, 426, 432, 434, and 436 of memory device 80. In one aspect of the embodiment, the horizontal electrodes may have two laterally spaced sidewall surfaces, each sidewall surface may further include one or more portions protruding from the sidewall surface. The protruding portions may include surface portions, such as a portion of a curved sidewall surface. In a non-limiting example, the first horizontal electrode 622 may have protrusions including curved protruding sidewall surface portions 622a and 622b, and the second horizontal electrode 624 may have protrusions including curved protruding sidewall surface portions 624a and 624b. On one hand, each pair of curved protruding sidewall surface portions (e.g., 622a and 622b) may be directly opposite each other. On the other hand, the curved protruding sidewall surface portions may also be formed in an interleaved configuration based on an alternative mask design. Some or all of the other horizontal electrodes 626, 632, 634, and 636 may have curved protruding sidewall surface portions similar to those of the aforementioned horizontal electrodes 622 and 624. The horizontal electrodes in memory device 80B are positioned relative to the switching layer and vertical electrodes in a configuration similar to that of the horizontal electrodes in memory device 80, such that the relative positions of the electrode portions on the horizontal electrodes with respect to the switching layer 150 and the electrode portions on the vertical electrodes are similar to those already described for memory device 80, to achieve confinement of the conductive wire to a specific region. For example, referring to memory device 80B, a conductive filament is confined within a portion of a switching layer 150 located between an edge portion of the first vertical electrode 102 and a curved, protruding sidewall surface portion of the first horizontal electrode 622. In another example, the filament confinement may be implemented in a first portion of the switching layer 150 located between a portion of the edge 104b of the first vertical electrode 104 facing and adjacent to the curved, protruding sidewall surface portion 622b of the first horizontal electrode 622. The filament confinement may also be implemented in a second portion of the switching layer 150 located between another portion of the edge 104b of the first vertical electrode 104 facing and adjacent to the curved, protruding sidewall surface portion 632b of the second horizontal electrode 632.In another example, a second portion of the switching layer 150 may be located between a portion of the edge 104a of the first vertical electrode 104 facing and close to the curved protruding sidewall surface portion 634a on the third horizontal electrode 634, and wire confinement may occur therein. In a preferred embodiment, the switching layer contacts at least one of the electrode portions. For example, a portion of the switching layer 150 contacts at least the curved protruding sidewall surface portion of the horizontal electrode of the memory device 80B. In another example, a portion of the switching layer 150 contacts the edge portion of the vertical electrode and the curved protruding sidewall surface portion of the horizontal electrode.

[0057] refer to Figure 16A The same reference numerals indicate Figure 2B The memory device 10 includes the same features as those in the previous embodiment, and according to another aspect of the embodiment, the memory device 10 includes conductive vias 12 that connect horizontal electrodes to conductive lines 14, 16, 18, and 20 for applying voltage. Conductive lines 16 and 18 are not in... Figure 16A The relative positions of conductive lines 14 and 20 are shown in the diagram to avoid obscuring their positions for illustrative purposes. Horizontal electrodes on the same level can be connected to different conductive lines by staggering the electrode lengths and varying the height of the conductive via 12. For example, horizontal electrodes 132 and 134 can be connected to different conductive lines 14 and 16 by having different electrode lengths and different via heights.

[0058] Now for reference Figure 16B The diagram shows a simplified top view of the memory device 10, where the bottom-level horizontal electrodes 132, 134, 136, and 138 have staggered lengths, such that horizontal electrodes 132 and 136 are connected to conductive line 14, while horizontal electrodes 134 and 138 are connected to conductive line 16. The dashed circular via outline 12 shows the relative positions of the conductive vias 12 that connect the conductive lines to the respective horizontal electrodes. Dashed outlines 18 and 20 show the relative positions of conductive lines 18 and 20, respectively, used to connect the horizontal electrodes of different levels. Figure 16C A simplified top view of another different level (e.g., top level) of horizontal electrodes is shown, where horizontal electrodes 122 and 126 are connected to conductive line 18, while horizontal electrodes 124 and 128 are connected to conductive line 20. Similarly, the dashed circular via outline 12 shows the relative positions of conductive vias 12 that connect conductive lines to the respective horizontal electrodes. The dashed outline shows the relative positions of conductive lines 14 and 16 on the horizontal electrodes of different levels. As shown, the staggered horizontal electrode lengths and the configuration of the conductive vias 12 allow conductive lines to be connected to the respective horizontal electrodes without contacting other horizontal electrodes. For improved manufacturing efficiency and to facilitate electrical routing, the height of the conductive vias 12 can also be varied for each pair of connected horizontal electrodes.

[0059] Figures 17A to 17K Exemplary processes for manufacturing various embodiments of the present invention described above are illustrated. References Figure 17A A first interlayer dielectric layer 162 is disposed above a substrate 100, and a first mask layer 164 is deposited above the first interlayer dielectric layer 162. The first mask layer 164 may include a dielectric material, such as silicon dioxide or silicon nitride, and may be patterned by photolithography and etching processes to define a mask opening 168. The shape and size of the mask opening 168 are determined based on the desired shape and size of the resulting horizontal electrode and the selection of a suitable process for fabricating the opening 166 in the first interlayer dielectric layer 162. For example, a reactive ion etching (RIE) process tailored for erosive lateral etching can form an opening 166 with a top width greater than the size of the opening 168. Other material removal processes that result in the opening 166 having substantially inclined sidewalls 167a and 167b can also be used instead of the RIE process. This can ultimately form a horizontal electrode having a triangular cross-section including sidewalls 167a and 167b. Figure 18A In another embodiment shown, the wet etching process combined with a larger mask opening 168a can result in an opening 166R with a substantially curved surface. This can ultimately form a horizontal electrode with a curved surface. Figure 18B Another embodiment is shown, in which a larger mask opening 168a, combined with a RIE process tailored for minimal lateral etching, can form an opening 166S with a substantially flat bottom surface and substantially vertical sidewalls. This can ultimately form a horizontal electrode with a cross-section such as a rectangle, square, or trapezoid. It is understood that process limitations may result in a non-flat bottom surface and sloping sidewalls, as well as rounded edges.

[0060] Now for reference Figure 17B and Figure 17C The subsequent processing steps involve removing the first mask layer 164 from the top surface of the first interlayer dielectric layer 162 using a suitable etching or stripping process. The first conductive material 170 selected for forming the horizontal electrodes is then deposited over the first interlayer dielectric material 162 by, for example, physical vapor deposition (PVD), thereby filling the opening 166. Excess conductive material 170 is then removed from the top surface of the first interlayer dielectric material 162 using a suitable material removal process, such as chemical mechanical planarization (CMP), leaving a first row of horizontal electrodes 130 with a top surface substantially flush with the top surface of the first interlayer dielectric material 162.

[0061] Now for reference Figure 17DThen, using a suitable deposition technique, such as chemical vapor deposition (CVD) as an example, a second interlayer dielectric material 172 is deposited above the horizontal electrode 130 and the top surface of the first interlayer dielectric material 162. The first interlayer dielectric material and the second interlayer dielectric material may be the same or different, and are collectively referred to as interlayer dielectric material 160.

[0062] refer to Figure 17E In subsequent processing steps, a second mask layer 174 is deposited over the second interlayer dielectric material 172, and the second mask layer 174 is patterned by suitable photolithography and etching processes similar to those used for the first mask layer 164 to form mask openings 178. Similar to the processing steps for... Figure 17A , Figure 18A and Figure 18B The description states that the size of the mask opening 178, combined with a suitable material removal process, will result in the desired cross-section of the horizontal electrode manufactured in the opening 176.

[0063] Now for reference Figure 17F and Figure 17G The second mask layer 174 can then be removed from the top surface of the second interlayer dielectric layer 172 using a suitable etching or stripping process. The second conductive material 180, selected to form the horizontal electrodes, is then deposited over the first interlayer dielectric material 172 by, for example, physical vapor deposition (PVD), thereby filling the opening 176. Excess conductive material 180 can then be removed from the top surface of the first interlayer dielectric material 172 using a suitable material removal process, such as chemical mechanical planarization (CMP), leaving a second row of horizontal electrodes 120 with a top surface substantially flush with the top surface of the first interlayer dielectric material 172. The second conductive material 180 can be the same as the first conductive material 170, or it can be different depending on the design requirements of the memory device. For example, different conductive materials can be used to create different memory states for different memory primitives.

[0064] refer to Figure 17H and Figure 17I In subsequent processing steps, a third mask layer 182 is deposited over the surface of the horizontal electrode 120 and the second interlayer dielectric material 172. The third mask layer can be patterned using suitable photolithography and etching processes to form mask openings 186. Openings 184 can be formed in the interlayer dielectric material 160 using suitable material removal processes such as RIE, exposing the edges of the horizontal electrodes 120 and 130 along the sidewalls 184a and 184b of the openings 184. Figure 17IThe subsequent processing steps are illustrated, wherein a switching layer 188 is conformally deposited over the top surface of the horizontal electrode 120 and the second interlayer dielectric material 172, as well as over the sidewalls 184a and 184b. Suitable conformal deposition methods may include, but are not limited to, atomic layer deposition (ALD) and chemical vapor deposition (CVD). Due to the high aspect ratio of the opening 184, there may be little or no deposit of the switching layer at the bottom surface of the opening 184. Any switching layer deposited at the bottom surface of the opening 184 can be removed by selective material removal methods, such as anisotropic etching.

[0065] Figure 17J The subsequent processing steps are illustrated, wherein the third conductive material 190 selected for forming the vertical electrodes is then deposited on the switching layer 188 by a suitable deposition method, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) as examples, thereby filling the opening 184. Excess conductive material 190 can then be removed from the top surfaces of the first interlayer dielectric material 172 and the horizontal electrode 120 by a suitable material removal process, such as chemical mechanical planarization (CMP), leaving vertical electrodes 112 and 114, each of which has a top surface substantially flush with the top surfaces of the first interlayer dielectric material 172 and the horizontal electrode 120.

[0066] Figures 19A to 19L An exemplary manufacturing process for a memory device according to an alternative embodiment of the present invention is illustrated. In particular, the process is suitable for forming… Figure 12 , Figure 13A , Figure 13B , Figure 14 and Figure 15 The memory devices 80, 80A, and 80B are shown. This process is related to… Figures 17A to 17K The described processes are similar, and the same reference numerals indicate the same features. First, refer to... Figure 19A A first interlayer dielectric layer 162 is disposed on a substrate 100, and a first mask layer 164 is deposited on the first interlayer dielectric material 162. The first mask layer 164 is patterned according to suitable photolithography and etching processes to define mask openings 168a. The shape and size of the mask openings 168a are determined based on the desired shape and size of the resulting horizontal electrodes and the selection of suitable processes for fabricating openings 166 in the first interlayer dielectric layer 162. For example, the mask openings 168a may have a chain-like design to form openings 166S with laterally spaced sidewalls, the openings 166S further including sidewall or edge portions that extend deeper into the interlayer dielectric material 162 than these sidewalls to form horizontal electrodes with laterally spaced sidewall surfaces including protrusions, for example... Figure 12 , Figure 14 and Figure 15 The horizontal electrode. Opening 166S can be formed using a reactive ion etching (RIE) process tailored to minimize lateral etching, such that the size and design of opening 166S track the size and design of mask opening 168a. It is understood that process constraints may result in a non-flat bottom surface and slightly sloping sidewalls, as well as rounded edges.

[0067] Now for reference Figures 19B to 19D The subsequent processing steps involve removing the first mask layer 164 from the top surface of the first interlayer dielectric layer 162 using a suitable etching or stripping process. The first conductive material 170 selected for forming the horizontal electrodes is then deposited on the first interlayer dielectric material 162 by, for example, physical vapor deposition (PVD), thereby filling the opening 166S. Excess conductive material 170 can be removed from the top surface of the first interlayer dielectric material 162 using a suitable material removal process, such as chemical mechanical planarization (CMP), leaving a first row of horizontal electrodes 430 with a top surface substantially flush with the top surface of the first interlayer dielectric material 162. A second interlayer dielectric material 172 is then deposited on the horizontal electrodes 430 and the top surface of the first interlayer dielectric material 162 using a suitable deposition technique, such as chemical vapor deposition (CVD). The first and second interlayer dielectric materials may be the same or different. The second mask layer 174 is deposited on the second interlayer dielectric material 172 and patterned by appropriate photolithography and etching processes to form mask openings 178a.

[0068] refer to Figures 19E to 19G An opening 176S, similar to the previous opening 166S, is formed using a suitable material removal process, and the second mask layer 174 is subsequently removed from the top surface of the second interlayer dielectric layer 172 by a suitable etching or stripping process. A second conductive material 180, selected to form the horizontal electrodes, is then deposited on top of the first interlayer dielectric material 172 by physical vapor deposition (PVD), as an example, to fill the opening 176S. Excess conductive material 180 is then removed from the top surface of the first interlayer dielectric material 172 by a suitable material removal process, such as chemical mechanical planarization (CMP), leaving a second row of horizontal electrodes 420 with a top surface substantially flush with the top surface of the first interlayer dielectric material 172. The second conductive material 180 may be the same as the first conductive material 170, or it may be different depending on the design requirements of the memory device. For example, different conductive materials may be used to create different memory states for different memory primitives.

[0069] refer to Figures 19H to 19JIn subsequent processing steps, a third interlayer dielectric material 181 is deposited on the surface of the horizontal electrode 120 and the second interlayer dielectric material 172 using a suitable deposition technique. The first, second, and third interlayer dielectric materials may be the same or different, and are collectively referred to as interlayer dielectric material 160. A third mask layer 182 is deposited on the top surface of the interlayer dielectric material 160. Due to the presence of the third interlayer dielectric material 181, the top surface of the horizontal electrode 420 is not exposed when the third mask layer is formed. A mask opening 186 is formed in the third mask layer 182, and an opening 184 can be formed in the interlayer dielectric material 160 using a suitable material removal process such as RIE, exposing the edges of the horizontal electrodes 420 and 430 along the sidewalls 184a and 184b of the opening 184. Figure 19J The subsequent processing steps are illustrated, wherein a switching layer 188 is conformally deposited over the top surface of the third interlayer dielectric material 181 and over the sidewalls 184a and 184b. Suitable conformal deposition methods may include, but are not limited to, atomic layer deposition (ALD) and chemical vapor deposition (CVD). Due to the high aspect ratio of the opening 184, there may be little or no deposit of the switching layer at the bottom surface of the opening 184. Any switching layer deposited at the bottom surface of the opening 184 can be removed by selective material removal methods, such as anisotropic etching.

[0070] Figure 19K The subsequent processing steps are illustrated, wherein the third conductive material 190 selected for forming the vertical electrode is then deposited on the switching layer 188 by a suitable deposition method, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) as examples, thereby filling the opening 184. Reference Figure 19L The excess conductive material 190 can then be removed from the top surface of the first interlayer dielectric material 172 and the horizontal electrode 120 by a suitable material removal process, such as chemical mechanical planarization (CMP), leaving vertical electrodes 112 and 114, each of which has a top surface substantially flush with the top surface of the third interlayer dielectric material 181.

[0071] The description of the embodiments herein is intended as illustrative and not to limit one to these examples. Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” and “below” in the specification and claims are used, when present, to establish a reference frame, and are not necessarily used to describe permanent relative positions. The term “horizontal” is defined as a plane parallel to the conventional plane of the semiconductor substrate, not its actual three-dimensional orientation in space. The terms “vertical” and “normal” refer to a plane perpendicular to the horizontal. The term “lateral” refers to a direction parallel to the horizontal plane.

[0072] Terms such as “connected” or “coupled” indicate that a feature can be directly connected to or coupled to another feature, or that one or more intermediate features may exist. If no intermediate features exist, a feature can be “directly connected” or “directly coupled” to another feature. If at least one intermediate feature exists, a feature can be “indirectly connected” or “indirectly coupled” to another feature. Terms such as “located on” or “in contact” indicate that a feature can be directly located on or in direct contact with another feature, or that one or more intermediate features may exist. If no intermediate features exist, a feature can be “directly on” or “in direct contact” with another feature. If at least one intermediate feature exists, a feature can be “indirectly on” or “indirectly in contact” with another feature.

[0073] The terms “first,” “second,” “third,” etc., used in the specification and claims, when present, are used to distinguish similar elements and are not necessarily used to describe a specific desired order or chronological sequence. The methods described herein are not necessarily limited in practice to the exact order or number of steps listed, and in practice, certain steps may be omitted and / or other steps not described herein may be performed. Terms such as “comprising,” “including,” “having,” and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or not inherent to those processes, methods, articles, or devices. The appearance of the phrase “in one embodiment” does not necessarily refer to the same embodiment.

[0074] Although several exemplary embodiments have been given in the above detailed description of the device, it should be understood that many variations exist. It should be further understood that the embodiments are merely examples and are not intended to limit the scope, applicability, size, or configuration of the device in any way. Rather, the above detailed description will provide a convenient guide for those skilled in the art to implement exemplary embodiments of the device, and it will be understood that various changes can be made to the function and arrangement of the elements described in the exemplary embodiments and the methods of manufacture without departing from the scope of this disclosure set forth in the appended claims.

Claims

1. A memory device, comprising: A first electrode is located above a substrate and has a length along a vertical axis perpendicular to the substrate. The second electrode has a length along a horizontal axis, wherein the second electrode has a first side adjacent to the first electrode, and wherein the second electrode has a protruding edge portion toward the first electrode; A third electrode having a length along the vertical axis, wherein the third electrode is positioned adjacent to a second side of the second electrode that is different from the first side; and A switching layer is located adjacent to the first electrode, and a portion of the switching layer is located between the first electrode and the protruding edge portion and contacts the protruding edge portion.

2. The device of claim 1, wherein the switching layer is conformally fitted to the surface of the first electrode.

3. The device of claim 1, wherein the protruding edge portion has a single protruding edge portion facing the first electrode.

4. The device of claim 1, wherein a portion of the switching layer is in contact with the first electrode.

5. The device according to claim 1, wherein the first electrode includes a protruding edge portion.

6. The device according to claim 1, wherein the first electrode comprises a first electrode surface.

7. The device of claim 1, wherein the first electrode, when viewed along the vertical axis, comprises a polygonal cross-section.

8. The device of claim 1, wherein the first electrode, when viewed along the vertical axis, comprises a circular cross-section.

9. The device of claim 1, wherein the protruding edge portion is parallel to the horizontal axis.

10. The device of claim 3, wherein the protruding edge portion includes an electrode edge.

11. The device of claim 1, wherein the memory device comprises a resistive random access memory.

12. A memory device, comprising: Substrate; A first vertical electrode and a second vertical electrode are located above the substrate, and the first vertical electrode and the second vertical electrode are perpendicular to the substrate; A first horizontal electrode parallel to the substrate, wherein the first horizontal electrode has a first side adjacent to the first vertical electrode and a second side adjacent to the second vertical electrode, the second side being opposite to the first side, wherein the first horizontal electrode has a first protruding edge portion on the first side facing the first vertical electrode and a second protruding edge portion on the second side facing the second vertical electrode; A first switching layer, conformally to the first vertical electrode, is located between the first vertical electrode and the first horizontal electrode and contacts the first protruding edge portion; and The second switching layer is conformal to the second vertical electrode and is located between the second vertical electrode and the first horizontal electrode, and contacts the second protruding edge portion.

13. The device of claim 12, wherein the first vertical electrode is laterally displaced relative to the second vertical electrode.

14. The device of claim 12, further comprising a second horizontal electrode parallel to the first horizontal electrode, wherein the first horizontal electrode is vertically displaced relative to the second horizontal electrode.

15. The device of claim 14, wherein the first horizontal electrode and the second horizontal electrode are connected to different electrical inputs.

16. The device of claim 14, further comprising a third horizontal electrode parallel to and laterally displaced relative to the first and second horizontal electrodes, wherein the second vertical electrode is located between the second horizontal electrode and the third horizontal electrode, and the first and third horizontal electrodes are connected to the same electrical input.

17. A method for manufacturing a memory device, comprising: A first electrode is disposed above a substrate, the first electrode having a length along a vertical axis perpendicular to the substrate; A second electrode is provided, the second electrode having a length along a horizontal axis, wherein the second electrode has a first side adjacent to the first electrode, wherein the second electrode has a protruding edge portion on the first side facing the first electrode; A third electrode is provided, the third electrode having a length along the vertical axis, wherein the third electrode is positioned adjacent to a second side of the second electrode that is different from the first side; and A switching layer is provided adjacent to the first electrode, a portion of which is located between the first electrode and the protruding edge portion and contacts the protruding edge portion.

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