Duty cycle monitoring and a method of monitoring the duty cycle of a target signal

Abstract

A duty cycle monitoring circuit is coupled to a functional circuit that generates a first output signal in response to a target signal. The duty cycle monitoring circuit includes a modulation circuit that receives the target signal and modulates the target signal to generate a modulated target signal, a replica circuit that receives the modulated target signal and generates a second output signal in response to the modulated target signal, and an error detection circuit that is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and generate an error detection result based on the first output signal and the second output signal. When the duty cycle of the modulated target signal is not sufficient for the replica circuit to operate properly, the second output signal generated by the replica circuit can have an erroneous waveform, and thus the error detection result can indicate whether the functional circuit is about to or likely to have an error due to a duty cycle degradation.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a duty cycle monitoring circuit and a method for monitoring the duty cycle of a target signal. Background Technology

[0002] Signal processing circuits, such as processors, memory devices, and input / output (I / O) devices, typically communicate with each other using digital data signals and clock signals, with the clock signal used at the receiving device to time the received data. Therefore, the clock signal is a crucial signal in the field of signal processing.

[0003] The duty cycle of a clock signal is defined as a portion of the clock cycle during which the clock is in the active state. For some high-performance circuits triggered by clock signals and requiring a strict duty cycle (also known as operational margin or duty cycle margin, which is the margin or safety margin for the circuit to operate correctly or receive data correctly), the duty cycle of the clock signal is a critical factor determining the circuit's reliability. However, the duty cycle of the clock signal is susceptible to the effects of circuit component aging, signal transmission distance, or process variations.

[0004] Therefore, there is a great need for circuit designs and related methods for detecting duty cycle degradation. Summary of the Invention

[0005] In view of this, the present invention provides a duty cycle monitoring circuit and a method for monitoring the duty cycle of a target signal, adjusting the signal's duty margin or duty cycle as needed to avoid circuit malfunction due to duty cycle degradation.

[0006] According to a first aspect of the present invention, a duty cycle monitoring circuit is disclosed, coupled to a functional circuit that generates a first output signal in response to a target signal. The duty cycle monitoring circuit includes:

[0007] A modulation circuit is used to receive the target signal and modulate the target signal to generate a modulated target signal;

[0008] A replication circuit is configured to receive the modulated target signal and generate a second output signal in response to the modulated target signal; and

[0009] An error detection circuit, coupled to the functional circuit and the replication circuit, is used to receive the first output signal and the second output signal, and generate an error detection result based on the first output signal and the second output signal.

[0010] According to a second aspect of the present invention, a method for monitoring the duty cycle of a target signal is disclosed, comprising:

[0011] The target signal is provided to the functional circuit so that the functional circuit generates a first output signal in response to the target signal;

[0012] The target signal is modulated to generate a modulated target signal, and the modulated target signal is provided to the replication circuit so that the replication circuit generates a second output signal in response to the modulated target signal, wherein the replication circuit is a replica of the functional circuit; and

[0013] An error detection result is generated based on the first output signal and the second output signal.

[0014] According to a third aspect of the present invention, a duty cycle circuit is disclosed for monitoring and controlling a target signal, comprising:

[0015] Multiple circuit subunits, each circuit subunit including: a functional circuit for receiving the target signal and generating a first output signal in response to the target signal; and a duty cycle monitoring circuit coupled to the functional circuit for monitoring the duty cycle of the target signal according to the first output signal to generate an error detection result;

[0016] A data acquisition circuit, coupled to this circuit subunit, is used to acquire the error detection result and generate a control signal based on the error detection result; and

[0017] A control circuit, coupled to the acquisition circuit, is used to adjust the duty cycle of the target signal according to the control signal.

[0018] The duty cycle monitoring circuit of the present invention is coupled to a functional circuit that generates a first output signal in response to a target signal. The duty cycle monitoring circuit includes: a modulation circuit for receiving the target signal and modulating the target signal to generate a modulated target signal; a replication circuit for receiving the modulated target signal and generating a second output signal in response to the modulated target signal; and an error detection circuit coupled to the functional circuit and the replication circuit for receiving the first output signal and the second output signal, and generating an error detection result based on the first output signal and the second output signal. Using the above-described solution, more stringent conditions can be used to detect whether the functional circuit is about to or may experience an error caused by duty cycle degradation. When the duty margin or duty cycle of the modulated target signal is insufficient for the replication circuit to operate normally, the second output signal generated by the replication circuit may have an erroneous waveform, thereby detecting whether the functional circuit is about to or may experience an error caused by duty cycle degradation. Attached Figure Description

[0019] Figure 1An exemplary waveform of a clock signal is shown.

[0020] Figure 2 An exemplary block diagram of a circuit for monitoring (or surveillance) and controlling the duty cycle of a signal according to an embodiment of the present invention is shown.

[0021] Figure 3 Exemplary waveforms of a target signal, a modulated target signal, a first output signal, a second output signal, and an error detection signal according to embodiments of the present invention are shown.

[0022] Figure 4 A flowchart of a method for monitoring the duty cycle of a target signal according to an embodiment of the present invention is shown.

[0023] Figure 5 An exemplary block diagram of a circuit for monitoring and controlling the duty cycle of a signal according to another embodiment of the present invention is shown.

[0024] Figure 6 An exemplary block diagram of a circuit for monitoring and controlling the duty cycle of a signal according to yet another embodiment of the present invention is shown.

[0025] Figure 7 An exemplary circuit diagram of a modulation circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0026] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0027] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0028] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0029] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0031] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0032] Figure 1An exemplary waveform of a clock signal is shown. Clock signal Clock_1 is a clock signal transmitted over a relatively short distance, and clock signal Clock_2 is the same clock signal transmitted over a relatively long distance. In the Clock_2 waveform, the solid line represents the original waveform of the clock signal before duty cycle degradation, and the dashed line represents the waveform after duty cycle degradation. Figure 1 As shown, when the duty cycle of the clock signal begins to decrease, the pulse width of the clock signal narrows.

[0033] When a clock signal is used as a high-level active signal, i.e., when the logic high state of the clock signal is recognized as an active state, the degradation (or decrease) of the duty cycle reduces the clock signal's duty margin (or working margin), i.e., the duration of the logical high state. Here, the clock signal's duty margin can also be called operational margin or duty cycle margin; it is the margin by which the circuit receiving the clock signal can correctly operate or correctly receive data in response to the clock signal's startup state. To avoid circuit malfunction due to duty cycle degradation, the following disclosure proposes a circuit design and related method to detect the duty cycle degradation of a target signal by monitoring the duty cycle and further controlling the target signal's duty margin (or working margin) or duty cycle when necessary. It should be noted that although the above example uses long transmission distance leading to duty cycle degradation, the present invention is not limited thereto. The proposed circuit and related methods are also applicable to detecting duty cycle degradation caused by other factors, such as aging of circuit components and process variations.

[0034] Figure 2 An exemplary block diagram of a circuit for monitoring and controlling the duty cycle of a signal according to an embodiment of the present invention is shown. Circuit 200 may be referred to as a duty cycle control circuit or duty cycle circuit, etc. Circuit 200 may include at least a functional circuit 210, a duty cycle monitoring circuit 220, and a control circuit 230. In an embodiment of the invention, circuit 200 is designed to monitor and control the duty cycle of a target signal, wherein the duty cycle monitoring circuit 220 is arranged to monitor the duty cycle of the target signal by monitoring the signal output by the functional circuit 210, and the control circuit 230 is arranged to control the duty margin (or, in some embodiments, the duty cycle) of the target signal and provide the target signal to a delay chain 240 and subsequent digital circuit block 250. According to an embodiment of the invention, the target signal may be a pulse signal comprising only one or at least one pulse, or it may be a clock signal comprising multiple consecutive pulses.

[0035] Functional circuit 210 can receive a target signal from delay chain 240, which may be a delayed version of the original target signal output by control circuit 230, and is arranged to generate an output signal (e.g., a first output signal) in response to the target signal. For ease of understanding, the target signal provided to functional circuit 210 is labeled CK1.

[0036] In embodiments of the present invention, the functional circuit 210 may be a duty-sensitive unit sensitive to changes in the duty margin or duty cycle of the target signal. For example, when the duty margin or duty cycle of the target signal CK1 is insufficient, the functional circuit 210 may malfunction or generate a first output signal with an erroneous waveform (the first output signal may also be a normal signal). In one embodiment of the present invention, the functional circuit 210 is a memory circuit used to receive the input data signal and sample the input data signal in response to the target signal CK1 to generate the first output signal. However, the present invention is not limited thereto. For ease of understanding, the input data signal provided to the functional circuit 210 is labeled Data_in, and the first output signal generated by the functional circuit 210 is labeled Q1.

[0037] According to one embodiment of the present invention, the duty cycle monitoring circuit 220 may include a modulation circuit 260, a replication circuit 270, and an error detection circuit 280. The modulation circuit 260 is used to receive the target signal CK1 and modulate or adjust the target signal CK1 to generate a modulated target signal. The replication circuit 270 is used to receive the modulated target signal and generate a second output signal in response to the modulated target signal. For ease of understanding, the modulated target signal (also referred to as the modulated target signal or the modulated target signal) provided to the replication circuit 270 is labeled CK2, and the second output signal generated by the replication circuit 270 is labeled Q2.

[0038] According to one embodiment of the present invention, the replication circuit 270 is a copy or replica of the functional circuit 210. That is, the replication circuit 270 can be designed to have the same circuit structure and operation as the functional circuit 210. In the embodiments of the present invention, the replication circuit 270, like the functional circuit 210, is also a memory circuit, used to receive the same input data signal Data_in, and to sample the input data signal Data_in in response to the modulated target signal (modulated target signal) CK2 to generate a second output signal Q2. However, the replication circuit 270 can actually be a dummy circuit. It should be noted that, in the embodiments of the present invention, the functional circuit 210 and the replication circuit 270 are not limited to being implemented as memory circuits.

[0039] According to one embodiment of the present invention, the modulation circuit 260 can modulate the target signal CK1 by adjusting the pulse width of the target signal CK1 (modulating or adjusting the target signal CK1). For example, in one embodiment of the present invention, the modulation circuit 260 can narrow the pulse width of the target signal CK1 to generate a modulated target signal (modulated target signal) CK2 with a pulse width narrower than that of the target signal CK1. Since the pulse width of the modulated target signal CK2 is narrower than that of the target signal CK1, the replication circuit 270 actually operates under tighter conditions than the functional circuit 210. In embodiments of the present invention, tighter conditions can be used to detect whether the functional circuit 210 is about to or may experience an error caused by duty cycle degradation. When the duty margin or duty cycle of the modulated target signal CK2 is insufficient for the replication circuit 270 to operate normally, the second output signal Q2 generated by the replication circuit 270 may have an erroneous waveform, thereby allowing detection of whether the functional circuit 210 is about to or may experience an error caused by duty cycle degradation. When a duty cycle degradation error is detected to be imminent or likely to occur, the control circuit 230 will adjust the duty margin or duty cycle in advance to avoid functional failure of the functional circuit due to the duty cycle degradation and / or to prevent the error from actually occurring.

[0040] In one embodiment of the present invention, the error detection circuit 280 is coupled to the functional circuit 210 and the replication circuit 270 to receive the first output signal Q1 and the second output signal Q2, and to generate an error detection result based on the first output signal Q1 and the second output signal Q2.

[0041] According to one embodiment of the present invention, the error detection result can be an error detection signal having a default signal level for indicating an error-free state and a predetermined signal level for indicating a detected error. For example, when the error detection circuit 280 detects an error, a high voltage level can be set in the error detection signal or an error flag can be set to asserted. For ease of understanding, the error detection result or the error detection signal output by the error detection circuit 280 is labeled Err_Flag. The error detection result can indicate whether the target signal has no error or has an error.

[0042] According to one embodiment of the present invention, the error detection circuit 280 can be used to compare the difference between a first output signal Q1 and a second output signal Q2 to generate an error detection signal Err_Flag. For example, in this embodiment, the functional circuit 210 is used to sample the input data signal Data_in in response to a target signal CK1 to generate the first output signal Q1, and the replication circuit 270 is used to sample the same input data signal Data_in in response to a modulated target signal CK2 to generate the second output signal Q2. The error detection circuit 280 can be designed to detect whether the second output signal Q2 has the same value as the first output signal Q1 and generate the error detection signal Err_Flag accordingly. According to one embodiment of the present invention, the error detection circuit 280 can be implemented as or include an exclusive OR (XOR) gate.

[0043] The error detection signal Err_Flag is further provided to the control circuit 230. The control circuit 230 is configured to control the duty margin (or, in some embodiments, the duty cycle) of the target signal based on the error detection signal Err_Flag. For example, when the control circuit 230 detects an error flag in the error detection signal Err_Flag (or when the error detection signal Err_Flag is set to a predetermined signal level), the control circuit 230 adjusts the duty margin (duty cycle) of the target signal. In one embodiment of the invention, since the error detection result indicates that the duty margin or duty cycle of the modulated target signal CK2 is insufficient, the control circuit 230 can extend or increase the duty margin or duty cycle of the target signal.

[0044] Figure 3 Exemplary waveforms of the target signal CK1, the modulated target signal CK2, the first output signal Q1, the second output signal Q2, and the error detection signal Err_Flag according to an embodiment of the present invention are shown. The pulse width of the modulated target signal CK2 is narrower than that of the target signal CK1. The difference between the pulse width of the target signal CK1 and the pulse width of the modulated target signal CK2 can be considered as a reserved margin. In an embodiment of the present invention, when the duty margin or duty cycle of the modulated target signal CK2 is sufficient to enable the replication circuit 270 to operate normally, since the replication circuit 270 samples the same input data signal as the functional circuit 210, the waveform of the second output signal Q2 should be the same as the waveform of the first output signal Q1. Figure 3In the example shown, the waveform of the second output signal Q2 differs from that of the first output signal Q1, indicating that the duty cycle of the target signal CK2 has insufficient margin or is not fully adjusted. When the error detection circuit 280 detects that the waveform of the second output signal Q2 differs from that of the first output signal Q1, the error detection circuit 280 sets the error flag in the error detection signal Err_Flag. In this way, the control circuit 230 can adjust the duty cycle of the target signal in response to the error detection signal Err_Flag.

[0045] Figure 4 A flowchart of a method for monitoring the duty cycle of a target signal according to an embodiment of the present invention is shown. The method for monitoring the duty cycle of the target signal can be a duty cycle monitoring circuit, such as the duty cycle monitoring circuit 220 described above, or a circuit including a duty cycle monitoring circuit, such as the circuit 200 described above, and may include the following steps:

[0046] Step S402: Provide the target signal to be monitored to the functional circuit, such as the functional circuit 210 described above, so that the functional circuit can generate a first output signal according to (in response to) the target signal.

[0047] Step S404: Modulate (or adjust) the target signal to generate a modulated target signal, and provide the modulated target signal to the replication circuit, such as the replication circuit 270 described above, so that the replication circuit generates a second output signal in response to the modulated target signal. In embodiments of the present invention, the replication circuit is a copy or replica of a functional circuit, or a circuit that replicates a functional circuit.

[0048] Step S406: Compare the first output signal with the second output signal, and generate an error detection result based on the first output signal and the second output signal.

[0049] According to one embodiment of the present invention, the first output signal may be the result of data sampling performed by the functional circuit in response to the target signal, while the second output signal may be the result of data sampling performed by the replication circuit in response to the modulated target signal. Furthermore, the comparison in step S406 can be performed by comparing the difference between the first output signal and the second output signal, or by detecting whether the second output signal has the same value or the same waveform as the first output signal.

[0050] Furthermore, in some embodiments of the present invention, the method for monitoring the duty cycle of the target signal may also include the step of providing the error (or fault) detection result to the control circuit, such as the control circuit 230 described above, for controlling or adjusting the duty cycle of the target signal based on the fault detection result.

[0051] Figure 5An exemplary block diagram of a circuit for monitoring and controlling the duty cycle of a signal according to another embodiment of the present invention is shown. Circuit 500 may include at least a plurality of circuit subunits 520-1 to 520-N, an acquisition circuit 510, and a control circuit 530, where N is a positive integer greater than 1. In an embodiment of the invention, circuit 500 is used to monitor and control the duty cycle of a target signal, wherein a duty cycle monitoring circuit in a circuit subunit is used to monitor the duty cycle of the target signal by monitoring the signal output by a functional circuit in the monitoring circuit subunit, and control circuit 530 is arranged to control the duty margin (or duty cycle) of the target signal and provide the target signal to a delay chain 540 and a subsequent digital circuit block 550. According to an embodiment of the invention, the target signal may be a pulse signal comprising only one or at least one pulse, or it may be a clock signal comprising multiple consecutive pulses.

[0052] In embodiments of the present invention, each circuit subunit may include functional circuitry, such as... Figure 2 The functional circuit 210 shown is used to receive the target signal and generate a first output signal in response to the target signal, and a duty cycle monitoring circuit, for example... Figure 2 The duty cycle monitoring circuit 220 shown is coupled to the functional circuit to monitor the duty cycle of the target signal based on the first output signal in order to generate an error detection result.

[0053] According to one embodiment of the present invention, the functional circuits in circuit subunits 520-1 to 520-N can receive target signals with the same or different delay amounts generated by the control circuit 530 from the delay chain 540. Thus, the duty cycle monitoring circuit in each circuit subunit can monitor the duty cycle of the target signals from different delay points.

[0054] According to one embodiment of the present invention, the duty cycle monitoring circuit in each circuit subunit may include a modulation circuit, such as... Figure 2 The modulation circuit 260 shown is used to receive a target signal and modulate the target signal to generate a modulated target signal. According to one embodiment of the invention, the modulation circuit in each circuit subunit can modulate the target signal by adjusting the pulse width of the target signal as described above. For example, in one embodiment of the invention, the modulation circuit can narrow the pulse width of the target signal to generate a modulated target signal with a pulse width narrower than the target signal.

[0055] Furthermore, according to one embodiment of the present invention, the duty cycle monitoring circuit in each circuit sub-unit may further include a replication circuit, such as... Figure 2The replica circuit 270 shown is a replica of the functional circuit, used to receive a modulated target signal and generate a second output signal in response to the modulated target signal. According to one embodiment of the present invention, when the functional circuit is used to receive an input data signal and sample the input data signal in response to the target signal to generate a first output signal, the replica circuit is used to receive the same input data signal and sample the input data signal in response to the modulated target signal to generate a second output signal.

[0056] Furthermore, according to one embodiment of the present invention, the duty cycle monitoring circuit in each circuit sub-unit may further include an error detection circuit, such as... Figure 2 The error detection circuit 280 shown is coupled to the functional circuit and the replication circuit to receive a first output signal and a second output signal, and to generate an error detection result based on the first output signal and the second output signal. For example, the error detection circuit can compare the difference between the first output signal and the second output signal to generate an error detection result. As described above, the error detection result generated by each circuit subunit can be an error detection signal having a preset signal level (or default signal level) for indicating an error-free state and a predetermined signal level for indicating a detected error. For example, when an error is detected, a high voltage level can be set in the error detection signal or an error flag can be set to valid.

[0057] The acquisition circuit 510 is coupled to circuit subunits 520-1 to 520-N to acquire error detection results (e.g., error detection signals) generated by circuit subunits 520-1 to 520-N and generate a control signal Ctrl based on the error detection results (e.g., error detection signals). According to one embodiment of the invention, the acquisition circuit 510 may be an OR tree circuit containing one or more OR gates, used to perform a logical OR operation on the error detection results (e.g., error detection signals) output by circuit subunits 520-1 to 520-N to generate the control signal Ctrl. For example, when any error detection signal contains a high level or an error flag, the level of the control signal Ctrl can also be set to a high level to indicate the duty cycle (or, in some embodiments, the duty cycle itself) of the target signal for control or adjustment.

[0058] Control circuit 530 is coupled to acquisition circuit 510 to adjust the duty cycle (or duty cycle) of the target signal according to control signal Ctrl. For example, when control circuit 530 detects that control signal Ctrl is set to a high voltage level (or that an error flag exists in control signal Ctrl), control circuit 530 adjusts the duty cycle of the target signal. In one embodiment of the invention, control circuit 530 may extend or increase the duty margin or duty cycle of the target signal because a high voltage level or error flag in control signal Ctrl indicates that the duty margin or duty cycle of the modulated target signal is insufficient.

[0059] Figure 6 An exemplary block diagram of a circuit for monitoring and controlling the duty cycle of a signal according to another embodiment of the present invention is shown. Circuit 600 may include at least a functional circuit 610, a duty cycle monitoring circuit 620, and a control circuit 630. In embodiments of the invention, circuit 600 is designed to monitor and control the duty cycle of a target signal, wherein the duty cycle monitoring circuit 620 is arranged to monitor the duty cycle of the target signal by monitoring the signal output from the functional circuit 610, and the control circuit 630 is arranged to control the duty cycle of the target signal (or, in some embodiments, the duty cycle itself) and provide the target signal to a delay chain 640 and subsequent digital circuit block 650. According to embodiments of the invention, the target signal may be a pulse signal comprising only one or at least one pulse, or it may be a clock signal pulse signal comprising multiple consecutive pulses.

[0060] Functional circuit 610 can receive a target signal from delay chain 640, which may be a delayed version of the original target signal output by control circuit 630, and is arranged to generate an output signal (e.g., a first output signal) in response to the target signal. Duty cycle monitoring circuit 620 may include modulation circuit 660, replication circuit 670, and error detection circuit 680. Modulation circuit 660 is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. Replication circuit 670 is configured to receive the modulated target signal and generate a second output signal in response to the modulated target signal. Error detection circuit 680 is coupled to functional circuit 610 and replication circuit 670 to receive the first output signal and the second output signal, and generate an error detection result based on the first output signal and the second output signal. It should be noted that circuit 600 has... Figure 2 The circuit 200 shown has a similar structure and function; therefore, a detailed description of circuit 600 can be found in [reference needed]. Figure 2 The description, in which the same number represents the same element.

[0061] and Figure 2 The difference between the embodiments shown is that, in Figure 6In the illustrated embodiment, circuit 600 may further include a delay circuit 615 coupled to replication circuit 670 for delaying the input data signal Data_in provided to replication circuit 670, and a delay circuit 617 coupled to the output of functional circuit 610 for delaying the first output signal generated by functional circuit 610. In embodiments of the present invention, the delay amounts applied by delay circuits 615 and 617 are adjustable, thus allowing further fine-tuning of the timing of the first and second output signals before they are provided to error detection circuit 680.

[0062] Figure 7 An exemplary circuit diagram of a modulation circuit according to an embodiment of the present invention is shown. In one embodiment of the invention, the modulation circuit 760 may include an inverter, a delay circuit, and a logic gate (e.g., an AND gate), wherein the inverter may be disposed in the delay circuit. The modulation circuit 760 may perform a logical operation, such as a logical AND operation, on a target signal CK1 and its inverted and delayed versions to generate a modulated target signal CK2, wherein the delay amount may be determined based on a reserved margin (or reserved tolerance) to be monitored. It should be noted that... Figure 7 This is merely an example circuit for modulation, and the invention is not limited thereto.

[0063] In summary, as described above, the pulse width of the modulated target signal CK2 generated by the modulation circuit is narrower than that of the target signal CK1, thus creating a more stringent condition for comparison for the replication circuit. In this way, by monitoring the duty cycle of the target signal and detecting operational differences between the functional circuit and the replication circuit—for example, detecting the difference between the output signals of the functional circuit and the replication circuit based on the same input signal—it is possible to detect whether an error caused by duty cycle degradation is imminent or likely to occur in the functional circuit. When an error caused by duty cycle degradation is detected to be imminent or likely to occur, the control circuit will adjust the duty margin or duty cycle in advance to avoid functional circuit malfunction and / or prevent the error from actually occurring.

[0064] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A duty cycle monitoring circuit, coupled to a functional circuit, characterized in that, The functional circuit generates a first output signal in response to the target signal. The duty cycle monitoring circuit includes: A modulation circuit is used to receive the target signal and modulate the target signal to generate a modulated target signal; A replication circuit is configured to receive the modulated target signal and generate a second output signal in response to the modulated target signal; and An error detection circuit, coupled to the functional circuit and the replication circuit, is used to receive the first output signal and the second output signal, and generate an error detection result based on the first output signal and the second output signal; The replication circuit is further configured to receive an input data signal and perform data sampling on the input data signal in response to the modulation target signal to generate the second output signal, wherein the error detection circuit is used to compare the difference between the first output signal and the second output signal to generate an error detection result.

2. The duty cycle monitoring circuit as described in claim 1, characterized in that, This replication circuit is a replication of the functional circuit.

3. The duty cycle monitoring circuit as described in claim 1, characterized in that, The target signal is a pulse signal or a clock signal.

4. The duty cycle monitoring circuit as described in claim 1, characterized in that, The modulation circuit modulates the target signal by adjusting the pulse width of the target signal.

5. The duty cycle monitoring circuit as described in claim 4, characterized in that, The pulse width of the modulated target signal is narrower than the pulse width of the target signal.

6. The duty cycle monitoring circuit as described in claim 1, characterized in that, It also includes a control circuit coupled to the error detection circuit, used to adjust the duty cycle of the target signal based on the error detection result.

7. A method for monitoring the duty cycle of a target signal, characterized in that, include: The target signal is provided to the functional circuit so that the functional circuit generates a first output signal in response to the target signal; The target signal is modulated to generate a modulated target signal, and the modulated target signal is provided to the replication circuit so that the replication circuit generates a second output signal in response to the modulated target signal, wherein the replication circuit is a copy of the functional circuit; as well as An error detection result is generated based on the first output signal and the second output signal; The replication circuit is further configured to receive an input data signal and perform data sampling on the input data signal in response to the modulation target signal to generate the second output signal, wherein the error detection circuit is used to compare the difference between the first output signal and the second output signal to generate an error detection result.

8. The method as described in claim 7, characterized in that, The step of generating the error detection result based on the first output signal and the second output signal further includes: The error detection result is generated by comparing the difference between the first output signal and the second output signal. The first output signal is the result of data sampling performed by the functional circuit in response to the target signal, while the second output signal is the result of data sampling performed by the replication circuit in response to the modulated target signal.

9. A duty cycle circuit for monitoring and controlling target signals, characterized in that, include: Multiple circuit subunits, each circuit subunit including: a functional circuit for receiving the target signal and generating a first output signal in response to the target signal; and a duty cycle monitoring circuit coupled to the functional circuit for monitoring the duty cycle of the target signal according to the first output signal to generate an error detection result; A data acquisition circuit, coupled to this circuit subunit, is used to acquire the error detection result and generate a control signal based on the error detection result; and A control circuit, coupled to the acquisition circuit, is used to adjust the duty cycle of the target signal according to the control signal; The duty cycle monitoring circuit also includes: A modulation circuit is used to receive the target signal and modulate the target signal to generate a modulated target signal; A replication circuit is configured to receive the modulated target signal and generate a second output signal in response to the modulated target signal; and An error detection circuit, coupled to the functional circuit and the replication circuit, is used to receive the first output signal and the second output signal, and generate the error detection result based on the first output signal and the second output signal; The replication circuit is further configured to receive an input data signal and perform data sampling on the input data signal in response to the modulation target signal to generate the second output signal, wherein the error detection circuit is used to compare the difference between the first output signal and the second output signal to generate an error detection result.

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