Performing scrambling and / or descrambling on a parallel computing architecture

Abstract

Devices, systems, and techniques for descrambling or scrambling data use a graphics processing unit (GPU) to perform the descrambling. For example, in at least one embodiment, the generation of the descrambling sequence is distributed among GPU threads for parallel computation of the descrambling sequence and / or for descrambling distributed among the GPU threads.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 559,442, filed September 3, 2019, entitled “Performing scrambling and / or descrambling on parallel computing architectures,” the entire contents of which are incorporated herein by reference and used for all purposes. Technical Field

[0003] This disclosure relates to at least one embodiment for performing scrambling and / or descrambling of communication data, and more specifically, at least one embodiment relates to using a parallel computing architecture in wireless communication and processing to perform scrambling and / or descrambling of communication data. Background Technology

[0004] In some communication protocols, data is received and processed by a receiver pipeline, and the steps in the receiver pipeline may involve applying a sequence to the received data, which either descrambles data scrambled with the corresponding sequence or scrambles unscrambled data. In many communication applications, descrambling is time-consuming, especially for current and future applications that rely on increasing communication speed. Attached Figure Description

[0005] Figure 1 Data reception at the physical layer (PHY) of a mobile device network is illustrated according to one or more embodiments;

[0006] Figure 2A The operation of generating a segment of the first descrambled sequence using a many-to-one linear feedback shift register (LFSR) is illustrated according to one or more embodiments;

[0007] Figure 2B The operation of generating segments for generating a second descrambling sequence using a many-to-one LFSR according to one or more embodiments is illustrated;

[0008] Figure 3A The generation of a one-to-many LFSR according to one or more embodiments is illustrated. Figure 2A The operation of generating the first descrambled sequence shown;

[0009] Figure 3B The generation of a one-to-many LFSR according to one or more embodiments is illustrated. Figure 2B The operation of generating the second descrambled sequence shown;

[0010] Figure 4 The operation of generating segments of a specific descrambling sequence using a one-to-many LFSR according to one or more embodiments is illustrated, wherein the LFSR advances a predetermined number of loops based on thread index and / or thread bundle index;

[0011] Figure 5 The operation of generating segments for generating generalized descrambling sequences using multiple one-to-many LFSRs according to one or more embodiments is illustrated, wherein the LFSRs advance a predetermined number of loops based on thread indices and / or thread bundle indices;

[0012] Figure 6 Elements of a GPU-based scrambling / descrambling processing unit, which can be used for GPU-based scrambling / descrambling according to one or more embodiments, are shown.

[0013] Figure 7 The operation of generating parallel descrambling sequences using GPU threads is illustrated according to one or more embodiments;

[0014] Figure 8 Parallelized scrambling / descrambling operations using GPU warps are illustrated according to one or more embodiments;

[0015] Figure 9 This is a flowchart of the steps of a parallel descrambling sequence generation method according to one or more embodiments;

[0016] Figure 10 This is a flowchart of the steps of a parallelized scrambling / descrambling method according to one or more embodiments;

[0017] Figure 11A The inference and / or training logic according to at least one embodiment is illustrated;

[0018] Figure 11B The inference and / or training logic according to at least one embodiment is illustrated;

[0019] Figure 12 An example data center system according to at least one embodiment is shown;

[0020] Figure 13A An example of an autonomous vehicle according to at least one embodiment is shown;

[0021] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and field of view for autonomous vehicles;

[0022] Figure 13C It is shown that according to at least one embodiment Figure 13A A block diagram of an example system architecture for an autonomous vehicle;

[0023] Figure 13D This illustrates a method for using one or more cloud-based servers according to at least one embodiment. Figure 13A A diagram of a system for communication between autonomous vehicles;

[0024] Figure 14 This is a block diagram illustrating a computer system according to at least one embodiment;

[0025] Figure 15 This is a block diagram illustrating a computer system according to at least one embodiment;

[0026] Figure 16 A computer system according to at least one embodiment is shown;

[0027] Figure 17 A computer system according to at least one embodiment is shown;

[0028] Figure 18 An exemplary integrated circuit and associated graphics processor, which can be manufactured using one or more IP cores according to at least one embodiment, are shown;

[0029] Figure 19A A computer system according to at least one embodiment is shown;

[0030] Figure 19B A computer system according to at least one embodiment is shown;

[0031] Figure 19C A computer system according to at least one embodiment is shown;

[0032] Figure 19D A computer system according to at least one embodiment is shown;

[0033] Figure 19E A computer system according to at least one embodiment is shown;

[0034] Figure 19F A computer system according to at least one embodiment is shown;

[0035] Figure 20A and 20B An exemplary integrated circuit and associated graphics processor, which can be manufactured using one or more IP cores according to at least one embodiment, are shown;

[0036] Figure 21A and Figure 21B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0037] Figure 22 A computer system according to at least one embodiment is shown;

[0038] Figure 23A A parallel processor according to at least one embodiment is shown;

[0039] Figure 23B A partitioning unit according to at least one embodiment is shown;

[0040] Figure 23C A processing cluster according to at least one embodiment is shown;

[0041] Figure 23D A graphics multiprocessor according to at least one embodiment is shown;

[0042] Figure 24 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0043] Figure 25 A graphics processor according to at least one embodiment is shown;

[0044] Figure 26 This is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0045] Figure 27 A deep learning application processor according to at least one embodiment is shown;

[0046] Figure 28 This is a block diagram illustrating an example neuromorphic processor according to at least one embodiment;

[0047] Figure 29 and Figure 30 At least a portion of a graphics processor according to at least one embodiment is shown;

[0048] Figure 31 It is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0049] Figure 32A and Figure 32B The thread execution logic according to at least one embodiment is shown;

[0050] Figure 33 A parallel processing unit (“PPU”) according to at least one embodiment is shown.

[0051] Figure 34 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0052] Figure 35 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown; and

[0053] Figure 36 A streaming multiprocessor according to at least one embodiment is shown. Detailed Implementation

[0054] For many communication protocols, such as 5G and LTE protocols used with mobile communications, data is processed at the receiver and / or transmitter according to the specifications of these protocols. In at least one embodiment, one such operation is to descramble the received data. In at least one embodiment, if the data stream is scrambled in some way before being transmitted, it can be descrambled at reception using the reverse process of the scrambling process. In at least one embodiment, where scrambling involves performing an XOR operation on the bits of the input data sequence and the corresponding bits of the scrambled sequence, descrambling can be accomplished by performing the XOR operation again to return to the original input data sequence. In at least one embodiment, the example of descrambling described herein can therefore be used for scrambling.

[0055] In at least one embodiment, the descrambling sequence may be a pseudo-random bit sequence generated using a linear feedback shift register (LFSR). In at least one embodiment, as the LFSR cycles through its state, the LFSR output is a bit sequence as a function of its feedback connections and its initial state.

[0056] In at least one embodiment, for an LFSR referred to as a many-to-one LFSR or a Fibonacci LFSR, the feedback connection or tap may have an input to such an LFSR, which is an XOR of the values ​​of several shift register stages of the LFSR. In at least one embodiment, a given future state of the Fibonacci LFSR can be obtained by loading the shift register stages of the Fibonacci LFSR with an initial state and then looping through the Fibonacci LFSR, wherein each loop involves shifting each stage to the next stage in the Fibonacci LFSR, outputting the LFSR output from the last stage of the Fibonacci LFSR, and loading the first stage of the Fibonacci LFSR with an XOR of the values ​​in the shift register stages corresponding to these taps. In at least one embodiment, the tap pattern of the LFSR can be represented as the generator polynomial of the LFSR.

[0057] A feedback tap of an LFSR, referred to as a one-to-many LFSR or a Galois LFSR, may have the output of the Galois LFSR as the input to the first stage of that Galois LFSR, and its output XORed with the value, shifting between the shift register stages of the Galois LFSR. In at least one embodiment, a given future state of the Galois LFSR can be obtained by loading a shift register stage of the Galois LFSR with an initial state, then looping the Galois LFSR, shifting each stage to the next stage in the Galois LFSR, and outputting the LFSR output from the last stage. In at least one embodiment, the tap pattern in which the stage values ​​are XORed with their outputs can be represented as the generator polynomial of the LFSR.

[0058] In at least one embodiment, the descrambling sequence defined by the generator polynomial and the Fibonacci LFSR is generated by multiple threads of a graphics processing unit (GPU) by operating each thread to generate a descrambling segment of a larger descrambling sequence. In at least one embodiment, the descrambling sequence is defined by multiple LFSRs. In at least one embodiment, the descrambling sequence is defined as the XOR of the outputs of a first LFSR and the outputs of a second LFSR, wherein the first LFSR is tapped according to a first generator polynomial and begins at an initial state of the first LFSR, and wherein the second LFSR is tapped according to a second generator polynomial and begins at an initial state of the second LFSR.

[0059] In at least one embodiment, for a specific protocol and communication system, the first Fibonacci LFSR may have 31 levels, F1(x) = x 31 +x 3 The first Fibonacci LFSR initial state is a constant sum of the first generator polynomials, F10(x) = {k1(30)=...=k1(1)=0, k1(0)=1}, where k1(i) refers to the initial value of the i-th level. In at least one embodiment, for that particular protocol and communication system, the second Fibonacci LFSR may also have 31 levels, F2(x)=x 31 +x 3 +x 2 The second generator polynomial +x+1 and the second LFSR initial state are seed values, which are functions of values ​​associated with a specific data stream. In at least one embodiment, the seed value associated with a specific data stream is calculated based on a user identifier and a base station identifier, in which case the seed value may be specific to a particular connection. In at least one embodiment, the descrambling sequence is a bitwise XOR of the first Fibonacci LFSR output and the second Fibonacci LFSR output after a number of loops. In at least one embodiment, descrambling occurs at a base station, such as a cellular network base station, when data is received from a user's mobile device in a cellular network.

[0060] In at least one embodiment, descrambling sequences derived from one or more Fibonacci LFSRs are generated using a Galois LFSR. Multiple threads of the GPU are used, with each thread running on one or more Galois LFSRs that proceed through multiple loops, the number of loops varying for different threads. In at least one embodiment, by parallelizing the generation of descrambling sequences, descrambling sequences can be generated faster and low latency can be provided for scrambling and descrambling. The GPU threads are used as part of a software-defined radio access network (RAN) interface.

[0061] In at least one embodiment, a GPU thread descrambles a bit of an input data sequence, which can be represented as a soft-bit sequence of floating-point numbers stored as a scrambling block of the physical layer (PHY) of the network pipeline. In at least one embodiment, each bit of the input data sequence has a position, and each bit of the descrambling sequence has a corresponding position, wherein a "0" at a specific position in the descrambling sequence may indicate that the soft bits of the input data sequence will pass unchanged, while a "1" at that specific position in the descrambling sequence may indicate that the soft bits of the input data sequence will be passed by inversion or sign flipping. In at least one embodiment, depending on how the input data value is stored, the input data value can be converted from a storage format unsuitable for a sign bit to a storage format in which the floating-point sign is represented by a single bit, such as a sign bit followed by an exponent value, followed by a mantissa. In at least one embodiment, the sign of the input data value can be flipped in other ways.

[0062] In at least one embodiment, GPU threads can be used to generate descrambling sequences, wherein each thread generates descrambling segments in parallel, such as highly parallel operations with independent thread operations, and GPU threads can be used to scramble / descramble input data sequences using parallel descrambling sequences, such as highly parallel operations with independent thread operations.

[0063] In at least one embodiment, the LFSR can be brought into a "fast-forward" state using parallel operations by converting from a Fibonacci feedback mode or a set of taps to an equivalent Galois feedback mode. In at least one embodiment, the "fast-forward" state of the LFSR can be achieved by initializing the LFSR with an initial LFSR state, looping the LFSR for a number of cycles, and then obtaining the output from the LFSR while undergoing additional loops. In at least one embodiment, the fast-forwarding of the LFSR is performed by using a Galois LFSR and loading a value as the initial LFSR state, which is the result of multiplying the initial state and a monomial having a number of fast-forwarded loops modulo the generator polynomial. In at least one embodiment, if the protocol expects a descrambled sequence of the outputs of one or more Fibonacci LFSRs, a conversion to one or more Galois LFSRs can be performed, and a back-conversion can be performed if necessary.

[0064] In at least one embodiment, each monomial that may be used can be pre-computed modulo the generator polynomial and stored in GPU memory. In at least one embodiment, where a thread operates on one byte at a time, the pre-computed modulo the generator polynomial can be performed on powers of eight.

[0065] Figure 1 Data reception at the physical layer (PHY) of a mobile device network is illustrated according to one or more embodiments. In at least one embodiment, network system 100 may provide multiple mobile devices 102(1)-(4) connected to base station 104(1)-(4), wherein the received signal is demodulated by demodulator 106(1)-(4) and processed by various other signal processing elements 108, such as channel estimation, multiple-input multiple-output signal processing, transform decoding, and constellation mapping. In at least one embodiment, the output of signal processing element 108 may resolve the signal into multiple paths. In at least one embodiment, one or more descramblers 110(1)-(4) receive an input data sequence and descramble the input data sequence according to a descrambler sequence. In at least one embodiment, descrambler 110 outputs the descrambled input data sequence to other elements 112(1)-(4), which may include a rate matcher, a low-density parity-check (LDPC) decoder, and a cyclic redundancy check (CRC) unit. In at least one embodiment, when the network system 100 provides real-time data transmission or otherwise requires fast processing, using a GPU to perform descrambling and the parallelization available to the GPU can provide fast descrambling.

[0066] In at least one embodiment, although Figure 1This illustration demonstrates descrambling within the context of a base station processing signals received from a user mobile device over a cellular network; however, other contexts may exist, such as the user mobile device descrambling signals received from the base station. In at least one embodiment, the base station may be programmed to the expectation that a given user mobile device may be reused within a finite time period. In at least one embodiment, the user mobile device may remain within the base station's range for hours or days, in which case the base station may cache the descrambling sequence once a user- and base station-specific descrambling sequence is calculated, provided that the descrambling sequence is expected to be used and will not change.

[0067] Figure 2A The operation of generating a segment using a many-to-one LFSR 202 to generate a first descrambled sequence is illustrated according to one or more embodiments. In at least one embodiment, the many-to-one LFSR has 31 levels, and when an initial state is loaded, it can cycle through the states and output a pseudo-random sequence. In at least one embodiment, the initial state has the least significant bit loaded into the last level of the many-to-one LFSR 202 and the most significant bit loaded into the first level of the many-to-one LFSR 202. In at least one embodiment, the many-to-one LFSR 202 cycles through values ​​from each level to the next, loads the first level with an XOR of the tap level, according to the generator polynomial taps of the many-to-one LFSR 202, and outputs the level value from the last level of the many-to-one LFSR 202. In at least one embodiment, the initial state of the many-to-one LFSR 202 is a constant.

[0068] Figure 2B The operation of generating a segment using a many-to-one LFSR 204 to generate a second descrambled sequence is illustrated according to one or more embodiments. In at least one embodiment, the many-to-one LFSR has 31 levels, and when an initial state is loaded, it can cycle through the states and output a pseudo-random sequence. In at least one embodiment, the initial state has the least significant bit loaded into the last level of the many-to-one LFSR 204 and the most significant bit loaded into the first level of the many-to-one LFSR 204. In at least one embodiment, the many-to-one LFSR 204 is cycled to transfer values ​​from each level to the next level, the first level is loaded with an XOR of the tap level, taps are generated according to the generator polynomial of the many-to-one LFSR 204, and the level value is output from the last level of the many-to-one LFSR 204.

[0069] In at least one embodiment, the initial state of the many-to-one LFSR 204 is a seed value derived from the user identifier and the base station identifier. In at least one embodiment, the outputs of the many-to-one LFSR 202 and the many-to-one LFSR 204 can be combined.

[0070] Figure 3AThe generation of one-to-many LFSRs according to one or more embodiments is illustrated. Figure 2A The operation of the generation segment of the first descrambled sequence is shown. As illustrated, in at least one embodiment, the one-to-many LFSR 302 has 31 stages and can be loaded with an initial state, wherein the most significant bit is loaded into the last stage of the one-to-many LFSR 302 and the least significant bit is loaded into the first stage of the many-to-one LFSR 204. In at least one embodiment, the cyclic one-to-many LFSR 302 transfers values ​​from each stage to the next stage, outputs stage values ​​from the last stage of the one-to-many LFSR 302, and performs an XOR operation on the shifted values ​​according to the tap pattern, based on the generator polynomial taps of the one-to-many LFSR 302.

[0071] In at least one embodiment, the one-to-many LFSR 302 can output with Figure 2A The pseudo-random sequence shown is similar to the many-to-one LFSR 202, with the initial state of the many-to-one LFSR 202 being modified appropriately by bit reversal and shifting 31 cycles.

[0072] Figure 3B This illustrates the use of a one-to-many LFSR 304 to generate, according to one or more embodiments. Figure 2B The operation of the generation segment of the first descrambled sequence is shown. In at least one embodiment, as shown, the one-to-many LFSR 304 also has 31 levels and can be loaded with an initial state, wherein the most significant bit is loaded into the last level of the one-to-many LFSR 304 and the least significant bit is loaded into the first level of the many-to-one LFSR 204. In at least one embodiment, the cyclic one-to-many LFSR 304 transfers values ​​from each level to the next level, outputs the level value from the last level of the one-to-many LFSR 304, and performs an XOR operation on the shifted values ​​according to the tap pattern, based on the generator polynomial taps of the one-to-many LFSR 304.

[0073] In at least one embodiment, the one-to-many LFSR 304 can output with Figure 2B The many-to-one LFSR 204 shown is a pseudo-random sequence in which the initial state of the many-to-one LFSR 204 is appropriately modified by bit reversal and shifting 31 cycles. In at least one embodiment, the one-to-many LFSR 302 and / or one-to-many LFSR 304 can be implemented in multiple threads, where different threads operate on different segments of the descrambled sequence using the one-to-many LFSR, wherein each thread's LFSR is fast forwarded to a set of cycles corresponding to the position of the generated segment in the descrambled sequence.

[0074] Figure 4Operations are illustrated for generating segments of a specific descrambling sequence using a one-to-many LFSR according to one or more embodiments, the LFSR advancing a predetermined number of loops based on a thread index and / or a thread bundle index. In at least one embodiment, descrambler 402 includes two one-to-many LFSRs 404(1)-(2), the outputs of which are applied to corresponding load registers 406(1)-(2) of many-to-one LFSRs 408(1)-(2), and output to an XOR element 410 to form a descrambler output. In at least one embodiment, the descrambler output can be used to scramble data.

[0075] In at least one embodiment, a one-to-many LFSR is used, whose state can be set to the state they would have if they were loaded with an initial state and then looped through a predetermined number of cycles, but without requiring a looping process. In at least one embodiment, a one-to-many LFSR 404(1) is loaded with state x. j G10(x)%P(x) and one-to-many LFSR404(2) loaded with state x j G20(x)%P(x), where G10(x) is the initial state of the first LFSR, G20(x) is the initial state of the second LFSR, and x j Let P(x) be a j-th degree monomial and P(x) be a generator polynomial. In at least one embodiment, the output of a one-to-many LFSR of such a state is loaded, fed into a many-to-one LFSR, and then looped as needed to obtain the output, which can be used to achieve an effect similar to looping a many-to-one LFSR in a large number of loops.

[0076] In at least one embodiment, the descrambler 402 is implemented as a thread of the GPU, and multiple descramblers can run in parallel with the thread's execution unit, the thread's local memory, and / or the thread's load / store unit, operations for reading and / or writing to shared memory shared by the thread and / or global memory available to the GPU. In at least one embodiment, different descramblers each use the same set of LFSR operations, but they are initialized as different parts of the descrambler sequence, thereby allowing more descrambler sequences to be covered in parallel. In at least one embodiment, the order j can be a function of the thread and / or meridian. In at least one embodiment, for example, the descrambler sequence comprises a 1024-bit pseudo-random sequence and the GPU allocates 32 threads to generate the descrambler sequence, so each thread will operate on a 32-bit descrambler segment that is the descrambler sequence. In at least one embodiment, where each thread operates on a 32-bit descrambler segment, j can be equal to 32 times the thread position, where the thread positions are numbered from 0 to 31. In at least one embodiment, for example, the LFSR 404(1) of the thread at thread position 0 will have a first LFSR initial state of G10(x)%P(x), and the LFSR 404(2) of that thread will have a second LFSR initial state of G20(x)%P(x), while the LFSR 404(1) of the thread at thread position 1 will have x 32 The first LFSR initial state of G10(x)%P(x) and the LFSR 404(2) of this thread will have x 32 The second LFSR initial state of G20(x)%P(x). In at least one embodiment, x 32 %P(x), x 64 %P(x), x 96 The values ​​of %P(x), etc., can be pre-computed and stored in shared memory or global memory because they may be constant for a given protocol.

[0077] In at least one embodiment, G10(x) can correspond to F1'0(x)P(x) / x 31 F1'0(x) is the bit-reversed form of F10(x), where F10(x) is the initial state of the corresponding many-to-one LFSR that generates a portion of the descrambler sequence. In at least one embodiment, F10(x) can be a constant in which the least significant bit is 1 and all other bits are zero. In at least one embodiment, F10(x) is a constant, x 32i The value of G10(x)%P(x) can be pre-calculated and stored in shared memory or global memory. In at least one embodiment, G20(x) can correspond to F2'0(x)P(x) / x 31F2'0(x) is the bit-reversed form of F20(x), where F20(x) is the initial state of the corresponding many-to-one LFSR, which generates a partial descrambler sequence. In at least one embodiment, F20(x) can be a seed value calculated based on the user identifier and the base station identifier. In at least one embodiment, once the seed value is known and stored in shared memory or global memory, x can be calculated. 32i The value of G20(x)%P(x). In at least one embodiment, in a particular implementation, the initial value of the LFSR can begin after a predetermined number of cycles, such as 1600 cycles, and, using the corresponding one-to-many LFSR feedback pattern, can be achieved by multiplying the initial state of the LFSR by x. 1600 The process proceeds for 1600 cycles by taking the modulus of P(x). In at least one embodiment, different protocols may be supported, where the number of progression cycles is not 1600 and / or where F10(x) is not a constant.

[0078] In at least one embodiment, Figure 4 In the descrambler 402 shown, LFSR 404(1) has a corresponding generator polynomial G1(x)=x 31 +x 3 +1 feedback mode and LFSR 404(2) has a corresponding generator polynomial G2(x)=x 31 +x 3 +x 2 The feedback pattern is +x+1. In at least one embodiment, another set of feedback patterns can be used. In at least one embodiment, the output of this one-to-many LFSR is then fed to a load register, which provides an initial state for the many-to-one LFSR, and can then be looped to generate the desired output.

[0079] Figure 5 Operations are illustrated for generating segments of a generalized descrambling sequence using multiple one-to-many LFSRs that advance a predetermined number of loops based on thread indices and / or thread bundle indices, according to one or more embodiments. In at least one embodiment, descrambler 502 includes two one-to-many LFSRs 504 (1)-(2) whose outputs are applied to corresponding load registers 506 (1)-(2) of many-to-one LFSRs 508 (1)-(2), whose outputs are XORed with element 510 to form a descrambler output. In at least one embodiment, the descrambler output can be used to scramble data.

[0080] In at least one embodiment, a one-to-many LFSR is used, whose states can be set such that if they are loaded with an initial state, they are then looped through a predetermined number of loops according to their respective feedback patterns, these loops being defined by the taps of these LFSRs, but no looping process is required. In at least one embodiment, a one-to-many LFSR is used and loaded into a state corresponding to the result of a polynomial multiplication of the LFSR initial state with an order corresponding to a predetermined number of monomials of the loop and modulo the generating polynomial. In at least one embodiment, the initial state and tap patterns can be different for different LFSRs. In at least one embodiment, since the LFSR can be fast-forwarded by multiplying monomials by polynomials, multiple such LFSRs can be deployed on multiple threads of the GPU so that the LFSR outputs can be generated in parallel, rather than serially looping the LFSRs through each of their sequential states. In at least one embodiment, the order j can be a function of the number or position of threads and / or the number or position of thread bundles. In at least one embodiment, loading the output of a one-to-many LFSR with such a state, feeding it into a many-to-one LFSR, and then looping as needed to obtain the output can be used to achieve an effect similar to looping a many-to-one LFSR in a large number of loops.

[0081] In at least one embodiment, the descrambler 502 can be implemented as a thread of the GPU, and multiple descramblers can operate in parallel with the thread's execution unit, the thread's local memory, and / or the thread's load / store unit, shared memory for reading and / or writing to shared memory and / or global memory available to the GPU. In at least one embodiment, the output of such a many-to-one LFSR is then fed to a load register, which provides an initial state for the many-to-one LFSR, and can then be looped to generate the desired output.

[0082] Figure 6Elements of a GPU-based descrambler 600 according to one or more embodiments are shown, including a plurality of GPU-based scrambling / descrambling processing units 602(1)-(N) that can be used for GPU-based scrambling / descrambling. In at least one embodiment, N is the number of threads used for scrambling / descrambling. In at least one embodiment, the GPU-based scrambling / descrambling processing unit 602(1), similar to other GPU-based scrambling / descrambling processing units shown, includes a load / store unit 604, an execution core 606, a register file 608, an instruction cache 610, and access to shared memory 612 and global memory 614. In at least one embodiment, in the operation described herein, the GPU-based scrambling / descrambling processing unit 602(1) can read in a plurality of input data values, load data into the register file 608, access those input data values ​​using the execution core 606, and return thread output to the register file 608. In at least one embodiment, the GPU-based scrambling / descrambling processing unit scrambles or descrambles input data values ​​by bit-flipping the sign of the input data values ​​based on the descrambling sequence, and operates on multiple input data values ​​in parallel. In at least one embodiment, the GPU-based scrambling / descrambling processing unit generates a descrambling sequence and operates on multiple descrambling segments of the descrambling sequence in parallel.

[0083] Figure 7 The diagram illustrates operations for generating parallel descrambling sequences using GPU threads, according to one or more embodiments. In at least one embodiment, such as Figure 7 As shown in thread 702, sequence generation is performed by the Tth thread out of K threads. In at least one embodiment, the seed is provided as a plurality of bytes 706(1)-(4) and stored in the local memory 704 of thread 702, where it is shown as C. init (0) to C init (30) and one bit of byte 706(4) is set to zero. In at least one embodiment, other seed sizes may be used. In at least one embodiment, the seed value used corresponds to a 5G protocol or LTE protocol value, where one seed value is a non-zero constant and another seed value is based on the user identifier and the cellular base station identifier. In at least one embodiment, execution unit 706 performs actions similar to Figure 4 The operation shown initializes the first LFSR to x. 1600+32T G10(x)%P(x), the second LFSR is initialized to x. 1600+32TG20(x)%P(x) is calculated, and the output is stored in shared memory 712. In at least one embodiment, the value of the monomial can be pre-computed and stored in global memory 710. In at least one embodiment, thread 702 performs a four-way shift and XOR operation to generate 32 outputs in eight cycles of the LFSR, a serial shift through 32 cycles, or some other variation. In at least one embodiment, the effect of the operation of execution unit 706 of thread 702 is to generate a generator polynomial and descrambler segments from the various seed values, which form a descrambler sequence that can be stored in shared memory across multiple threads. In at least one embodiment, if execution unit 706 operates serially, then X is stored in global memory 710. 1600+32T That might be enough.

[0084] Figure 8 Parallelized scrambling / descrambling operations using a GPU warp are illustrated according to one or more embodiments. In at least one embodiment, the descrambling warp 802 includes 32 threads, each receiving an input data value in 32-bit soft-bit form, reading corresponding bits of a descrambler sequence from GPU shared memory to reach a bit selector for each thread. In at least one embodiment, each thread may use an execution unit to perform an XOR operation on the sign bit of the bit selector and the soft-bit value, and insert the result as a new sign bit. In at least one embodiment, the descrambling process involves changing the sign of the soft bit if the corresponding bit in the descrambling sequence is 1 and leaving it unchanged if the corresponding bit is zero. In at least one embodiment, the descrambling sequence is used for both scrambling and descrambling, with the descrambling sequence resulting in descrambling to counteract the effects of scrambling.

[0085] Figure 9 This is a flowchart of the steps of a parallel descrambling sequence generation method according to one or more embodiments. In at least one embodiment, the scrambling / descrambling sequence generation process includes obtaining a seed bit (step 901) and obtaining a generator polynomial for a many-to-one linear feedback shift register (Fibonacci LFSR) (step 902). In at least one embodiment, the process then converts the Fibonacci LFSR to a one-to-many LFSR (Galois LFSR) (step 903) and converts the Fibonacci LFSR initial state to a one-to-many LFSR initial state (Galois initial state) (step 904). In at least one embodiment, the process instantiates a GPU warp with 32 threads (step 905) and passes the Galois initial state G0(x) to each thread (step 906). In at least one embodiment, each thread can compute x. jG0(x) (j=0, 1, ..., 31) (step 907) and each thread loops its LFSR 32 times to derive a 32-bit LFSR sequence (step 908). In at least one embodiment, each thread stores its sequence result in shared memory, 32 bits per thread, for a total of 32 32-bit words in the shared memory (step 909) to complete the process shown.

[0086] Figure 10 This is a flowchart of the steps of a parallelized scrambling / descrambling method according to one or more embodiments. In at least one embodiment, the scrambling / descrambling process using the GPU begins by instantiating 32 GPU warps, each with 32 threads (step 1001). In at least one embodiment, each warp reads a 32-bit word of a stored sequence from shared memory (step 1002), and each thread of the warp extracts one bit from that thread's 32-bit word (step 1003). In at least one embodiment, each thread reads a floating-point value representing either a soft bit for descrambling or a soft or hard bit for scrambling (step 1004). In at least one embodiment, each thread flips the sign bit of its soft / hard bits based on the bit extracted from the stored sequence (step 1005) and outputs the result (step 1006).

[0087] Figure 11A Inference and / or training logic 1115 is illustrated for performing inference and / or training operations associated with one or more embodiments. This is combined with... Figure 11A And / or 11B provides details about the reasoning and / or training logic 1115.

[0088] In at least one embodiment, the inference and / or training logic 1115 may include, but is not limited to, code and / or data storage 1101 for storing forward and / or output weights and / or input / output data, and / or other parameters configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, the training logic 1115 may include or be coupled to code and / or data storage 1101 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 1101 stores the weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 1101 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0089] In at least one embodiment, any portion of the data storage 1101 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the data storage 1101 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the data storage 1101 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0090] In at least one embodiment, the inference and / or training logic 1115 may include, but is not limited to, code and / or data storage 1105 to store backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, the code and / or data storage 1105 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 1115 may include or be coupled to code and / or data storage 1105 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of the code and / or data storage 1105 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 1105 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 1105 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 1105 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0091] In at least one embodiment, data storage 1101 and data storage 1105 may be separate storage structures. In at least one embodiment, data storage 1101 and data storage 1105 may be the same storage structure. In at least one embodiment, data storage 1101 and data storage 1105 may be partially the same storage structure and partially independent storage structures. In at least one embodiment, any portion of data storage 1101 and data storage 1105 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0092] In at least one embodiment, the inference and / or training logic 1115 may include, but is not limited to, one or more arithmetic logic units (“ALU(s)”) 1110, including integer and / or floating-point units, performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graphical code), the results of which may produce activations (e.g., output values ​​of layers or neurons in a neural network) stored in activation memory 1120, which are functions of input / output and / or weight parameter data stored in code and / or data memory 1101 and / or code and / or data memory 1105. In at least one embodiment, the activation stored in activation memory 1120 is generated based on linear algebra and / or matrix-based mathematics performed by ALU 1110 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 1105 and / or data 1101 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, wherein any or all of them may be stored in code and / or data memory 1105 or code and / or data memory 1101 or another memory on or off the chip.

[0093] In at least one embodiment, ALU(s) 1110 is included within one or more processors or other hardware logic devices or circuits, or ALU(s) 1110 may be outside of a processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, ALU 1110 may be included within an execution unit of a processor or otherwise included within an ALU library accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed-function unit, etc.). In at least one embodiment, data storage 1101, data storage 1105, and activation storage 1120 may be on the same processor or other hardware logic device or circuit, or they may be in different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage device 1120 may be included together with other on-chip or off-chip data storage devices, including the processor's L1, L2, or L3 cache or system memory. Furthermore, in at least one embodiment, the inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be acquired and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0094] In at least one embodiment, the active memory 1120 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 1120 may be wholly or partially within or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 1120 is inside or outside the processor, for example, or composed of DRAM, SRAM, flash memory, or some other memory type, may depend on the available on-chip and off-chip memory, the latency requirements of the training and / or inference functions being performed, the data batch size used in neural network inference and / or training, or some combination of these factors. In at least one embodiment, Figure 11A The inference and / or training logic 1115 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor from Intel Corporation (e.g., “Lake Crest”). In at least one embodiment, Figure 11A The inference and / or training logic 1115 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate array (“FPGA”).

[0095] Figure 11B An inference and / or training logic 1115 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 1115 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 11B The inference and / or training logic 1115 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® processor (e.g., “Lake Crest”) from Intel Corp. In at least one embodiment, Figure 11BThe inference and / or training logic 1115 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 1115 includes, but is not limited to, code and / or data storage 1101 and code and / or data storage 1105, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 11B In at least one embodiment shown, each of code and / or data storage 1101 and code and / or data storage 1105 is associated with dedicated computing resources (e.g., computing hardware 1102 and computing hardware 1106), respectively. In at least one embodiment, each of computing hardware 1102 and computing hardware 1106 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) only on the information stored in code and / or data storage 1101 and code and / or data storage 1105, respectively, and the results of the function execution are stored in activation memory 1120.

[0096] In at least one embodiment, each of the data stores 1101 and 1105 and the corresponding computing hardware 1102 and 1106 corresponds to a different layer of the neural network, such that activations obtained from one “store / computation pair 1101 / 1102” of the data store 1101 and computing hardware 1102 are provided as inputs to the next “store / computation pair 1105 / 1106” of the data store 1105 and computing hardware 1106, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 1101 / 1102 and 1105 / 1106 may correspond to more than one neural network layer. In at least one embodiment, additional store / computation pairs (not shown) may be included in the inference and / or training logic 1115 following or paralleling the store / computation pairs 1101 / 1102 and 1105 / 1106.

[0097] Data Center

[0098] Figure 12 An example data center 1200 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 1200 includes a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0099] In at least one embodiment, such as Figure 12As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, packet computing resources 1214, and node computing resources (“nodes CR”) 1216(1)-1216(N), where “N” represents any integer, a positive integer. In at least one embodiment, nodes CR 1216(1)-1216(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 1216(1)-1216(N) may be servers having one or more of the aforementioned computing resources.

[0100] In at least one embodiment, the grouped computing resource 1214 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographical locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resource 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0101] In at least one embodiment, resource coordinator 1212 may be configured or otherwise control one or more nodes CR1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may include a Software Design Infrastructure (“SDI”) management entity for data center 1200. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0102] In at least one embodiment, such as Figure 12As shown, framework layer 1220 includes a job scheduler 1232, a configuration manager 1234, a resource manager 1236, and a distributed file system 1238. In at least one embodiment, framework layer 1220 may include a framework of software 1232 supporting software layer 1230 and / or one or more applications 1242 supporting application layer 1240. In at least one embodiment, software 1232 or application 1242 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 1238 for large-scale data processing (e.g., "big data"). TM (Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1232 may include a Spark driver to facilitate the scheduling of workloads supported by various layers of data center 1200. In at least one embodiment, the configuration manager 1234 may be able to configure different layers, such as software layer 1230 and framework layer 1220 including Spark and a distributed file system 1238 for supporting large-scale data processing. In at least one embodiment, the resource manager 1236 is able to manage cluster or group computing resources mapped to or allocated to support distributed file system 1238 and job scheduler 1232. In at least one embodiment, cluster or group computing resources may include group computing resources 1214 on data center infrastructure layer 1210. In at least one embodiment, the resource manager 1236 may coordinate with resource coordinator 1212 to manage these mapped or allocated computing resources.

[0103] In at least one embodiment, the software 1232 included in the software layer 1230 may include software used by at least a portion of the nodes CR1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0104] In at least one embodiment, one or more applications 1242 included in application layer 1240 may include one or more types of applications used by at least a portion of nodes CR 1216(1)-1216(N), grouped computing resources 1214, and / or the distributed file system 1238 of framework layer 1220. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow®, Caffe, etc.), or other machine learning applications used in conjunction with at least one embodiment.

[0105] In at least one embodiment, any of the configuration manager 1234, resource manager 1236, and resource coordinator 1212 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 1200 and can prevent underutilization and / or poor performance of the data center.

[0106] In at least one embodiment, data center 1200 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 1200. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 1200, by using weight parameters calculated through one or more training techniques described herein.

[0107] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0108] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. In conjunction with this... Figure 11A11B and / or 11B provide details about the inference and / or training logic 1115. In at least one embodiment, the inference and / or training logic 1115 can be in the system Figure 12 The operation is used to infer or predict based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0109] Autonomous vehicles

[0110] Figure 13A An example of an autonomous vehicle 1300 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1300 (which may alternatively be referred to herein as "vehicle 1300") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 1300 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 1300 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0111] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 1300 may be able to function according to one or more of Levels 1 through 5 of autonomous driving levels. For example, in at least one embodiment, vehicle 1300 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0112] In at least one embodiment, vehicle 1300 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1300 may include, but is not limited to, propulsion system 1350, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1350 may be connected to the drivetrain of vehicle 1300, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 1300. In at least one embodiment, propulsion system 1350 may be controlled in response to receiving signals from one or more throttles / accelerators 1352.

[0113] In at least one embodiment, when the propulsion system 1350 is operating (e.g., when the vehicle 1300 is traveling), the steering system 1354 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1300 (e.g., along a desired path or route). In at least one embodiment, the steering system 1354 may receive signals from the steering actuator 1356. In at least one embodiment, the fully automated (Level 5) function does not require a steering wheel. In at least one embodiment, the brake sensor system 1346 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1348 and / or brake sensors.

[0114] In at least one embodiment, the controller 1336 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 13AA controller 1336 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1300. For example, in at least one embodiment, controller 1336 may send signals to operate vehicle braking via brake actuator 1348, to operate steering system 1354 via one or more steering actuators 1356, and to operate propulsion system 1350 via one or more throttles / accelerators 1352. In at least one embodiment, one or more controllers 1336 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 1300. In at least one embodiment, one or more controllers 1336 may include a first controller for autonomous driving functions, a second controller 1336 for functional safety functions, a third controller 1336 for artificial intelligence functions (e.g., computer vision), a fourth controller 1336 for infotainment functions, a fifth controller 1336 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1336 may handle two or more of the functions described above, and two or more controllers 1336 may handle a single function and / or any combination thereof.

[0115] In at least one embodiment, one or more controllers 1336, in response to sensor data received from one or more sensors (e.g., sensor inputs), provide signals for controlling one or more components and / or systems of vehicle 1300. In at least one embodiment, the sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 1358 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1360, one or more ultrasonic sensors 1362, one or more LIDAR sensors 1364, one or more Inertial Measurement Unit (IMU) sensors 1366 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1396, one or more stereo cameras 1368, one or more wide-angle cameras 1370 (e.g., fisheye cameras), one or more infrared cameras 1372, one or more surround cameras 1374 (e.g., 360-degree cameras), and remote cameras (…). Figure 13A (not shown in the image), medium-range camera ( Figure 13A(Not shown in the diagram) One or more speed sensors 1344 (e.g., for measuring the speed of vehicle 1300), one or more vibration sensors 1342, one or more steering sensors 1340, one or more brake sensors (e.g., as part of brake sensor system 1346) and / or other sensor types are received.

[0116] In at least one embodiment, one or more controllers 1336 may receive input (e.g., represented by input data) from the dashboard 1332 of the vehicle 1300 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1334, a voice signaler, a speaker, and / or via other components of the vehicle 1300. In at least one embodiment, the output may include, for example, vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 13A Information such as (not shown in the image), location data (e.g., the location of vehicle 1300, for example on a map), direction, the location of other vehicles (e.g., occupying a grid), information about objects, and the object status perceived by controller 1336. For example, in at least one embodiment, HMI display 1334 may display information about the presence of one or more objects (e.g., street signs, warning signs, traffic light changes, etc.), and / or information about driving actions that the vehicle has performed, is performing, or will perform (e.g., changing lanes now, exiting from exit 34B within two miles, etc.).

[0117] In at least one embodiment, vehicle 1300 further includes a network interface 1324 that can communicate over one or more networks using one or more wireless antennas 1326 and / or one or more modems. For example, in at least one embodiment, network interface 1324 may be able to communicate via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”), etc. In at least one embodiment, one or more wireless antennas 1326 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter “LPWAN”) (e.g., LoRaWAN, SigFox, etc.).

[0118] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 can be implemented in the system. Figure 13A The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0119] In at least one embodiment, as with Figure 13A A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0120] Figure 13B The illustration shows an embodiment according to at least one of the embodiments. Figure 13A Examples of camera positions and fields of view for the autonomous vehicle 1300. In at least one embodiment, the camera and corresponding field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1300.

[0121] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for components and / or systems applicable to vehicle 1300. One or more cameras may operate under Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, depending on the embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent transparent (“RCCC”) color filter array, a red transparent blue (“RCCB”) color filter array, a red turquoise transparent (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a transparent pixel camera, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, may be used to increase light sensitivity.

[0122] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function monochrome camera may be mounted to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0123] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”-printed) assembly, to cut out stray light and reflections from inside the vehicle (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera’s image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D-printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0124] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 1300 can be used for surround view and, with the assistance of one or more controllers 1336 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0125] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“complementary metal-oxide-semiconductor” color imager. In at least one embodiment, a wide-angle camera 1370 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the street, or bicycles). Although in Figure 13BOnly one wide-angle camera 1370 is shown; however, in at least one embodiment, the vehicle 1300 may have any number (including zero) of wide-angle cameras 1370. In at least one embodiment, any number of remote cameras 1398 (e.g., a pair of remote stereo cameras) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 1398 may also be used for object detection and classification, as well as basic object tracking.

[0126] In at least one embodiment, any number of stereo cameras 1368 may also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1368 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 1300, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1368 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 1300 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1368 may also be used in addition to those described herein.

[0127] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 1300 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 1374 (e.g., as...) Figure 13B The four surround cameras 1374 shown can be positioned on the vehicle 1300. In at least one embodiment, one or more surround cameras 1374 may include, but are not limited to, any number and combination of wide-angle cameras 1370, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras may be located at the front, rear, and sides of the vehicle 1300. In at least one embodiment, the vehicle 1300 may use three surround cameras 1374 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0128] In at least one embodiment, a camera 1300 (e.g., a rear-view camera) having a field of view including a portion of the vehicle's rear environment can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras also suitable as one or more forward-facing cameras (e.g., long-range camera 1398 and / or one or more mid-range cameras 1376, one or more stereo cameras 1368, one or more infrared cameras 1372, etc.), as described herein.

[0129] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. (Combined) Figure 11A and / or Figure 11B This document provides details regarding inference and / or training logic 1115. In at least one embodiment, inference and / or training logic 1115 can be... Figure 13B Used in systems for reasoning or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0130] In at least one embodiment, as with Figure 13B A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0131] Figure 13C The illustration shows an embodiment according to at least one of the embodiments. Figure 13A A block diagram of an example system architecture for an autonomous vehicle 1300. In at least one embodiment, Figure 13C Each of one or more components, one or more features, and one or more systems of vehicle 1300 is shown as connected via bus 1302. In at least one embodiment, bus 1302 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 1300 used to help control various features and functions of vehicle 1300, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 1302 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1302 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1302 may be an ASIL B compliant CAN bus.

[0132] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or from CAN. In at least one embodiment, there may be any number of buses 1302, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1302 may be used to perform different functions and / or may be used for redundancy. For example, a first bus 1302 may be used for a collision avoidance function, and a second bus 1302 may be used for actuation control. In at least one embodiment, each bus 1302 may communicate with any component of vehicle 1300, and two or more buses 1302 may communicate with the same component. In at least one embodiment, each of any number of system-on-chip (“SoC”) 1304, each of one or more controllers 1336, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1300) and may be connected to a common bus, such as a CAN bus.

[0133] In at least one embodiment, vehicle 1300 may include one or more controllers 1336, such as those described herein. Figure 13A As described above. In at least one embodiment, controller 1336 can be used for a variety of functions. In at least one embodiment, controller 1336 can be coupled to any of various other components and systems of vehicle 1300 and can be used to control vehicle 1300, artificial intelligence of vehicle 1300, infotainment of vehicle 1300 and / or the like.

[0134] In at least one embodiment, vehicle 1300 may include any number of SoCs 1304, each of which may include, but is not limited to, a central processing unit (“one or more CPUs”) 1306, a graphics processing unit (“one or more GPUs”) 1308, one or more processors 1310, one or more caches 1312, one or more accelerators 1314, one or more data storage 1316, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1304 may be used to control vehicle 1300 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 1304 may be combined with a high-definition (“HD”) map 1322 in a system (e.g., the system of vehicle 1300), the HD map 1322 being accessible from one or more servers via a network interface 1324. Figure 13C (Not shown in the image) Get map refresh and / or update.

[0135] In at least one embodiment, one or more CPUs 1306 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1306 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 1306 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 1306 may include four dual-core clusters, each cluster having a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 1306 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 1306 can be active at any given time.

[0136] In at least one embodiment, one or more CPUs 1306 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when a core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 1306 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0137] In at least one embodiment, one or more GPUs 1308 may include integrated GPUs (or “iGPUs” herein). In at least one embodiment, one or more GPUs 1308 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1308 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1308 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 136 KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512 KB of storage capacity). In at least one embodiment, one or more GPUs 1308 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1308 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 1308 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA).

[0138] In at least one embodiment, one or more GPU 1308s may be power-optimized for optimal performance in automotive and embedded use cases. In at least one embodiment, for example, one or more GPU 1308s may be fabricated on a FinFET (“FinFET”). In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0139] In at least one embodiment, one or more GPUs 1308 may include high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 1300 GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as graphics double data rate type five synchronous random access memory (“GDDR5”), may be used.

[0140] In at least one embodiment, one or more GPUs 1308 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 1308 to directly access the page tables of one or more CPUs 1306. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 1308 experiences a miss, an address translation request can be sent to one or more CPUs 1306. In response, in at least one embodiment, one or more CPUs 1306 can look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 1308. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 1306 and one or more GPUs 1308, thereby simplifying the programming of one or more GPUs 1308 and the porting of applications to one or more GPUs 1308.

[0141] In at least one embodiment, one or more GPUs 1308 may include any number of access counters that can track the frequency with which one or more GPUs 1308 access the memory of other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0142] In at least one embodiment, one or more SoCs 1304 may include any number of caches 1312, including those described herein. For example, in at least one embodiment, one or more caches 1312 may include a Level 3 (“L3”) cache available for one or more CPUs 1306 and one or more GPUs 1308 (e.g., connected to CPUs 1306 and GPUs 1308). In at least one embodiment, one or more caches 1312 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, the L3 cache may include 4 MB or more, depending on the embodiment.

[0143] In at least one embodiment, one or more SoCs 1304 may include one or more accelerators 1314 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 1304 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1308 and offload some tasks from one or more GPUs 1308 (e.g., freeing up more cycles from one or more GPUs 1308 to perform other tasks). In at least one embodiment, one or more accelerators 1314 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0144] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphone 1396; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0145] In at least one embodiment, the DLA can perform any function of one or more GPUs 1308, and by using inference accelerators, for example, the designer can target one or more DLAs or one or more GPUs 1308 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 1308 and / or one or more other accelerators 1314.

[0146] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include one or more programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1338, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0147] In at least one embodiment, the RISC core may be similar to an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, and / or the like. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0148] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 1306. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0149] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) and / or a Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0150] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory to enhance overall system security.

[0151] In at least one embodiment, one or more accelerators 1314 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 1314. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0152] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0153] In at least one embodiment, one or more SoCs 1304 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0154] In at least one embodiment, one or more accelerators 1314 (e.g., one or more hardware accelerator clusters) have broad applications for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that require predictable runtimes with low latency and low power consumption. In at least one embodiment, the PVA in an autonomous vehicle, such as vehicle 1300, is designed to run classical computer vision algorithms because they are efficient in object detection and integer mathematical operations.

[0155] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0156] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0157] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. For example, in at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 1366 related to the vehicle 1300 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 1364 or one or more RADAR sensors 1360).

[0158] In at least one embodiment, one or more SoCs 1304 may include one or more data storage devices 1316 (e.g., memory). In at least one embodiment, one or more data storage devices 1316 may be on-chip memory of one or more SoCs 1304, which may store neural networks to be executed on one or more GPUs 1308 and / or DLAs. In at least one embodiment, one or more data storage devices 1316 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 1316 may include L2 or L3 caches.

[0159] In at least one embodiment, one or more SoCs 1304 may include any number of processors 1310 (e.g., embedded processors). In at least one embodiment, one or more processors 1310 may include a startup and power management processor, which may be a dedicated processor and subsystem for handling startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 1304 and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 1304s, and / or power state management of one or more SoCs 1304s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 1304s may use the ring oscillator to detect the temperature of one or more CPUs 1306s, one or more GPUs 1308s, and / or one or more accelerators 1314s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 1304s into a lower power state and / or place the vehicle 1300 into a driver’s safe stopping pattern (e.g., bring the vehicle 1300 to a safe stop).

[0160] In at least one embodiment, one or more processors 1310 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0161] In at least one embodiment, one or more processors 1310 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support devices (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0162] In at least one embodiment, one or more processors 1310 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1310 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1310 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0163] In at least one embodiment, one or more processors 1310 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1370, one or more surround cameras 1374, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of SoC 1304, the neural network being configured to recognize in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0164] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0165] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 1308 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1308 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 1308 to improve performance and responsiveness.

[0166] In at least one embodiment, one or more SoCs of SoC 1304 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 1304 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0167] In at least one embodiment, one or more SoCs of SoC 1304 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 1304 may be used to process data from (e.g., via gigabit multimedia serial links and Ethernet connections) cameras, sensors (e.g., one or more LiDAR sensors 1364, one or more RADAR sensors 1360, etc., which may be connected via Ethernet), data from bus 1302 (e.g., vehicle 1300 speed, steering wheel position, etc.), data from one or more GNSS sensors 1358 (e.g., via Ethernet bus or CAN bus connection), etc. In at least one embodiment, one or more SoCs of SoC 1304 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs 1306 from routine data management tasks.

[0168] In at least one embodiment, one or more SoCs 1304 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1304 can be faster, more reliable, and even more energy and space efficient than other systems. For example, in at least one embodiment, one or more accelerators 1314, when combined with one or more CPUs 1306, one or more GPUs 1308, and one or more data storage devices 1316, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0169] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (such as C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0170] In at least one embodiment, multiple neural networks can be executed simultaneously and / or sequentially, and the results can be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 1320) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0171] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, the warning sign includes: “Caution: flashing lights indicate icy conditions.” The warning sign, consisting of the lights, can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on the CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1308.

[0172] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 1300. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1304 provide protection against theft and / or carjacking.

[0173] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 1396 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1304 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 1358. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1362, to execute emergency vehicle safety routines, slow down the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0174] In at least one embodiment, vehicle 1300 may include one or more CPUs 1318 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1304 via high-speed interconnects (e.g., PCIe). For example, in at least one embodiment, one or more CPUs 1318 may include x86 processors. In at least one embodiment, one or more CPUs 1318 may be used to perform any of a variety of functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 1304, and / or monitoring the status and health of one or more monitoring controllers 1336 and / or on-chip information systems (“information SoCs”) 1330.

[0175] In at least one embodiment, vehicle 1300 may include one or more GPUs 1320 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to one or more SoCs 1304 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, one or more GPUs 1320 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 1300 (e.g., sensor data).

[0176] In at least one embodiment, vehicle 1300 may further include a network interface 1324, which may include, but is not limited to, one or more wireless antennas 1326 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1324 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 130 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1300 with information about vehicles near vehicle 1300 (e.g., vehicles in front, to the side, and / or behind vehicle 1300). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 1300.

[0177] In at least one embodiment, network interface 1324 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 1336 to communicate over a wireless network. In at least one embodiment, network interface 1324 may include a radio frequency (RF) front-end for up-conversion from baseband to RF and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. In at least one embodiment, frequency conversion may be performed, for example, by known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0178] In at least one embodiment, vehicle 1300 may further include one or more data storage units 1328, which may include, but are not limited to, off-chip (e.g., one or more SoC 1304) storage. In at least one embodiment, one or more data storage units 1328 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0179] In at least one embodiment, the vehicle 1300 may further include one or more GNSS sensors 1358 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1358 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0180] In at least one embodiment, vehicle 1300 may further include one or more RADAR sensors 1360. One or more RADAR sensors 1360 can be used by vehicle 1300 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. One or more RADAR sensors 1360 may use a CAN bus and / or bus 1302 (e.g., to transmit data generated by one or more RADAR sensors 1360) for control and access to object tracking data, and in some examples, may access Ethernet to access raw data. In at least one embodiment, a wide variety of RADAR sensor types can be used. For example, but not limited to, one or more of the RADAR sensors 1360 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 1360 are one or more pulse Doppler RADAR sensors.

[0181] In at least one embodiment, one or more RADAR sensors 1360 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 250m range). In at least one embodiment, one or more RADAR sensors 1360 can help distinguish between stationary and moving objects and can be used by the ADAS system 1338 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 1360 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas, can create a focused beammap designed to record the surrounding environment of the vehicle 1300 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 1300 entering or leaving the lane.

[0182] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1360 designed to be mounted at both ends of the rear bumper. In at least one embodiment, when mounted at both ends of the rear bumper, the RADAR sensor system may generate two beams that continuously monitor blind spots behind and beside the vehicle. In at least one embodiment, the short-range RADAR system may be used in ADAS system 1338 for blind spot detection and / or lane change assistance.

[0183] In at least one embodiment, the vehicle 1300 may further include one or more ultrasonic sensors 1362. One or more ultrasonic sensors 1362, which may be positioned at the front, rear, and / or sides of the vehicle 1300, can be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 1362 can be used, and different ultrasonic sensors 1362 can be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 1362 can operate at the ASIL B functional safety level.

[0184] In at least one embodiment, vehicle 1300 may include one or more LiDAR sensors 1364. In at least one embodiment, one or more LiDAR sensors 1364 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LiDAR sensor 1364 may be at functional safety level ASIL B. In at least one embodiment, vehicle 1300 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 1364 that can use Ethernet channels (e.g., providing data to a Gigabit Ethernet switch).

[0185] In at least one embodiment, one or more LiDAR sensors 1364 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 1364 may, for example, have an advertising range of approximately 100m, an accuracy of 2cm-3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used and may be implemented as small devices that can be embedded in the front, rear, sides, and / or corners of vehicle 1300. In at least one embodiment, one or more LiDAR sensors 1364, in such embodiments, can provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 200m. In at least one embodiment, one or more forward-facing LiDAR sensors 1364 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0186] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 1300. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from the vehicle 1300 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 1300. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as intensity data in the form of a 3D ranging point cloud and co-registered data.

[0187] In at least one embodiment, vehicle 1300 may further include one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 may be located at the center of the rear axle of vehicle 1300. In at least one embodiment, one or more IMU sensors 1366 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1366 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0188] In at least one embodiment, one or more IMU sensors 1366 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 1366 may enable vehicle 1300 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 1366. In at least one embodiment, one or more IMU sensors 1366 and one or more GNSS sensors 1358 may be combined in a single integrated unit.

[0189] In at least one embodiment, vehicle 1300 may include one or more microphones 1396 placed inside and / or around vehicle 1300. In at least one embodiment, in addition, one or more microphones 1396 may be used for emergency vehicle detection and identification.

[0190] In at least one embodiment, vehicle 1300 may further include any number of camera types, including one or more stereo cameras 1368, one or more wide-angle cameras 1370, one or more infrared cameras 1372, one or more surround cameras 1374, one or more long-range cameras 1398, one or more mid-range cameras 1376, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 1300. In at least one embodiment, the type of camera used depends on vehicle 1300. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1300. In at least one embodiment, the number of cameras can vary depending on the embodiment. For example, in at least one embodiment, vehicle 1300 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. The cameras may be examples, but are not limited to, supporting Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, previously referenced herein Figure 13A and Figure 13B Each camera can be described in more detail.

[0191] In at least one embodiment, the vehicle 1300 may further include one or more vibration sensors 1342. The one or more vibration sensors 1342 can measure vibrations of components of the vehicle 1300 (e.g., axles). For example, in at least one embodiment, changes in vibration can indicate changes in road surface conditions. In at least one embodiment, when two or more vibration sensors 1342 are used, differences between vibrations can be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0192] In at least one embodiment, vehicle 1300 may include ADAS system 1338. In at least one embodiment, ADAS system 1338 may include, but is not limited to, SoC, in some examples. In at least one embodiment, ADAS system 1338 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0193] In at least one embodiment, the ACC system may use one or more RADAR sensors 1360, one or more LIDAR sensors 1364, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 1300 and automatically adjusts the speed of vehicle 1300 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 1300 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0194] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 1324 and / or one or more wireless antennas 1326 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. In at least one embodiment, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 1300 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 1300, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0195] In at least one embodiment, the FCW system is designed to warn the driver of danger so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1360, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual, haptic, and / or rapid braking pulses.

[0196] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0197] In at least one embodiment, when vehicle 1300 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1300 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 1300.

[0198] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0199] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 1300 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 1360 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration assembly.

[0200] In at least one embodiment, the ADAS system may be prone to generating false alarms, which may annoy and distract the driver, but are generally not catastrophic because the ADAS system alerts the driver and allows the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 1300 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first controller 1336 or the second controller 1336). For example, in at least one embodiment, the ADAS system 1338 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1338 may be provided to a monitoring MCU. In at least one embodiment, if the outputs from the primary computer and the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0201] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0202] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from both the host computer and the auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the output of the auxiliary computer can be trusted and when it cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system recognizes a metallic object that is not actually dangerous, such as a drain grat or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 1304s.

[0203] In at least one embodiment, the ADAS system 1338 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0204] In at least one embodiment, the output of the ADAS system 1338 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 1338 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0205] In at least one embodiment, vehicle 1300 may further include an infotainment SoC 1330 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 1330 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1330 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 1300. For example, the infotainment SoC 1330 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 1334, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 1330 may further be used to provide information (e.g., visual and / or auditory) to users of the vehicle, such as information from ADAS system 1338, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0206] In at least one embodiment, the infotainment SoC 1330 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1330 may communicate with other devices, systems, and / or components of the vehicle 1300 via a bus 1302 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 1330 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 1336 (e.g., the main computer and / or backup computer of the vehicle 1300). In at least one embodiment, the infotainment SoC 1330 may cause the vehicle 1300 to enter a driver-to-safe-stop mode, as described herein.

[0207] In at least one embodiment, vehicle 1300 may further include instrument panel 1332 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 1332 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 1332 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1330 and instrument panel 1332. In at least one embodiment, instrument panel 1332 may be included as part of infotainment SoC 1330, or vice versa.

[0208] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 can be implemented in the system. Figure 13C The operation is used to infer or predict the operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0209] In at least one embodiment, as with Figure 13C A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0210] Figure 13DIt is based on at least one embodiment in a cloud-based server and Figure 13A A diagram of a system 1376 for communication between autonomous vehicles 1300. In at least one embodiment, system 1376 may include, but is not limited to, one or more servers 1378, one or more networks 1390, and any number and type of vehicles, including vehicle 1300. In at least one embodiment, one or more servers 1378 may include, but is not limited to, multiple GPUs 1384(A)-1384(H) (collectively referred to herein as GPU 1384), PCIe switches 1382(A)-1382(H) (collectively referred to herein as PCIe switch 1382), and / or CPUs 1380(A)-1380(B) (collectively referred to herein as CPU 1380). GPU 1384, CPU 1380, and PCIe switch 1382 may be interconnected with high-speed cables, such as, but not limited to, NVLink interface 1388 developed by NVIDIA and / or PCIe connection 1386. In at least one embodiment, the GPU 1384 is connected via NVLink and / or NVSwitchSoC, and the GPU 1384 and PCIe switch 1382 are connected via PCIe interconnect. In at least one embodiment, although eight GPUs 1384, two CPUs 1380, and four PCIe switches 1382 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1378 may include, but is not limited to, any combination of any number of GPUs 1384, CPUs 1380, and / or PCIe switches 1382. For example, in at least one embodiment, one or more servers 1378 may each include eight, sixteen, thirty-two, and / or more GPUs 1384.

[0211] In at least one embodiment, one or more servers 1378 may receive image data representing images from vehicles via one or more networks 1390, the images showing unexpected or changed road conditions, such as recently started roadworks. In at least one embodiment, one or more servers 1378 may transmit, via one or more networks 1390 and to vehicles, neural network 1392, updated neural network 1392, and / or map information 1394, including but not limited to information about traffic and road conditions. In at least one embodiment, updating the map information 1394 may include, but is not limited to, updating the HD map 1322, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1392, updated neural network 1392, and / or map information 1394 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 1378 and / or other servers).

[0212] In at least one embodiment, one or more servers 1378 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 1390), and / or the machine learning model may be used by one or more servers 1378 to remotely monitor the vehicle.

[0213] In at least one embodiment, one or more servers 1378 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 1378 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1384, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1378 may include a deep learning infrastructure in a data center using CPU power.

[0214] In at least one embodiment, the deep learning infrastructure of one or more servers 1378 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processor, software, and / or associated hardware in vehicle 1300. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1300, such as image sequences and / or objects located by vehicle 1300 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 1300, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 1300 is malfunctioning, one or more servers 1378 may signal to vehicle 1300 to instruct the fail-safe computer of vehicle 1300 to take control, notify passengers, and complete a safe stopping operation.

[0215] In at least one embodiment, one or more servers 1378 may include one or more GPUs 1384 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 1115 is used to execute one or more embodiments. This document incorporates... Figure 11A and / or Figure 11B Provide details about hardware architecture 1115.

[0216] Computer System

[0217] Figure 14 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 1400 may include, but is not limited to, components such as processor 1402, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 1400 may include a processor, such as the PENTIUM® processor family or Xeon processor, available from Intel Corporation of Santa Clara, California. TMItanium®, XScale TM and / or StrongARM TM The system may use an Intel® Core™ or Intel® Nervana™ microprocessor, although other systems (including PCs, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 1400 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0218] In at least one embodiment, the functionality is implemented in other devices, such as handheld devices and embedded applications, for example, cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and / or handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0219] In at least one embodiment, computer system 1400 may include, but is not limited to, processor 1402, which may include, but is not limited to, one or more execution units 1408, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1400 is a single-processor desktop or server system, or computer system 1400 may be a multiprocessor system. In at least one embodiment, processor 1402 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1402 may be coupled to processor bus 1410, which can transmit data signals between processor 1402 and other components in computer system 1400.

[0220] In at least one embodiment, processor 1402 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1402. Other embodiments may also include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1406 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0221] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 1402. In at least one embodiment, the processor 1402 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode for certain macro instructions. In at least one embodiment, the execution unit 1408 may include logic for processing a packaged instruction set 1409. In at least one embodiment, by including the packaged instruction set 1409 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, packaged data in the general-purpose processor 1402 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0222] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that can be executed by processor 1402.

[0223] In at least one embodiment, the system logic chip may be coupled to processor bus 1410 and memory 1420. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 1416, and processor 1402 may communicate with MCH 1416 via processor bus 1410. In at least one embodiment, MCH 1416 may provide a high-bandwidth memory path 1418 to memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 1416 may initiate data signals between processor 1402, memory 1420, and other components in computer system 1400, and bridge data signals between processor bus 1410, memory 1420, and system I / O 1422. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1416 may be coupled to memory 1420 via high-bandwidth memory path 1418, and graphics / video card 1412 may be coupled to MCH 1416 via Accelerated Graphics Port (“AGP”) interconnect 1414.

[0224] In at least one embodiment, computer system 1400 may use system I / O 1422 as a proprietary hub interface bus to couple MCH 1416 to I / O controller hub (“ICH”) 1430. In at least one embodiment, ICH 1430 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub (“Flash BIOS”) 1428, a wireless transceiver 1426, a data storage 1424, a conventional I / O controller 1423 including a user input and keyboard interface, a serial expansion port 1427 (e.g., a Universal Serial Bus (USB) port), and a network controller 1434. In at least one embodiment, data storage 1424 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0225] In at least one embodiment, Figure 14 A system including interconnected hardware devices or "chips" is shown, and / or Figure 14 An exemplary system-on-chip (“SoC”) may be illustrated. In at least one embodiment, Figure 14The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 1400 are interconnected using a Compute Fast Link (CXL) interconnect.

[0226] The inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details are provided regarding the inference and / or training logic 1115. In at least one embodiment, the inference and / or training logic 1115 can... Figure 14 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0227] In at least one embodiment, as with Figure 14 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0228] Figure 15 This is a block diagram illustrating an electronic device 1500 for utilizing a processor 1510 according to at least one embodiment. In at least one embodiment, the electronic device 1500 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0229] In at least one embodiment, system 1500 may include, but is not limited to, processor 1510 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1510 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. Figure 15 A system is shown that includes interconnected hardware devices or "chips", and / or Figure 15 An exemplary system-on-chip (“SoC”) may be illustrated. In at least one embodiment, Figure 15 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0230] In at least one embodiment, Figure 15 This may include a display 1524, a touchscreen 1525, a touchpad 1530, a near-field communication unit (“NFC”) 1545, a sensor hub 1540, a thermal sensor 1546, a fast chipset (“EC”) 1535, a trusted platform module (“TPM”) 1538, a BIOS / firmware / flash (“BIOS, FW Flash”) 1522, a DSP 1560, a drive (“SSD or HDD”) 1520 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless LAN unit (“WLAN”) 1550, a Bluetooth unit 1552, a wireless wide area network unit (“WWAN”) 1556, a global positioning system (GPS) 1555, a camera (“USB 3.0 camera”) 1554 (e.g., a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1515 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0231] In at least one embodiment, other components may be communicatively coupled to processor 1510 via the components described above. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1546, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 1564, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1564 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as WLAN unit 1550, Bluetooth unit 1552, and WWAN unit 1556 can be implemented as next-generation form factor (NGFF).

[0232] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11BDetails regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 can be implemented in the system. Figure 15 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0233] In at least one embodiment, as with Figure 15 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0234] Figure 16 A computer system 1600 according to at least one embodiment is shown. In at least one embodiment, the computer system 1600 is configured to implement various processes and methods described throughout this disclosure.

[0235] In at least one embodiment, the computer system 1600 includes, but is not limited to, at least one central processing unit (“CPU”) 1602 connected to a communication bus 1610 implemented using any suitable protocol, such as PCI (“Peripheral Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1600 includes, but is not limited to, main memory 1604 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 1604 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 1622 provides an interface to other computing devices and networks for receiving data using the computer system 1600 and transferring data to other systems.

[0236] In at least one embodiment, the computer system 1600 includes, but is not limited to, an input device 1608, a parallel processing system 1612, and a display device 1606, which may be implemented using a cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light-emitting diode (“LED”), a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1608 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0237] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 can be implemented in the system. Figure 16 It is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architecture or neural network use cases described herein.

[0238] In at least one embodiment, as with Figure 16 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0239] Figure 17 A computer system 1700 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1700 includes, but is not limited to, a computer 1710 and a USB flash drive 1720. In at least one embodiment, the computer 1710 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1710 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0240] In at least one embodiment, the USB flash drive 1720 includes, but is not limited to, a processing unit 1730, a USB interface 1740, and USB interface logic 1750. In at least one embodiment, the processing unit 1730 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1730 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1730 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1730 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1730 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0241] In at least one embodiment, the USB interface 1740 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1740 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1740 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1750 may include any amount and type of logic enabling the processing unit 1730 to connect to a device (e.g., computer 1710) via the USB connector 1740.

[0242] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 can be implemented in the system. Figure 17 In use, at least in part, the operation is based on weight parameters, neural network functions and / or architectures computed using neural network training operations, or neural network use cases described herein to infer or predict operations.

[0243] In at least one embodiment, as with Figure 17 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0244] Figure 18 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein are illustrated. In at least one embodiment, in addition to what is shown, other logic and circuitry may be included, such as additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0245] Figure 18This is a block diagram illustrating an exemplary system-on-chip (SOC) integrated circuit 1800 manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1800 includes peripheral or bus logic, including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I2S / I2C controller 1840. In at least one embodiment, the integrated circuit 1800 may include a display device 1845 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industrial Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860 including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1870.

[0246] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. In conjunction with this... Figure 11A 11B and / or 11B provide details about the inference and / or training logic 1115. In at least one embodiment, the inference and / or training logic 1115 may be used in integrated circuit 1800 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0247] In at least one embodiment, as with Figure 18 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0248] Figure 19A An exemplary architecture is illustrated, in which multiple GPUs 1910-1913 are communicatively coupled to multiple multi-core processors 1905-1906 via high-speed links 1940-1943 (e.g., bus, point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1940-1943 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0249] Furthermore, in at least one embodiment, two or more GPUs 1910-1913 are interconnected via high-speed links 1929-1930, which can be implemented using the same or different protocols / links as those used for high-speed links 1940-1943. Similarly, in at least one embodiment, two or more multi-core processors 1905-1906 can be connected via high-speed link 1928, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, in at least one embodiment, Figure 19A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure).

[0250] In at least one embodiment, each multi-core processor 1905-1906 is communicatively coupled to processor memories 1901-1902 via memory interconnects 1926-1927, and each GPU 1910-1913 is communicatively coupled to GPU memories 1920-1923 via GPU memory interconnects 1950-1953. In at least one embodiment, memory interconnects 1926-1927 and 1950-1953 may utilize the same or different memory access technologies. In at least one embodiment, by way of example and not limitation, processor memories 1901-1902 and GPU memories 1920-1923 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In at least one embodiment, portions of some processor memories 1901-1902 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0251] In at least one embodiment, as described herein, although the various multiprocessors 1905-1906 and GPUs 1910-1913 can be physically coupled to specific memories 1901-1902 and 1920-1923 respectively, a unified memory architecture can be implemented, wherein the same virtual system address space (also referred to as the “effective address” space) is distributed across the various physical memories. In at least one embodiment, for example, processor memories 1901-1902 may each include 64GB of system memory address space and GPU memories 1920-1923 may each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0252] Figure 19B Additional details are shown for the interconnection between a multi-core processor 1907 and a graphics acceleration module 1946 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1946 may include one or more GPU chips integrated on a line card coupled to the processor 1907 via a high-speed link 1940. In at least one embodiment, optionally, the graphics acceleration module 1946 may be integrated on the same package or chip as the processor 1907.

[0253] In at least one embodiment, processor 1907 is described as including a plurality of cores 1960A-1960D, each core having a translation back buffer 1961A-1961D and one or more caches 1962A-1962D. In at least one embodiment, cores 1960A-1960D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, caches 1962A-1962D may include level 1 (L1) and level 2 (L2) caches, and one or more shared caches 1956 may be included in caches 1962A-1962D and shared by the respective groups of cores 1960A-1960D. In at least one embodiment, for example, at least one embodiment of processor 1907 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches, and two adjacent cores sharing one or more L2 and L3 caches. In at least one embodiment, the processor 1907 and the graphics acceleration module 1946 are connected to a system memory 1914, which may include... Figure 19A The processor memory in the memory is 1901-1902.

[0254] In at least one embodiment, consistency of data and instructions stored in the various caches 1962A-1962D, 1956 and system memory 1914 is maintained via inter-core communication through the consistency bus 1964. For example, in at least one embodiment, each cache may have associated cache consistency logic / circuitology to communicate via the consistency bus 1964 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1964 to snoop on cache accesses.

[0255] In at least one embodiment, proxy circuitry 1925 communicatively couples graphics acceleration module 1946 to coherence bus 1964, thereby allowing graphics acceleration module 1946 to participate in cache coherence protocols as a peer of cores 1960A-1960D. In at least one embodiment, interface 1935 provides connectivity to proxy circuitry 1925 via high-speed link 1940 (e.g., PCIe bus, NVLink, etc.), and interface 1937 connects graphics acceleration module 1946 to link 1940.

[0256] In at least one embodiment, the accelerator integrated circuit 1936 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 1931, 1932, and N of the graphics acceleration module. In at least one embodiment, the graphics processing engines 1931, 1932, and N may each include a separate graphics processing unit (GPU). In at least one embodiment, optionally, the graphics processing engines 1931, 1932, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1946 may be a GPU having multiple graphics processing engines 1931-1932, and N, or the graphics processing engines 1931-1932, and N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0257] In at least one embodiment, the accelerator integrated circuit 1936 includes a memory management unit (MMU) 1939 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1914. In at least one embodiment, the MMU 1939 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, a cache 1938 stores commands and data for effective access by graphics processing engines 1931-1932, N. In at least one embodiment, a fetch unit 1944 may be used to keep data stored in cache 1938 and graphics memories 1933-1934, M consistent with core caches 1962A-1962D, 1956 and system memory 1914. As previously mentioned, this task can be accomplished via proxy circuitry 1925 representing cache 1938 and graphics memory 1933-1934, M (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1962A-1962D, 1956 to cache 1938 and receiving updates from cache 1938).

[0258] In at least one embodiment, a set of registers 1945 stores context data of threads executed by graphics processing engines 1931-1932, N, and context management circuitry 1948 manages the thread context. For example, in at least one embodiment, context management circuitry 1948 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., saving a first thread and storing a second thread so that the graphics processing engine can execute the second thread). In at least one embodiment, for example, during context switching, context management circuitry 1948 can store the current register value to a designated area in memory (e.g., identified by a context pointer). In at least one embodiment, it can subsequently restore the register value upon returning to the context. In at least one embodiment, interrupt management circuitry 1947 receives and processes interrupts received from system devices.

[0259] In at least one embodiment, the virtual / effective address from the graphics processing engine 1931 is translated by the MMU 1939 into a real / physical address in system memory 1914. In at least one embodiment, the accelerator integrated circuit 1936 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1946 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1946 may be dedicated to a single application executing on the processor 1907, or it may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein the resources of the graphics processing engines 1931-1932, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0260] In at least one embodiment, the accelerator integrated circuit 1936 acts as a system bridge for the graphics acceleration module 1946 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1936 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1931-1932.

[0261] In at least one embodiment, since the hardware resources of the graphics processing engines 1931-1932 are explicitly mapped to the real address space seen by the host processor 1907, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1936 is to physically separate the graphics processing engines 1931-1932 and N, making them appear as independent units to the system.

[0262] In at least one embodiment, one or more graphics memories 1933-1934, M are coupled to each graphics processing engine 1931-1932, N, respectively, and N = M. In at least one embodiment, graphics memories 1933-1934, M store instructions and data processed by each graphics processing engine 1931-1932, N. In at least one embodiment, graphics memories 1933-1934, M may be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0263] In at least one embodiment, to reduce data traffic on link 1940, a biasing technique is used to ensure that the data stored in graphics memories 1933-1934, M is the data most frequently used by graphics processing engines 1931-1932, N, and preferably not used (or at least infrequently used) by cores 1960A-1960D. In at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not graphics processing engines 1931-1932, N) in caches 1962A-1962D, 1956 cores, and system memory 1914.

[0264] Figure 19C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1936 is integrated within the processor 1907, wherein the graphics processing engines 1931, 1932, and N communicate directly with the accelerator integrated circuit 1936 via a high-speed link 1940 through interfaces 1937 and 1935 (which can also be used for any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1936 can perform operations related to... Figure 19B The operations described are the same. However, due to its close proximity to the coherence bus 1964 and caches 1962A-1962D, 1956, it may have higher throughput. In at least one embodiment, different programming models are supported, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1936 and a programming model controlled by the graphics acceleration module 1946.

[0265] In at least one embodiment, the graphics processing engine 19311932,N is dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to the graphics processing engine 19311932,N, thereby providing virtualization within a VM / partition.

[0266] In at least one embodiment, the graphics processing engine 19311932, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize the graphics processing engine 19311932, N to allow each operating system to access it. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engine 19311932, N. In at least one embodiment, the operating system can virtualize the graphics processing engine 19311932, N to provide access to each process or application.

[0267] In at least one embodiment, the graphics acceleration module 1946 or the individual graphics processing engine 19311932,N uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1914 and can be addressed using the effective address to physical address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 19311932,N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0268] Figure 19D An exemplary accelerator integration slice 1990 is illustrated. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1936. In at least one embodiment, the application is an effective address space 1982 in system memory 1914, which stores process element 1983. In at least one embodiment, process element 1983 is stored in response to a GPU call 1981 from an application 1980 executing on processor 1907. In at least one embodiment, process element 1983 contains the process state of the corresponding application 1980. In one embodiment, a job descriptor (WD) 1984 contained in process element 1983 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1984 is a pointer to a job request queue in the effective address space 1982 of the application.

[0269] The graphics acceleration module 1946 and / or the various graphics processing engines 1931, 1932, and N can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1984 to the graphics acceleration module 1946 to begin operations in a virtualized environment.

[0270] In at least one embodiment, the dedicated process programming model is implementation-specific, wherein a single process owns either the graphics acceleration module 1946 or an individual graphics processing engine 1931. In at least one embodiment, when the graphics acceleration module 1946 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1946 is assigned, the operating system initializes the accelerator integrated circuit 1936 for the owned process.

[0271] In at least one embodiment, during operation, the WD acquisition unit 1991 in the accelerator integration slice 1990 acquires the next WD 1984, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1946. In at least one embodiment, data from the WD 1984 may be stored in register 1945 and used by the MMU 1939, interrupt management circuitry 1947, and / or context management circuitry 1948, as shown. In at least one embodiment, for example, one embodiment of the MMU 1939 includes segment / page roaming circuitry for accessing segment / page tables 1986 within the OS virtual address space 1985. In at least one embodiment, the interrupt management circuitry 1947 may process an interrupt event 1992 received from the graphics acceleration module 1946. In at least one embodiment, when performing graphics operations, a valid address 1993 generated by graphics processing engines 1931-1932, N is translated into a real address by the MMU 1939.

[0272] In at least one embodiment, the same set of registers 1945 is copied for each graphics processing engine 1931-1932, N, and / or graphics acceleration module 1946, and can be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers can be included in the accelerator integration slice 1990. Exemplary registers that can be initialized by a hypervisor in at least one embodiment are shown in Table 1.

[0273]

[0274] In at least one embodiment, exemplary registers that can be initialized by the operating system are shown in Table 2.

[0275]

[0276] In at least one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or graphics processing engine 1931-1932, N, and each WD 1984 contains information required for the graphics processing engine 1931-1932, N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0277] Figure 19E Additional details of an exemplary embodiment of the shared model are shown. In at least one embodiment, a hypervisor physical address space 1998 is included, wherein a process element list 1999 is stored. In at least one embodiment, the hypervisor physical address space 1998 can be accessed via a hypervisor 1996, which virtualizes the graphics acceleration module engine for operating system 1995.

[0278] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1946. In at least one embodiment, two programming models exist where the graphics acceleration module 1946 is shared by multiple processes and partitions: time-slice sharing and graphics-directed sharing, wherein the hypervisor 1996 owns the graphics acceleration module 1946 and makes its functionality available to all operating systems 1995. In at least one embodiment, to enable the graphics acceleration module 1946 to support the virtualization of the hypervisor 1996, the graphics acceleration module 1946 may comply with the following provisions: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 1946 must provide context saving and restoration mechanisms; 2) The graphics acceleration module 1946 guarantees that application job requests are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1946 provides the ability to preempt job processing; 3) When operating in the directed shared programming model, fairness among the processes of the graphics acceleration module 1946 must be ensured.

[0279] In at least one embodiment, application 1980 needs to make an operating system 1995 system call using the graphics acceleration module type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1946 and can take the form of graphics acceleration module 1946 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1946. In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementations of accelerator integrated circuit 1936 (not shown) and graphics acceleration module 1946 do not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1996 may apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1983. In at least one embodiment, the CSRP is one of registers 1945 containing the effective address of a region in the application's address space 1982 for the graphics acceleration module 1946 to save and restore context state. In at least one embodiment, this pointer is not required if saving state between jobs or when a job is preempted is not necessary. In at least one embodiment, the context save / restore region may be fixed system memory.

[0280] In at least one embodiment, upon receiving a system call, operating system 1995 may verify that application 1980 has been registered and granted permission to use graphics acceleration module 1946. Then, in at least one embodiment, operating system 1995 uses the information shown in Table 3 to invoke hypervisor 1996.

[0281]

[0282] In at least one embodiment, upon receiving a hypervisor call, hypervisor 1996 verifies that operating system 1995 has been registered and granted permission to use graphics acceleration module 1946. Then, in at least one embodiment, hypervisor 1996 adds process element 1983 to a linked list of process elements of the corresponding graphics acceleration module 1946 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0283]

[0284] In at least one embodiment, the management program initializes multiple accelerator integration slice 1990 registers 1945.

[0285] like Figure 19F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1901-1902 and GPU memories 1920-1923. Operations performed on GPUs 1910-1913 utilize the same virtual / effective memory address space to access processor memories 1901-1902, and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1901, a second portion to second processor memory 1902, a third portion to GPU memory 1920, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1901-1902 and GPU memories 1920-1923, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0286] In at least one embodiment, the bias / coherence management circuitry 1994A-1994E within one or more MMUs 1939A-1939E ensures cache coherence between the caches of one or more host processors (e.g., 1905) and the GPUs 1910-1913, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 19F Several instances of bias / coherence management circuitry 1994A-1994E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1905 and / or within the accelerator integrated circuit 1936.

[0287] In at least one embodiment, GPU-attached memories 1920-1923 are mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU-attached memories 1920-1923 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1905 software to set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memories 1920-1923 without cache coherence overhead can be critical for the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1910-1913. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0288] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure controlled at the memory page level, comprising 1 or 2 bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1910-1913, the bias table can be implemented across one or more stolen memory ranges of GPU-attached memory 1920-1923. In at least one embodiment, alternatively, the entire bias table can be maintained within the GPU.

[0289] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1920-1923 is performed, resulting in the following operations: First, a local request from GPUs 1910-1913 to locate its page in the GPU bias is directly forwarded to the corresponding GPU memory 1920-1923. In at least one embodiment, a local request from the GPU to locate its page in the host bias is forwarded to processor 1905 (e.g., via the high-speed link described above). In at least one embodiment, a request from processor 1905 to locate the requested page in the host processor bias completes a request similar to a normal memory read. In at least one embodiment, alternatively, a request to a GPU bias page can be forwarded to GPUs 1910-1913. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, in limited cases, purely hardware-based mechanisms.

[0290] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migration from the host processor 1905 bias to the GPU bias, but not for the reverse migration.

[0291] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1905 cannot cache. In at least one embodiment, to access these pages, the processor 1905 may request access from the GPU 1910, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1905 and the GPU 1910, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU rather than those needed by the host processor 1905, and vice versa.

[0292] In at least one embodiment, one or more hardware structures 1115 are used to perform one or more embodiments. This document incorporates... Figure 11A And / or 11B provides details about the hardware architecture (x)1115.

[0293] In at least one embodiment, as part of a communication process or system used with the system of FIG19, a GPU-based scrambling / descrambling unit may be used to perform scrambling and / or descrambling.

[0294] Figures 20A-20B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to those shown, other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores, may be included in at least one embodiment.

[0295] Figure 20A and 20B This is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 20A An exemplary graphics processor 2010, which can be fabricated using one or more IP cores according to at least one embodiment, is shown. Figure 20B An additional exemplary graphics processor 2040, which can be fabricated using one or more IP cores, is shown according to at least one embodiment. In at least one embodiment, Figure 20A The graphics processor 2010 is a low-power graphics processor core. In at least one embodiment, Figure 20B The graphics processor 2040 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 2010 and 2040 may be... Figure 18 A variant of the 1810 graphics processor.

[0296] In at least one embodiment, the graphics processor 2010 includes a vertex processor 2005 and one or more fragment processors 2015A-2015N (e.g., 2015A, 2015B, 2015C, 2015D to 2015N-1 and 2015N). In at least one embodiment, the graphics processor 2010 may execute different shader programs via separate logic, such that the vertex processor 2005 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2015A-2015N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 2005 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 2015A-2015N use the primitive and vertex data generated by the vertex processor 2005 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 2015A-2015N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0297] In at least one embodiment, the graphics processor 2010 additionally includes one or more memory management units (MMUs) 2020A-2020B, one or more caches 2025A-2025B, and one or more circuit interconnects 2030A-2030B. In at least one embodiment, the one or more MMUs 2020A-2020B provide a virtual-to-physical address mapping for the graphics processor 2010, including for the vertex processor 2005 and / or fragment processors 2015A-2015N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 2025A-2025B. In at least one embodiment, the one or more MMUs 2020A-2020B can be synchronized with other MMUs within the system, including with… Figure 18 One or more application processors 1805, graphics processors 1815, and / or video processors 1820 are associated with one or more MMUs, enabling each processor 1805-1820 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2030A-2030B enable the graphics processor 2010 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0298] In at least one embodiment, the graphics processor 2040 includes Figure 20AThe graphics processor 2010 includes one or more MMUs 2020A-2020B, caches 2025A-2025B, and circuit interconnects 2030A-2030B. In at least one embodiment, the graphics processor 2040 includes one or more shader cores 2055A-2055N (e.g., 2055A, 2055B, 2055C, 2055D, 2055E, 2055F, to 2055N-1 and 2055N), providing a unified shader core architecture where a single core or a type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2040 includes an inter-core task manager 2045 that acts as a thread dispatcher to assign execution threads to one or more shader cores 2055A-2055N and tile units 2058 to accelerate tile-based rendering operations, wherein rendering operations of a scene are subdivided in image space, for example, to take advantage of local spatial consistency within the scene or to optimize the use of internal caches.

[0299] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 may be integrated into an integrated circuit. Figure 20A and / or Figure 20B The method is used to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0300] In at least one embodiment, as with Figure 20A In communication processes or as part of a system used in conjunction with a 20B system, a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0301] Figures 21A-21B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 21A It shows that it can be included in Figure 18 The graphics core 2100 within the graphics processor 1810, and in at least one embodiment, may be as follows: Figure 20B The Unified Shader Cores 2055A-2055N are shown. Figure 21B A highly parallel general-purpose graphics processing unit 2130 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0302] In at least one embodiment, the graphics core 2100 includes a shared instruction cache 2102, texture units 2118, and a cache / shared memory 2120, which are common to the execution resources within the graphics core 2100. In at least one embodiment, the graphics core 2100 may include multiple slices 2101A-2101N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2100. In at least one embodiment, slices 2101A-2101N may include supporting logic, including local instruction caches 2104A-2104N, thread schedulers 2106A-2106N, thread dispatchers 2108A-2108N, and a set of registers 2110A-2110N. In at least one embodiment, slices 2101A-2101N may include a set of additional functional units (AFU 2112A-2112N), floating-point units (FPU 2114A-2114N), integer arithmetic logic units (ALU 2116-2116N), address calculation units (ACU 2113A-2113N), double-precision floating-point units (DPFPU 2115A-2115N), and matrix processing units (MPU 2117A-2117N).

[0303] In at least one embodiment, the FPU 2114A-2114N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 2115A-2115N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 2116A-2116N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 2117A-2117N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 2117-2117N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 2112A-2112N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0304] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 11A and / or Figure 11BDetails regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 may be used in the graphics core 2100 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0305] Figure 21B A general-purpose processing unit (GPGPU) 2130 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 2130 can be directly linked to other instances of the GPGPU 2130 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 2130 includes a host interface 2132 for connection to a host processor. In at least one embodiment, the host interface 2132 is a PCI Express interface. In at least one embodiment, the host interface 2132 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 2130 receives commands from the host processor and uses a global scheduler 2134 to allocate execution threads associated with those commands to a set of compute clusters 2136A-2136H. In at least one embodiment, the compute clusters 2136A-2136H share a cache memory 2138. In at least one embodiment, cache memory 2138 can be used as a higher-level cache within the cache memory of computing clusters 2136A-2136H.

[0306] In at least one embodiment, the GPGPU 2130 includes memories 2144A-2144B, which are coupled to computing clusters 2136A-2136H via a set of memory controllers 2142A-2142B. In at least one embodiment, memories 2144A-2144B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0307] In at least one embodiment, each of the computing clusters 2136A-2136H includes a set of graphics cores, for example... Figure 21AThe graphics core 2100 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 2136A-2136H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of these floating-point units may be configured to perform 64-bit floating-point operations.

[0308] In at least one embodiment, multiple instances of GPGPU 2130 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by computing clusters 2136A-2136H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 2130 communicate via host interface 2132. In at least one embodiment, GPGPU 2130 includes an I / O hub 2139 that couples GPGPU 2130 to GPU link 2140, enabling direct connection to other instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2130. In at least one embodiment, GPU link 2140 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2130 reside in a separate data processing system and communicate via network devices accessible through host interface 2132. In at least one embodiment, GPU link 2140 may be configured to enable connection to a host processor other than or as a replacement for host interface 2132.

[0309] In at least one embodiment, GPGPU 2130 can be configured to train a neural network. In at least one embodiment, GPGPU 2130 can be used within an inference platform. In at least one embodiment, when GPGPU 2130 is used for inference, GPGPU 2130 may include fewer compute clusters 2136A-2136H compared to when GPGPU 2130 is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2144A-2144B can differ between inference and training configurations, wherein higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 2130 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0310] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 may be used in the GPGPU 2130 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0311] In at least one embodiment, as with Figure 21A or Figure 21B A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0312] Figure 22 A block diagram of a computer system 2200 according to at least one embodiment is shown. In at least one embodiment, the computer system 2200 includes a processing subsystem 2201 having one or more processors 2202 and a system memory 2204 communicating via an interconnect path that may include a memory hub 2205. In at least one embodiment, the memory hub 2205 may be a separate component within a chipset component or may be integrated within one or more processors 2202. In at least one embodiment, the memory hub 2205 is coupled to an I / O subsystem 2211 via a communication link 2206. In one embodiment, the I / O subsystem 2211 includes an I / O hub 2207 that enables the computer system 2200 to receive input from one or more input devices 2208. In at least one embodiment, the I / O hub 2207 enables a display controller to provide output to one or more display devices 2210A, the display controller being included in one or more processors 2202. In at least one embodiment, one or more display devices 2210A coupled to I / O hub 2207 may include local, internal or embedded display devices.

[0313] In at least one embodiment, the processing subsystem 2201 includes one or more parallel processors 2212 coupled to the memory hub 2205 via a bus or other communication link 2213. In at least one embodiment, the communication link 2213 may use any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, the one or more parallel processors 2212 form a compute-intensive parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, the one or more parallel processors 2212 form a graphics processing subsystem that can output pixels to one or more display devices 2210A coupled via an I / O hub 2207. In at least one embodiment, the one or more parallel processors 2212 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 2210B.

[0314] In at least one embodiment, system storage unit 2214 may be connected to I / O hub 2207 to provide a storage mechanism for computer system 2200. In at least one embodiment, I / O switch 2216 may be used to provide an interface mechanism to enable connectivity between I / O hub 2207 and other components, such as network adapter 2218 and / or wireless network adapter 2219 which may be integrated into the platform, and various other devices that can be added via one or more additional devices 2220. In at least one embodiment, network adapter 2218 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 2219 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0315] In at least one embodiment, the computer system 2200 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 2207. In at least one embodiment, the interconnection can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express) or other bus or point-to-point communication interfaces and / or protocols. Figure 22 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0316] In at least one embodiment, one or more parallel processors 2212 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2212 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 2200 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2212, memory hub 2205, processor 2202, and I / O hub 2207 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 2200 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 2200 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0317] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the inference and / or training logic 1115 may be used in system 2200 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0318] In at least one embodiment, as with Figure 22 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0319] processor

[0320] Figure 23A A parallel processor 2300 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2300 is according to an exemplary embodiment. Figure 22 The variant of the 2212, which includes one or more parallel processors, is shown.

[0321] In at least one embodiment, the parallel processor 2300 includes a parallel processing unit 2302. In at least one embodiment, the parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of the parallel processing unit 2302. In at least one embodiment, the I / O unit 2304 can be directly connected to other devices. In at least one embodiment, the I / O unit 2304 is connected to other devices using a hub or switch interface (e.g., a memory hub 2205). In at least one embodiment, the connection between the memory hub 2205 and the I / O unit 2304 forms a communication link 2213. In at least one embodiment, the I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, wherein the host interface 2306 receives commands for performing processing operations, and the memory crossbar switch 2316 receives commands for performing memory operations.

[0322] In at least one embodiment, when host interface 2306 receives a command buffer via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to assign commands or other work items to processing cluster array 2312. In at least one embodiment, scheduler 2310 ensures that processing cluster array 2312 is correctly configured and in an active state before assigning tasks to processing cluster array 2312. In at least one embodiment, scheduler 2310 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can demonstrate workloads scheduled on processing array 2312 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed on the processing array 2312 by the scheduler 2310 logic within the microcontroller, which includes the scheduler 2310.

[0323] In at least one embodiment, the processing cluster array 2312 may include up to "N" processing clusters (e.g., clusters 2314A, 2314B to 2314N). In at least one embodiment, each cluster 2314A-2314N of the processing cluster array 2312 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2310 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2314A-2314N of the processing cluster array 2312, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 2310, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 2312. In at least one embodiment, different clusters 2314A-2314N of the processing cluster array 2312 may be assigned to process different types of programs or to perform different types of computations.

[0324] In at least one embodiment, the processing cluster array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2312 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2312 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0325] In at least one embodiment, the processing cluster array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2302 may transfer data from system memory via I / O unit 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) and then written back to system memory.

[0326] In at least one embodiment, when the parallel processing unit 2302 is used to perform graphics processing, the scheduler 2310 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 2314A-2314N of the processing cluster array 2312. In at least one embodiment, portions of the processing cluster array 2312 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2314A-2314N may be stored in a buffer to allow intermediate data to be transferred between the clusters 2314A-2314N for further processing.

[0327] In at least one embodiment, the processing cluster array 2312 may receive processing tasks to be executed via a scheduler 2310, which receives commands defining the processing tasks from a front end 2308. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 2310 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 2308. In at least one embodiment, the front end 2308 may be configured to ensure that the processing cluster array 2312 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0328] In at least one embodiment, each of one or more instances of the parallel processing unit 2302 may be coupled to the parallel processor memory 2322. In at least one embodiment, the parallel processor memory 2322 may be accessed via a memory crossbar switch 2316, which may receive memory requests from the processing cluster array 2312 and the I / O unit 2304. In at least one embodiment, the memory crossbar switch 2316 may access the parallel processor memory 2322 via a memory interface 2318. In at least one embodiment, the memory interface 2318 may include a plurality of partition units (e.g., partition units 2320A, 2320B to 2320N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 2322. In at least one embodiment, the plurality of partition units 2320A-2320N are configured to be equal to the number of memory units, such that the first partition unit 2320A has a corresponding first memory unit 2324A, the second partition unit 2320B has a corresponding memory unit 2324B, and the Nth partition unit 2320N has a corresponding Nth memory unit 2324N. In at least one embodiment, the number of partition units 2320A-2320N may not be equal to the number of memory devices.

[0329] In at least one embodiment, memory cells 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 2324A-2324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 2324A-2324N, allowing partitioning cells 2320A-2320N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 2322. In at least one embodiment, local instances of the parallel processor memory 2322 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0330] In at least one embodiment, any of the clusters 2314A-2314N of the processing cluster array 2312 can process data to be written to any memory cell 2324A-2324N within the parallel processor memory 2322. In at least one embodiment, the memory crossbar switch 2316 can be configured to transfer the output of each cluster 2314A-2314N to any partition cell 2320A-2320N or another cluster 2314A-2314N, and the clusters 2314A-2314N can perform further processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with the memory interface 2318 via the memory crossbar switch 2316 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 2316 has a connection to a memory interface 2318 for communication with I / O unit 2304, and a connection to a local instance of parallel processor memory 2322, thereby enabling processing units within different processing clusters 2314A-2314N to communicate with system memory or other memory not local to parallel processing unit 2302. In at least one embodiment, the memory crossbar switch 2316 may use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0331] In at least one embodiment, multiple instances of the parallel processing unit 2302 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2302 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2302 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 2302 or the parallel processor 2300 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0332] Figure 23B This is a block diagram of a partitioning unit 2320 according to at least one embodiment. In at least one embodiment, the partitioning unit 2320 is... Figure 23AThis is an example of one of the partitioning units 2320A-2320N. In at least one embodiment, the partitioning unit 2320 includes an L2 cache 2321, a frame buffer interface 2325, and a ROP 2326 (raster operation unit). In at least one embodiment, the L2 cache 2321 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 2316 and the ROP 2326. In at least one embodiment, the L2 cache 2321 outputs read misses and urgent write-back requests to the frame buffer interface 2325 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 2325. In at least one embodiment, the frame buffer interface 2325 communicates with memory cells in the parallel processor memory (such as...). Figure 23A It interacts with one of the memory cells 2324A-2324N (e.g., within the parallel processor memory 2322).

[0333] In at least one embodiment, ROP 2326 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 2326 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 2326 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 2326 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0334] In at least one embodiment, ROP 2326 is included within each processing cluster (e.g., Figure 23A Clusters 2314A-2314N are used instead of partition units 2320. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 2316 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 22 Displayed by one or more display devices 2210, routed by processor 2202 for further processing, or by Figure 23A One of the processing entities within the parallel processor 2300 is routed for further processing.

[0335] Figure 23C This is a block diagram of a processing cluster 2314 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 23A An instance of one of the processing clusters 2314A-2314N. In at least one embodiment, the processing cluster 2314 can be configured to execute a number of threads in parallel, wherein the term "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0336] In at least one embodiment, the operation of the processing cluster 2314 can be controlled by a pipeline manager 2332 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2332 receives instructions from the scheduler 2310 of FIG. 23 and manages the execution of these instructions via the graphics multiprocessor 2334 and / or texture unit 2336. In at least one embodiment, the graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 2314 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 2314 may include one or more instances of the graphics multiprocessor 2334. In at least one embodiment, the graphics multiprocessor 2334 can process data, and the data cross switch 2340 can be used to distribute the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 2332 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data cross switch 2340.

[0337] In at least one embodiment, each graphics multiprocessor 2334 within the processing cluster 2314 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0338] In at least one embodiment, instructions transmitted to the processing cluster 2314 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2334. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more of the processing engines may be idle during a loop in which the thread group is being processed. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2334, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2334.

[0339] In at least one embodiment, the graphics multiprocessor 2334 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2334 may forgo the internal cache and use a cache memory (e.g., L1 cache 2348) within the processing cluster 2314. In at least one embodiment, each graphics multiprocessor 2334 may also access an L2 cache within partition units (e.g., partition units 2320A-2320N of FIG. 23), which are shared among all processing clusters 2314 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2334 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 2302 may be used as global memory. In at least one embodiment, the processing cluster 2314 includes multiple instances of the graphics multiprocessor 2334, which may share common instructions and data that may be stored in the L1 cache 2348.

[0340] In at least one embodiment, each processing cluster 2314 may include a memory management unit (“MMU”) 2345 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside within the memory interface 2318 of FIG. 23. In at least one embodiment, the MMU 2345 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more about tiles) and cache line indexes (if needed). In at least one embodiment, the MMU 2345 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 2334, the L1 cache 2348, or the processing cluster 2314. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indexes may be used to determine whether a request for a cache line is a hit or a miss.

[0341] In at least one embodiment, the processing cluster 2314 can be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2334, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2334 outputs a processed task to a data crossbar switch 2340 to provide the processed task to another processing cluster 2314 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 2316. In at least one embodiment, a preROP 2342 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2334 and direct the data to a ROP unit, which may be associated with a partitioning unit (e.g., [missing information]). Figure 23A The PreROP 2342 unit is located together with the partitioning units 2320A-2320N. In at least one embodiment, the PreROP 2342 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0342] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11BDetails regarding inference and / or training logic 1115 are provided. In at least one embodiment, inference and / or training logic 1115 may be used in a graphics processing cluster 2314 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0343] Figure 23D A graphics multiprocessor 2334 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 2334 is coupled to a pipeline manager 2332 of a processing cluster 2314. In at least one embodiment, the graphics multiprocessor 2334 has an execution pipeline including, but not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more general-purpose graphics processing unit (GPGPU) cores 2362, and one or more load / store units 2366. In at least one embodiment, the GPGPU cores 2362 and the load / store units 2366 are coupled to a cache memory 2372 and a shared memory 2370 via a memory and cache interconnect 2368.

[0344] In at least one embodiment, instruction cache 2352 receives a stream of instructions to be executed from pipeline manager 2332. In at least one embodiment, instructions are cached in instruction cache 2352 and dispatched to instruction unit 2354 for execution. In one embodiment, instruction unit 2354 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 2362. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 2356 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 2366.

[0345] In at least one embodiment, register file 2358 provides a set of registers for the functional units of graphics multiprocessor 2334. In at least one embodiment, register file 2358 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 2334 (e.g., GPGPU core 2362, load / store unit 2366). In at least one embodiment, register file 2358 is partitioned among each of those functional units, such that a dedicated portion of register file 2358 is allocated to each functional unit. In at least one embodiment, register file 2358 is partitioned among different thread bundles being executed by graphics multiprocessor 2334.

[0346] In at least one embodiment, each of the GPGPU cores 2362 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2334. The GPGPU cores 2362 may be architecturally similar or may differ in architecture. A first portion of the GPGPU core 2362 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2334 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0347] In at least one embodiment, the GPGPU core 2362 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 2362 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0348] In at least one embodiment, the memory and cache interconnect 2368 is an interconnect network connecting each functional unit of the graphics multiprocessor 2334 to the register file 2358 and the shared memory 2370. In at least one embodiment, the memory and cache interconnect 2368 is a cross-switch interconnect that allows the load / store unit 2366 to perform load and store operations between the shared memory 2370 and the register file 2358. In at least one embodiment, the register file 2358 can operate at the same frequency as the GPGPU core 2362, resulting in very low latency for data transfer between the GPGPU core 2362 and the register file 2358. In at least one embodiment, the shared memory 2370 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 2334. In at least one embodiment, the cache memory 2372 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 2336. In at least one embodiment, the shared memory 2370 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 2372, the thread executing on GPGPU core 2362 can also programmatically store data in shared memory.

[0349] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (e.g., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0350] The inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 11A and / or Figure 11BDetails are provided regarding the inference and / or training logic 1115. In at least one embodiment, the inference and / or training logic 1115 may be used in the graphics multiprocessor 2334 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0351] In at least one embodiment, a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling, as well as... Figures 23A to 23D A communication process or part of a system used by other systems.

[0352] Figure 24 A multi-GPU computing system 2400 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 2400 may include a processor 2402 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2406A-D via a host interface switch 2404. In at least one embodiment, the host interface switch 2404 is a PCI Express switch device that couples the processor 2402 to a PCI Express bus, through which the processor 2402 can communicate with the GPGPUs 2406A-D. In at least one embodiment, the GPGPUs 2406A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 2416. In at least one embodiment, the GPU-to-GPU links 2416 are connected to each of the GPGPUs 2406A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 2416 enable direct communication between each GPGPU 2406A-D without communication via the host interface bus 2404 to which the processor 2402 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 2416, the host interface bus 2404 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 2400 via one or more network devices. In at least one embodiment, although the GPGPU 2406A-D is connected to the processor 2402 via the host interface switch 2404, in at least one embodiment, the processor 2402 includes direct support for the P2P GPU link 2416 and can be directly connected to the GPGPU 2406A-D.

[0353] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11BDetails regarding inference and / or training logic 1115 are provided. In at least one embodiment, inference and / or training logic 1115 may be used in a multi-GPU computing system 2400 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0354] In at least one embodiment, as with Figure 24 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0355] Figure 25 This is a block diagram of a graphics processor 2500 according to at least one embodiment. In at least one embodiment, the graphics processor 2500 includes a ring interconnect 2502, a pipeline front end 2504, a media engine 2537, and graphics cores 2580A-2580N. In at least one embodiment, the ring interconnect 2502 couples the graphics processor 2500 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 2500 is one of many processors integrated within a multi-core processing system.

[0356] In at least one embodiment, the graphics processor 2500 receives multiple batches of commands via a ring interconnect 2502. In at least one embodiment, the input commands are interpreted by a command streamer 2503 in a pipeline front-end 2504. In at least one embodiment, the graphics processor 2500 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2580A-2580N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2503 provides the commands to the geometry pipeline 2536. In at least one embodiment, for at least some media processing commands, the command streamer 2503 provides the commands to a video front-end 2534, which is coupled to a media engine 2537. In at least one embodiment, the media engine 2537 includes a video quality engine (VQE) 2530 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 2533 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2536 and the media engine 2537 each generate an execution thread for the thread execution resources provided by at least one graphics core 2580A.

[0357] In at least one embodiment, the graphics processor 2500 includes scalable thread execution resources having modular cores 2580A-2580N (sometimes referred to as core slices), each having multiple sub-cores 2550A-550N, 2560A-2560N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2500 may have any number of graphics cores 2580A to 2580N. In at least one embodiment, the graphics processor 2500 includes a graphics core 2580A having at least a first sub-core 2550A and a second sub-core 2560A. In at least one embodiment, the graphics processor 2500 is a low-power processor having a single sub-core (e.g., 2550A). In at least one embodiment, the graphics processor 2500 includes multiple graphics cores 2580A-2580N, each graphics core including a set of first sub-cores 2550A and 2550N and a set of second sub-cores 2560A-2560N. In at least one embodiment, each of the first sub-cores 2550A-2550N includes at least a first set of execution units 2552A, 2552N and media / texture samplers 2554A-2554N. In at least one embodiment, each of the second sub-cores 2560A-2560N includes at least a second set of execution units 2562A-2562N and samplers 2564A-2564N. In at least one embodiment, each sub-core 2550A-2550N, 2560A, and 2560N shares a set of shared resources 2570A-2570N. In at least one embodiment, the shared resources include a shared cache memory and pixel operation logic.

[0358] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding inference and / or training logic 1115 are provided. In at least one embodiment, inference and / or training logic 1115 may be used in graphics processor 2500 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0359] In at least one embodiment, as with Figure 25 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0360] Figure 26This is a block diagram illustrating a microarchitecture for a processor 2600 according to at least one embodiment, the processor 2600 including logic circuitry for executing instructions. In at least one embodiment, the processor 2600 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2600 may include registers for storing packaged data, such as the 64-bit wide MMX registers used in Intel Corporation's Santa Clara, California-enabled microprocessors employing MMX technology. TM Registers. In at least one embodiment, MMX registers available in integer and floating-point forms can operate alongside packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies can hold such packaged data operands. In at least one embodiment, processor 2610 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0361] In at least one embodiment, processor 2600 includes an ordered front end (“front end”) 2601 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 2601 may include several units. In at least one embodiment, instruction prefetcher 2626 fetches instructions from memory and provides the instructions to instruction decoder 2628, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2628 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 2628 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2630 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 2634 for execution. In at least one embodiment, when trace cache 2630 encounters complex instructions, microcode ROM 2632 provides the micro-instructions required to complete the operation.

[0362] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 2628 may access the microcode ROM 2632 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 2628. In at least one embodiment, if multiple micro-instructions are required to complete an operation, the instructions may be stored in the microcode ROM 2632. In at least one embodiment, the trace cache 2630 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2632 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2632 has completed the micro-operation ordering of the instructions, the machine front end 2601 may resume fetching micro-operations from the trace cache 2630.

[0363] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2603 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2603 includes, but is not limited to, an allocator / register renamer 2640, a memory microinstruction queue 2642, an integer / floating-point microinstruction queue 2644, a memory scheduler 2646, a fast scheduler 2602, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2604, and a simple floating-point scheduler (“simple FP scheduler”) 2606. In at least one embodiment, the fast scheduler 2602, the slow / general-purpose floating-point scheduler 2604, and the simple floating-point scheduler 2606 are also collectively referred to as “microinstruction schedulers 2602, 2604, 2606”. In at least one embodiment, the allocator / register renamer 2640 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 2640 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2640 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 2642 for memory operations and an integer / floating-point microinstruction queue 2644 for non-memory operations, preceding the memory scheduler 2646 and microinstruction schedulers 2602, 2604, and 2606. In at least one embodiment, the microinstruction schedulers 2602, 2604, and 2606 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2602 may schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2604 and the simple floating-point scheduler 2606 may schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 2602, 2604, and 2606 arbitrate the scheduling port to schedule microinstructions for execution.

[0364] In at least one embodiment, execution block b11 includes, but is not limited to, integer register file / tribute network 2608, floating-point register file / tribute network (“FP register file / tribute network”) 2610, address generation units (“AGU”) 2612 and 2614, fast arithmetic logic units (“fast ALU”) 2616 and 2618, slow arithmetic logic unit (“slow ALU”) 2620, floating-point ALU (“FP”) 2622, and floating-point movement unit (“FP movement”) 2624. In at least one embodiment, integer register file / tribute network 2608 and floating-point register file / bypass network 2610 are also referred to herein as “register files 2608, 2610”. In at least one embodiment, AGUs 2612 and 2614, fast ALUs 2616 and 2618, slow ALU 2620, floating-point ALU 2622, and floating-point movement unit 2624 are also referred to herein as "execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624". In at least one embodiment, execution block b11 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0365] In at least one embodiment, register files 2608, 2610 may be arranged between microinstruction schedulers 2602, 2604, 2606 and execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624. In at least one embodiment, integer register file / tribute network 2608 performs integer operations. In at least one embodiment, floating-point register file / tribute network 2610 performs floating-point operations. In at least one embodiment, each of register files 2608, 2610 may include, but is not limited to, a tribute network that can bypass or forward recently completed results not yet written to the register file to a new dependent object. In at least one embodiment, register files 2608, 2610 may communicate data with each other. In at least one embodiment, integer register file / tribute network 2608 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 2610 may include, but is not limited to, entries with a width of 128 bits, since floating-point instructions typically have operands with a width of 64 to 128 bits.

[0366] In at least one embodiment, execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624 can execute instructions. In at least one embodiment, register files 2608 and 2610 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2600 can include, but is not limited to, any number of execution units 2612, 2614, 2616, 2618, 2620, 2622, and 2624, and combinations thereof. In at least one embodiment, floating-point ALU 2622 and floating-point move unit 2624 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2622 can include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2616 and 2618. In at least one embodiment, fast ALUs 2616 and 2618 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to slow ALU 2620, because slow ALU 2620 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUS 2612 and 2614. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2616, fast ALU 2618, and slow ALU 2620 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2622 and the floating-point moving unit 2624 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0367] In at least one embodiment, microinstruction schedulers 2602, 2604, and 2606 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 2600, processor 2600 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0368] In at least one embodiment, "register" can refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register can be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0369] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, some or all of the inference and / or training logic 1115 may be incorporated into execution block 2611 along with other memory or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 2611. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2611 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0370] In at least one embodiment, as with Figure 26A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0371] Figure 27 A deep learning application processor 2700 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2700 uses instructions, which, if executed by the deep learning application processor 2700, cause the deep learning application processor 2700 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2700 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2700 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2700 includes, but is not limited to, processing clusters 2710(1)-2710(12), inter-chip links (“ICL”) 2720(1)-2720(12), inter-chip controllers (“ICC”) 2730(1)-2730(2), second-generation high-bandwidth memory (“HBM2”) 2740(1)-2740(4), memory controllers (“Mem Ctrlr”) 2742(1)-2742(4), high-bandwidth memory physical layers (“HBM PHY”) 2744(1)-2744(4), management controller central processing unit (“management controller CPU”) 2750, serial peripheral device interfaces, internal integrated circuits and general purpose input / output blocks (“SPI, I2C, GPIO”) 2760, peripheral component interconnect fast controller and direct memory access block (“PCIe controller and DMA”) 2770, and sixteen-channel peripheral component interconnect fast port (“PCI Express x”). 16”2780.

[0372] In at least one embodiment, processing cluster 2710 can perform deep learning operations, including inference or prediction operations based on weight parameters computed at least in part based on one or more training techniques (including those described herein). In at least one embodiment, each processing cluster 2710 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2700 can include any number and type of processing cluster 2700. In at least one embodiment, inter-chip link 2720 is bidirectional. In at least one embodiment, inter-chip link 2720 and inter-chip controller 2730 enable multiple deep learning application processors 2700 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2700 can include any number (including zero) and type of ICL 2720 and ICC 2730.

[0373] In at least one embodiment, the HBM2 2740 provides a total of 32 GB of memory. In at least one embodiment, the HBM2 2740(i) is associated with both the memory controller 2742(i) and the HBM PHY 2744(i). In at least one embodiment, any number of HBM2 2740s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2742 and HBM PHY 2744. In at least one embodiment, any number and type of blocks can replace SPI, I2C, GPIO 3360, PCIe controller 2760 and DMA 2770 and / or PCIe 2780 to implement any number and type of communication standards in any technically feasible manner.

[0374] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2700. In at least one embodiment, the deep learning application processor 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2700. In at least one embodiment, the processor 2700 may be used to perform one or more neural network use cases described herein.

[0375] Figure 28This is a block diagram of a neuromorphic processor 2800 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2800 may receive one or more inputs from a source external to the neuromorphic processor 2800. In at least one embodiment, these inputs may be transmitted to one or more neurons 2802 within the neuromorphic processor 2800. In at least one embodiment, the neurons 2802 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, thousands upon thousands of instances of neurons 2802, but any suitable number of neurons 2802 may be used. In at least one embodiment, each instance of a neuron 2802 may include a neuron input 2804 and a neuron output 2806. In at least one embodiment, a neuron 2802 may generate an output that can be transmitted to the inputs of other instances of the neuron 2802. In at least one embodiment, the neuron input 2804 and the neuron output 2806 may be interconnected via synapses 2808.

[0376] In at least one embodiment, neuron 2802 and synapse 2808 may be interconnected, causing neuromorphic processor 2800 to operate to process or analyze information received by neuromorphic processor 2800. In at least one embodiment, neuron 2802 may send an output pulse (or “trigger” or “peak”) when the input received through neuron input 2804 exceeds a threshold. In at least one embodiment, neuron 2802 may sum or integrate the signal received at neuron input 2804. For example, in at least one embodiment, neuron 2802 may be implemented as a leaky integral-triggered neuron, wherein if the summation (referred to as “membrane potential”) exceeds a threshold, neuron 2802 may use a transfer function such as a sigmoid or threshold function to generate an output (or “trigger”). In at least one embodiment, the leaky integral-triggered neuron may sum the signal received at neuron input 2804 to a membrane potential and may apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaking integral-triggered neuron may trigger if multiple input signals are received at neuron input 2804 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2802 may be implemented using circuitry or logic that receives input, integrates the input to the membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2802 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2806 when the result of applying the transfer function to neuron input 2804 exceeds a threshold. In at least one embodiment, once neuron 2802 is triggered, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2802 may resume normal operation after a suitable period of time (or recovery period).

[0377] In at least one embodiment, neurons 2802 can be interconnected via synapses 2808. In at least one embodiment, synapses 2808 can be operated to transmit signals from the output of a first neuron 2802 to the input of a second neuron 2802. In at least one embodiment, neurons 2802 can transmit information on more than one instance of synapses 2808. In at least one embodiment, one or more instances of neuron outputs 2806 can be connected via instances of synapses 2808 to instances of neuron inputs 2804 in the same neuron 2802. In at least one embodiment, an instance of neuron 2802 that produces an output to be transmitted on the instance of synapse 2808 can be referred to as a "presynaptic neuron". In at least one embodiment, an instance of neuron 2802 that receives input transmitted via an instance of synapse 2808 can be referred to as a "postsynaptic neuron". In at least one embodiment, regarding various instances of synapse 2808, since an instance of neuron 2802 can receive input from one or more instances of synapse 2808 and can also transmit output through one or more instances of synapse 2808, a single instance of neuron 2802 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0378] In at least one embodiment, neurons 2802 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2802 may have a neuron output 2806, which may fan out to one or more neuron inputs 2804 via one or more synapses 2808. In at least one embodiment, the neuron output 2806 of neuron 2802 in the first layer 2810 may be connected to the neuron input 2804 of neuron 2802 in the second layer 2812. In at least one embodiment, layer 2810 may be referred to as a “feedforward layer.” In at least one embodiment, each instance of neuron 2802 in an instance of the first layer 2810 may fan out to each instance of neuron 2802 in the second layer 2812. In at least one embodiment, the first layer 2810 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each instance of neuron 2802 in an instance of the second layer 2812 fan out to fewer than all instances of neuron 2802 in the third layer 2814. In at least one embodiment, the second layer 2812 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2802 in the second layer 2812 may fan out to neurons 2802 in multiple other layers, including neurons 2802 fan out to (the same) second layer 2812. In at least one embodiment, the second layer 2812 may be referred to as a “recurrent layer.” The neuromorphic processor 2800 may include, but is not limited to, any suitable combination of recurrent layers and feedforward layers, including, but not limited to, sparsely connected feedforward layers and fully connected feedforward layers.

[0379] In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect synapses 2808 to neurons 2802. In at least one embodiment, the neuromorphic processor 2800 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2802 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2808 may be connected to neurons 2802 using interconnect structures such as on-chip networks or via dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0380] Figure 29This is a block diagram of a graphics processor 2900, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2900 communicates with registers on the graphics processor 2900 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2900 includes a memory interface 2914 for accessing memory. In at least one embodiment, the memory interface 2914 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0381] In at least one embodiment, the graphics processor 2900 further includes a display controller 2902 for driving display output data to the display device 2920. In at least one embodiment, the display controller 2902 includes a combination of hardware for one or more overlay planes of the display device 2920 and multi-layer video or user interface elements. In at least one embodiment, the display device 2920 may be an internal or external display device. In at least one embodiment, the display device 2920 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2900 includes a video codec engine 2906 for encoding, decoding, or transcoding media into, from, or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC, and SMPTE 421M / VC-1), and Joint Picture Experts Group (JPEG) formats (e.g., JPEG) and MotionJPEG (MJPEG).

[0382] In at least one embodiment, the graphics processor 2900 includes a block image transfer (BLIT) engine 2904 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in at least one embodiment, one or more components of a graphics processing engine (GPE) 2910 are used to perform 2D graphics operations. In at least one embodiment, the GPE 2910 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0383] In at least one embodiment, GPE 2910 includes a 3D pipeline 2912 for performing 3D operations, such as rendering 3D images and scenes using processing functions that manipulate 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, 3D pipeline 2912 includes programmable and fixed function elements that perform various tasks and / or generate execution threads to 3D / media subsystem 2915. While 3D pipeline 2912 can be used to perform media operations, in at least one embodiment, GPE 2910 also includes a media pipeline 2916 for performing media operations such as video post-processing and image enhancement.

[0384] In at least one embodiment, the media pipeline 2916 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, replacing or representing the video codec engine 2906. In at least one embodiment, the media pipeline 2916 also includes a thread generation unit for generating threads to execute on the 3D / media subsystem 2915. In at least one embodiment, the generated threads perform computations of media operations on one or more graphics execution units included in the 3D / media subsystem 2915.

[0385] In at least one embodiment, the 3D / media subsystem 2915 includes logic for executing threads generated by the 3D pipeline 2912 and the media pipeline 2916. In at least one embodiment, the 3D pipeline 2912 and the media pipeline 2916 send thread execution requests to the 3D / media subsystem 2915, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2915 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2915 also includes shared memory, including registers and addressable memory, for sharing data among threads and storing output data.

[0386] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A and / or Figure 11B Details regarding the inference and / or training logic 1115 are provided. In at least one embodiment, some or all of the inference and / or training logic 1115 may be incorporated into the processor 2900. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs included in the 3D pipeline 2912. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, except for... Figure 11A or Figure 11B The logic other than that shown is used to perform the task. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2900 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0387] Figure 30 This is a block diagram of a graphics processing engine 3010 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 3010 is... Figure 29 The version of GPE 2910 shown is illustrated. In at least one embodiment, the media pipeline 2916 may not be explicitly included in GPE 3010. In at least one embodiment, a separate media and / or image processor is coupled to GPE 3010.

[0388] In at least one embodiment, GPE 3010 is coupled to or includes command stream converter 3003, which provides command streams to 3D pipeline 2912 and / or media pipeline 2916. In at least one embodiment, command stream converter 3003 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command stream converter 3003 receives commands from memory and sends the commands to 3D pipeline 3012 and / or media pipeline 3016. In at least one embodiment, the commands are instructions, primitives, or micro-operations retrieved from a circular buffer that stores commands for 3D pipeline 2912 and media pipeline 2916. In at least one embodiment, the circular buffer may further include a batch command buffer storing multiple commands in batches. In at least one embodiment, commands for 3D pipeline 2912 may further include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2912 and / or image data and memory objects for media pipeline 2916. In at least one embodiment, the 3D pipeline 2912 and the media pipeline 2916 process commands and data by performing operations or by dispatching one or more execution threads to the graphics core array 3014. In at least one embodiment, the graphics core array 3014 includes one or more graphics core blocks (e.g., one or more graphics cores 3015A, one or more graphics cores 3015B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources, including general-purpose and graphics-specific execution logic for performing graphics and computation operations, and fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic, including... Figure 11Aand Figure 11B The reasoning and / or training logic in 1115.

[0389] In at least one embodiment, the 3D pipeline 2912 includes fixed functions and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 3014. In at least one embodiment, the graphics core array 3014 provides a unified execution resource block for processing shader programs. In at least one embodiment, the multipurpose execution logic (e.g., execution units) within the graphics cores 3015A-3015B of the graphics core array 3014 includes support for various 3D API shader languages ​​and can execute multiple concurrently running threads associated with multiple shaders.

[0390] In at least one embodiment, the graphics core array 3014 further includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution unit also includes general-purpose logic programmable to perform parallel general-purpose computing operations.

[0391] In at least one embodiment, output data can be output to memory in a unified return buffer (URB) 3018, the output data being generated by a thread executing on the graphics core array 3014. In at least one embodiment, the URB 3018 can store data from multiple threads. In at least one embodiment, the URB 3018 can be used to send data between different threads executing on the graphics core array 3014. In at least one embodiment, the URB 3018 can also be used for synchronization between threads on the graphics core array 3014 and fixed-function logic within shared-function logic 3020.

[0392] In at least one embodiment, the graphics core array 3014 is scalable, such that it includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 3010. In at least one embodiment, the execution resources are dynamically scalable, such that they can be enabled or disabled as needed.

[0393] In at least one embodiment, the graphics core array 3014 is coupled to shared function logic 3020, which includes multiple resources shared among the graphics cores in the graphics core array 3014. In at least one embodiment, the shared functions performed by the shared function logic 3020 are embodied in hardware logic units that provide dedicated supplementary functions to the graphics core array 3014. In at least one embodiment, the shared function logic 3020 includes, but is not limited to, a sampler unit 3021, a math unit 3022, and inter-thread communication (ITC) logic 3023. In at least one embodiment, one or more caches 3025 are included in or coupled to the shared function logic 3020.

[0394] In at least one embodiment, shared functionality is used if the demand for dedicated functionality is insufficient to be contained within the graphics core array 3014. In at least one embodiment, a single instance of the dedicated functionality is used in shared functionality logic 3020 and shared among other execution resources within the graphics core array 3014. In at least one embodiment, a specific shared functionality may be included within shared functionality logic 3016 within the graphics core array 3014, said specific shared functionality being widely used within shared functionality logic 3020 of the graphics core array 3014. In at least one embodiment, shared functionality logic 3016 within the graphics core array 3014 may include some or all of the logic within shared functionality logic 3020. In at least one embodiment, all logic elements within shared functionality logic 3020 may be replicated within shared functionality logic 3026 of the graphics core array 3014. In at least one embodiment, shared functionality logic 3020 is excluded to support shared functionality logic 3026 within the graphics core array 3014.

[0395] Inference and / or training logic 1115 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 11A 11B and / or 11B provide details about the inference and / or training logic 1115. In at least one embodiment, some or all of the inference and / or training logic 1115 may be incorporated into the graphics processor 2900. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in the 3D pipeline 3012, graphics core 3015, shared function logic 3026, shared function logic 3020, or... Figure 30 In other logic within the [unclear context]. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use [unclear context]. Figure 11A or Figure 11BThe logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 3010 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0396] In at least one embodiment, as with Figure 30 A communication process or part of a system used together with a GPU-based scrambling / descrambling unit can be used to perform scrambling and / or descrambling.

[0397] Figure 31 This is a block diagram of the hardware logic of a graphics processor core 3100 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 3100 is included within a graphics core array. In at least one embodiment, the graphics processor core 3100 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 3100 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 3100 may include a fixed-function block 3130, also referred to as a sub-slice, coupled to a plurality of sub-cores 3101A-3101F, which includes modules of general-purpose and fixed-function logic.

[0398] In at least one embodiment, the fixed-function block 3130 includes a geometry and fixed-function pipeline 3136, which, for example, may be shared by all sub-cores of the graphics processor 3100 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry fixed-function pipeline 3136 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0399] In at least one fixed embodiment, the fixed functional block 3130 further includes a graphics SoC interface 3137, a graphics microcontroller 3138, and a media pipeline 3139. In at least one embodiment, the graphics SoC interface 3137 provides an interface between the graphics core 3100 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 3138 is a programmable subprocessor configurable to manage various functions of the graphics processor 3100, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 3139 includes logic that facilitates decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 3139 implements media operations via requests for computation or sampling logic within subcores 3101-3101F.

[0400] In at least one embodiment, the SoC interface 3137 enables the graphics core 3100 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 3137 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 3100 and the CPU within the SoC. In at least one embodiment, the graphics SoC interface 3137 also implements power management control for the graphics processor core 3100 and enables interfacing between the clock domain of the graphics processor core 3100 and other clock domains within the SoC. In at least one embodiment, the SoC interface 3137 enables the receipt of command buffers from a command stream converter and a global thread dispatcher, configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to the media pipeline 3139, or when a graphics processing operation is to be performed, they can be assigned to the geometry and fixed-function pipeline (e.g., geometry and fixed-function pipeline 3136, geometry and fixed-function pipeline 3114).

[0401] In at least one embodiment, the graphics microcontroller 3138 can be configured to perform various scheduling and management tasks on the graphics core 3100. In at least one embodiment, the graphics microcontroller 3138 can perform graphics and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 3102A-3102F, 3104A-3104F in subcores 3101A-3101F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 3100 can submit a workload of one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 3138 may also facilitate a low-power or idle state of the graphics core 3100, thereby providing the graphics core 3100 with the ability to save and restore registers across low-power state transitions within the graphics core 3100, independent of the operating system and / or the graphics driver software on the system.

[0402] In at least one embodiment, the graphics core 3100 may have more than or less than the equivalent of N modular sub-cores compared to the sub-cores 3101A-3101F shown. For each group of N sub-cores, in at least one embodiment, the graphics core 3100 may further include shared functional logic 3110, shared and / or cache memory 3112, geometry / fixed-function pipeline 3114, and additional fixed-function logic 3116 to accelerate various graphics and computational processing operations. In at least one embodiment, the shared functional logic 3110 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 3100. In at least one embodiment, the shared and / or cache memory 3112 may be the last-level cache of the N sub-cores 3101A-3101F within the graphics core 3100, and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, a geometry / fixed function pipeline 3114 may be included to replace the geometry / fixed function pipeline 3136 within the fixed function block 3130, and similar logic units may...

Claims

1. A method comprising: At least in part, multiple threads of a plurality of one-to-many linear feedback shift registers (LFSRs) are operated by a plurality of parallel processing units (PPUs) to generate a descrambling sequence derived from a plurality of many-to-one LFSRs, wherein the plurality of one-to-many LFSRs are advanced by different numbers of loops between the plurality of threads.

2. The method of claim 1, wherein the descrambling sequence is a pseudo-random bit sequence, and the pseudo-random bit sequence is a function of the user identifier of the user equipment that has transmitted the input data sequence and the base station identifier of the base station that has received the input data sequence.

3. The method of claim 2, further comprising: The descrambled sequence is stored in the shared memory of the PPU as a stored descrambled sequence associated with the sequence user identifier and the sequence base station identifier; Determine the user identifier and the base station identifier for the subsequent input data sequence; Determine whether the user identifier is equal to the sequence user identifier; Determine whether the base station identifier is equal to the sequence base station identifier; as well as If the user identifier is equal to the sequence user identifier and the base station identifier is equal to the sequence base station identifier, then the stored descrambling sequence is used to descramble the subsequent scrambled input data sequence.

4. The method of claim 1, further comprising: The descrambled sequence is stored in the shared memory of the PPU; Determine the bit size of the descrambling sequence; Determine the data width of the thread; as well as The number of allocated threads for generating the descrambling sequence is determined based on the bit size of the descrambling sequence and the data width of the thread, the number of allocated threads being sufficient to descramble at least as many input data values ​​as the bit size of the descrambling sequence in parallel.

5. The method of claim 1, further comprising: The descrambled sequence is stored in the shared memory of the PPU; Determine the bit size of the descrambling sequence; Determine the data width of the thread; Based on the bit size of the descrambling sequence and the data width of the thread, determine the number of allocated threads for generating the multiple thread blocks of the descrambling sequence, the number of allocated threads being sufficient to descramble at least as many input data values ​​as the bit size of the descrambling sequence in parallel; Read the array of input data values ​​into the thread's local memory; Read the descrambled segment from the shared memory; as well as The array of input data values ​​is descrambled using the descrambling segment.

6. The method of claim 1, wherein the PPU is an element of a cellular network base station.

7. The method of claim 1, further comprising: An initialization value for a first loop process is obtained from a first generator polynomial used to generate the descrambled sequence, wherein the first loop process generates the descrambled sequence in a loop and the first generator polynomial corresponds to the many-to-one LFSR having a first feedback mode in which multiple register values ​​are fed back to a single input of the many-to-one LFSR. A second cyclic process, represented by the one-to-many LFSR, is determined, and the process is converted from the first feedback mode to a second feedback mode represented by a second generator polynomial, in which a single input of the one-to-many LFSR is fed back to multiple stages of the one-to-many LFSR according to the second generator polynomial. Multiple threads of the PPU are initialized to process at least a portion of the second loop process; The first thread of the plurality of threads is initialized to operate the first thread LFSR, wherein the first thread LFSR is initialized to a first position in the descrambling sequence by performing polynomial multiplication and modulo on the second generator polynomial and a first monomial of the first order corresponding to the first position; The second thread among the plurality of threads is initialized to operate the second thread LFSR, wherein the second thread LFSR is initialized to a second position in the descrambling sequence by performing polynomial multiplication and modulo on the second generator polynomial and a second monomial having a second order corresponding to the second position, wherein the first position and the second position are different; as well as The first output of the first thread and the second output of the second thread are stored in the shared memory of the PPU as at least part of the descrambling sequence.

8. A parallel processing unit (PPU), comprising: One or more circuits are used to operate multiple one-to-many LFSRs, at least in part, based on multiple threads of one or more PPUs, to generate descrambled sequences derived from one or more many-to-one LFSRs, wherein the multiple one-to-many LFSRs are advanced by different numbers of loops between the multiple threads.

9. The PPU of claim 8, wherein the descrambling sequence is defined by a generator polynomial and a Fibonacci LFSR, and one or more circuits generate the descrambling sequence by operating each of the multiple threads of the PPU to generate a descrambling segment of the descrambling sequence.

10. The PPU as claimed in claim 8, wherein, The one or more circuits use the descrambling sequence by performing an XOR operation on the output of the first LFSR and the output of the second LFSR.

11. The PPU as claimed in claim 8, wherein, The one or more circuits use two or more threads to execute the descrambling sequence by performing a bitwise XOR operation on the output of the first Fibonacci LFSR and the output of the second Fibonacci LFSR.

12. The PPU as claimed in claim 8, wherein, The one or more circuits execute the cyclic progression of the LFSR in parallel on the plurality of threads of the PPU, wherein each descrambling segment of the descrambling sequence is output by at least one of the plurality of threads.

13. A computer-readable medium having a set of instructions stored thereon, which, when executed by one or more processors, cause the one or more processors to perform the following operations: At least in part, multiple threads of one or more PPUs operate on multiple one-to-many LFSRs to generate descrambled sequences derived from one or more many-to-one LFSRs, wherein, The multiple one-to-many LFSRs are advanced by varying numbers of loops between the multiple threads.

14. The computer-readable medium of claim 13, wherein the descrambling sequence is 1024 bits, the plurality of threaded hardware units includes 32 threaded hardware units, and one or more descrambling segments are 32 bits wide, and wherein the first array location and the second array location are word-length memory locations in shared memory.

15. The computer-readable medium of claim 13, wherein the descrambling sequence is a pseudo-random bit sequence, the pseudo-random bit sequence being a function of the user identifier of the user equipment that has transmitted the input data sequence and the base station identifier of the base station that has received the input data sequence.

16. The computer-readable medium of claim 13, wherein, When these instructions are executed by the one or more processors, the one or more processors are configured to cause the following operations to be performed: The global memory of the PPU is accessible to both the first-thread hardware unit and the second-thread hardware unit; and The global memory stores sequence identifiers, including sequence user identifiers and sequence base station identifiers associated with an array of descrambling segments. This storage can be used to match user identifiers of subsequent input data sequences with the sequence user identifiers, and to match base station identifiers of the subsequent input data sequences with the sequence base station identifiers. If the user identifier is equal to the sequence user identifier and the base station identifier is equal to the sequence base station identifier, then the array of descrambling segments is provided for descrambling the subsequent input data sequences.

17. The computer-readable medium of claim 13, wherein when the instructions are executed by the one or more processors, the one or more processors are configured to perform the operation of allocating two or more threads to generate the descrambling sequence.

18. The computer-readable medium of claim 13, wherein when the instructions are executed by the one or more processors, the one or more processors are configured to perform the following operation: allocate two or more threads to generate the descrambling sequence based on the bit size of the descrambling sequence, the data width of the allocated two or more threads, and / or the number of allocated threads sufficient to generate the bits of the descrambling sequence in parallel.

19. A system comprising: One or more processors are configured to operate multiple one-to-many LFSRs, at least in part based on multiple threads of one or more PPUs, to generate descrambling sequences derived from one or more many-to-one LFSRs, wherein the multiple one-to-many LFSRs are advanced by varying numbers of loops between the multiple threads.

20. The system of claim 19, wherein the generated descrambling sequence comprises a bit sequence to be used for XOR operation to descramble the input data.

21. The system of claim 19, wherein, The one or more processors cause each thread of the PPU to compute a different set of bits for the descrambled sequence.

22. The system of claim 19, wherein, The one or more processors will derive the descrambling sequence from one or more Fibonacci LFSRs, which are generated by multiple threads of the PPU using Galois LFSRs.

23. The system of claim 19, wherein, The PPU is part of the Software-Defined Radio Access Network (RAN) interface.

24. The system of claim 19, wherein the descrambling sequence is a pseudo-random bit sequence, which is a function of the user identifier of the user equipment that has transmitted the input data sequence and the base station identifier of the base station that has received the input data sequence.

25. The system of claim 19, wherein the descrambling sequence is 1024 bits, the first descrambling segment is 32 bits, the second descrambling segment is 32 bits, and wherein 32 thread hardware units operate in parallel.

26. The system of claim 19, wherein, The descrambling sequence is 1024 bits, with 32 thread hardware units operating in block parallel mode, using the instruction set shared by the 32 thread hardware units for each operation.

27. The system of claim 19, wherein the descrambling sequence is a pseudo-random bit sequence, the pseudo-random bit sequence being a function of the user identifier of the user equipment that has sent the input data sequence to be descrambled and the base station identifier of the base station that has received the input data sequence.

28. The system of claim 19, wherein, The one or more processors utilize each of two or more threads of the PPU to compute different bit sets of the descrambling sequence, thereby enabling the two or more threads to generate the descrambling sequence in parallel.

29. The system of claim 19, wherein the plurality of threaded hardware units of the PPU include elements of a cellular network base station.

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