Three-dimensional memory devices, systems, and methods for forming the same

Abstract

A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and an array of NAND memory strings. The second semiconductor structure is below a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite a first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit includes a first transistor in contact with a first side of the second semiconductor layer. The second peripheral circuit includes a second transistor in contact with a second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite the first side of the second semiconductor layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to International Application No. PCT / CN2021 / 103762, filed on June 30, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to memory devices and methods of manufacturing the same, and more particularly to three-dimensional (3D) memory devices and methods of manufacturing the same. Background Technology

[0004] Planar memory cells can be miniaturized to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density of planar memory cells is approaching its upper limit.

[0005] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0006] This article discloses the implementation methods and formation methods of 3D memory devices.

[0007] In one aspect, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and a NAND flash memory string array. The source of the NAND flash memory string array is in contact with a first side of the first semiconductor layer. The second semiconductor structure is located below a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the NAND flash memory string array, and a second peripheral circuit of the NAND flash memory string array. The first peripheral circuit includes a first transistor in contact with the first side of the second semiconductor layer. The second peripheral circuit includes a second transistor in contact with the second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite to the first side of the second semiconductor layer.

[0008] In some embodiments, the first semiconductor layer is located between the NAND flash memory string array and a first peripheral circuitry of the NAND flash memory string array. In some embodiments, the first semiconductor layer includes a polysilicon layer.

[0009] In some embodiments, the second semiconductor layer includes a silicon substrate. In some embodiments, the second semiconductor structure further includes a first interconnect layer and a second interconnect layer, such that a first peripheral circuit is located between the first interconnect layer and a first side of the second semiconductor layer, and a second peripheral circuit is located between the second interconnect layer and a second side of the second semiconductor layer.

[0010] In some embodiments, the second semiconductor structure further includes a first through-substrate via electrically connected between the first interconnect layer and the second interconnect layer. In some embodiments, the first semiconductor structure further includes a first contact structure electrically connected between the first interconnect layer and multiple word lines of the NAND memory string array. In some embodiments, the first contact structure penetrates the first semiconductor layer.

[0011] In some embodiments, the second semiconductor structure further includes a pad lead-out structure, with the second peripheral circuitry of the NAND memory string array located between the pad lead-out structure and a second side of the second semiconductor structure.

[0012] In some embodiments, the first semiconductor structure further includes a pad lead-out structure, with the NAND memory string array located between the pad lead-out structure and a first side of the first semiconductor layer.

[0013] In some embodiments, the first transistor includes a first gate dielectric, the second transistor includes a second gate dielectric, and the thickness of the first gate dielectric is greater than the thickness of the second gate dielectric. In some embodiments, the difference between the thicknesses of the first and second gate dielectrics is at least five times.

[0014] In another aspect, a system includes a memory device configured to store data. The memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and a NAND flash memory string array. The source of the NAND flash memory string array is in contact with a first side of the first semiconductor layer. The second semiconductor structure is below a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, first peripheral circuitry for the NAND flash memory string array, and second peripheral circuitry for the NAND flash memory string array. The first peripheral circuitry includes a first transistor in contact with the first side of the second semiconductor layer. The second peripheral circuitry includes a second transistor in contact with the second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite to the first side of the second semiconductor layer. The system also includes a memory controller coupled to the memory device and configured to control the memory cell array via the first and second peripheral circuitry.

[0015] In another aspect, a method for forming a 3D memory device is disclosed. A first transistor is formed on a first side of a substrate. A semiconductor layer is formed on the first transistor on the first side of the substrate. A NAND memory string array is formed on the semiconductor layer. A second transistor is formed on a second side of the substrate opposite to the first side.

[0016] In some embodiments, a first interconnect layer is formed on the first transistor. In some embodiments, a polysilicon layer is formed on top of the first interconnect layer.

[0017] In some implementations, the substrate is thinned before the second transistor is formed.

[0018] In some embodiments, a pad lead-out structure is formed above the NAND memory string array on a first side of the substrate. In some embodiments, a first contact structure is formed prior to the formation of the pad lead-out structure, and the first contact structure is electrically connected between the first interconnect layer and the pad lead-out structure.

[0019] In some embodiments, a pad lead-out structure is formed above the second transistor on the second side of the substrate. In some embodiments, a through-substrate via is formed extending through the substrate. In some embodiments, the through-substrate via electrically connects the first interconnect layer and the second interconnect layer. Attached Figure Description

[0020] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0021] Figure 1 A schematic diagram of a cross-section of a 3D memory device according to some aspects of this disclosure is shown.

[0022] Figure 2 A schematic circuit diagram of a memory device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0023] Figure 3 A block diagram of a memory device including a memory cell array and peripheral circuitry, according to some aspects of this disclosure, is shown.

[0024] Figure 4A Block diagrams of peripheral circuits with various voltages provided according to some aspects of this disclosure are shown.

[0025] Figure 4B A schematic diagram is shown of peripheral circuits with various voltages arranged in a discrete semiconductor structure, according to some aspects of this disclosure.

[0026] Figure 5A and Figure 5B Perspective and side views of a planar transistor according to some aspects of this disclosure are shown respectively.

[0027] Figure 6A and Figure 6B Perspective and side views of 3D transistors according to some aspects of this disclosure are shown respectively.

[0028] Figure 7 Circuit diagrams of word line drivers and page buffers according to some aspects of this disclosure are shown.

[0029] Figure 8 A side view of a NAND memory string in a 3D memory device according to some aspects of this disclosure is shown.

[0030] Figure 9A and Figure 9B A schematic diagram of the cross-section of a 3D memory device with different pad lead-out structures according to various aspects of this disclosure is shown.

[0031] Figure 10A and Figure 10B The various aspects of this disclosure are shown. Figure 9A and Figure 9B Side view of various examples of 3D memory devices.

[0032] Figure 11-16 This disclosure illustrates some aspects of the formation of Figure 10A The manufacturing process of 3D memory devices.

[0033] Figure 17 This disclosure illustrates some aspects of the formation of Figure 11-16 A flowchart of a method for creating a 3D memory device.

[0034] Figure 18-23 This disclosure illustrates some aspects of the formation of Figure 10B The manufacturing process of 3D memory devices.

[0035] Figure 24 A block diagram of an exemplary system having a memory device is shown, according to some aspects of this disclosure.

[0036] Figure 25A A view of an exemplary memory card having a memory device is shown, according to some aspects of this disclosure.

[0037] Figure 25BA view of an exemplary solid-state drive (SSD) having a memory device is shown, according to some aspects of this disclosure.

[0038] The contents of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0039] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other in a manner not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0040] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "described" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the presence of other factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0041] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with an intermediate feature or layer, and “above” or “on top of” means not only “above” or “on top of” but also includes “on” or “on top of” without an intermediate feature or layer (i.e., directly on).

[0042] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” and “above” may be used herein to describe the relationship between an element or feature as shown in the figures and one or more other elements or features. In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted accordingly.

[0043] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias are formed) and one or more dielectric layers.

[0044] As 3D memory devices (e.g., 3D NAND flash memory devices) evolve, the more layers are stacked (e.g., more word lines and more resulting memory cells), the more peripheral circuitry (and components forming that peripheral circuitry, such as transistors) is required to operate the 3D memory device. For example, the number and / or size of page buffers need to increase to match the increased number of memory cells. In another example, the number of string drivers in the word line drivers is proportional to the number of word lines in the 3D NAND flash memory. Therefore, the continuous increase in word lines also increases the area occupied by the word line drivers, the complexity of the metal wiring, and sometimes even the number of metal layers. Furthermore, in some 3D memory devices where the memory cell array and peripheral circuitry are fabricated on different substrates and bonded together, the continuous increase in the area of ​​the peripheral circuitry makes it a bottleneck for reducing the overall chip size, since the memory cell array can be vertically scaled up by increasing the number of layers rather than increasing the planar size.

[0045] Therefore, it is desirable to reduce the planar area occupied by the peripheral circuitry of 3D memory devices as the number of peripheral circuits and their transistors increases. However, following the trend of advanced complementary metal-oxide-semiconductor (CMOS) technology nodes for logic devices, scaling down the transistor size of peripheral circuitry would result in a significant increase in cost and higher leakage current, which is undesirable for memory devices. Furthermore, because 3D NAND flash memory devices require relatively high voltages (e.g., above 5V) for certain memory operations (e.g., programming and erasing), unlike logic devices whose operating voltages can be reduced with advancements in CMOS technology nodes, the voltage supplied to the memory peripheral circuitry cannot be reduced. Therefore, scaling down the size of memory peripheral circuitry by following the development trends of CMOS technology nodes (as with conventional logic devices) becomes impractical.

[0046] To address one or more of the aforementioned problems, this disclosure introduces various solutions in which the peripheral circuitry of the memory device is arranged in different planes (levels, tiers) in the vertical direction, i.e., formed vertically above each other, to reduce the planar chip size of the peripheral circuitry and the overall chip size of the memory device. In some embodiments, memory cell arrays (e.g., NAND flash memory strings), memory peripheral circuitry providing relatively high voltages (e.g., above 5V), and memory peripheral circuitry providing relatively low voltages (e.g., below 1.3V) are arranged in different planes in the vertical direction, i.e., formed vertically above each other, to further reduce the chip size. Furthermore, in some embodiments, memory peripheral circuitry providing relatively high voltages (e.g., above 5V) and memory peripheral circuitry providing relatively low voltages (e.g., below 1.3V) are arranged on opposite sides of the same substrate to further reduce the chip size. The 3D memory device architecture and manufacturing process disclosed in this disclosure can be easily vertically scaled up to stack more peripheral circuitry in different planes to further reduce the chip size.

[0047] Based on different performance requirements, such as the voltage applied to the transistors in the peripheral circuitry (which affects the transistor dimensions (e.g., gate dielectric thickness), the dimensions of the substrate in which the transistors are formed (e.g., substrate thickness), and the thermal budget (e.g., interconnect material)), the peripheral circuitry can be separated into different planes in the vertical direction. Therefore, peripheral circuitry with different dimensional requirements (e.g., gate dielectric thickness and substrate thickness) and thermal budgets can be fabricated in different processes to reduce design and process constraints on each other, thereby improving device performance and manufacturing complexity.

[0048] According to some aspects of this disclosure, a first layer of memory peripheral circuitry can be formed on a first side of a substrate, and a memory cell array can be formed on the memory peripheral circuitry on the same side of the substrate. Next, the substrate can be flipped and thinned, and a second layer of memory peripheral circuitry can be formed on a second side of the substrate opposite to the first side. As a result, the fabrication size of the memory peripheral circuitry can be doubled on a single substrate to reduce chip size and manufacturing costs. Furthermore, the second layer of memory peripheral circuitry can be a low-voltage memory peripheral circuitry providing a relatively low voltage (e.g., below 1.3V) and can be formed after the fabrication of the memory cell array. Therefore, the low-voltage memory peripheral circuitry will not be affected by the high temperatures during the fabrication of the memory cell array. Furthermore, the channel length of the low-voltage memory peripheral circuitry can be reduced, and the input / output (I / O) speed of the memory device can also be improved. In some embodiments, the channel length of the low-voltage memory peripheral circuitry can be further minimized.

[0049] The 3D memory device architecture and manufacturing process disclosed in this disclosure also offer flexibility to allow various device pad lead-out schemes to meet different needs and designs of memory cell arrays. In some embodiments, the pad lead-out interconnect layer is formed from the side of the semiconductor structure with peripheral circuitry to shorten the interconnect distance between the pad lead-out interconnect layer and the transistors of the peripheral circuitry, thereby reducing parasitic capacitance from the interconnect and improving electrical performance. In some embodiments, the pad lead-out interconnect layer is formed on the side of the semiconductor structure with memory cell arrays to enable interlayer vias (LLVs, e.g., submicron scale) with high I / O throughput and low manufacturing complexity.

[0050] Figure 1 A schematic cross-sectional view of a 3D memory device 100 according to some aspects of this disclosure is shown. The 3D memory device 100 represents an example of a periphery under cell (PUC) structure. In some embodiments, peripheral circuitry 104 may first be formed on a substrate 102, and then a memory cell array 106 may be formed on the peripheral circuitry 104. In some embodiments, peripheral circuitry 104 may be formed on the substrate 102, and a semiconductor layer (e.g., a polysilicon layer) may be formed on the peripheral circuitry 104. The memory cell array 106 may be formed on the semiconductor layer. In some embodiments, the PUC wafer is flipped, and a thinning operation may be performed on the substrate 102. Peripheral circuitry 108 may then be formed on the thinned substrate 102.

[0051] Note that in Figure 1An x-axis and a y-axis have been added to further illustrate the spatial relationships of components of the semiconductor device. The substrate 102 of the 3D memory device 100 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (lateral or width direction). As used herein, the y-direction (vertical or thickness direction) relative to the substrate 102 of the 3D memory device 100 determines whether a component (e.g., a layer or device) of the semiconductor device is “on,” “above,” or “below” another component (e.g., a layer or device). The same concepts used to describe spatial relationships are applied in this disclosure.

[0052] In some embodiments, the memory cell array 106 includes a NAND flash memory cell array. For ease of description, a NAND flash memory cell array may be used as an example for describing the memory cell array 106 in this disclosure. However, it should be understood that the memory cell array 106 is not limited to a NAND flash memory cell array and may include any other suitable type of memory cell array, such as a NOR flash memory cell array, a phase change memory (PCM) cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name just a few.

[0053] The memory cell array 106 may be a NAND flash memory device, wherein the memory cells are provided in the form of a 3D NAND memory string array and / or a two-dimensional (2D) NAND memory cell array. The NAND memory cells may be organized into pages or fingers, which are then organized into blocks in which each NAND memory cell is coupled to a separate line called a bit line (BL). All cells in the NAND memory cell having the same vertical position may be coupled by word lines (WL) via control gates. In some embodiments, the memory plane contains a specific number of blocks coupled via the same bit lines. The memory cell array 106 may include one or more memory planes, and the peripheral circuitry required to perform all read / program (write) / erase operations may be included in peripheral circuitry 104 and peripheral circuitry 108.

[0054] In some embodiments, the NAND memory cell array is a 2D NAND memory cell array, each of which includes a floating-gate transistor. According to some embodiments, the 2D NAND memory cell array includes a plurality of 2D NAND memory strings, each of which includes a plurality of memory cells (similar to NAND gates) connected in series and two select transistors. According to some embodiments, each 2D NAND memory string is arranged in the same plane on the substrate (i.e., a flat two-dimensional (2D) surface herein, as opposed to the term "memory plane" in this disclosure). In some embodiments, the NAND memory cell array is a 3D NAND memory string array, each of which extends vertically above the substrate (in 3D) through a stacked structure, such as a memory stack. Depending on the 3D NAND technology (e.g., the number of layers / levels in the memory stack), a 3D NAND memory string typically includes a number of NAND memory cells, each of which includes a floating-gate transistor or a charge-trapping transistor.

[0055] like Figure 1 As shown, the 3D memory device 100 may further include peripheral circuitry 104 and peripheral circuitry 108, each peripheral circuitry comprising some of the peripheral circuitry of the memory cell array 106. That is, the peripheral circuitry of the memory cell array 106 may be divided into at least two other semiconductor structures (e.g., Figure 1 The peripheral circuits 104 and 108 are described in the text. The peripheral circuits (also known as control and sensing circuits) may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array 106. For example, the peripheral circuits may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), I / O circuits, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits in peripheral circuits 104 and 108 may utilize CMOS technology, which, for example, can be implemented using logic processing at any suitable technology node.

[0056] Figure 2A schematic circuit diagram of a memory device 200 including peripheral circuitry according to some aspects of this disclosure is shown. The memory device 200 may include a memory cell array 201 and peripheral circuitry 202 coupled to the memory cell array 201. A 3D memory device 100 may be an example of a memory device 200 in which at least two portions of the memory cell array 201 and the peripheral circuitry 202 may be included in various peripheral circuitry 104 and peripheral circuitry 108.

[0057] The memory cell array 201 may be a NAND flash memory cell array, wherein the memory cells 206 are provided in the form of an array of NAND memory strings 208, each NAND memory string extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 208 includes a plurality of memory cells 206 connected in series and stacked vertically. Each memory cell 206 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 206. Each memory cell 206 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0058] In some implementations, each memory cell 206 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 206 is a multi-level cell (MLC) capable of storing more than a single data bit in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to employ a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to employ one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used in the erase state.

[0059] like Figure 2As shown, each NAND flash memory string 208 may include a source-select-gate (SSG) transistor 210 at its source end and a drain-select-gate (DSG) transistor 212 at its drain end. The SSG transistor 210 and DSG transistor 212 may be configured to initiate the selection of the NAND flash memory string 208 (column of the array) during read and program operations. In some embodiments, the SSG transistors 210 of the NAND flash memory strings 208 in the same block 204 are coupled to ground via the same source line (SL) 214 (e.g., a common SL). According to some embodiments, the DSG transistor 212 of each NAND flash memory string 208 is coupled to a corresponding bit line 216 from which data can be read or programmed via an output bus (not shown). In some implementations, each NAND memory string 208 is configured to be selected or not selected by applying a selection voltage (e.g., higher than the threshold voltage of DSG transistor 212) or a non-selection voltage (e.g., 0V) to the corresponding DSG transistor 212 via one or more DSG lines 213 and / or by applying a selection voltage (e.g., higher than the threshold voltage of SSG transistor 210) or a non-selection voltage (e.g., 0V) to the corresponding SSG transistor 210 via one or more SSG lines 215.

[0060] like Figure 2 As shown, NAND memory strings 208 can be organized into multiple blocks 204, each of which may have a common source line 214. In some embodiments, each block 204 is a basic data unit for erase operations, i.e., all memory cells 206 on the same block 204 are erased simultaneously. Memory cells 206 adjacent to the NAND memory strings 208 can be coupled via word lines 218, which select which row of memory cells 206 is affected by read and program operations. In some embodiments, each word line 218 is coupled to a page 220 of memory cells 206, which is a basic data unit for program and read operations. The bit size of a page 220 may correspond to the number of NAND memory strings 208 coupled by word lines 218 in a block 204. Each word line 218 may include multiple control gates (gate electrodes) at each memory cell 206 in the corresponding page 220, and gate lines coupled to the control gates.

[0061] Figure 8 A side view of a NAND storage string 208 in a 3D memory device according to some aspects of this disclosure is shown. Figure 8As shown, NAND flash memory string 208 may extend vertically through memory stack 804 above semiconductor layer 805. Memory stack 804 may include staggered gate conductive layers 806 and dielectric layers 808. The number of pairs of gate conductive layers 806 and dielectric layers 808 in memory stack 804 determines the number of memory cells 206 in memory cell array 201. Gate conductive layers 806 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 806 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 806 includes a doped polysilicon layer. Each gate conductive layer 806 may include a control gate surrounding a memory cell, a gate of a DSG transistor 212, or a gate of an SSG transistor 210, and may extend laterally as a DSG line 213 at the top of the memory stack 804, an SSG line 215 at the bottom of the memory stack 804, or a word line 218 between the DSG line 213 and the SSG line 215.

[0062] like Figure 8 As shown, the NAND flash memory string 208 includes a channel structure 812 extending vertically through the memory stack 804. In some embodiments, the channel structure 812 includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel 820) and one or more dielectric materials (e.g., as a memory film 818). In some embodiments, the semiconductor channel 820 includes silicon, such as polysilicon. In some embodiments, the memory film 818 is a composite dielectric layer including a tunneling layer 826, a storage layer 824 (also referred to as a "charge trap / storage layer"), and a barrier layer 822. The channel structure 812 may have a cylindrical shape (e.g., columnar). According to some embodiments, the semiconductor channel 820, tunneling layer 826, storage layer 824, and barrier layer 822 are arranged radially from the center of the column toward the outer surface in this order. The tunneling layer 826 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 824 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 822 may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 818 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0063] like Figure 8As shown, in some embodiments, semiconductor layer 805 contacts the semiconductor channel 820 of the bottom open channel structure 812 on the source end of NAND memory string 208. A portion of the memory film 818 of the channel structure 812 on the source end may be removed to expose the semiconductor channel 820 to contact semiconductor layer 805. In some embodiments, a portion of the semiconductor channel 820 on the source end of NAND memory string 208 is doped to form a doped region 834 in contact with semiconductor layer 805. Semiconductor layer 805 may include a semiconductor material, such as polysilicon. In some embodiments, semiconductor layer 805 includes N-type doped polysilicon to enable GILD erase operations. Slit structure 828 may extend vertically through memory stack 804 and contact semiconductor layer 805.

[0064] refer to Figure 2 The peripheral circuitry 202 can be coupled to the memory cell array 201 via bit line 216, word line 218, source line 214, SSG line 215, and DSG line 213. As described above, the peripheral circuitry 202 can include any suitable circuitry to apply and sense voltage and / or current signals through bit line 216 to each target memory cell 206 via word line 218, source line 214, SSG line 215, and DSG line 213, thereby facilitating the operation of the memory cell array 201. The peripheral circuitry 202 can include various types of peripheral circuitry formed using CMOS technology. For example, Figure 3 Some exemplary peripheral circuitry 202 is shown, including a page buffer 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, a register 314, an interface (I / F) 316, and a data bus 318. It should be understood that additional peripheral circuitry 202 may also be included in some examples.

[0065] Page buffer 304 can be configured to buffer data read from or programmed into memory cell array 201 according to control signals of control logic 312. In one example, page buffer 304 may store a page of programming data (write data) in a page 220 to be programmed into memory cell array 201. In another example, page buffer 304 also performs a programming verification operation to ensure that data has been correctly programmed into memory cell 206 coupled to selected word line 218.

[0066] The row decoder / word line driver 308 can be configured to be controlled by control logic 312, selection block 204 of memory cell array 201, and word line 218 of selection block 204. The row decoder / word line driver 308 can be further configured to drive memory cell array 201. For example, the row decoder / word line driver 308 can use a word line voltage generated from voltage generator 310 to drive memory cell 206 coupled to selected word line 218.

[0067] The column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and to select one or more 3D NAND memory strings 208 by applying a bit line voltage generated from voltage generator 310. For example, the column decoder / bit line driver 306 can apply a column signal to select from page buffer 304 the set of N bits of data to be output in a read operation.

[0068] Control logic 312 can be coupled to each peripheral circuit 202 and configured to control the operation of the peripheral circuit 202. Register 314 can be coupled to control logic 312 and includes a status register, a command register, and an address register for storing status information, command opcode (OP code), and command address for controlling the operation of each peripheral circuit 202.

[0069] Interface 316 is coupled to control logic 312 and configured to interface memory cell array 201 with a memory controller (not shown). In some embodiments, interface 316 acts as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) to control logic 312, and to buffer and relay status information received from control logic 312 to the memory controller and / or host. Interface 316 is also coupled to page buffer 304 and column decoder / bitline driver 306 via data bus 318, and acts as an I / O interface and data buffer to buffer and relay programming data received from the memory controller and / or host to page buffer 304, and to buffer and relay read data from page buffer 304 to the memory controller and / or host. In some embodiments, interface 316 and data bus 318 are part of the I / O circuitry of peripheral circuitry 202.

[0070] Voltage generator 310 can be configured to be controlled by control logic 312 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and check voltage) and bit line voltages to be supplied to memory cell array 201. In some embodiments, voltage generator 310 is part of a voltage source that provides voltages at various levels at different peripheral circuits 202, as described in detail below. Consistent with the scope of this disclosure, in some embodiments, the voltages supplied by voltage generator 310 to, for example, row decoder / word line driver 308, column decoder / bit line driver 306, and page buffer 304 are higher than certain levels sufficient to perform memory operations. For example, the voltage supplied to the page buffer circuitry in page buffer 304 and / or the logic circuitry in control logic 312 may be between 1.3V and 5V, such as 3.3V, and the voltage supplied to the drive circuitry in row decoder / word line driver 308 and / or column decoder / bit line driver 306 may be between 5V and 30V.

[0071] Unlike logic devices (e.g., microprocessors), memory devices (e.g., 3D NAND flash memory) require a wide range of voltages to be supplied to various peripheral memory circuits. For example, Figure 4A Block diagrams of peripheral circuitry provided with various voltages according to some aspects of this disclosure are shown. In some embodiments, a memory device (e.g., memory device 200) includes a very low voltage (LLV) source 401, a low voltage (LV) source 403, and a high voltage (HV) source 405, each configured to provide a voltage at a corresponding level (Vdd1, Vdd2, or Vdd3). For example, Vdd3 > Vdd2 > Vdd1. Each voltage source 401, 403, or 405 can receive a voltage input at an appropriate level from an external power source (e.g., a battery). Each voltage source 401, 403, or 405 may also include a voltage converter and / or voltage regulator to convert the external voltage input to the corresponding level (Vdd1, Vdd2, or Vdd3) and maintain the voltage at the corresponding level (Vdd1, Vdd2, or Vdd3) and output a voltage at the corresponding level (Vdd1, Vdd2, or Vdd3) through a corresponding power rail. In some implementations, the voltage generator 310 of the memory device 200 is part of the voltage sources 401, 403 and 405.

[0072] In some implementations, the LLV source 401 is configured to provide a voltage below 1.3V, such as between 0.9V and 1.2V (e.g., 0.9V, 0.95V, 1V, 1.05V, 1.1V, 1.15V, 1.2V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). In one example, the voltage is 1.2V. In some implementations, the LV source 403 is configured to provide a voltage between 1.3V and 3.3V (e.g., 1.3V, 1.4V, 1.5V, 1.6V, 1.7V, 1.8V, 1.9V, 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). In one example, the voltage is 3.3V. In some implementations, HV source 405 is configured to provide a voltage greater than 3.3V, such as between 5V and 30V (e.g., 5V, 6V, 7V, 8V, 9V, 10V, 11V, 12V, 13V, 14V, 15V, 16V, 17V, 18V, 19V, 20V, 21V, 22V, 23V, 24V, 25V, 26V, 27V, 28V, 29V, 30V, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that the voltage ranges described above with respect to HV source 405, LV source 403, and LLV source 401 are for illustrative purposes and not limiting, and that HV source 405, LV source 403, and LLV source 401 can provide any other suitable voltage range.

[0073] Based on their appropriate voltage levels (Vdd1, Vdd2, or Vdd3), memory peripheral circuits (e.g., peripheral circuit 202) can be classified as LLV circuit 402, LV circuit 404, and HV circuit 406, which can be coupled to LLV source 401, LV source 403, and HV source 405, respectively. In some embodiments, HV circuit 406 includes one or more drive circuits coupled to the memory cell array (e.g., memory cell array 201) via word lines, bit lines, SSG lines, DSG lines, source lines, etc., and configured to drive the memory cell array by applying voltages at appropriate levels to the word lines, bit lines, SSG lines, DSG lines, source lines, etc., when performing memory operations (e.g., read, program, or erase). In one example, HV circuit 406 may include word line driver circuitry (e.g., in row decoder / word line driver 308) coupled to the word line and applying a programming voltage (Vprog) or pass voltage (Vpass) in the range of, for example, 5V to 30V during programming operations. In another example, HV circuit 406 may include bit line driver circuitry (e.g., in column decoder / bit line driver 306) coupled to the bit line and applying an erase voltage (Veras) in the range of, for example, 5V to 30V during erase operations. In some embodiments, LV circuit 404 includes page buffer circuitry (e.g., in a latch of page buffer 304) and is configured to buffer data read from or programmed into the memory cell array. For example, a voltage of, for example, 3.3V may be provided to the page buffer by LV source 403. LV circuit 404 may also include logic circuitry (e.g., in control logic 312). In some implementations, the LLV circuit 402 includes I / O circuitry configured to interface the memory cell array with a memory controller (e.g., in interface 316 and / or data bus 318). For example, a voltage of, for instance, 1.2V may be supplied to the I / O circuitry from the LLV source 401.

[0074] As described above, in order to reduce the total area occupied by the memory peripheral circuitry, the peripheral circuitry 202 can be formed in different planes based on different performance requirements (e.g., the applied voltage). For example, Figure 4BSchematic diagrams of peripheral circuits with various voltages arranged in separate semiconductor structures according to some aspects of this disclosure are shown. In some embodiments, due to the significant voltage difference between LLV circuit 402 and HV circuit 406 and the resulting differences in device size, such as different semiconductor layer (e.g., substrate or thinned substrate) thicknesses and different gate dielectric thicknesses, they are, for example, separated in semiconductor structures 408 and 410, respectively. In one example, the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which HV circuit 406 is formed in semiconductor structure 410 may be greater than the thickness of the semiconductor layer (e.g., substrate or thinned substrate) in which LLV circuit 402 is formed in semiconductor structure 408. In another example, the thickness of the gate dielectric of the transistor forming HV circuit 406 may be greater than the thickness of the gate dielectric of the transistor forming LLV circuit 402. For example, the thickness difference may be at least 5 times. It is understood that the thickness of the semiconductor layer (e.g., substrate or thinned substrate) may be greater than the thickness of the gate dielectric of the transistor forming LLV circuit 402. Figure 1 On the opposite side of the middle section, LLV circuit 402 and HV circuit 406 are formed in different planes.

[0075] The LV circuit 404 can be formed in semiconductor structures 408 or 410, or in another semiconductor, that is, in the same plane as the LLV circuit 402 or HV circuit 406, or in a different plane from the LLV circuit 402 and HV circuit 406. For example... Figure 4BAs shown, in some embodiments, some of the LV circuits 404 are formed in semiconductor structure 408, i.e., in the same plane as the LLV circuit 402, while some of the LV circuits 404 are formed in semiconductor structure 410, i.e., in the same plane as the HV circuit 406. That is, the LV circuits 404 can also be separated into different planes. For example, when the same voltage is applied to the LV circuits 404 in different semiconductor structures 408 and 410, the thickness of the gate dielectric of the transistor forming the LV circuit 404 in semiconductor structure 408 can be the same as the thickness of the gate dielectric of the transistor forming the LV circuit 404 in semiconductor structure 410. In some embodiments, the same voltage is applied to both the LV circuit 404 in semiconductor structure 408 and the LV circuit 404 in semiconductor structure 410, such that the voltage applied to the HV circuit 406 in semiconductor structure 410 is higher than the voltage applied to the LV circuit 404 in semiconductor structures 408 or 410, and the voltage applied to the LV circuit 404 in semiconductor structures 408 or 410 is higher than the voltage applied to the LLV circuit 402 in semiconductor structure 408. Furthermore, according to some embodiments, since the voltage applied to the LV circuit 404 is between the voltages applied to the HV circuit 406 and the LLV circuit 402, the thickness of the gate dielectric of the transistor forming the LV circuit 404 is between the thickness of the gate dielectric of the transistor forming the HV circuit 406 and the thickness of the gate dielectric of the transistor forming the LLV circuit 402. For example, the thickness of the gate dielectric of the transistor forming the LV circuit 404 can be greater than the thickness of the gate dielectric of the transistor forming the LLV circuit 402, but less than the thickness of the gate dielectric of the transistor forming the HV circuit 406.

[0076] Based on different performance requirements (e.g., associated with different applied voltages), peripheral circuitry 202 can be isolated into at least two stacked semiconductor structures 408 and 410 in different planes. In some embodiments, the I / O circuitry in interface 316 and / or data bus 318 (as LLV circuitry 402) and the logic circuitry in control logic 312 (as part of LV circuitry) are disposed in semiconductor structure 408, while the page buffer circuitry in page buffer 304 and the drive circuitry in row decoder / word line driver 308 and column decoder / bit line driver 306 are disposed in semiconductor structure 410. For example, Figure 7 A circuit diagram of a word line driver 308 and a page buffer 304 according to some aspects of this disclosure is shown.

[0077] In some embodiments, page buffer 304 includes a plurality of page buffer circuits 702, each page buffer circuit 702 being coupled to a NAND memory string 208 via a corresponding bit line 216. That is, memory device 200 may include bit lines 216 respectively coupled to NAND memory string 208, and page buffer 304 may include page buffer circuits 702 respectively coupled to bit lines 216 and NAND memory string 208. Each page buffer circuit 702 may include one or more latches, switches, power supplies, nodes (e.g., data nodes and I / O nodes), current mirrors, verification logic, sensing circuitry, etc. In some embodiments, each page buffer circuit 702 is configured to store sensing data corresponding to read data received from the corresponding bit line 216 during a read operation and to output the stored sensing data; each page buffer circuit 702 is also configured to store programming data during a programming operation and to output the stored programming data to the corresponding bit line 216.

[0078] In some embodiments, word line driver 308 includes a plurality of string drivers 704 (also referred to as drive circuitry) respectively coupled to word lines 218. Word line driver 308 may also include a plurality of local word lines 706 (LWLs) respectively coupled to string drivers 704. Each string driver 704 may include a gate coupled to a decoder (not shown), a source / drain coupled to the corresponding local word line 706, and another source / drain coupled to the corresponding word line 218. In some memory operations, the decoder may select certain string drivers 704, for example, by applying a voltage signal greater than a threshold voltage of the string driver 704 to each local word line 706, and a voltage (e.g., programming voltage, pass voltage, or erase voltage), such that a voltage is applied to the corresponding word line 218 by each selected string driver 704. Conversely, the decoder may also not select certain string drivers 704, for example, by applying a voltage signal less than the threshold voltage of the string driver 704, such that each unselected string driver 704 floats the corresponding word line 218 during memory operations.

[0079] In some embodiments, the page buffer circuit 702 includes a portion of the LV circuit 404 disposed within the semiconductor structure 408 and / or 410. In one example, because the number of page buffer circuits 702 increases with the number of bits, which can occupy a large area for memory devices with a large number of memory cells, the page buffer circuits 702 may be distributed across the semiconductor structures 408 and 410. In some embodiments, the string driver 704 includes a portion of the HV circuit 406 disposed within the semiconductor structure 410.

[0080] Consistent with the scope of this disclosure, each peripheral circuit 202 may include multiple transistors as its basic building blocks. The transistors may be 2D (also known as planar transistors) or 3D (3D transistors) metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, Figure 5A and Figure 5B Perspective and side views of a planar transistor 500 according to some aspects of this disclosure are shown respectively, and Figure 6A and Figure 6B Perspective and side views of a 3D transistor 600 according to some aspects of this disclosure are shown respectively. Figure 5B It shows Figure 5A A side view of the cross-section of the planar transistor 500 in the BB plane, and Figure 6B It shows Figure 6A Side view of the 3D transistor 600 in the BB plane.

[0081] like Figure 5A and Figure 5B As shown, the planar transistor 500 may be a MOSFET on a substrate 502, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator (SOI), or any other suitable material. Trench isolation 503, such as shallow trench isolation (STI), may be formed in the substrate 502 and between adjacent planar transistors 500 to reduce current leakage. The trench isolation 503 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the high-k dielectric material includes any dielectric material having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, the trench isolation 503 includes silicon oxide.

[0082] like Figure 5A and Figure 5B As shown, the planar transistor 500 may further include a gate structure 508 on the substrate 502. In some embodiments, the gate structure 508 is on the top surface of the substrate 502. Figure 5BAs shown, the gate structure 508 may include a gate dielectric 507 on the substrate 502, specifically above and in contact with the top surface of the substrate 502. The gate structure 508 may also include a gate electrode 509 on the gate dielectric 507, specifically above and in contact with the gate dielectric 507. The gate dielectric 507 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 507 includes silicon oxide, i.e., a gate oxide. The gate electrode 509 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 509 includes doped polysilicon, i.e., gate polysilicon.

[0083] like Figure 5A As shown, the planar transistor 500 may further include a pair of source and drain electrodes 506 in the substrate 502. The source and drain electrodes 506 may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). In the planar view, the source and drain electrodes 506 may be separated by a gate structure 508. In other words, according to some embodiments, in the planar view, the gate structure 508 is formed between the source and drain electrodes 506. When the gate voltage applied to the gate electrode 509 of the gate structure 508 is higher than the threshold voltage of the planar transistor 500, a channel of the planar transistor 500 may be laterally formed in the substrate 502 below the gate structure 508, between the source and drain electrodes 506. Figure 5A and Figure 5B As shown, the gate structure 508 can be above and in contact with the top surface of the portion of the substrate 502 where a channel (active region) can be formed. That is, according to some embodiments, the gate structure 508 is in contact with only one side of the active region, i.e., in the plane of the top surface of the substrate 502. It should be understood that, although in Figure 5A and Figure 5B The planar transistor 500 may include additional components such as wells and spacers, though not shown in the diagram.

[0084] like Figure 6A and Figure 6BAs shown, the 3D transistor 600 may be a MOSFET on a substrate 602, which may include silicon (e.g., monocrystalline silicon, c-Si), SiGe, GaAs, Ge, silicon-on-insulator (SOI), or any other suitable material. In some embodiments, the substrate 602 comprises monocrystalline silicon. Trench isolation 603, such as STI, may be formed in the substrate 602 and between adjacent 3D transistors 600 to reduce current leakage. The trench isolation 603 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, the trench isolation 603 comprises silicon oxide.

[0085] like Figure 6A and Figure 6B As shown, unlike the planar transistor 500, the 3D transistor 600 may also include a 3D semiconductor body 604 above the substrate 602. That is, in some embodiments, the 3D semiconductor body 604 extends at least partially above the top surface of the substrate 602 to expose not only the top surface of the 3D semiconductor body 604 but also both side surfaces. Figure 6A and Figure 6B As shown, for example, the 3D semiconductor body 604 can be a 3D structure, also referred to as a "fin," to expose its three sides. According to some embodiments, the 3D semiconductor body 604 is formed from a substrate 602 and therefore has the same semiconductor material as the substrate 602. In some embodiments, the 3D semiconductor body 604 comprises monocrystalline silicon. Since a channel can be formed in the 3D semiconductor body 604 opposite to the substrate 602, the 3D semiconductor body 604 can be considered as the active region of the 3D transistor 600.

[0086] like Figure 6A and Figure 6B As shown, the 3D transistor 600 may further include a gate structure 608 on the substrate 602. Unlike the planar transistor 500, in which the gate structure 608 contacts only one side of the active region (i.e., in the plane of the top surface of the substrate 502), the gate structure 608 of the 3D transistor 600 may contact multiple sides of the active region, i.e., in multiple planes of the top and side surfaces of the 3D semiconductor body 604. In other words, the active region of the 3D transistor 600 (i.e., the 3D semiconductor body 604) may be at least partially surrounded by the gate structure 608.

[0087] The gate structure 608 may include a gate dielectric 607 on the 3D semiconductor body 604, for example, in contact with the top surface and two side surfaces of the 3D semiconductor body 604. The gate structure 608 may also include a gate electrode 609 on and in contact with the gate dielectric 607. The gate dielectric 607 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate dielectric 607 includes silicon oxide, i.e., a gate oxide. The gate electrode 609 may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. In some embodiments, the gate electrode 609 includes doped polysilicon, i.e., gate polysilicon.

[0088] like Figure 6A As shown, the 3D transistor 600 may further include a pair of source and drain electrodes 606 within the 3D semiconductor body 604. The source and drain electrodes 606 may be doped with any suitable P-type dopant (e.g., B or Ga) or any suitable N-type dopant (e.g., P or Ar). In a planar view, the source and drain electrodes 606 may be separated by a gate structure 608. In other words, according to some embodiments, in a planar view, the gate structure 608 is formed between the source and drain electrodes 606. As a result, when the gate voltage applied to the gate electrode 609 of the gate structure 608 is higher than the threshold voltage of the 3D transistor 600, multiple channels of the 3D transistor 600 can be laterally formed between the source and drain electrodes 606 surrounded by the gate structure 608. Unlike the planar transistor 500, in which only a single channel can be formed on the top surface of the substrate 502, multiple channels can be formed on the top and side surfaces of the 3D semiconductor body 604 in the 3D transistor 600. In some implementations, the 3D transistor 600 includes a multi-gate transistor. It should be understood that, although in Figure 6A and Figure 6B Not shown, but the 3D transistor 600 may include additional components such as wells, spacers, and stress sources (also known as strain elements) at the source and drain 606.

[0089] It should also be understood that Figure 6A and Figure 6BAn example of a 3D transistor that can be used in memory peripheral circuitry is shown, and any other suitable 3D multi-gate transistor can also be used in memory peripheral circuitry, including, for example, gate all around (GAA) silicon on nothing (SON) transistors, multi-gate independent FETs (MIGET), tri-gate FETs, Π-gate FETs, and Ω-FETs, quad-gate FETs, cylindrical FETs, or multi-bridge / stacked nanowire FETs.

[0090] Regardless of whether it is a planar transistor 500 or a 3D transistor 600, each transistor in the memory peripheral circuitry may include a thickness T (gate dielectric thickness, e.g., Figure 5B and Figure 6B The gate dielectric (e.g., gate dielectrics 507 and 607) shown in the diagram. The gate dielectric thickness T of the transistor can be designed to adapt to the voltage applied to the transistor. For example, refer to... Figure 4A and Figure 4B The gate dielectric thickness of the transistors in the HV circuit 406 (e.g., a drive circuit such as the string driver 704) can be greater than the gate dielectric thickness of the transistors in the LV circuit 404 (e.g., the page buffer circuit 702, or the logic circuit in control logic 312), which in turn can be greater than the gate dielectric thickness of the transistors in the LLV circuit 402 (e.g., the I / O circuit in interface 316 and data bus 318). In some embodiments, the difference between the gate dielectric thickness of the transistors in the HV circuit 406 and the dielectric thickness of the transistors in the LLV circuit 402 is at least 5 times, for example, between 5 and 50 times. For example, the gate dielectric thickness of the transistors in the HV circuit 406 can be at least 5 times greater than the gate dielectric thickness of the transistors in the LLV circuit 402.

[0091] In some implementations, the dielectric thickness of the transistors in the LLV circuit 402 is between 2 nm and 4 nm (e.g., 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, 3.1 nm, 3.2 nm, 3.3 nm, 3.4 nm, 3.5 nm, 3.6 nm, 3.7 nm, 3.8 nm, 3.9 nm, 4 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that the thickness may be commensurate with the range of LLV voltages applied to the LLV circuit 402, as described in detail above, for example, below 1.3 V (e.g., 1.2 V). In some implementations, the dielectric thickness of the transistor in the LV circuit 404 is between 4 nm and 10 nm (e.g., 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that the thickness may be commensurate with the range of LV voltages applied to the LV circuit 404, as described in detail above, for example, between 1.3 V and 3.3 V (e.g., 3.3 V). In some embodiments, the dielectric thickness of the transistor in HV circuit 406 is between 20 nm and 100 nm (e.g., 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range defined by any one of these values ​​as a lower limit, or any range defined by any two of these values). It should be understood that the thickness may be commensurate with the range of HV voltages applied to HV circuit 406, as described in detail above, for example, greater than 3.3 V (e.g., between 5 V and 30 V).

[0092] Figure 9A and Figure 9B A schematic cross-sectional view of 3D memory devices 900 and 901 with different pad lead-out structures according to various aspects of this disclosure is shown. 3D memory devices 900 and 901 can be... Figure 1An example of a 3D memory device 100 is provided, wherein a memory cell array 106 is formed above peripheral circuitry 104, and peripheral circuitry 104 and peripheral circuitry 108 are formed on opposite sides of a substrate 102. In some embodiments, the memory cell array 106 may include a NAND flash memory string array (e.g., the NAND flash memory string 208 disclosed herein), and the source of the NAND flash memory string array may be in contact with a semiconductor layer 805 (e.g., as shown in the image). Figure 8 (As shown in the diagram). A semiconductor layer 805 is formed between the memory cell array 106 and the peripheral circuitry 104, and may include a semiconductor material, such as polysilicon (e.g., a deposited layer), depending on the type of channel structure of the NAND memory string (e.g., a bottom open channel structure 812).

[0093] In some embodiments, substrate 102 may include two opposite sides, such as an upper side and a bottom side, and peripheral circuitry 104 is formed on the upper side of substrate 102, while peripheral circuitry 108 is formed on the bottom side of substrate 102. That is, transistors of the first portion of the peripheral circuitry (e.g., planar transistor 500 and 3D transistor 600) and transistors of the second portion of the peripheral circuitry (e.g., planar transistor 500 and 3D transistor 600) may be in contact with opposite sides of substrate 102. Therefore, according to some embodiments, transistors of two separate portions of the peripheral circuitry are formed vertically relative to each other across different planes of substrate 102.

[0094] In some embodiments, the substrate 102 on which the transistor is formed may comprise monocrystalline silicon, but not polycrystalline silicon, due to the superior carrier mobility of monocrystalline silicon desired for transistor performance. Through-contacts (e.g., interlayer vias (ILVs) / through substate vias (TSVs)) through the substrate 102 can form a direct, short-distance (e.g., submicron-scale) electrical connection between two portions (peripheral circuitry 104 and peripheral circuitry 108) of the peripheral circuitry on opposite sides of the substrate 102. In some embodiments, bonding operations are not used to combine the memory cell array 106 and the peripheral circuitry 104. Alternatively, a semiconductor layer 805 (e.g., polycrystalline silicon material) may be formed on the peripheral circuitry 104, and the memory cell array 106 may be formed on the semiconductor layer 805. The fabrication process will be described in detail below.

[0095] In addition, such as Figure 9A and Figure 9B As shown, the 3D memory device 900 or 901 may further include a pad-out interconnect layer 902 for pad-out purposes, i.e., interconnection with external devices using contact pads on which solderable bonding wires are applied. Figure 9AIn one example shown, the peripheral circuitry 108 may include a pad-out interconnect layer 902. In this example, the 3D memory device 900 can be led out from the peripheral circuitry-side pads to reduce the interconnect distance between the contact pads and the peripheral circuitry, thereby reducing parasitic capacitance from the interconnect and improving the electrical performance of the 3D memory device 900. Figure 9B In another example shown, the memory cell array 106 may include a pad-out interconnect layer 902.

[0096] Figure 10A and Figure 10B The various aspects of this disclosure are shown. Figure 9A and Figure 9B Side views of various examples of 3D memory devices 900 and 901. (See also...) Figure 10A As shown, as Figure 9A One example of a 3D memory device 900 is, according to some embodiments, a 3D memory device 1000 that is a semiconductor structure including a substrate 102, peripheral circuitry 104, a memory cell array 106, and peripheral circuitry 108, wherein the substrate 102, peripheral circuitry 104, memory cell array 106, and peripheral circuitry 108 are arranged in the vertical direction (e.g., Figure 10A In the y-direction, they are formed vertically on different planes.

[0097] In some embodiments, substrate 102 is a silicon substrate having monocrystalline silicon. Devices such as transistors can be formed on both sides of substrate 102. In some embodiments, the thickness of substrate 102 is between 1 μm and 10 μm. Peripheral circuitry 108 is located on the first side of substrate 102 (e.g., on...). Figure 10A The center is oriented downwards (towards the negative y-direction) and in contact with the first side.

[0098] In some embodiments, peripheral circuitry 108 may include device circuitry 1004 and device circuitry 1006. Device circuitry 1004 may include LLV circuitry 402, such as I / O circuitry (e.g., in interface 316 and data bus 318), and device circuitry 1006 may include LV circuitry 404, such as page buffer circuitry (e.g., page buffer circuitry 702 in page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, device circuitry 1004 includes a plurality of transistors contacting a first side of substrate 102, and device circuitry 1006 includes a plurality of transistors contacting a first side of substrate 102. The transistors may include any transistors disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor includes a gate dielectric, and due to the lower voltage applied to the LLV transistor, the thickness of the gate dielectric of the LLV transistor (e.g., in LLV circuit 402) is less than the thickness of the gate dielectric of the LV transistor (e.g., in LV circuit 404). Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of the transistor) may also be formed on a first side of substrate 102.

[0099] In some embodiments, the peripheral circuit 108 further includes an interconnect layer 1012 beneath the device circuits 1004 and 1006 for transmitting electrical signals to and from the peripheral circuit 108. For example... Figure 10A As shown, device circuits 1004 and 1006 can be vertically disposed between substrate 102 and interconnect layer 1012. Interconnect layer 1012 can include multiple interconnects. Interconnects in interconnect layer 1012 can be coupled to transistors of device circuits 1004 and 1006. Interconnect layer 1012 may also include one or more interlayer dielectric (ILD) layers in which lateral lines and vias can be formed. That is, interconnect layer 1012 can include lateral lines and vias in multiple ILD layers. In some embodiments, devices in peripheral circuit 108 are coupled to each other through interconnects in interconnect layer 1012. For example, device circuit 1004 can be coupled to device circuit 1006 through interconnect layer 1012. Interconnects in interconnect layer 1012 can include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in interconnect layer 1012 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0100] In some embodiments, the interconnects in interconnect layer 1012 include Cu, which has a relatively low resistivity (better electrical performance) among conductive metal materials. As described below regarding the manufacturing process, although Cu has a relatively low thermal budget (incompatible with high-temperature processes), the interconnects of interconnect layer 1012 with Cu can become feasible because the fabrication of interconnect layer 1012 can be performed after the high-temperature processes that form peripheral circuits 104, peripheral circuits 108, and memory cell array 106.

[0101] In some embodiments, the peripheral circuitry 104 may be formed on a second side of the substrate 102 opposite to the first side (e.g., in...). Figure 10A The peripheral circuit 104 and peripheral circuit 108 are thus arranged in different planes in the vertical direction, that is, formed one above the other on opposite sides of the substrate 102.

[0102] In some embodiments, peripheral circuitry 104 may include device circuitry 1008 and device circuitry 1010. Device circuitry 1008 may include HV circuitry, such as driver circuitry (e.g., the serial driver 704 in row decoder / word line driver 308 and the driver in column decoder / bit line driver 306), and device circuitry 1010 may include LV circuitry, such as page buffer circuitry (e.g., page buffer circuitry 702 in page buffer 304) and logic circuitry (e.g., in control logic 312). In some embodiments, device circuitry 1008 includes a plurality of transistors, and device circuitry 1010 also includes a plurality of transistors. Transistors may include any transistor disclosed herein, such as planar transistor 500 and 3D transistor 600. As described in detail above with respect to transistors 500 and 600, in some embodiments, each transistor includes a gate dielectric, and due to the higher voltage applied to the HV transistor, the thickness of the gate dielectric of the HV transistor (e.g., in HV circuitry 406) is greater than the thickness of the gate dielectric of the LV transistor (e.g., in LV circuitry 404). In some embodiments, because the voltage applied to the HV transistor is higher than that of the LLV transistor, the thickness of the gate dielectric of the HV transistor (e.g., in HV circuit 406) is greater than that of the LLV transistor (e.g., in LLV circuit 402). Trench isolation (e.g., STI) and doped regions (e.g., the well, source, and drain of the transistor) may also be formed on the second side of the substrate 102.

[0103] like Figure 10A As shown, the peripheral circuit 104 may further include an interconnect layer 1014 on the device circuit 1008 and device circuit 1010 to transmit electrical signals to and from the device circuit 1008 and device circuit 1010. Figure 10AAs shown, interconnect layer 1014 may be vertically located between semiconductor layer 805 and peripheral circuit 104. Interconnect layer 1014 may include multiple interconnects of transistors coupled to device circuit 1008 and device circuit 1010. Interconnect layer 1014 may also include one or more ILD layers in which interconnects can be formed. That is, interconnect layer 1014 may include lateral lines and vias in multiple ILD layers. In some embodiments, devices in device circuit 1008 and device circuit 1010 are coupled to each other through interconnects in interconnect layer 1014. For example, device circuit 1008 may be coupled to device circuit 1010 through interconnect layer 1014. Interconnects in interconnect layer 1014 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. ILD layers in interconnect layer 1014 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments, the interconnects in interconnect layer 1014 include W, which has a relatively high thermal budget (compatible with high-temperature processes) and good quality (fewer defects, such as voids) in a conductive metallic material.

[0104] like Figure 10A As shown, the 3D memory device 1000 may further include one or more contacts 1016 extending vertically through the substrate 102. In some embodiments, the contacts 1016 couple interconnects in interconnect layer 1012 to interconnects in interconnect layer 1014 to form an electrical connection between opposite sides of the substrate 102. The contacts 1016 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, the contacts 1016 include vias surrounded by a dielectric separator (e.g., having silicon oxide) to electrically isolate the vias from the substrate 102. Depending on the thickness of the substrate 102, the contacts 1016 may be interlayer vias (ILVs) with a submicron depth (e.g., between 10 nm and 1 μm) or through-silicon vias (TSVs) with a micron or tens of micron depth (e.g., between 1 μm and 100 μm).

[0105] like Figure 10AAs shown, a semiconductor layer 805 is formed on an interconnect layer 1014, and a memory cell array 106 is formed on the semiconductor layer 805. In some embodiments, the semiconductor layer 805 is formed on an ILD layer. In some embodiments, the semiconductor layer 805 may comprise a polycrystalline silicon material. In some embodiments, the semiconductor layer 805 may comprise doped polycrystalline silicon, doped amorphous silicon, and / or doped monocrystalline silicon, and may be formed by any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), or any combination thereof.

[0106] Memory cell array 106 (e.g., NAND flash memory string array) and contacts 1018 are formed on semiconductor layer 805. In some embodiments, each NAND flash memory string extends vertically through multiple pairs of layers, each comprising a conductive layer and a dielectric layer. The stacked and interleaved conductive and dielectric layers are also referred to herein as a stacked structure, e.g., a memory stack. A memory stack can be... Figure 8 Examples of memory stacks 804 include conductive and dielectric layers, which may be examples of gate conductive layer 806 and dielectric layer 808, respectively, in memory stack 804. According to some embodiments, the interleaved conductive and dielectric layers in the memory stack alternate in the vertical direction. Each conductive layer may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer may extend laterally as a word line, terminating in one or more stepped structures of the memory stack. In some embodiments, each NAND memory string is a "charge-trapping" type NAND memory string, which includes any suitable channel structure disclosed herein, such as those described above relative to... Figure 8 Detailed description of the bottom open channel structure 812.

[0107] like Figure 10AAs shown, the 3D memory device 1000 may further include a pad-out interconnect layer 902 for pad-out purposes, i.e., interconnection with external devices using contact pads on which bonding wires can be soldered. The pad-out interconnect layer 902 may be below and in contact with the interconnect layer 1012. The pad-out interconnect layer 902 may include interconnects, such as contact pads, in one or more ILD layers. The pad-out interconnect layer 902 and the interconnect layer 1012 may be formed on the same side of the 3D memory device 1000. In some embodiments, for example for pad-out purposes, the interconnects in the pad-out interconnect layer 902 may transmit electrical signals between the 3D memory device 1000 and external devices.

[0108] like Figure 10A As shown, the 3D memory device 1000 may include a carrier substrate 1002 on a memory cell array 106. In some embodiments, the carrier substrate 1002 may be bonded to the memory cell array 106 after the memory cell array 106 has been formed. The carrier substrate 1002 can provide support for the 3D memory device 1000 when the 3D memory device 1000 is flipped to perform fabrication processes for the peripheral circuitry 108 and the pad-out interconnect layer 902.

[0109] Therefore, device circuits 1004, 1006, 1008, and 1010 on different sides of substrate 102 can be coupled to the NAND flash memory strings in memory cell array 106 via various interconnect structures, including interconnect layers 1012 and 1014, and contacts 1016 and 1018. Furthermore, device circuits 1004, 1006, 1008, 1010, and memory cell array 106 can be further coupled to external devices via pads leading out from interconnect layer 902.

[0110] It should be understood that the pad leads of 3D memory devices are not limited to those from, for example... Figure 10A (corresponding to) Figure 9A The peripheral circuit 108 shown in the diagram may be derived from the memory cell array 106 (corresponding to...). Figure 9B For example, such as Figure 10B As shown, the 3D memory device 1001 may include a pad-out interconnect layer 904 above the memory cell array 106.

[0111] Figure 11-16 This disclosure illustrates some aspects of the formation of Figure 10A The manufacturing process of 3D memory devices. Figure 17 This disclosure illustrates some aspects of the formation of Figure 11-16A flowchart of method 1700 for a 3D memory device. For the purpose of better describing this disclosure, it will be described together. Figure 11-16 The cross-section of the 3D memory device 1000 and Figure 17 Method 1700. It should be understood that the operations shown in Method 1700 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 11-16 and Figure 17 The different orders shown are executed.

[0112] like Figure 11 ,as well as Figure 17 As shown in operation 1702, peripheral circuitry 104 is formed on a first side of substrate 102. In some embodiments, a plurality of transistors are formed on the first side of substrate 102. Substrate 102 may be a silicon substrate having monocrystalline silicon. Transistors (device circuitry 1008 and device circuitry 1010) are formed on one side of substrate 102. Transistors can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process. In some embodiments, doped regions are formed in substrate 102 by ion implantation and / or thermal diffusion, which serve, for example, as well as the well and source / drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed in substrate 102 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of the transistor in device circuit 1008 may differ from the thickness of the gate dielectric of the transistor in device circuit 1010, for example, by depositing a thicker silicon oxide film in a region of device circuit 1008 than in a region of device circuit 1010, or by etching back a portion of the silicon oxide film deposited in a region of device circuit 1010. It should be understood that the details of transistor fabrication may depend on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The details vary depending on whether it is a planar transistor 500 or a 3D transistor 600, and therefore will not be elaborated upon for the sake of description.

[0113] In some embodiments, an interconnect layer 1014 is formed over the transistors on substrate 102. The interconnect layer 1014 may include multiple interconnects in one or more ILD layers. The interconnect layer 1014 may include interconnects of middle-end-of-line (MEOL) interconnects and / or back-end-of-line (BEOL) interconnects in multiple ILD layers for electrical connection to the transistors.

[0114] In some embodiments, interconnect layer 1014 includes multiple ILD layers and interconnects formed therein in multiple processes. For example, the interconnects in interconnect layer 1014 may include a conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include a dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, the interconnects in interconnect layer 1014 include W, which has a relatively high thermal budget in a conductive metal material to withstand subsequent high-temperature processes.

[0115] like Figure 12 ,as well as Figure 17 As shown in operation 1704, a semiconductor layer 805 is formed over the interconnect layer 1014. In some embodiments, the polysilicon layer can be formed using a thin-film deposition process (e.g., LPCVD, PECVD, ALD, or any other suitable process).

[0116] like Figure 12 ,as well as Figure 17As shown in operation 1706, a memory cell array 106 is formed on semiconductor layer 805. In some embodiments, a stacked structure is formed on semiconductor layer 805, such as a memory stack comprising staggered conductive and dielectric layers. To form the memory stack, in some embodiments, a dielectric stack (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on semiconductor layer 805. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack can then be formed by a gate replacement process, for example, replacing the sacrificial layers with conductive layers by wet / dry etching of the dielectric-selective sacrificial layers and filling the resulting trenches with conductive layers. In some embodiments, each conductive layer comprises a metal layer, such as a W layer. It should be understood that, in some examples, the memory stack can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process.

[0117] A NAND memory string is formed above semiconductor layer 805, each of the NAND memory strings extending vertically through the memory stack to contact semiconductor layer 805. In some embodiments, the fabrication process for forming the NAND memory string includes forming a channel via through the memory stack (or dielectric stack) and into semiconductor layer 805 using dry etching / wet etching (e.g., DRIE), followed by filling the channel via with multiple layers (e.g., memory films (e.g., tunneling layer, storage layer, and barrier layer) and semiconductor layer) using thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string can depend on the type of channel structure of the NAND memory string (e.g., Figure 8 The bottom open channel structure (812) varies and is therefore not elaborated upon for ease of description.

[0118] In some embodiments, an interconnect layer is formed over the NAND flash memory string array. The interconnect layer may include multiple interconnects in one or more ILD layers. The interconnect layer may include interconnects of MEOLs and / or BEOLs in multiple ILD layers for electrical connection to the NAND flash memory string. In some embodiments, the interconnect layer includes multiple ILD layers and interconnects formed therein in multiple processes. For example, the interconnects in the interconnect layer may include conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnect may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0119] like Figure 13 As shown, after forming the memory cell array 106, a carrier substrate 1002 can be bonded to the memory cell array 106. In subsequent operations, when the 3D memory device 1000 is flipped to perform the fabrication process of the peripheral circuitry 108 and the pad-out interconnect layer 902, the carrier substrate 1002 can provide support for the 3D memory device 1000. Then, as... Figure 14 As shown, the 3D memory device 1000 is flipped. In some embodiments, a thinning process may be performed on a second side of the substrate 102 to thin the substrate 102 to a desired thickness. The second side is opposite to the first side of the substrate 102 on which the peripheral circuitry 104 is formed. In some embodiments, the substrate 102 may be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof.

[0120] like Figure 15 ,as well as Figure 17As shown in operation 1708, peripheral circuitry 108 is formed on a second side of substrate 102 opposite to the first side. In some embodiments, a plurality of transistors are formed on the second side of substrate 102. Transistors (device circuitry 1004 and device circuitry 1006) are formed on the second side of substrate 102. Transistors can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed on the second side of substrate 102 by ion implantation and / or thermal diffusion, the doped regions serving, for example, as well as the well and source / drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed on the second side of substrate 102 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of the transistor in device circuit 1004 may differ from the thickness of the gate dielectric of the transistor in device circuit 1006, for example, by depositing a thicker silicon oxide film in a region of device circuit 1004 than in a region of device circuit 1006, or by etching back a portion of the silicon oxide film deposited in a region of device circuit 1006. It should be understood that the details of transistor fabrication may depend on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The details vary depending on whether it is a planar transistor 500 or a 3D transistor 600, and therefore will not be elaborated upon for the sake of description.

[0121] In some embodiments, an interconnect layer 1012 is formed over the transistor. Interconnect layer 1012 may include multiple interconnects in one or more ILD layers. Interconnect layer 1012 may include interconnects of MEOL and / or BEOL in the multiple ILD layers for electrical connection to device circuitry 1004 and device circuitry 1006. In some embodiments, interconnect layer 1012 includes multiple ILD layers and interconnects formed therein in multiple processes. For example, interconnects in interconnect layer 1012 may include conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0122] Unlike interconnect layer 1014, in some embodiments, the interconnects in interconnect layer 1012 include Cu, which has a relatively low resistivity among conductive metal materials. It is understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), using Cu as the conductive material for the interconnects in interconnect layer 1012 becomes feasible because there are no longer high-temperature processes after the fabrication of interconnect layer 1012.

[0123] In some implementations, contacts are formed through the thinned substrate. For example... Figure 15 As shown, one or more contacts 1016 are formed, each extending vertically through the substrate 102. The contacts 1016 may couple to interconnects in interconnect layer 1012 and interconnects in interconnect layer 1014. The contacts 1016 may be formed by first patterning contact holes through the substrate 102 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0124] like Figure 16 As shown, a pad-out interconnect layer 902 can be formed above the interconnect layer 1012. The pad-out interconnect layer 902 may include interconnects formed in one or more ILD layers, such as contact pads. The contact pads may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0125] The 3D memory device 1000 is formed through the above operations. A first layer of memory peripheral circuitry can be formed on a first side of the substrate, and a memory cell array can be formed on the memory peripheral circuitry on the same side of the substrate. Next, the substrate can be flipped and thinned, and a second layer of memory peripheral circuitry can be formed on a second side of the substrate opposite to the first side. Therefore, the fabrication size of the memory peripheral circuitry can be doubled on a single substrate, reducing chip size and manufacturing costs. Furthermore, the second layer of memory peripheral circuitry can be a low-voltage memory peripheral circuitry provided with a relatively low voltage (e.g., below 1.3V), and can be formed after the fabrication of the memory cell array. Therefore, the low-voltage memory peripheral circuitry will not be affected by the high temperatures during the fabrication of the memory cell array. Furthermore, the channel length of the low-voltage memory peripheral circuitry can be reduced, and the input / output (I / O) speed of the memory device can be improved. In some embodiments, the channel length of the low-voltage memory peripheral circuitry can be further minimized.

[0126] Figure 18-23 This disclosure illustrates some aspects of the formation of Figure 10B The manufacturing process of 3D memory devices. Figure 18-23 The manufacturing process in it can be similar to Figure 11-16 The manufacturing process in the 3D memory device involves pads that are brought out from the memory cell array side.

[0127] like Figure 18 As shown, peripheral circuitry 104 is formed on a first side of substrate 102. In some embodiments, a plurality of transistors are formed on the first side of substrate 102. Substrate 102 may be a silicon substrate having monocrystalline silicon. Transistors (device circuitry 1008 and device circuitry 1010) are formed on one side of substrate 102. Transistors can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed in substrate 102 by ion implantation and / or thermal diffusion, the doped regions serving, for example, as well as the well and source / drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed in substrate 102 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of the transistor in device circuit 1008 may differ from the thickness of the gate dielectric of the transistor in device circuit 1010, for example, by depositing a thicker silicon oxide film in a region of device circuit 1008 than in a region of device circuit 1010, or by etching back a portion of the silicon oxide film deposited in a region of device circuit 1010. It should be understood that the details of transistor fabrication may depend on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The details vary depending on whether it is a planar transistor 500 or a 3D transistor 600, and therefore will not be elaborated upon for the sake of description.

[0128] In some embodiments, an interconnect layer 1014 is formed over the transistors on substrate 102. Interconnect layer 1014 may include multiple interconnects in one or more ILD layers. Interconnect layer 1014 may include MEOL interconnects and / or BEOL interconnects in multiple ILD layers for electrical connection to the transistors.

[0129] In some embodiments, interconnect layer 1014 includes multiple ILD layers and interconnects formed therein in multiple processes. For example, the interconnects in interconnect layer 1014 may include a conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include a dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, the interconnects in interconnect layer 1014 include W, which has a relatively high thermal budget in a conductive metal material to withstand subsequent high-temperature processes.

[0130] like Figure 19 As shown, a semiconductor layer 805 is formed over an interconnect layer 1014. In some embodiments, the polysilicon layer can be formed using a thin-film deposition process (e.g., LPCVD, PECVD, ALD, or any other suitable process). A memory cell array 106 is formed on the semiconductor layer 805. In some embodiments, a stacked structure is formed on the semiconductor layer 805, such as a memory stack comprising staggered conductive and dielectric layers. To form the memory stack, in some embodiments, a dielectric stack (not shown) comprising staggered sacrificial layers (not shown) and dielectric layers is formed on the semiconductor layer 805. In some embodiments, each sacrificial layer comprises a silicon nitride layer, and each dielectric layer comprises a silicon oxide layer. The staggered sacrificial and dielectric layers can be formed using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The memory stack can then be formed using a gate replacement process, for example, replacing the sacrificial layers with conductive layers by wet / dry etching of the dielectric-selective sacrificial layers and filling the resulting trenches with conductive layers. In some implementations, each conductive layer includes a metal layer, such as a W layer. It should be understood that in some examples, the memory stack can be formed by alternately depositing conductive layers (e.g., doped polysilicon layers) and dielectric layers (e.g., silicon oxide layers) without a gate replacement process.

[0131] A NAND memory string is formed above semiconductor layer 805, each of the NAND memory strings extending vertically through the memory stack to contact semiconductor layer 805. In some embodiments, the fabrication process for forming the NAND memory string includes forming a channel via through the memory stack (or dielectric stack) and into semiconductor layer 805 using dry etching / wet etching (e.g., DRIE), followed by filling the channel via with multiple layers (e.g., memory films (e.g., tunneling layer, storage layer, and barrier layer) and semiconductor layer) using thin film deposition processes (e.g., ALD, CVD, PVD, or any combination thereof). It should be understood that the details of fabricating the NAND memory string can depend on the type of channel structure of the NAND memory string (e.g., Figure 8 The bottom open channel structure (812) varies and is therefore not elaborated upon for ease of description.

[0132] In some embodiments, an interconnect layer is formed over the NAND flash memory string array. The interconnect layer may include multiple interconnects in one or more ILD layers. The interconnect layer may include interconnects of MEOLs and / or BEOLs in multiple ILD layers for electrical connection to the NAND flash memory string. In some embodiments, the interconnect layer includes multiple ILD layers and interconnects formed therein in multiple processes. For example, the interconnects in the interconnect layer may include conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process forming the interconnect may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0133] like Figure 19 As shown, a pad-out interconnect layer 904 may be formed during or after the formation of the memory cell array 106. In some embodiments, the pad-out interconnect layer 904 may be located near the memory cell array 106, and contact pads may be above the memory cell array 106. In subsequent operations, the pad-out interconnect layer 904 may be pads from 3D memory devices on the memory cell array side. The pad-out interconnect layer 904 may include interconnects formed in one or more ILD layers, such as contact pads. Contact pads may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

[0134] like Figure 20As shown, after forming the memory cell array 106, a carrier substrate 1002 can be bonded to the memory cell array 106. In subsequent operations, when the 3D memory device 1001 is flipped to perform the fabrication process of the peripheral circuitry 108, the carrier substrate 1002 can provide support for the 3D memory device 1001. Then, as... Figure 21 As shown, the 3D memory device 1001 is flipped. In some embodiments, a thinning process may be performed on a second side of the substrate 102 to thin the substrate 102 to a desired thickness. The second side is opposite to the first side of the substrate 102 on which the peripheral circuitry 104 is formed. In some embodiments, the substrate 102 may be thinned by processes including, but not limited to, wafer grinding, dry etching, wet etching, CMP, any other suitable process, or any combination thereof.

[0135] like Figure 22 As shown, peripheral circuitry 108 is formed on a second side of substrate 102 opposite to the first side. In some embodiments, a plurality of transistors are formed on the second side of substrate 102. Transistors (device circuitry 1004 and device circuitry 1006) are formed on the second side of substrate 102. Transistors can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable process. In some embodiments, doped regions are formed on the second side of substrate 102 by ion implantation and / or thermal diffusion, the doped regions serving, for example, as well as the well and source / drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed on the second side of substrate 102 by wet / dry etching and thin film deposition. In some embodiments, for example, the thickness of the gate dielectric of the transistor in device circuit 1004 may differ from the thickness of the gate dielectric of the transistor in device circuit 1006, for example, by depositing a thicker silicon oxide film in a region of device circuit 1004 than in a region of device circuit 1006, or by etching back a portion of the silicon oxide film deposited in a region of device circuit 1006. It should be understood that the details of transistor fabrication may depend on the type of transistor (e.g., Figure 5A , Figure 5B , Figure 6A and Figure 6B The details vary depending on whether it is a planar transistor 500 or a 3D transistor 600, and therefore will not be elaborated upon for the sake of description.

[0136] In some embodiments, an interconnect layer 1012 is formed over the transistor. Interconnect layer 1012 may include multiple interconnects in one or more ILD layers. Interconnect layer 1012 may include interconnects of MEOL and / or BEOL in the multiple ILD layers for electrical connection to device circuitry 1004 and device circuitry 1006. In some embodiments, interconnect layer 1012 includes multiple ILD layers and interconnects formed therein in multiple processes. For example, interconnects in interconnect layer 1012 may include conductive material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The fabrication process forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer may include dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0137] Unlike interconnect layer 1014, in some embodiments, the interconnects in interconnect layer 1012 include Cu, which has a relatively low resistivity among conductive metal materials. It is understood that although Cu has a relatively low thermal budget (incompatible with high-temperature processes), using Cu as the conductive material for the interconnects in interconnect layer 1012 becomes feasible because there are no longer high-temperature processes after the fabrication of interconnect layer 1012.

[0138] In some implementations, contacts are formed through the thinned substrate. For example... Figure 22 As shown, one or more contacts 1016 are formed, each extending vertically through the substrate 102. The contacts 1016 may couple to interconnects in interconnect layer 1012 and interconnects in interconnect layer 1014. The contacts 1016 may be formed by first patterning contact holes through the substrate 102 using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes may be filled with a conductor (e.g., W or Cu). In some embodiments, filling the contact holes includes depositing a spacer (e.g., a silicon oxide layer) before depositing the conductor.

[0139] like Figure 23 As shown, the 3D memory device 1001 is flipped over, and the carrier substrate 1002 is removed. The pads are then exposed to bring out the interconnect layer 904 for external connections.

[0140] By forming the 3D memory device 1001 using the above operations, a first layer of memory peripheral circuitry can be formed on a first side of the substrate, and a memory cell array can be formed on the memory peripheral circuitry on the same side of the substrate. Next, the substrate can be flipped and thinned, and a second layer of memory peripheral circuitry can be formed on a second side of the substrate opposite to the first side. Therefore, the fabrication size of the memory peripheral circuitry can be doubled on a single substrate to reduce chip size and manufacturing costs. Furthermore, the second layer of memory peripheral circuitry can be a low-voltage memory peripheral circuitry providing a relatively low voltage (e.g., below 1.3V), and can be formed after the fabrication of the memory cell array. Therefore, the low-voltage memory peripheral circuitry will not be affected by the high temperatures during the fabrication of the memory cell array. Furthermore, the channel length of the low-voltage memory peripheral circuitry can be reduced, and the input / output (I / O) speed of the memory device can be improved. In some embodiments, the channel length of the low-voltage memory peripheral circuitry can be further minimized.

[0141] Figure 24 A block diagram of a system 1800 having a memory device according to some aspects of this disclosure is shown. System 1800 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 24 As shown, system 1800 may include a host 1808 and a memory system 1802 having one or more memory devices 1804 and a memory controller 1806. The host 1808 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 1808 may be configured to send data to or receive data from memory device 1804.

[0142] Memory device 1804 can be any memory device disclosed herein, such as 3D memory devices 100, 200, 900, 901, 1000, and 1001. In some embodiments, each memory device 1804 includes a memory cell array, a first peripheral circuitry of the memory cell array, and a second peripheral circuitry of the memory cell array, which are stacked one on top of the other in different planes, as described in detail above.

[0143] According to some embodiments, memory controller 1806 is coupled to memory device 1804 and host 1808 and is configured to control memory device 1804. Memory controller 1806 can manage data stored in memory device 1804 and communicate with host 1808. In some embodiments, memory controller 1806 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, memory controller 1806 is designed to operate in high duty cycle environments such as SSDs or embedded multi-media cards (eMMCs) used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 1806 can be configured to control the operation of memory device 1804, such as read, erase, and program operations. In some embodiments, the memory controller 1806 is configured to control the memory cell array via first and second peripheral circuitry. The memory controller 1806 may also be configured to manage various functions relating to data stored or to be stored in the memory device 1804, including (but not limited to) bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1806 is also configured to process error correction codes (ECCs) for data read from or written to the memory device 1804. Any other suitable function, such as formatting the memory device 1804, may also be performed by the memory controller 1806. The memory controller 1806 may communicate with external devices (e.g., host 1808) according to specific communication protocols.For example, the memory controller 1806 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0144] The memory controller 1806 and one or more memory devices 1804 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 1802 can be implemented and packaged into different types of end electronic products. Figure 25A In one example shown, the memory controller 1806 and a single memory device 1804 may be integrated into a memory card 1902. The memory card 1902 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1902 may further include a connection between the memory card 1902 and a host (e.g., Figure 24 The host (1808) is coupled to the memory card connector 1904. In such a... Figure 25B In another example shown, the memory controller 1806 and multiple memory devices 1804 can be integrated into the SSD 1906. The SSD 1906 may also include interfaces for connecting the SSD 1906 to a host computer (e.g., ...). Figure 24 The host 1808 is coupled to the SSD connector 1908. In some embodiments, the storage capacity and / or operating speed of the SSD 1906 is greater than the storage capacity and / or operating speed of the memory card 1902.

[0145] The specific embodiments described above can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0146] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: A first semiconductor structure, the first semiconductor structure comprising: First semiconductor layer; and A NAND flash memory string array, wherein the source of the NAND flash memory string array is in contact with a first side of the first semiconductor layer; and A second semiconductor structure located below a second side of the first semiconductor layer, wherein the second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer, the second semiconductor structure comprising: Second semiconductor layer; The first peripheral circuit of the NAND memory string array includes a first transistor in contact with a first side of the second semiconductor layer; and The second peripheral circuit of the NAND flash memory array includes a second transistor in contact with a second side of the second semiconductor layer, the second side of which is opposite to the first side of the second semiconductor layer. in: The first transistor includes a first gate dielectric; The second transistor includes a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

2. The three-dimensional memory device according to claim 1, wherein, The first semiconductor layer is located between the NAND flash memory array and the first peripheral circuitry of the NAND flash memory array.

3. The three-dimensional memory device according to claim 1, wherein, The first semiconductor layer includes a polycrystalline silicon layer.

4. The three-dimensional memory device according to claim 1, wherein, The second semiconductor layer includes a silicon substrate.

5. The three-dimensional memory device according to claim 1, wherein, The second semiconductor structure further includes a first interconnect layer and a second interconnect layer, such that the first peripheral circuit is located between the first interconnect layer and a first side of the second semiconductor layer, and the second peripheral circuit is located between the second interconnect layer and a second side of the second semiconductor layer.

6. The three-dimensional memory device according to claim 5, wherein, The second semiconductor structure further includes a first through-substrate via electrically connected between the first interconnect layer and the second interconnect layer.

7. The three-dimensional memory device according to claim 6, wherein, The first semiconductor structure further includes a first contact structure electrically connected between the first interconnect layer and multiple word lines of the NAND memory string array.

8. The three-dimensional memory device according to claim 7, wherein, The first contact structure penetrates the first semiconductor layer.

9. The three-dimensional memory device according to any one of claims 5-8, wherein, The second semiconductor structure further includes a pad lead-out structure, and the second peripheral circuit of the NAND memory string array is located between the pad lead-out structure and the second side of the second semiconductor structure.

10. The three-dimensional memory device according to any one of claims 5-8, wherein, The first semiconductor structure further includes a pad lead-out structure, and the NAND memory string array is located between the pad lead-out structure and a first side of the first semiconductor layer.

11. The three-dimensional memory device according to claim 1, wherein, The difference between the thickness of the first gate dielectric and the thickness of the second gate dielectric is at least 5 times.

12. A memory system, comprising: A memory device configured to store data, and comprising: A first semiconductor structure, the first semiconductor structure comprising: First semiconductor layer; and A NAND flash memory string array, wherein the source of the NAND flash memory string array is in contact with a first side of the first semiconductor layer; and A second semiconductor structure located below a second side of the first semiconductor layer, wherein the second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer, the second semiconductor structure comprising: Second semiconductor layer; The first peripheral circuit of the NAND memory string array includes a first transistor in contact with a first side of the second semiconductor layer; and The second peripheral circuit of the NAND memory string array includes a second transistor contacting a second side of the second semiconductor layer, the second side of the second semiconductor layer being opposite to the first side of the second semiconductor layer; and A memory controller, coupled to the memory device and configured to control the NAND flash memory array via the first peripheral circuitry and the second peripheral circuitry. in: The first transistor includes a first gate dielectric; The second transistor includes a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

13. A method for forming a three-dimensional (3D) memory device, comprising: A first transistor is formed on a first side of the substrate; A semiconductor layer is formed on the first transistor on a first side of the substrate; A NAND memory string array is formed on the semiconductor layer; as well as A second transistor is formed on a second side of the substrate opposite to the first side. in: The first transistor includes a first gate dielectric; The second transistor includes a second gate dielectric; and The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

14. The method of claim 13, further comprising: A first interconnect layer is formed on the first transistor.

15. The method according to claim 14, wherein, Forming the semiconductor layer over the first transistor on a first side of the substrate includes: A polysilicon layer is formed on top of the first interconnect layer.

16. The method of claim 15, further comprising: The substrate is thinned before the second transistor is formed.

17. The method of claim 16, further comprising: A pad lead-out structure is formed above the NAND memory string array on the first side of the substrate.

18. The method of claim 17, further comprising: A first contact structure is formed before the pad lead-out structure is formed, and the first contact structure is electrically connected between the first interconnect layer and the pad lead-out structure.

19. The method of claim 16, further comprising: A pad lead-out structure is formed above the second transistor on the second side of the substrate.

20. The method according to any one of claims 16-19, further comprising: Forming a through-substrate via that extends through the substrate.

21. The method according to claim 20, wherein, The through-substrate via electrically connects the first interconnect layer and the second interconnect layer on the second transistor.

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