Thin-film transistors and display devices

Abstract

Embodiments of this disclosure relate to thin-film transistors and display devices. By providing capacitor electrodes on the gate electrodes of a thin-film transistor including dual gate electrodes, the area occupied by the storage capacitor in a sub-pixel is reduced, and space utilization is improved. Furthermore, in the dual gate electrodes, the gate electrode forming the storage capacitor does not overlap with a portion of the channel, and a portion of the capacitor electrode overlaps with a portion of the channel. This allows the electric field to be controlled by the capacitor electrodes, thus providing a thin-film transistor with high output current and current stability.

Description

Technical Field

[0001] Embodiments of this disclosure relate to thin-film transistors and display devices. Background Technology

[0002] The development of the information society has led to an increased demand for display devices that display images and for various types of display devices such as liquid crystal displays and organic light-emitting diode displays.

[0003] For example, a display device may include a display panel having a plurality of sub-pixels and various driving circuits for driving the display panel. Furthermore, depending on the type of display device, each sub-pixel may include a light-emitting element and circuit elements for driving the light-emitting element.

[0004] Here, as the area of ​​the circuit elements disposed in the sub-pixel increases, the area of ​​the light-emitting region may decrease, thus potentially reducing luminous efficiency. Furthermore, when improving the driving characteristics of the circuit elements to enhance luminous efficiency, there is a possibility of reducing the driving stability of the circuit elements.

[0005] Therefore, there is a need for methods to improve the luminous efficiency of sub-pixels while simultaneously enhancing the driving characteristics and driving stability of the circuit elements disposed within the sub-pixels. Summary of the Invention

[0006] Technical problems to be solved

[0007] Embodiments of this disclosure provide a method for improving current stability while simultaneously enhancing the current characteristics of driving transistors disposed in sub-pixels.

[0008] Embodiments of this disclosure provide a method for achieving a high-resolution display device by reducing the area occupied by circuit elements in sub-pixels while simultaneously improving the current characteristics and current stability of driving transistors.

[0009] Solution to the problem

[0010] In one aspect, embodiments of the present disclosure may provide a display device, comprising: a first gate electrode located on a substrate; an active layer located on the first gate electrode and including a channel region overlapping at least a portion of the first gate electrode; a second gate electrode located on the active layer and overlapping a first region of the channel region; and a capacitor electrode comprising: a first portion located on the second gate electrode and overlapping at least a portion of the second gate electrode; and a second portion connected to the first portion and overlapping at least a portion of a second region other than the first region of the channel region.

[0011] Here, the second gate electrode can be located in a region other than the region that overlaps with the second region of the channel region.

[0012] The first portion of the capacitor electrode can be positioned above the second portion of the capacitor electrode. Furthermore, the point where the first and second portions of the capacitor electrode connect to each other can be located in a region other than the area overlapping with the second gate electrode.

[0013] The same voltage can be supplied to the first gate electrode and the second gate electrode, and a constant voltage different from the voltage supplied to the second gate electrode can be supplied to the capacitor electrode.

[0014] In another aspect, embodiments of this disclosure may provide a display device, comprising: a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels; a plurality of light-emitting elements disposed in each of the plurality of sub-pixels; and a plurality of driving transistors disposed in each of the plurality of sub-pixels and electrically connected to the light-emitting elements, wherein the driving transistors comprise: an active layer; a first gate electrode located on one surface of the active layer and overlapping a channel region of the active layer; a second gate electrode located on another surface of the active layer and overlapping a portion of the channel region of the active layer; and a third gate electrode located on another surface of the active layer, positioned further away from the active layer than the second gate electrode, and overlapping the channel region of the active layer.

[0015] In another aspect, embodiments of this disclosure may provide a thin-film transistor, comprising: a first gate electrode; an active layer located on the first gate electrode and including a channel region overlapping at least a portion of the first gate electrode; a second gate electrode located on the active layer and overlapping a first region of the channel region; and a third gate electrode located at least partially on the second gate electrode, overlapping at least a portion of the second gate electrode, and overlapping at least a portion of a second region other than the first region of the channel region.

[0016] Beneficial effects of the present invention

[0017] According to various embodiments of this disclosure, since the top gate electrode of the driving transistor including the dual gate electrode overlaps with a portion of the channel, and the capacitor electrode located on the top gate electrode overlaps with a portion of the channel, the current stability of the driving transistor can be improved by controlling the electric field of the capacitor electrode.

[0018] Furthermore, by using a capacitor electrode located on the top gate electrode of the driving transistor to perform electric field control, the current characteristics and current stability of the driving transistor can be improved, while minimizing the area occupied by the circuit elements in the sub-pixel. Attached Figure Description

[0019] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings:

[0020] Figure 1 This is a diagram illustrating a schematic configuration of a display device according to an embodiment of the present disclosure.

[0021] Figure 2 This is a diagram illustrating an example of the circuit structure of a sub-pixel provided in a display device according to an embodiment of the present disclosure.

[0022] Figure 3 This is a diagram illustrating an example of a planar structure of subpixels provided in a display device according to an embodiment of the present disclosure.

[0023] Figure 4 It is shown Figure 3 A diagram showing an example of the cross-sectional structure of the I-I' section.

[0024] Figure 5 It is shown Figure 3 A diagram showing another example of the cross-sectional structure of the I-I' section.

[0025] Figure 6 It is shown Figure 3 A diagram showing another example of the cross-sectional structure of the I-I' section.

[0026] Figure 7 It is shown Figure 3 A diagram showing an example of the circuit structure for a sub-pixel. Detailed Implementation

[0027] In the following description of examples or embodiments of this disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to denote the same or similar components even when the same or similar components are shown in different drawings. Furthermore, in the following description of examples or embodiments of this disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such detailed descriptions would make the subject matter of some embodiments of this disclosure considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0028] This document may use terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” to describe elements of this disclosure. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0029] When it is mentioned that the first element is "connected or coupled to" the second element, or "in contact with or overlaps" the second element, it should be interpreted as meaning that the first element can not only be "directly connected or coupled to" the second element or "directly in contact with or overlaps" the second element, but also that a third element can be "inserted" between the first and second elements, or that the first and second elements can be "connected or coupled to" each other, or "in contact with or overlaps" each other, via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled to" each other, or that "in contact with or overlaps" each other.

[0030] When using time-related terms such as "after," "subsequent to," "next," "before," etc., to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation unless used with the terms "directly" or "immediately after."

[0031] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information (e.g., levels, ranges, etc.) of a component or feature include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Additionally, the term "may" fully encompasses all the meanings of the term "can."

[0032] Figure 1 This is a diagram illustrating a schematic configuration of a display device 100 according to an embodiment of the present disclosure.

[0033] Reference Figure 1 The display device 100 according to an exemplary embodiment may include: a display panel 110, the display panel 110 including an active region A / A and a non-active region N / A located outside the active region A / A; and components for driving the display panel 110, such as a gate driving circuit 120, a data driving circuit 130 and a controller 140.

[0034] In the display panel 110, multiple gate lines GL and multiple data lines DL can be provided, and multiple sub-pixels SP can be provided in the area where the multiple gate lines GL and multiple data lines DL intersect. Each of the multiple sub-pixels SP may include circuit elements, and two or more sub-pixels SP can provide a single pixel.

[0035] The gate drive circuit 120 is controlled by the controller 140 to sequentially output scan signals to multiple gate lines GL disposed in the display panel 110, thereby controlling the timing of driving multiple sub-pixels SP.

[0036] Furthermore, the gate drive circuit 120 can output a light emission signal to control the light emission time of the sub-pixel SP. The circuitry for outputting the scan signal and the circuitry for outputting the light emission signal can be provided as a whole or separately.

[0037] The gate driving circuit 120 may include one or more gate driver integrated circuits (GDICs) and may be disposed on one or both sides of the display panel 110 depending on the driving system. Furthermore, the gate driving circuit 120 may be implemented as a GIP (Gate In-Panel) type disposed in the bezel area of ​​the display panel 110.

[0038] The data driving circuit 130 receives image data from the controller 140 and converts the image data into analog data voltage. Furthermore, the data driving circuit 130 outputs the data voltage to the data line DL at the time points when a scan signal is applied through the gate line GL, such that the sub-pixel SP represents the luminous intensity corresponding to the image data.

[0039] The data driving circuit 130 may include one or more source driver integrated circuits (SDICs). Furthermore, depending on the driving system, the data driving circuit 130 may be located on one or both sides of the display panel 110.

[0040] The controller 140 provides various control signals to the gate drive circuit 120 and the data drive circuit 130 to control the operation of the gate drive circuit 120 and the data drive circuit 130.

[0041] The controller 140 controls the gate drive circuit 120 to output a scan signal at a time point defined by the frame, and the controller 140 converts the image data received from the external source into a data signal format that can be read by the data drive circuit 130, and outputs the converted image data to the data drive circuit 130.

[0042] In addition to image data, the controller 140 also receives various timing signals from external sources (e.g., host systems), including vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, input data enable signal DE, clock signal CLK, etc.

[0043] The controller 140 can generate various control signals using various timing signals received from external sources, and output the control signals to the gate drive circuit 120 and the data drive circuit 130.

[0044] For example, the controller 140 outputs various gate control signals GCS, including gate start pulse GSP, gate shift clock GSC, gate output enable signal GOE, etc., to control the gate drive circuit 120.

[0045] Here, the gate start pulse GSP controls the start time of operation of one or more gate driver integrated circuits (GDICs) in the gate drive circuit 120. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits (GDICs) to control the shift time of the scan signal. The gate output enable signal GOE specifies the timing information of one or more gate driver integrated circuits (GDICs).

[0046] In addition, the controller 140 outputs various data control signals DCS, including source start pulse SSP, source sampling clock SSC, source output enable signal SOE, etc., to control the data drive circuit 130.

[0047] Here, the source start pulse SSP controls the data sampling start time of one or more source driver integrated circuits in the data drive circuit 130. The source sampling clock SSC is a clock signal that controls the data sampling time in each of the source driver integrated circuits SDIC. The source output enable signal SOE controls the output time of the data drive circuit 130.

[0048] The display device 100 may also include a power management integrated circuit to provide various forms of voltage or current to the display panel 110, gate driving circuit 120, data driving circuit 130, etc., or to control various forms of voltage or current to be provided to the display panel 110, gate driving circuit 120, data driving circuit 130, etc.

[0049] Each subpixel SP can accommodate multiple circuit elements for driving the subpixel SP, and liquid crystal or light-emitting element ED can be provided in the subpixel SP depending on the type of display device 100.

[0050] Here, the light-emitting element ED can be, for example, an organic light-emitting diode. Alternatively, the light-emitting element ED can be an inorganic light-emitting diode (LED), or it can be a micro-LED with a size of tens of micrometers.

[0051] The circuit elements set in the sub-pixel SP can be configured differently depending on the type of the sub-pixel. For example, circuit elements such as multiple thin-film transistors and capacitors can be set in the sub-pixel SP.

[0052] Figure 2 This is a diagram illustrating an example of the circuit structure of a sub-pixel SP provided in a display device 100 according to an embodiment of the present disclosure.

[0053] Reference Figure 2 The light-emitting element (ED) can be located in the sub-pixel SP. Furthermore, the switching transistor (SWT), the driving transistor (DRT), and the storage capacitor (Cst) can also be located in the sub-pixel SP.

[0054] In other words, Figure 2 An example of a 2T1C structure with two thin-film transistors and one capacitor is shown, but depending on the driving timing of the sub-pixel SP or whether the sub-pixel SP includes a compensation circuit, one or more thin-film transistors or one or more capacitors may be further provided in the sub-pixel SP.

[0055] Moreover, as an example, Figure 2 The diagram shows a structure with a P-type thin-film transistor, but an N-type thin-film transistor can be provided, or in some cases, both P-type and N-type thin-film transistors can be provided.

[0056] The switching transistor SWT is electrically connected between the data line DL and the first node N1. The switching transistor SWT can be controlled by a scan signal applied to the gate line GL.

[0057] The driving transistor DRT is electrically connected between the first driving voltage line DVL1, which provides the first driving voltage Vdd, and the light-emitting element ED. The driving transistor DRT is controlled according to the voltage level of the first node N1, and the driving transistor DRT can control the driving current Ied supplied to the light-emitting element ED.

[0058] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2. The storage capacitor Cst can maintain the data voltage supplied to the first node N1 within a frame.

[0059] The light-emitting element ED can be electrically connected between the driving transistor DRT and the second driving voltage line DVL2, which provides the second driving voltage Vss.

[0060] To briefly illustrate the driving scheme, when a scan signal of the on-level is applied to the gate line GL, the switching transistor SWT can be turned on. During the period when the switching transistor SWT is on, the data voltage is supplied to the data line DL and applied to the first node N1.

[0061] With the first driving voltage Vdd applied to the second node N2, when the data voltage is applied to the first node N1, the driving transistor DRT can be turned on, and a driving current Ied corresponding to the data voltage can be provided to the light-emitting element ED. The light-emitting element ED emits light according to the driving current Ied provided by the driving transistor DRT, and can represent the brightness corresponding to the data voltage.

[0062] Therefore, the current output characteristics of the driving transistor DRT are crucial for the light-emitting element (ED) to accurately represent the brightness according to the data voltage. Furthermore, despite improvements in the performance of the driving transistor DRT, the light-emitting area of ​​the ED can still be maximized by minimizing the area occupied by the circuit elements within the sub-pixel SP.

[0063] In other words, in order to improve the driving characteristics and driving efficiency of the sub-pixel SP and achieve a high-resolution display device 100, it is necessary to improve the driving characteristics of the driving transistor DRT without increasing the area of ​​the circuit elements including the driving transistor DRT.

[0064] The embodiments of this disclosure can provide a method to improve the current output characteristics and current stability of the driving transistor DRT while minimizing the area of ​​circuit elements disposed in the sub-pixel SP.

[0065] Figure 3 This diagram illustrates an example of the planar structure of sub-pixels SP provided in a display device 100 according to an embodiment of the present disclosure, and is also a diagram illustrating an example of the structure of the aforementioned 2T1C. Figure 4 An example of the cross-sectional structure of the driving transistor DRT disposed in the sub-pixel SP is shown, and it is shown that... Figure 3 An example of the cross-sectional structure of the I-I' section is shown.

[0066] Reference Figure 3 and Figure 4 The buffer layer BUF can be disposed on the substrate SUB, and the first gate electrode GE1 made of the first gate metal GAT1 can be disposed on the buffer layer SUF.

[0067] Since the first gate electrode GE1 is the gate electrode of the driving transistor DRT, it can be electrically connected to the data line DL via the switching transistor SWT.

[0068] A first gate insulating layer GI1 can be disposed on a first gate electrode GE1. An active layer ACT can also be disposed on the first gate insulating layer GI1.

[0069] The active layer ACT may include a channel region CH as a semiconductor region, and a source region SE and a drain region DE as P+ or N+ doped regions.

[0070] Figure 4 The example shown illustrates the case where the source region SE and the drain region DEP+ are doped. The source region SE can be electrically connected to the first drive voltage line DVL1 via a contact hole, and the drain region DE can be electrically connected to the first electrode E1, which serves as the anode electrode of the light-emitting element ED.

[0071] The second gate insulating layer GI2 can be disposed on the active layer ACT. Furthermore, the second gate electrode GE2, made of the second gate metal GAT2, can be disposed on the second gate insulating layer GI2. Additionally, the gate line GL, made of the second gate metal GAT2, can be disposed on the same layer as the second gate electrode GE2.

[0072] The second gate electrode GE2 can overlap with a portion of the channel region CH of the active layer ACT, and can be electrically connected to the data line DL via the switching transistor SWT.

[0073] In other words, the driving transistor DRT according to the embodiments of this disclosure can be a structure including dual gate electrodes. Since an electric field is formed by the first gate electrode GE1 and the second gate electrode GE2, the output current of the driving transistor DRT can be increased.

[0074] A third gate insulating layer GI3 can be disposed on the second gate electrode GE2, and a capacitor electrode CE made of a third gate metal GAT3 can be disposed on the third gate insulating layer GI3. Furthermore, an interlayer insulating layer ILD can be disposed on the capacitor electrode CE.

[0075] The data line DL, the first drive voltage line DVL1, and the second drive voltage line DVL2, made of source / drain metal SD, can be disposed on the interlayer insulating layer ILD.

[0076] Here, the capacitor electrode CE can be regarded as the third gate electrode GE3.

[0077] The capacitor electrode CE may include a first portion CEa located on and overlapping at least a portion of the second gate electrode GE2. Furthermore, the capacitor electrode CE may include a second portion CEb connected to the first portion CEa and located in a region other than the region overlapping the second gate electrode GE2.

[0078] The second part CEb of the capacitor electrode CE can overlap with a portion of the channel region CH of the active layer ACT.

[0079] Therefore, the first portion CEa of the capacitor electrode CE can form a storage capacitor Cst with the second gate electrode GE2. Furthermore, since the second portion CEb of the capacitor electrode CE overlaps with a portion of the channel region CH of the active layer ACT, it can function as a gate electrode to control the current output of the drive transistor DRT. And since the capacitor electrode CE should form a capacitance with the second gate electrode GE2, a constant voltage (e.g., a first drive voltage Vdd) different from the voltages applied to the first gate electrode GE1 and the second gate electrode GE2 can be applied to the capacitor electrode CE. Therefore, an electric field can be formed on the channel region CH adjacent to the drain region DE of the drive transistor DRT, and the output characteristics of the drive transistor can be stabilized. That is, a high current can be output by forming an electric field with the first gate electrode GE1 and the second gate electrode GE2, and furthermore, the capacitor electrode CE, with a constant voltage different from the voltages applied to the first gate electrode GE1 and the second gate electrode GE2, can disperse the electric field on the drain region DE, thereby stabilizing the current output.

[0080] As described above, since the capacitor electrode CE constituting the storage capacitor Cst in the sub-pixel SP is disposed on the second gate electrode GE2, the area increase caused by the arrangement of the storage capacitor Cst can be prevented.

[0081] Furthermore, since the second gate electrode GE2, which forms the storage capacitor Cst with the capacitor electrode CE, is configured not to overlap with a portion of the channel region CH, the capacitor electrode CE can overlap with a portion of the channel region CH of the active layer ACT.

[0082] Therefore, since it makes it possible to control the electric field of the capacitor electrode CE, the current stability of the driving transistor DRT can be improved by controlling the electric field of the capacitor electrode CE, while the output current of the driving transistor DRT can be increased by using the dual gate electrode.

[0083] Specifically, the structure of the gate electrode included in the driving transistor DRT is described, for example, the first gate electrode GE1 can be configured to overlap with the channel region CH of the active layer ACT.

[0084] Furthermore, the length of the first gate electrode GE1 can be the same as the length of the channel region CH.

[0085] Since the second gate electrode GE2, which serves as the top gate electrode in the dual-gate electrode structure, does not overlap with a portion of the channel region CH, the first gate electrode GE1, which serves as the bottom gate electrode, can be configured to completely overlap with the channel region CH.

[0086] The second gate electrode GE2 can be configured to overlap with the first region A1, which is a portion of the channel region CH of the active layer ACT. Furthermore, the second gate electrode GE2 can be configured not to overlap with the second region A2 of the channel region CH of the active layer ACT.

[0087] Therefore, the length of the second gate electrode GE2 can be shorter than the length of the channel region CH of the active layer ACT. Furthermore, the length of the second gate electrode GE2 can be shorter than the length of the first gate electrode GE1.

[0088] Here, one end of the second gate electrode GE2 can be configured to overlap with the boundary of the channel region CH. And the other end of the second gate electrode GE2 can be configured to be spaced apart from the boundary of the channel region CH.

[0089] In other words, such as Figure 4 In the example shown, the second gate electrode GE2 can be configured to align with the boundaries of the channel region CH and the source region SE of the active layer ACT, and can form a dual gate electrode with the first gate electrode GE1 to increase the output current of the drive transistor DRT.

[0090] The capacitor electrode CE is located on the second gate electrode GE2. The capacitor electrode CE may include a portion that overlaps with the second gate electrode GE2 and a portion that does not overlap with the second gate electrode GE2 but overlaps with the channel region CH of the active layer ACT.

[0091] For example, the capacitor electrode CE may include a first portion CEa that overlaps with a first region A1 of the channel region CH and a second portion CEb that overlaps with a second region A2 of the channel region CH.

[0092] Since the first part CEa of the capacitor electrode CE overlaps with the first region A1 of the channel region CH, it can form a storage capacitor Cst with the second gate electrode GE2.

[0093] Since the second part CEb of the capacitor electrode CE overlaps with the second region A2 of the channel region CH, and no other electrodes are placed between them, electric field control can be performed by the second part CEb of the capacitor electrode CE.

[0094] The length of the capacitor electrode CE can be the same as the length of the channel region CH.

[0095] For example, the source region SE and drain region DE of the active layer ACT can be formed by performing a doping process while the capacitor electrode CE is in place. Therefore, the boundary of the capacitor electrode CE and the boundary of the channel region CH of the active layer ACT can overlap with each other.

[0096] Furthermore, since the capacitor electrode CE is disposed after the third gate insulating layer GI3 is disposed on the second gate electrode GE2 which overlaps only with the first region A1 of the channel region CH, the capacitor electrode CE may include a portion with a height change.

[0097] Such as Figure 4 In the example shown, the first portion CEa of the capacitor electrode CE can be positioned at least a portion above the second portion CEb. Furthermore, the distance d1 between the first portion CEa of the capacitor electrode CE and the active layer ACT can be greater than the distance d2 between the second portion CEb of the capacitor electrode CE and the active layer ACT.

[0098] Therefore, the second part CEb of the capacitor electrode CE can be positioned closer to the active layer ACT, which can easily perform electric field control for stabilizing the output characteristics of the drive transistor DRT.

[0099] Here, the portion where the height of the capacitor electrode CE changes can be located in a region other than the area where the capacitor electrode CE and the second gate electrode GE2 overlap. For example, the portion where the height of the capacitor electrode CE changes can be positioned spaced d3 from the side surface of the second gate electrode GE2.

[0100] In other words, the storage capacitor Cst can be formed by making the distance between the capacitor electrode CE and the second gate electrode GE2 uniform. Furthermore, since the portion overlapping with the second region A2 of the channel region CH is positioned closer to the channel region CH when the height of the capacitor electrode CE changes, the output characteristics of the drive transistor DRT can be stabilized through electric field control.

[0101] Furthermore, since the first gate electrode GE1, which serves as the bottom gate electrode, can be located in a region that overlaps with the channel region CH, the length of the first gate electrode GE1 can be equal to or greater than the length of the channel region CH in certain circumstances.

[0102] Figure 5 Another example of the cross-sectional structure of the driving transistor DRT is shown, and it is shown that... Figure 3 A diagram showing another example of the cross-sectional structure of the I-I' section.

[0103] Reference Figure 5 The first gate electrode GE1 can be located below the active layer ACT. The second gate electrode GE2 and the capacitor electrode CE can be located on the active layer ACT.

[0104] The second gate electrode GE2 can be configured to overlap with the first region A1 of the channel region CH of the active layer ACT. A portion of the capacitor electrode CE can be located in the region overlapping with the first region A1 of the channel region CH to overlap with the second gate electrode GE2, and another portion of the capacitor electrode CE can be located in the region overlapping with the second region A2 of the channel region CH.

[0105] A portion of the boundary between the second gate electrode GE2 and the capacitor electrode CE may overlap with the boundary between the channel region CH and the source region SE of the active layer ACT.

[0106] The second gate electrode GE2 can overlap with the first region A1 of the channel region CH to form a dual-gate electrode with the first gate electrode GE1. Therefore, the output current of the driving transistor DRT can be increased.

[0107] Furthermore, since the second gate electrode GE2 is configured not to overlap with the second region A2 of the channel region CH and a portion of the capacitor electrode CE is configured to overlap with the second region A2 of the channel region CH, the current stability of the driving transistor DRT can be improved.

[0108] Therefore, since there is a region where the second gate electrode GE2 does not overlap with the channel region CH, the first gate electrode GE1, which forms a dual-gate electrode with the second gate electrode GE2, can be configured to completely overlap with the channel region CH. Furthermore, considering process margins, the first gate electrode GE1 can be configured such that its boundary lies outside the boundary of the channel region CH.

[0109] For example, a portion of the boundary of the first gate electrode GE1 may be located outside the channel region CH, spaced d4 apart from the boundaries of the channel region CH and the source region SE. Furthermore, a portion of the boundary of the first gate electrode GE1 may be located outside the channel region CH, spaced d5 apart from the boundaries of the channel region CH and the drain region DE.

[0110] In other words, the length of the first gate electrode GE1 along the channel direction can be greater than the length of the capacitor electrode CE located on the second gate electrode GE2 along the channel direction.

[0111] Furthermore, since the doping process is performed with the capacitor electrode CE set to be shorter than the first gate electrode GE1, a portion of the first gate electrode GE1 can overlap with the source region SE or the drain region DE.

[0112] Therefore, it is possible to prevent the occurrence of offset regions in the channel region CH of the active layer ACT, and to provide a drive transistor DRT that improves output current and stability.

[0113] The above example illustrates the case where the storage capacitor Cst is formed on the active layer ACT, but in some cases, embodiments of this disclosure can be applied to cases where the storage capacitor Cst is disposed below the active layer ACT.

[0114] For example, a capacitor electrode CE is provided, and the bottom gate electrode can be disposed on the capacitor electrode CE to overlap with a portion of the channel region CH. Furthermore, since the top gate electrode is configured to completely overlap with the channel region CH, a drive transistor DRT with improved drive performance and stability can be provided, while minimizing the device area.

[0115] Furthermore, the above example illustrates the case where the driving transistor DRT is P-type, but the embodiments of this disclosure can be applied to the case of N-type.

[0116] Figure 6 This is yet another example of the cross-sectional structure of the driving transistor DRT, and it is shown as... Figure 3 A diagram showing another example of the cross-sectional structure of the I-I' section.

[0117] Reference Figure 6 The active layer ACT can be disposed on the first gate electrode GE1. Furthermore, the second gate electrode GE2 and the capacitor electrode CE can be disposed on the active layer ACT.

[0118] The active layer ACT may include a lightly doped region LDD in at least one of the regions in contact with the source region SE and the drain region DE. The lightly doped region LDD is a region in which the doping level is lower than that of the source region SE or the drain region DE, and the lightly doped region LDD may be formed to reduce leakage current.

[0119] Since the lightly doped region LDD is the region where doping is performed, the inner boundary of the lightly doped region LDD can overlap with the boundary of the capacitor electrode CE.

[0120] Furthermore, since the first gate electrode GE1 is configured to be longer than the capacitor electrode CE, a portion of the first gate electrode GE1 can overlap with the lightly doped region LDD.

[0121] For example, the first gate electrode GE1 may overlap with the lightly doped region LDD and may be positioned inwardly spaced from the boundary d6 between the source region SE and the lightly doped region LDD. Furthermore, the first gate electrode GE1 may overlap with the lightly doped region LDD and may be positioned inwardly spaced from the boundary d7 between the drain region DE and the lightly doped region LDD.

[0122] In other words, the boundary of the first gate electrode GE1 can be located between the inner boundary and the outer boundary of the lightly doped region LDD. Alternatively, in some cases, the boundary of the first gate electrode GE1 can overlap with either the inner or outer boundary of the lightly doped region LDD.

[0123] When the first gate electrode GE1 overlaps with the lightly doped region LDD, even the lightly doped region LDD that overlaps with the first gate electrode GE1 can be regarded as the channel region CH.

[0124] Therefore, it can be assumed that the length of the first gate electrode GE1 is the same as the length of the channel region CH. Furthermore, it can be assumed that the length of the second gate electrode GE2 and the length of the capacitor electrode CE are less than the length of the channel region CH of the active layer ACT.

[0125] Even in a structure where the active layer ACT includes a lightly doped region LDD, the second gate electrode GE2 can overlap with a portion of the channel region CH of the active layer ACT. Therefore, the second gate electrode GE2 and the first gate electrode GE1 can form a dual-gate electrode, which can increase the output current of the driving transistor DRT.

[0126] Furthermore, a portion of the capacitor electrode CE located on the second gate electrode GE2 can overlap with the second gate electrode GE2 to form a storage capacitor Cst. Therefore, it is possible to prevent an increase in the area of ​​circuit elements due to the arrangement of the storage capacitor Cst in the sub-pixel SP.

[0127] Furthermore, a portion of the capacitor electrode CE can be disposed in the region where the second gate electrode GE2 is not disposed, and can overlap with a portion of the channel region CH. Therefore, the current stability of the driving transistor DRT can be improved by controlling the electric field of the capacitor electrode CE, which is subjected to a constant voltage different from the voltage applied to the first gate electrode GE1 or the second gate electrode GE2.

[0128] Figure 7 It is shown Figure 3 A diagram showing an example of the circuit structure of a sub-pixel SP.

[0129] Reference Figure 7 The switching transistor SWT, which does not require high output current, can be configured with a single gate electrode. Furthermore, the driving transistor DRT, which requires high output current to provide the driving current Ied to the light-emitting element ED, can be configured with a dual-gate electrode.

[0130] Therefore, the driving transistor DRT may include two gate electrodes electrically connected to the first node N1 to which the data voltage is applied.

[0131] Here, the area where one gate electrode forming the storage capacitor Cst overlaps with the channel region CH can be smaller than the area where the other gate electrode overlaps with the channel region CH. Furthermore, the capacitor electrode CE forming the storage capacitor Cst with the gate electrode can overlap with a portion of the channel region CH.

[0132] Therefore, it can be assumed that the driving transistor DRT includes a gate electrode electrically connected to the second node N2, which is supplied with a first driving voltage Vdd. In other words, it can be assumed that a portion of the capacitor electrode CE forms the gate electrode of the driving transistor DRT.

[0133] As described above, since the current stability is improved by controlling the electric field of the capacitor electrode CE, and the output current of the drive transistor DRT is increased by the structure of the dual-gate electrode, a drive transistor DRT with improved drive characteristics and stability can be provided.

[0134] Furthermore, since the capacitor electrode CE is disposed on the gate electrode of the driving transistor DRT, and the performance of the driving transistor DRT is improved by the structure of the capacitor electrode CE and the gate electrode, the area occupied by the circuit elements in the sub-pixel SP can be reduced.

[0135] Therefore, according to the embodiments of this disclosure, since the driving transistor DRT with improved driving performance and stability can be disposed in the sub-pixel SP while minimizing its area, a high-resolution display device 100 can be realized while improving luminous efficiency.

[0136] The foregoing description has been provided to enable any person skilled in the art to make and use the technical ideas of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this disclosure. The foregoing description and drawings provide examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of this disclosure. Therefore, the scope of this disclosure is not limited to the embodiments shown, but should be given the widest scope consistent with the claims. The scope of protection of this disclosure should be interpreted based on the appended claims, and all technical ideas within the equivalent scope of the claims should be interpreted as included within the scope of this disclosure.

[0137] Cross-references to related applications

[0138] This application claims priority to Korean Patent Application No. 10-2019-0141593, filed November 7, 2019, pursuant to Section 119(a) of the United States Patent Act (35 USC § 119(a)), which is incorporated herein by reference for all purposes as if it were fully set forth herein. Furthermore, if this application claims priority in a country other than the United States for the same reasons as described above, the entire contents of that country are incorporated herein by reference.

Claims

1. A display device, comprising: The first gate electrode is located on the substrate; An active layer is located on the first gate electrode and includes a channel region that overlaps with at least a portion of the first gate electrode. The second gate electrode is located on the active layer and overlaps with the first region of the channel region; as well as A capacitor electrode comprising: a first portion located on and overlapping at least a portion of a second gate electrode; and a second portion connected to the first portion and overlapping at least a portion of a second region other than the first region of the channel region. Wherein, one end of the capacitor electrode overlaps with the boundary of one side of the second gate electrode, and the other end of the capacitor electrode does not overlap with the boundary of the other side of the second gate electrode.

2. The display device according to claim 1, wherein, The length of the capacitor electrode is the same as or shorter than the length of the channel region.

3. The display device according to claim 1, wherein, At least a portion of the boundary of the capacitor electrode overlaps with the boundary of the channel region.

4. The display device according to claim 1, wherein, The first portion of the capacitor electrode is positioned above at least a portion of the second portion of the capacitor electrode.

5. The display device according to claim 1, wherein, The point where the first part of the capacitor electrode and the second part of the capacitor electrode connect to each other is located in a region other than the region overlapping with the second gate electrode.

6. The display device according to claim 4, wherein, The point of height change in the second part of the capacitor electrode is located in a region other than the region overlapping with the second gate electrode.

7. The display device according to claim 1, wherein, The capacitor electrode is electrically connected to the source region included in the active layer.

8. The display device according to claim 1, wherein, The length of the second gate electrode is shorter than the length of the channel region.

9. The display device according to claim 1, wherein, One end of the second gate electrode overlaps with the boundary of one side of the channel region, and the other end of the second gate electrode is spaced apart from the boundary of the other side of the channel region.

10. The display device according to claim 1, wherein, The second gate electrode is located in a region other than the region that overlaps with the second region of the channel region.

11. The display device according to claim 1, wherein, The length of the first gate electrode is the same as or greater than the length of the channel region.

12. The display device according to claim 1, wherein, At least a portion of the boundary of the first gate electrode is located outside the boundary of the channel region.

13. The display device according to claim 1, wherein, A constant voltage, different from the voltage supplied to the second gate electrode, is supplied to the capacitor electrode.

14. The display device according to claim 1, wherein, The same voltage is applied to both the first gate electrode and the second gate electrode.

15. A display device, comprising: The display panel is provided with a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels; Multiple light-emitting elements are disposed in each of the plurality of sub-pixels; as well as Multiple driving transistors are disposed in each of the plurality of sub-pixels and electrically connected to the light-emitting element. Each of the plurality of driving transistors includes: Active layer; A first gate electrode is located on one surface of the active layer and overlaps with the channel region of the active layer; A second gate electrode, located on another surface of the active layer and overlapping a portion of the channel region of the active layer; and A third gate electrode, located on the other surface of the active layer, is positioned further from the active layer than the second gate electrode and overlaps with the channel region of the active layer. In this configuration, a portion of the third gate electrode is positioned above at least a portion of the other portions of the third gate electrode.

16. The display device according to claim 15, wherein, The second gate electrode is located in a region other than a portion of the region where the third gate electrode overlaps with the channel region.

17. The display device according to claim 15, wherein, A portion of the third gate electrode overlaps with the second gate electrode.

18. The display device according to claim 15, wherein, A portion of the boundary of the third gate electrode overlaps with a portion of the boundary of the second gate electrode.

19. The display device according to claim 15, wherein, The same voltage is applied to the first gate electrode and the second gate electrode, and a constant voltage different from the voltage applied to the second gate electrode is applied to the third gate electrode.

20. A thin-film transistor, comprising: First gate electrode; An active layer is located on the first gate electrode and includes a channel region that overlaps with at least a portion of the first gate electrode. The second gate electrode is located on the active layer and overlaps with the first region of the channel region; as well as A third gate electrode, which is at least partially located on the second gate electrode, overlaps with at least a portion of the second gate electrode, and overlaps with at least a portion of the second region other than the first region of the channel region. Wherein, the vertical distance between a portion of the third gate electrode and the active layer is a first distance, and the vertical distance between another portion of the third gate electrode and the active layer is a second distance that is less than the first distance.

21. A display device comprising a thin-film transistor according to claim 20.

Images