Semiconductor device with improved short-circuit endurance time and method of manufacturing the same

Abstract

A semiconductor device (10) includes a substrate (12), a drift layer (14), a well region (16), and a source region (18). The substrate (12) has a first conductivity type. The drift layer (14) has the first conductivity type and is located on the substrate (12). The well region (16) has a second conductivity type opposite the first conductivity type and provides a channel region (28). The source region (18) is located in the well region (16) and has the first conductivity type. A doping concentration of the well region (16) along a surface of the drift layer (14) opposite the substrate (12) is variable such that the well region (16) includes a region of increased doping concentration at a distance from a junction between the source region (18) and the well region (16).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to improvements to semiconductor devices to increase their short-circuit withstand time. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in power electronics. An important performance characteristic of MOSFETs used in power applications is their short-circuit withstand time. The short-circuit withstand time of a MOSFET is the amount of time it can withstand a short-circuit event (e.g., a drain-to-source short circuit) before a failure occurs. The longer the short-circuit withstand time of a MOSFET, the less likely it is to fail due to a short-circuit event in its application. Therefore, a large short-circuit withstand time is desirable.

[0003] Recently, silicon carbide MOSFETs have replaced their silicon counterparts used in power applications. This is due to significant improvements in performance aspects such as on-resistance and switching speed of silicon carbide MOSFETs. However, the short-circuit withstand time of silicon carbide MOSFETs has been limited due to MOS channel characteristics and short-channel effects. For MOS channel characteristics, the threshold voltage of silicon carbide MOSFETs decreases with temperature, while the transconductance increases with temperature. These characteristics reduce the short-circuit withstand time of silicon carbide MOSFETs. For short-channel effects, this leads to poor saturation characteristics and relatively low output resistance. These effects further reduce the short-circuit withstand time of silicon carbide MOSFETs.

[0004] Typically, attempts to increase the short-circuit withstand time of a silicon carbide MOSFET involve increasing the resistance in the junction field-effect transistor (JFET) region of the device and / or adding an external resistor to the source of the device. While these solutions do increase the short-circuit withstand time of the silicon carbide MOSFET, they also increase its on-resistance, which degrades overall performance.

[0005] Therefore, there is a need for MOSFETs with improved short-circuit withstand time and methods for their fabrication that do not compromise other performance characteristics. Summary of the Invention

[0006] In one embodiment, a semiconductor device includes a substrate, a drift layer, a well region, and a source region. The substrate has a first conductivity type. The drift layer has a first conductivity type and is located on the substrate. The well region has a second conductivity type opposite to the first conductivity type and forms a channel region. The source region is located within the well region and has a first conductivity type. The well region lies between the source region and the drift layer. The doping concentration of the well region along the surface of the drift layer opposite the substrate is non-uniform, causing the doping concentration of the well region to vary in its lateral dimensions. As described, by providing a well region with a doped distribution, the short-circuit withstand time of the semiconductor device can be improved while maintaining other performance characteristics of the device.

[0007] In one embodiment, the well region includes a region of increased carrier concentration at a distance from the interface between the source region and the well region. This region of increased carrier concentration may overlap with the channel region.

[0008] In one embodiment, the semiconductor device includes a substrate, a drift layer, a well region, and a source region. The substrate has a first conductivity type. The drift layer has a first conductivity type and is located on the substrate. The well region has a second conductivity type opposite to the first conductivity type and forms a channel region. The source region is located in the well region and has a first conductivity type. The well region is located between the source region and the drift layer. The depth of the source region is non-uniform. As described, by providing a source region with a variable depth, the short-circuit withstand time of the semiconductor device can be improved while maintaining other performance characteristics of the device.

[0009] In one embodiment, the depth of the source region increases proportionally to the distance from the channel region.

[0010] In one embodiment, a method for manufacturing a semiconductor device includes: setting a substrate; setting a drift layer on the substrate; setting a well region in the drift layer; and setting a source region in the well region. The substrate and the drift layer have a first conductivity type. The well region has a second conductivity type opposite to the first conductivity type and is configured as a channel region. The source region has a first conductivity type and is positioned such that the well region lies between the source region and the drift layer. The doping concentration of the well region along the surface of the drift layer opposite the substrate is non-uniform, causing the doping concentration of the well region to vary in its lateral dimensions. By setting a well region with a variable doping concentration as described above, the short-circuit withstand time of the semiconductor device can be improved while maintaining other performance characteristics of the device.

[0011] In various embodiments, the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0012] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement its additional aspects. Attached Figure Description

[0013] The accompanying drawings, which are included in and form a part of this specification, illustrate several aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0014] Figure 1 A semiconductor device according to an embodiment of the present disclosure is shown.

[0015] Figures 2A to 2D The doping distribution of the well region in a MOSFET according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A semiconductor device according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A semiconductor device according to an embodiment of the present disclosure is shown.

[0018] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0019] Figures 6A to 6E A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0020] Figure 7 This is a flowchart illustrating a method for setting a well region in a semiconductor device according to an embodiment of the present disclosure.

[0021] Figure 8A and Figure 8B A method for setting a well region in a semiconductor device according to an embodiment of the present disclosure is shown.

[0022] Figure 9A and Figure 9B A method for setting a well region in a semiconductor device according to an embodiment of the present disclosure is shown.

[0023] Figure 10 This is a flowchart illustrating a method for setting a source region in a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 11A and Figure 11B A method for setting a source region in a semiconductor device according to an embodiment of the present disclosure is shown.

[0025] Figure 12A and Figure 12B A method for setting a source region in a semiconductor device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0026] The embodiments described below illustrate the necessary information to enable those skilled in the art to practice the embodiments and demonstrate the best mode for practicing the embodiments. When reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize their application unless specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0027] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it can be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending to another element," it can be directly above or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "directly extending to the other element," no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0029] This document may use relative terms such as “below,” “above,” “upper,” “lower,” “horizontal,” or “vertical” to describe the relationship between one element, layer, or region and another, as shown in the figure. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those shown in the figure.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the prior art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0032] Figure 1 A semiconductor device 10 according to an embodiment of the present disclosure is shown. The semiconductor device 10 includes: a substrate 12; a drift layer 14 on the substrate 12; a well region 16 in the surface of the drift layer 14 opposite to the substrate 12; a source region 18 in the surface of the drift layer 14 opposite to the substrate 12, such that the source region 18 is located within the well region 16; a source contact 20 on the surface of the drift layer 14 opposite to the substrate 12, and particularly on a portion of the well region 16 and the source region 18; a drain contact 22 on the surface of the substrate 12 opposite to the drift layer 14; a gate oxide layer 24 on the surface of the drift layer 14 opposite to the substrate 12, particularly on a portion of the well region 16 and the source region 18; and a gate contact 26 on the gate oxide layer 24. The source contact 20 is separated from the gate oxide layer 24 and the gate contact 26 on the surface of the drift layer 14 opposite to the substrate 12. The portion of the well region 16 along the surface of the drift layer 14 opposite to the substrate 12, below the gate oxide layer 24, forms the channel region 28 of the semiconductor device 10.

[0033] The substrate 12 and drift layer 14 may comprise silicon carbide. In one embodiment, the substrate 12, drift layer 14, and source region 18 are all n-doped, while the well region 16 is p-doped. However, the principles of this disclosure also apply to the semiconductor device 10, wherein the substrate 12, drift layer 14, and source region 18 are p-doped, while the well region is n-doped. The doping concentration of the substrate 12 can be 5 × 10⁻⁶. 17 Up to 1×10 20 cm -3Between. In various embodiments, the doping concentration of substrate 12 can be between 5 × 10⁻⁶. 17 Up to 1×10 20 cm -3 The doping concentration can be any concentration within the range of 5 × 10⁻⁶, or can cover any subrange of that range. The doping concentration of drift layer 14 can be 5 × 10⁻⁶. 13 Up to 1×10 18 cm -3 Between. In various embodiments, the doping concentration of the drift layer 14 can be between 5 × 10⁻⁶. 13 Up to 1×10 18 cm -3 Any doping concentration within the range of 2 × 10⁻⁶, or any subrange that may cover that range. As discussed in detail below, well region 16 may include a region 30 with increased doping concentration, having a doping concentration of 2 × 10⁻⁶. 17 Up to 5×10 19 cm -3 Between. The doping concentration in region 30, where the doping concentration increases, can be between 2 × 10⁻⁶. 17 Up to 5×10 19 cm -3 Any doping concentration within the range between, or any subrange within that range that can be covered. For example, the doping concentration in region 30, where the doping concentration increases, can be 5 × 10⁻⁶. 17 Up to 5×10 19 cm -3 Between, 1×10 18 Up to 5×10 19 cm -3 Between, 5×10 18 Up to 5×10 19 cm -3 Between, 1×10 19 Up to 5×10 19 cm -3 Between, 5×10 17 Up to 1×10 18 cm -3 Between, 1×10 18 Up to 1×10 19 cm -3 Between, etc. The doping concentration of the remaining part of well region 16 can be 5 × 10⁻⁶. 15 Up to 5×10 17 cm -3 The doping concentration of the remaining portion of well region 16 can be between 5 × 10⁻⁶. 15 Up to 5×10 17 cm -3 Any doping concentration within the range between, or any subrange within that range that can be covered. For example, the doping concentration of the remaining portion of well region 16 can be 1 × 10⁻⁶.16 Up to 5×10 17 cm -3 Between, 5×10 16 Up to 5×10 17 cm -3 Between, 1×10 17 Up to 5×10 17 cm -3 Between, 5×10 15 Up to 1×10 17 cm -3 Between, 5×10 15 Up to 5×10 16 cm -3 Between, etc. The doping concentration of source region 18 can be 1×10. 18 Up to 5×10 21 cm -3 Between. The doping concentration of source region 18 can be between 1 × 10⁻⁶. 18 Up to 5×10 21 cm -3 Any doping concentration within the range of 5 × 10⁻⁶, or any subrange within that range that can be covered. For example, the doping concentration of source region 18 can be 5 × 10⁻⁶. 18 Up to 5×10 21 cm -3 Between, 1×10 19 Up to 5×10 21 cm -3 Between, 5×10 19 Up to 5×10 21 cm -3 Between, 1×10 20 Up to 5×10 21 cm -3 Between, 5×10 20 Up to 5×10 21 cm -3 Between, 1×10 21 Up to 5×10 21 cm -3 Between, 1×10 18 Up to 1×10 21 cm -3 Between, 1×10 18 Up to 5×10 20 cm -3 Between, 1×10 18 Up to 1×10 20 cm -3 Between, 1×10 18 Up to 5×10 19 cm -3 Between, 1×10 18 Up to 1×10 19cm -3 Between, etc.

[0034] In one embodiment, the semiconductor device 10 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In operation, a bias voltage set at the gate contact 26 higher than the threshold voltage of the semiconductor device 10 makes the channel region 28 of the device conductive, allowing current to flow from its drain contact 22 to the source contact 20. When the bias voltage is lower than the threshold voltage of the semiconductor device 10, the channel region 28 is not sufficiently conductive to allow current to flow from the drain contact 22 to the source contact 20. Therefore, the semiconductor device 10 blocks the drain-to-source voltage across the drift layer 14. As described above, in some applications, the semiconductor device 10 may experience short-circuit events, causing the drain contact 22 to be short-circuited to another power source. These short-circuit events can result in extremely high currents flowing through the semiconductor device 10, leading to device damage and failure after a short period. As described above, the amount of time a device can withstand a short-circuit event without failure is called the short-circuit withstand time. Furthermore, as described above, conventional MOSFETs, and especially silicon carbide MOSFETs, experience relatively low short-circuit withstand times.

[0035] As mentioned above, one reason for the relatively low short-circuit withstand time of silicon carbide MOSFETs is due to the MOS channel characteristics, where transconductance increases with increasing temperature and threshold voltage decreases with increasing temperature. When semiconductor device 10 is turned on, current flows from drift layer 14 along the inversion layer in well region 16 into source region 18 and to source junction 20. Due to the finite resistance of source region 18, this current flow results in a voltage drop across source region 18. The voltage drop across the resistance of source region 18 ( V sp The value is positive, thus increasing the reverse bias between source region 18 and well region 16. The threshold voltage of semiconductor device 10 ( V th ) can be expressed according to equation (1):

[0036]

[0037] in, V th It is the threshold voltage of semiconductor device 10. V th0 Is when V sp The threshold voltage of semiconductor device 10 when the voltage across the source region 18 resistor is zero, γ is the bulk effect parameter given by equation (2):

[0038]

[0039] and pGiven by equation (3):

[0040]

[0041] in, N A This is the doping concentration of well region 16. As shown in the equation above, V th along with V sp The doping concentration increases with the increase of the doping concentration in well region 16. N A The faster it increases, V th The faster the increase, the better. Therefore, increasing the doping concentration of the well region 16 relative to the temperature of the semiconductor device 10 is one way to offset or compensate for the increase in transconductance and the decrease in threshold voltage. However, increasing the doping concentration throughout the well region 16 results in an unacceptably high threshold voltage and low channel mobility (or low transconductance) under normal operating conditions. While the channel region 28 of the semiconductor device 10 could be shortened to a length of less than 0.2 micrometers (μm) to reduce the threshold voltage and increase transconductance, fabricating MOSFETs with these small dimensions can be very difficult.

[0042] Therefore, to increase the short-circuit withstand time of the semiconductor device 10, the well region 16 has a non-uniform doping distribution that varies in lateral dimensions. Specifically, the well region 16 includes a region 30 with increased doping concentration. The region 30 with increased doping concentration is a sub-region of the well region 16 that is more heavily doped than the remainder of the well region 16. The region 30 with increased doping concentration is located within the well region 16 along the surface of the drift layer 14 opposite to the substrate 12, and thus within the channel region 28. The region 30 with increased doping concentration is located at a distance from the junction spacing between the source region 18 and the well region 16 along the surface of the drift layer 14 opposite to the substrate 12. D isAt this location, the region 30 with increased doping concentration is separated from the source region 18 by the distance described below. By including the region 30 with increased doping concentration and doping the remainder of the well region 16 to a smaller level, a favorable trade-off is achieved between short-circuit withstand time, threshold voltage, and transconductance. Specifically, the short-circuit withstand time is significantly increased with minimal impact on the threshold voltage and transconductance of the semiconductor device 10. Furthermore, the region 30 with increased doping concentration can also reduce short-channel effects by increasing the shielding of the channel region 28 against high electric fields by suppressing lateral depletion of the well region 16. Although the region 30 with increased doping concentration is shown as a discrete region within the well region 16, the depiction between the region 30 with increased doping concentration and the remainder of the well region 16 can be asymptotic. Typically, the doping concentration of the well region 16 can increase proportionally to the distance from the interface between the source region 18 and the well region 16 along the surface of the drift region 14 opposite to the substrate 12 (point X) towards the interface between the well region 16 and the drift region 14 along the surface of the drift region 14 opposite to the substrate 12 (point X''). Therefore, the highest doping concentration of the well region 16 can occur at the interface between the well region 16 and the drift region 14 along the surface of the drift region 14 opposite to the substrate 12 (point X''), while the lowest doping concentration of the well region 16 can occur at the interface between the source region 18 and the well region 14 along the surface of the drift region opposite to the substrate 12 (point X).

[0043] Figure 2A An embodiment of the present disclosure is shown in Figure 1 The doping distribution along the surface of the drift layer 14 opposite to the substrate 12 between points X and X'' is shown. Point X is located on the edge of the source region 18 extending perpendicularly to the surface of the drift layer 14 opposite to the substrate 12 (the interface between the source region 18 and the well region 16), and point X'' is located on the edge of the well region 16 extending perpendicularly to the surface of the drift layer 14 opposite to the substrate 12 (the interface between the well region 16 and the drift layer 14). As shown, the doping concentration of the well region 16 along the surface of the drift layer 14 opposite to the substrate 12 remains relatively constant between points X and X', increasing and remaining at that level until point X'', which is the interface between the well region 16 and the side of the drift layer 14. The region 30 where the doping concentration increases is between points X and X''.

[0044] In one embodiment, the doping concentration of the region 30 with increased doping concentration is 1.1 to 250 times greater than the doping concentration of the remainder of the well region 16. The doping concentration of the region 30 with increased doping concentration can be any factor within the range of 1.1 to 250 times greater than the doping concentration of the remainder of the well region 16, or any subrange of that range. For example, in various embodiments, the doping concentration of the region 30 with increased doping concentration is 10 to 250 times, 50 to 250 times, 100 to 250 times, and 200 to 250 times greater than the doping concentration of the remainder of the well region 16. Specifically, as described above, the doping concentration of the region 30 with increased doping concentration can be 2 × 10⁻⁶. 17 Up to 5×10 19 cm -3 Between, while the doping concentration of the remaining part of well region 16 can be 5 × 10 15 Up to 5×10 17 cm -3 The distance between points X and X'. D is That is, the distance between the source region 18 and the region 30 with increasing doping concentration along the surface of the drift layer 14 opposite to the substrate 12 can be between 0.2 and 2 μm, or any subrange of that range. For example, in various embodiments, the distance between points X and X' D is The doping concentration region 30, i.e., the distance between points X' and X'', can be between 0.3 and 2 μm, 0.4 and 2 μm, 0.5 and 2 μm, 0.6 and 2 μm, 0.7 and 2 μm, 0.8 and 2 μm, 0.9 and 2 μm, 1 and 2 μm, 1.1 and 2 μm, 1.2 and 2 μm, 1.3 and 2 μm, 1.4 and 2 μm, 1.5 and 2 μm, 1.6 and 2 μm, 1.7 and 2 μm, 1.8 and 2 μm, 1.9 and 2 μm, 0.5 and 1 μm, 0.5 and 1.5 μm, 1 and 1.5 μm, or any other subrange within that range. For example, in various embodiments, the width of the region 30 with increased doping concentration can be any other subrange between 0.1 and 0.5 μm, 0.15 and 0.5 μm, 0.2 and 0.5 μm, 0.25 and 0.5 μm, 0.3 and 0.5 μm, 0.35 and 0.5 μm, 0.4 and 0.5 μm, 0.45 and 0.5 μm, 0.1 and 0.2 μm, 0.1 and 0.3 μm, 0.1 and 0.4 μm, or 0.05 and 0.5 μm.

[0045] Figure 2BThe diagram illustrates the doping distribution of a well region 16 along the surface of a drift layer 14 opposite to the substrate 12 between points X and X'', according to an additional embodiment of this disclosure. As shown, the doping concentration of the well region 16 along the surface of the drift layer 14 opposite to the substrate 12 remains relatively constant until point X', at which point it increases in a stepwise manner to reach a higher level and remains at that level until point X''.

[0046] Figure 2C The diagram illustrates the doping distribution of a well region 16 along the surface of a drift layer 14 opposite to the substrate 12 between points X and X'', according to another embodiment of this disclosure. As shown, the doping concentration of the well region 16 along the surface of the drift layer 14 opposite to the substrate 12 remains relatively constant until point X', at which point it increases linearly to a higher level and remains at that level until point X''.

[0047] Figure 2D The diagram illustrates the doping distribution of a well region 16 along the surface of a drift layer 14 opposite to the substrate 12 between points X and X'', according to another embodiment of this disclosure. As shown, the doping concentration of the well region 16 along the surface of the drift layer 14 opposite to the substrate 12 remains relatively constant until point X', at which point it increases exponentially to reach a higher level and remains at that level until point X''. It is noteworthy that the preceding... Figures 2A to 2D This is merely an example, and the doping distribution of the well region 16 along the surface of the drift layer 14 opposite the substrate 12 can be varied in any suitable manner without departing from the principles of this disclosure. Typically, the doping concentration of the well region 16 is non-uniform, such that the doping concentration varies in the lateral dimension. The doping concentration of the well region 16 can be constant in a first sub-region (e.g., between X and X') and variable in a second sub-region (e.g., between X' and X''), or the doping concentration of the well region 16 can be variable across the entire well region 16 (e.g., between X and X''). The doping concentration of the well region 16 can be varied in any suitable manner (linear, gradient, step, exponential, etc.).

[0048] To further improve the short-circuit withstand time of semiconductor device 10, the resistance of source region 18 can be increased. As mentioned above, this is typically done by adding an external resistor to source region 18. However, adding an external resistor to source region 18 will adversely affect other performance characteristics of semiconductor device 10. Another way to increase the resistance of source region 18 is to reduce the doping concentration of source region 18. However, uniformly reducing the doping concentration of source region 18 may result in a nonlinear ohmic contact with source junction 20, which could increase the forward voltage drop of semiconductor device 10 significantly.

[0049] therefore, Figure 3A semiconductor device 10 according to an additional embodiment of the present disclosure is shown. Figure 3 The semiconductor device 10 shown is basically similar to Figure 1 The semiconductor device 10 shown has a non-uniform depth in its source region 18, causing the depth of the source region 18 to vary laterally. Specifically, the source region 18 includes a depth-reduced region 32, whose depth is less than the depth of the remaining portion of the source region 18. The depth-reduced region 32 is located on the edge adjacent to the channel region 28 of the source region 18 of the semiconductor device 10 (the interface between the source region 18 and the well region 16), wherein this edge is perpendicular to the surface of the drift layer 14 opposite the substrate 12. As shown, the source region 18 can be laterally positioned between points Y and Y'', where point Y'' is located on a first edge of the source region 18 extending perpendicularly to the surface of the drift layer 14 adjacent to the channel region 28 and opposite the substrate 12, and point Y is located on a second edge of the source region 18 extending parallel to the first edge. At point Y', the depth of the source region 18 can be reduced, thereby initiating the depth-reduced region 32. In one embodiment, the width of the source region 18 between points Y and Y' is between 0.1 and 5 μm or any subrange of that range. For example, in various embodiments, the width of the source region 18 between points Y and Y' can be between 0.2 and 5 μm, 0.3 and 5 μm, 0.4 and 5 μm, 0.5 and 5 μm, 1 and 5 μm, 1.5 and 5 μm, 2 and 5 μm, 2.5 and 5 μm, 3 and 5 μm, 3.5 and 5 μm, 4 and 5 μm, 4.5 and 5 μm, 0.1 and 1 μm, 1 and 2 μm, 0.1 and 3 μm, 1 and 3 μm, 1 and 4 μm, 2 and 4 μm, 3 and 5 μm, etc. The width of the depth-reduced region 32 (i.e., the distance between points Y' and Y'') is also between 0.1 and 5 μm or any subrange of that range. For example, the width of the depth-reduced region 32 can be between 0.2 and 5 μm, 0.3 and 5 μm, 0.4 and 5 μm, 0.5 and 5 μm, 1 and 5 μm, 1.5 and 5 μm, 2 and 5 μm, 2.5 and 5 μm, 3 and 5 μm, 3.5 and 5 μm, 4 and 5 μm, 4.5 and 5 μm, 0.1 and 1 μm, 1 and 2 μm, 0.1 and 3 μm, 1 and 3 μm, 1 and 4 μm, 2 and 4 μm, 3 and 5 μm, etc. The depth of the source region 18 within the depth-reduced region 32... D epThe depth of the source region 18 can be between 0.1 and 1.0 μm or any sub-range of that range, while the depth of the remaining portion of the source region 18 can be between 0.2 and 1.5 μm or any sub-range of that range. For example, the depth of the source region 18 within the depth-reducing region 32... D ep It may be between 0.2 and 1.0 μm, 0.3 and 1.0 μm, 0.4 and 1.0 μm, 0.5 and 1.0 μm, 0.6 and 1.0 μm, 0.7 and 1.0 μm, 0.8 and 1.0 μm, 0.9 and 1.0 μm, 0.1 and 0.2 μm, 0.1 and 0.3 μm, 0.1 and 0.4 μm, 0.1 and 0.5 μm, 0.1 and 0.6 μm, 0.1 and 0.7 μm, 0.1 and 0.8 μm, 0.1 and 0.9 μm, 0.2 and 0.5 μm, 0.3 and 0.6 μm, 0.5 and 0.8 μm, etc. The depth of the remaining portion of source region 18 may be between 0.3 and 1.5 μm, 0.4 and 1.5 μm, 0.5 and 1.5 μm, 0.6 and 1.5 μm, 0.7 and 1.5 μm, 0.8 and 1.5 μm, 0.9 and 1.5 μm, 1.0 and 1.5 μm, 1.1 and 1.5 μm, 1.2 and 1.5 μm, 1.3 and 1.5 μm, 1.4 and 1.5 μm, 0.5 and 1.0 μm, 0.1 and 1.0 μm, 0.1 and 0.5 μm, etc. The depth of the region 32 with reduced depth may be 0.06 to 0.93 times smaller than the depth of the remaining portion of source region 18. Although the depth-reduced region 32 is shown as a single step of depth decrease compared to the remainder of the source region 18, the depth-reduced region 32 can also be formed such that the depth slope of the source region 18 decreases as the source region 18 approaches the channel region 28, or decreases in any suitable manner. Typically, the depth of the source region 18 can be non-uniform, such that the depth of the source region 18 increases proportionally to the distance from the side edge of the source region 18 closest to the channel region, wherein the side edge is perpendicular to the surface of the drift layer 14 opposite the substrate 12.

[0050] Figure 4 Another embodiment of the semiconductor device 10 is shown, wherein the depth of the source region 18 gradually decreases as it approaches the channel region 28. This decreasing depth region 32 can increase the resistance of the source region 18 while maintaining a linear ohmic contact with the source junction 20. Therefore, the short-circuit withstand time of the semiconductor device 10 is improved without increasing the forward voltage drop. It is worth noting that... Figure 3 and Figure 4The illustrated embodiments are merely exemplary. Typically, the depth of source region 18 can be varied in any suitable manner. For example, the depth of source region 18 can vary in the lateral dimension across the entire source region 18 (e.g., between Y and Y'', or any of its subregions (e.g., between Y' and Y'')). The depth of source region 18 can be varied in any suitable manner (e.g., linear, gradient, step, exponential, etc.).

[0051] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present disclosure. Figures 6A to 6E It shows Figure 5 The steps in the flowchart will therefore be related to... Figure 5 Let's discuss this together. First, set up substrate 12 (box 100 and...) Figure 6A The substrate 12 may include silicon carbide, and particularly may include a silicon carbide semiconductor wafer. A drift layer 14 (box 102 and...) is disposed on the substrate 12. Figure 6B The drift layer 14 can be formed by any suitable process, such as an epitaxial process, wherein the drift layer 14 is grown on the substrate 12 and subsequently processed (e.g., cleaning, polishing, etc.). A well region 16 (box 104 and...) is formed in the surface of the drift layer 14 opposite to the substrate 12. Figure 6C As discussed in further detail below, the well region 16 can be formed via an implantation process such as ion implantation. During the implantation process, a dedicated mask can be formed on the surface of the drift layer 14 opposite to the substrate 12 to create a desired doping distribution in the well region 16, thereby creating a region 30 with increased doping concentration to increase the short-circuit withstand time of the semiconductor device 10 as described above. Source regions 18 (boxes 106 and 107) are formed in the surface of the drift layer 14 opposite to the substrate 12. Figure 6D As discussed in further detail below, the source region 18 can be formed via an implantation process such as ion implantation. During the implantation process, a dedicated mask can be formed on the surface of the drift layer 14 opposite the substrate 12 to create the desired depth distribution of the source region 18, thereby forming a depth-reduced region 32 to increase the short-circuit withstand time of the semiconductor device 10 as described above. Source contact 20, drain contact 22, gate oxide layer 24, and gate contact 26 (boxes 108 and 109) are formed. Figure 6E ).

[0052] Figure 7 This is a flowchart illustrating details of setting up the trap area 16 according to an embodiment of the present disclosure. Figures 8A to 8B as well as Figures 9A to 9B It shows Figure 7 The steps in the flowchart, therefore, are related to Figure 7Let's discuss this together. First, a well injection mask 34 (box 200) is set on the surface of the drift layer 14 opposite to the substrate 12. Figure 8A and Figure 9A It is worth noting that the well implantation mask 34 is a specialized mask configured to produce a desired doping distribution in the well region 16. Specifically, the thickness, density, and / or material of the well implantation mask 34 can be varied to produce the desired doping distribution in the well region 16. Changing the characteristics of the well implantation mask 34 and selecting the doping depth distribution for ion implantation into the drift layer 14 to produce the well region 16 alters the doping concentration of the well region 16 at the surface of the drift layer 14 opposite the substrate 12, because it changes the depth at which ions are implanted therein. Figure 8A The diagram illustrates a simple step-down of the thickness of the well implantation mask 34 in the region where the doped concentration increase region 30 is formed after ion implantation. This step-down of the thickness of the well implantation mask 34 in the doped concentration increase region 30 prevents ions from penetrating deeply into the doped concentration increase region 30, resulting in a larger doping concentration near the surface of the drift layer 14 opposite the substrate 12 in this region. Figure 9A In this process, after ion implantation, a slope of the thickness of a well implantation mask 34 is formed on the region 30 in which the doping concentration is increased. The slope of the well implantation mask 34 on the region 30 with increased doping concentration causes ions to penetrate to different depths on the slope in this region, resulting in an increase in the slope of the doping concentration in the region 30 with increased doping concentration. It is worth noting that... Figure 8A and Figure 9A The well implantation mask 34 shown is merely exemplary. Any suitable process for obtaining the region 30 with increased doping concentration can be used to generate the well region 16, all of which are considered herein. Ions are then implanted into the surface of the drift layer 14 opposite the substrate 12 and through the well implantation mask 34 (box 202, Figure 8B and Figure 9B As described above, this creates well region 16 and region 30 with increased doping concentration. Well region implantation mask 34 (not shown) can then be removed. In one embodiment, a reverse doping distribution can be used to implant ions such that the peak doping concentration resulting from implantation occurs at a certain distance below the implanted surface. As described above, controlling the reverse doping distribution of ion implantation and the characteristics (e.g., thickness) of well region implantation mask 34 allows the desired doping distribution of well region 16 to be generated along the surface of drift layer 14 opposite substrate 12. To achieve the desired doping distribution of well region 16, a 1×10⁻⁶ mask can be used. 12 Up to 5×10 15 cm -2The implantation dose and implantation energy are between 10 keV and 1.5 MeV. In various embodiments, the dopant used to form the well region can be aluminum, boron, or beryllium.

[0053] Figure 10 This is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present disclosure. Figures 11A to 11B and Figures 12A to 12B It shows Figure 10 The steps in the flowchart, therefore, are related to Figure 10 Let's discuss this together. First, a source region injection mask 36 (box 300) is set on the surface of the drift layer 14 opposite to the substrate 12. Figure 11A and Figure 12A It is worth noting that the source implantation mask 36 is a dedicated mask configured to produce a desired depth distribution in the source region 18. Specifically, the thickness, density, and / or material of the source implantation mask 36 can be varied to produce the desired depth distribution of the source region 18. Changing the characteristics of the source implantation mask 36 and the doping depth distribution used to implant ions into the drift layer 14 to produce the source region 18 alters the doping concentration of the source region 18 at the surface of the drift layer 14 opposite the substrate 12, because it changes the depth to which ions are implanted. Figure 11A In this process, the simple step-down of the thickness of the source region implantation mask 36 over the depth-reducing region 32 (not shown but to be formed after ion implantation) prevents ions from penetrating as deeply, thus creating the depth-reducing region 32. Figure 12A In this process, the slope of the source region implantation mask 36 (not shown but to be formed after ion implantation) provided on the depth-reducing region 32 causes the depth of the source region 18 to decrease as the slope towards the channel region 28 of the semiconductor device 10 thickens. It is worth noting that... Figure 11A and Figure 12A The source implantation mask 36 shown is merely exemplary. Any suitable process for obtaining the depth-reduced region 32 can be used to generate the source region 18, all of which are considered herein. Ions are then implanted into the surface of the drift layer 14 opposite the substrate 12 and through the source implantation mask 36 (box 302, ...). Figure 11B and Figure 12B As described above, this creates source region 18 and a region 32 with reduced depth. The mask (not shown) can then be removed. In one embodiment, a flat doping distribution can be used to implant ions, such that the doping concentration resulting from ion implantation is relatively constant up to the ion implantation depth. Controlling the flat doping distribution of ion implantation and the characteristics (e.g., thickness) of the source region implantation mask 36 allows for the desired depth distribution of source region 18. To achieve the desired doping distribution of source region 18, a 1×10⁻⁶ doping depth can be used.13 Up to 5×10 15 cm -2 The implantation dose and implantation energy are between 10 keV and 1.5 MeV. In various embodiments, the dopant used to form source region 18 can be nitrogen, phosphorus, or arsenic.

[0054] While the above examples have been discussed in the context of MOSFET devices, the principles of this disclosure are not limited thereto. The above features can be applied to any type of semiconductor device, such as any type of transistor device, any type of diode, etc. Furthermore, those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the appended claims.

Claims

1. A semiconductor device, comprising: Substrate, the substrate having a first conductivity type; The drift layer on the substrate, the drift layer having the first conductivity type; The well region in the drift layer, wherein: The well region has a second conductivity type opposite to the first conductivity type; and The trap region is provided with a channel region; and The source region in the well region, wherein: The well region is located between the source region and the drift layer; The source region has the first conductivity type; The well region includes a first region on the surface of the well region opposite the substrate, and the first region is laterally separated from the source region by a second region of the well region, the second region having a lower doping concentration than the first region; and The doping concentration of the first region is highest towards the interface between the well region and the drift layer, and the interface is the interface between the side of the first region and the drift layer.

2. The semiconductor device according to claim 1, wherein, The doping concentration of the first region increases proportionally to the distance between the interface between the source region and the well region, such that the increase in doping concentration is directed towards the interface between the well region and the drift layer. The width of the first region is between 0.05µm and 0.5µm.

3. The semiconductor device according to claim 1, wherein, The doping concentration of the first region is 1.1 to 250 times greater than that of the second region, and The lowest part of each of the first and second regions is flush with the lowest part of the trap region.

4. The semiconductor device according to claim 3, wherein, The doping concentration in the first region is 2×10 17 Up to 5×10 19 cm -3 between.

5. The semiconductor device according to claim 4, wherein, The doping concentration in the second region is 5 × 10⁻⁶. 15 Up to 5×10 17 cm -3 between.

6. The semiconductor device according to claim 1, wherein, The width of the second region is between 0.2 and 2 μm.

7. The semiconductor device according to claim 1, wherein, The doping concentration of the first region varies linearly between the interface between the first region and the second region and between the well region and the drift layer.

8. The semiconductor device according to claim 1, wherein, The doping concentration of the first region varies in a stepwise manner between the interface between the first region and the second region and between the well region and the drift layer.

9. The semiconductor device according to claim 1, wherein, The doping concentration of the first region varies exponentially between the interface between the first region and the second region and between the well region and the drift layer.

10. The semiconductor device according to claim 1, wherein, The semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET).

11. The semiconductor device of claim 10, further comprising: The drain contact on the surface of the substrate opposite to the drift layer; The source contact on the surface of the drift layer opposite to the substrate is such that the source contact contacts the source region and the well region. A gate oxide layer on the surface of the drift layer opposite to the substrate, such that the gate oxide layer contacts the well region and the source region and is separated from the source junction, wherein the channel region of the MOSFET is below the gate oxide layer in the well region; and The gate contact on the gate oxide layer.

12. The semiconductor device according to claim 1, wherein, The depth of the source region is non-uniform.

13. The semiconductor device according to claim 12, wherein, The depth of the source region increases proportionally to the distance from the channel region.

14. The semiconductor device according to claim 1, wherein, The channel region includes the first region of the well region, and the second region of the well region has a constant doping concentration that is lower than that of the first region.

15. The semiconductor device according to claim 1, wherein, The depth of the source region at the first edge closest to the channel region is between 6% and 93% of the depth of the source region at the second edge opposite to the first edge.

16. The semiconductor device according to claim 12, wherein, The depth of the source region varies linearly.

17. The semiconductor device according to claim 12, wherein, The depth of the source region varies in a stepped manner.

18. A method for manufacturing a semiconductor device, comprising: A substrate having a first conductivity type is provided; A drift layer is disposed on the substrate, the drift layer having the first conductivity type; A well region is provided in the drift layer such that: The well region has a second conductivity type opposite to the first conductivity type; and The trap region is provided with a channel region; and A source region is provided in the well region such that: The well region is located between the source region and the drift layer; The source region has the first conductivity type; The well region includes a first region on the surface of the well region opposite the substrate, and the first region is laterally separated from the source region by a second region of the well region, the second region having a lower doping concentration than the first region; and The doping concentration of the first region is highest towards the interface between the well region and the drift layer, and the interface is the interface between the side of the first region and the drift layer.

19. The method according to claim 18, wherein, The well region is configured such that the doping concentration of the first region is 1.1 to 250 times greater than the doping concentration of the second region, and The width of the first region is between 0.05µm and 0.5µm.

20. The method according to claim 18, wherein, The doping concentration in the first region is 2×10 17 Up to 5×10 19 cm -3 between.

21. The method according to claim 20, wherein, The doping concentration in the second region is 5 × 10⁻⁶. 15 Up to 5×10 17 cm -3 between.

22. The method according to claim 18, wherein, The width of the second region is between 0.2 μm and 2 μm.

23. The method of claim 18, wherein: Setting the well region includes: setting a well implantation mask on the drift layer and performing an ion implantation process; and Setting the source region includes: setting a source implantation mask on the drift layer that is different from the trap implantation mask and performing an ion implantation process.

24. The method according to claim 18, wherein, Setting the drift layer includes growing the drift layer via an epitaxial process.

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