Line fault feature analysis

Abstract

The present disclosure relates to line fault feature analysis. In described examples, a time domain analyzer (160) is arranged to generate an indication of a number of high frequency events (PULSE TRAIN DATA) of an electrical monitoring signal including a fundamental cycle frequency. The high frequency events include frequencies higher than the fundamental cycle frequency. A frequency domain analyzer (140) is arranged to generate frequency band information (FIR DATA) in response to frequencies of the electrical monitoring signal higher than the fundamental cycle frequency. A fault detector (174) is arranged to monitor the indication of the number of high frequency events (PULSE TRAIN DATA) and the generated frequency band information (FIR DATA), and generate a fault flag (FAULT FLAG) in response to the monitored indication of the number of high frequency events and the generated frequency band information.

Description

[0001] Information related to divisional application

[0002] This disclosure is a divisional application of the original Chinese invention patent application entitled "Line Fault Characteristic Analysis". The original application number is 201780068953.3; the original application date is December 18, 2017. Technical Field

[0003] This disclosure generally relates to power supply lines and systems, and more specifically, to the analysis of line fault characteristics. Background Technology

[0004] For example, electrical conductors in wiring and / or cables carry electrical energy and are configured to power circuits and systems. Faults in the conductor arrangement (e.g., improper contact, breaks or gaps in conductor elements, and short circuits) can cause interruptions in the power carried by the conductors. Such interruptions may include faults (e.g., transient faults and arcing faults) that can interrupt and / or disrupt the proper operation of the powered circuits and systems. Both arcing and transient faults contain high-frequency content superimposed on the fundamental periodic waveform of the original power signal. However, determining the frequency content of a power signal using frequency domain analysis may reveal that it is both power- and time-intensive. Summary of the Invention

[0005] In the described example, a time-domain analyzer is arranged to generate an indication of the number of high-frequency events comprising an electrical monitoring signal with a fundamental period frequency. The high-frequency events include frequencies higher than the fundamental period frequency. A frequency-domain analyzer is arranged to generate frequency band information in response to frequencies of the electrical monitoring signal higher than the fundamental period frequency. A fault detector is arranged to monitor the indication of the number of high-frequency events and the generated frequency band information, and generates a fault flag in response to the monitored indication of the number of high-frequency events and the generated frequency band information. Attached Figure Description

[0006] Figure 1 This is a block diagram of an example line fault feature analyzer.

[0007] Figure 2 This is a data flow diagram for the instance frequency domain and time domain processing of data derived from the electrical monitoring signals of the instance line fault feature analyzer.

[0008] Figure 3 This is a frequency response plot of the example bandpass filter parameters of the example frequency domain analyzer.

[0009] Figure 4 This is a flowchart illustrating the operation of the instance overlay memory to demonstrate the digital sampling waveform information of the instance line fault feature analyzer.

[0010] Figure 5This is a waveform diagram of the frequency domain processing of the analog-to-digital converter data of the example line fault characteristic analyzer.

[0011] Figure 6 A waveform diagram of instance fault signal information detected during a waveform segment of the period of the instance's basic periodic waveform.

[0012] Figure 7 This is a waveform diagram of signal interference caused by an instance fault in a band of an instance period of a basic periodic waveform. Detailed Implementation

[0013] In this description: (a) the term “part” may include the whole part or a part smaller than the whole part; and (b) the term “noise” may include signal interference caused by and / or used to indicate arc discharge or other transient events occurring during a fault condition.

[0014] This document describes effective techniques and circuits for monitoring electrical signals. For example, alternating current (AC) electrical signals (and their conduits) are subjected to conditions that may lead to faults (e.g., arcing and transient faults). Sensors can generate monitoring electrical signals for monitoring the signals. The monitoring electrical signals can be analyzed in the time and / or frequency domains to determine whether the received electrical signals indicate a fault condition. Fault conditions can be indicated by the high-frequency content superimposed on the originally generated signal (e.g., injected onto it or otherwise distorted). The frequency content in the received electrical signal can be determined in response to data captured by an analog-to-digital converter (ADC). The time-domain information of the captured data can be converted into frequency-domain information in response to real-time finite impulse response (FIR) filtering or fast Fourier transform (FFT).

[0015] Time-frequency domain transformation generates frequency analysis data from which specific frequency content in the signal can be detected using a low-power arithmetic processor (e.g., a low-energy accelerator (LEA) and / or a digital signal processor (DSP)). The LEA / DSP can be contained within a heterogeneous multi-core processor, which may also include a general-purpose processor, such as a mixed-signal processor (MSP). The LEA includes low-power modes and can quickly enter sleep mode or quickly "wake up." The MSP may also include similar power-saving features.

[0016] In this example, the fault characterization analyzer includes both a frequency domain analyzer and a time domain analyzer. In the examples described below, the frequency domain analyzer (e.g., which may be included in an LEA operating in low-power mode) typically dissipates less power than a general-purpose time domain analyzer. The frequency domain analyzer evaluates the received electrical signal to determine if a frequency indicative of a fault exists. The frequency domain analyzer can perform this evaluation multiple times during the period of the fundamental frequency waveform of the monitored signal. Therefore, the frequency domain analyzer can pinpoint the occurrence of a fault indication to a specific portion of the fundamental frequency waveform (e.g., a time slice or "band").

[0017] When a fault indication is detected (e.g., by detecting sufficient energy in a selected frequency band during a specific band period), a "wake-up" signal can optionally be asserted, activating the processor of the time-domain analyzer. The processor of the time-domain analyzer (when thus activated) is configured to compare the time-domain event with frequency-domain information and band number to determine whether a fault flag should be asserted. At the end of an activity cycle, the processor of the time-domain analyzer can be instructed to enter a sleep or low-power mode, which conserves power that would otherwise be consumed by a continuously active processor. To conserve even more power, the processor of the frequency-domain analyzer can optionally be activated only during a portion of each band and / or only during specific band periods. Specific bands can be selected to include bands close to (described below) the zero-crossing point of the fundamental frequency waveform of the monitored signal.

[0018] In an example, the time-domain analyzer portion of the frequency-domain analyzer may be implemented by a general-purpose processor (e.g., an MSP) of a multi-core processor. The multi-core processor may include a power-intensive section (e.g., a general-purpose processor) and a power-saving section (e.g., a LEA). As described herein, the power-intensive section of the multi-core processor (which may include a general-purpose processor) may be optionally activated and deactivated (e.g., moved from one power mode to another) in response to a signal generated by the power-saving section (which may include an integrated low-energy accelerator math engine / general-purpose processor and ADC). In an example, the LEA may assert a "wake-up" signal in response to detecting a level exceeding a threshold trigger in the frequency band.

[0019] In operation, waveform information of the received electrical signal is captured (e.g., digitized) by an ADC (which may be integrated into the substrate of a multi-core processor). The captured waveform information is then transmitted (e.g., stored) to (e.g., in) shared memory (e.g., static or dynamic random access memory) located on or outside the multi-core processor (e.g., the multi-core processor substrate). The power-saving portion of the multi-core processor includes circuitry (e.g., a DSP and / or LEA) for performing FIR filtering (or fast Fourier transform) on the sampled groups of the captured waveform information. Each sampled group is associated with a band number, enabling the determination and evaluation of the temporal location of a fault indication on a sub-basic time period basis.

[0020] In response to a "wake-up" signal, the transfer of signal information from memory to the power-intensive portion of the MSP can be performed at relatively high speed by a coprocessor. For example, the signal information includes: captured waveform data (e.g., which may be transferred to the DSP via a data bus); and frequency analysis data (e.g., which may be transferred from the DSP to memory via a data bus). Direct memory access (DMA) techniques can be implemented to access the various memories described herein to reduce data transfer time for processing.

[0021] In the example described herein, the captured waveform data is transmitted to the DSP at a relatively high data rate (e.g., approximately 200,000 samples per second). A frequency domain analyzer performs an FIR operation on the captured waveform data in real time (e.g., on an on-demand basis). The results of the FIR operation (e.g., frequency analysis data, which may contain energy from a specific frequency band or "frequency bin") are stored in memory for further analysis. The stored frequency analysis data can be further analyzed (e.g., via a general-purpose processor) to determine whether the frequency analysis data contains indications of the presence or relative absence of certain frequency components, which may indicate fault conditions.

[0022] In the example described herein, a time-domain analyzer is arranged to determine the higher frequency content of the received electrical signal. This arrangement saves power because the higher frequency content of the received electrical signal can be determined during the period when a portion of the frequency-domain analyzer is deactivated. The determination of the higher frequency content can be performed by incrementing a counter, such that a "wake-up" signal can be asserted in response to the counter's count value. The counter can be implemented using discrete logic circuitry to save power, allowing the counting to be performed when the general-purpose processor is deactivated. The general-purpose processor can be activated in response to the "wake-up" signal, allowing the energy content of at least one selected frequency band of the received electrical signal to be evaluated.

[0023] Figure 1 This is a block diagram of an example line fault feature analyzer. Analyzer 100 typically includes: a waveform sensor 112 (e.g., arranged to generate an electrical monitoring signal to indicate the amplitude of the current carried by the power line 110); and a line fault feature analyzer system 120 (e.g., including components arranged to analyze the electrical monitoring signal to determine potential fault conditions associated with the power line 110).

[0024] The waveform sensor 112 is typically positioned remotely from the system 120. For example, the waveform sensor 112 may be positioned adjacent to the power line 110 such that the sensor of the waveform sensor 112 can generate a waveform in response to a power signal transmitted through the power line 110. The waveform sensor 112 may include either or both of a current transformer (XFMR) 114 and a series shunt resistor 116. The current transformer 114 is arranged to inductively couple power from the power line 110 and generate a time-varying voltage indicating a change in the current in the power line 110. The series shunt resistor 116 is arranged to generate a voltage in response to the current in the power line 110.

[0025] Power line 110 includes a first conductor “line” (L) and a second conductor “neutral” (N). During non-fault conditions, the alternating current flowing through the first conductor L is equal to and opposite in direction to the current flowing through the second conductor N. During fault conditions (e.g., arcing faults and transient faults), the fundamental sinusoidal waveform of the alternating current is distorted by high-frequency energy. High-frequency energy indicates an interruption in the power supplied by power line 110. Such interruptions can be harmful.

[0026] To mitigate potential damage from power interruptions, electrical monitoring signals (e.g., generated by waveform sensor 112 and containing high-frequency information introduced by fault conditions) are coupled to the line fault feature analyzer system 120. In response, a subsystem of the line fault feature analyzer system 120 analyzes the received electrical monitoring signals to determine the presence of high-frequency information indicating fault conditions in the power line 110.

[0027] In this example, the electrical insulation of power line 110 may be damaged, causing a voltage arc or other transient fault that interrupts the sinusoidal waveform presented at the power line frequency (e.g., 60 or 50 Hz) of the power line signal. The voltage arc or other transient fault introduces high-frequency content into the line power supply. Waveform sensor 112 generates an electrical monitoring signal that includes high-frequency information indicating the introduced high-frequency energy. A subsystem of line fault characterization system 120 can detect the included high-frequency information in response to the presence of high-frequency information indicating a fault condition in power line 110 and can assert a fault flag (e.g., to indicate that tripping mechanism 118 should "trip" to disconnect the electrical connection).

[0028] Power line 110 can provide power to power line fault characterization analyzer system 120. For example, power converter 122 of line fault characterization analyzer system 120 is coupled to receive power from the “N” conductor of power line 110 and generates a 5-volt output in response. The 5-volt output is coupled to the input of low-loss voltage regulator (LDO VREG) 124, which is arranged to generate a 3.3-volt output (e.g., VCC, suitable for powering low-voltage circuits). A second low-loss voltage regulator may be included such that the first low-loss voltage regulator can be coupled to generate an analog VCC (AVCC), and the second low-loss voltage regulator can be coupled to generate a digital VCC (DVCC). Analog ground (AVSS) and digital ground (DVSS) may be coupled to the “L” conductor of power line 110 such that current received from the “N” conductor of power line 110 returns to the “L” conductor of power line 110.

[0029] As described above, the waveform sensor 112 may include either or both of a current transformer (XFMR) 114 and a series shunt resistor 116. The current transformer 114 (if present) and the series shunt resistor 116 (if present) each include first and second outputs (e.g., the “end” of a differential signal), respectively coupled to the first and second inputs of the level shifter 130. The second input resistor of the level shifter 130 is coupled to a voltage reference 132. The level shifter 130 is arranged to level-shift the electrical monitoring signal such that the oscillating waveform includes a “zero” value intermediate between VCC and ground potential (e.g., a dummy ground, average value, or an intermediate value of 1.6 volts). Therefore, the signal range of the level-shifted electrical monitoring signal is optimized for circuit operation in response to a 3.3-volt operating voltage.

[0030] The level-shifted electrical monitoring signal is coupled to the input of frequency domain analyzer 140 and to the input of time domain analyzer 160. Typically, frequency domain analyzer 140 is arranged to evaluate the lower frequency information of the level-shifted electrical monitoring signal, while time domain analyzer 160 is arranged to evaluate the higher frequency information of the level-shifted electrical monitoring signal.

[0031] The frequency domain analyzer 140 includes: a low-pass filter (LPF) 142; an analog-to-digital converter (ADC) 144; a digital signal processor (DSP) 146, which includes a tightly coupled memory 148 accessible by the ADC 144 and external processors and devices; and a band determiner 150.

[0032] A low-pass filter 142 is arranged to low-pass filter the level-shifted electrical monitoring signal and generate a low-frequency electrical monitoring signal. This low-frequency electrical monitoring signal is coupled to the input of the ADC 144 for digitization. Furthermore, low-pass filtering of the level-shifted electrical monitoring signal performs anti-aliasing on the input signal digitized by the ADC 144, ensuring that the Nyquist sampling theorem is not violated.

[0033] ADC 144 is configured to digitize low-frequency electronic monitoring signals. In this example, ADC 144 generates 12-bit samples at a sampling rate of 200,000 samples per second. ADC 144 is configured to stream (parallel or serial) the output samples for storage in memory 148 of DSP 146. Thus, the output sample stream of ADC 144 is a low-frequency electronic monitoring (e.g., digital) signal. The output samples can be streamed in real time, allowing DSP 146 to extract and process low-frequency information with reduced latency (e.g., enabling fault detection within a smaller half-cycle of the line frequency).

[0034] Band determiner 150 is coupled to receive low-frequency electrical monitoring (e.g., analog) signals. As described herein, arcing and transient faults often occur during time periods associated with the zero-crossing of a sinusoidal waveform of line power. Band determiner 150 evaluates the low-frequency electrical monitoring signal to determine the transient phase angle of a periodic waveform at the fundamental frequency (e.g., line frequency). For example, the transient phase angle of the periodic waveform at the fundamental frequency can be determined in response to the determination of the zero-crossing and the output of a timer (e.g., clock counter), such that the number of high-frequency events and the frequency band information generated by DSP 146 are correlated with time periods (e.g., associated with at least one band). Thus, the waveform segment can be a time period less than half a cycle of the fundamental periodic frequency, and timing alignment can be performed near the zero-crossing of the electrical monitoring signal.

[0035] If the fundamental frequency periodic waveform of the low-frequency electrical monitoring signal is a sinusoidal waveform divided into eight segments, then zero-crossings occur near the first, fourth, fifth, and eighth segments of the fundamental frequency periodic waveform. If an odd number of bands are used to divide the periodic waveform, then zero-crossings may occur during the bands. Bands adjacent to or containing zero-crossings can be described as "close to" zero-crossings. (At least regarding...) Figure 2 , Figure 6 and Figure 7 Describe the segmentation.

[0036] To save power, DSP 146 can be activated or deactivated in response to sampling from bands adjacent to or containing zero-crossing points, and possibly in response to high-frequency information extracted from the level-shifted electrical monitoring signal by time-domain analyzer 160. For example, the DSP can be activated for a time period (e.g., less than the band period) for each band, sufficient to extract frequency information from the ADC samples. In another instance, the DSP can be activated only during bands close to zero-crossing points.

[0037] The time-domain analyzer 160 includes a high-pass filter (HPF) 162, a comparator (COMP) 164 or 166, and an event counter 168. In this example, the time-domain analyzer 160 evaluates the high-frequency information of the level-shifted electrical monitoring signal by counting high-frequency events that occur in the level-shifted electrical monitoring symbol during a given band.

[0038] A high-pass filter 162 is arranged to high-pass filter the level-shifted electrical monitoring signal and generate a high-frequency content electrical monitoring signal. The high-frequency content electrical monitoring signal is coupled to the input of a computer (e.g., comparator 164 or comparator 166). In one example, comparator 166 is on the same substrate as the multi-core processor 126 and may be coupled to process the high-frequency content electrical monitoring signal when comparator 166 contains sufficient operating characteristics (e.g., at design time or configuration time). In another example, an "external" (e.g., outside the substrate of the multi-core processor 126) comparator 164 may be coupled to process the high-frequency content electrical monitoring signal.

[0039] Comparator 166 (or comparator 164) is arranged to compare a high-frequency electrical monitoring signal with a voltage reference (e.g., threshold 165). The voltage reference may be a digitally controlled analog voltage, allowing a programmable threshold to be specified to determine the presence of an event. For example, high-frequency information may be indicated (e.g.) as voltage spikes or transients (e.g.,...). Figure 6 The input signal 601 is shown. When the high-frequency content electrical monitoring signal exceeds the programmable threshold, comparator 166 (or comparator 164) switches the comparator output to high, and when the high-frequency content electrical monitoring signal is below the programmable threshold, comparator 166 (or comparator 164) switches to low.

[0040] Event counter 168 is arranged to count pulses generated by comparator 166 (and / or comparator 164). For example, event counter 168 may be reset in response to determination that the phase angle of the electrical monitoring signal is close to the band boundary (e.g., by band determiner 150 or DSP 146). Thus, events occurring within the band can be counted. In an embodiment, DSP 146 may be activated in response to the number of counted events exceeding an event threshold. In an embodiment, DSP 146 may be activated in response to the number of counted events exceeding the event threshold during a band period close to the zero-crossing point of the electrical monitoring signal. In an example, event counter 168 may maintain a required log of each event occurrence, allowing for highly specific determination of the time within a band period. Event counter may be arranged to provide an indication of the number of high-frequency events as a terminal count or a value indicating the energy level of high-frequency content exceeding threshold 165 during a band period.

[0041] Therefore, a portion of the time-domain analyzer 160 (e.g., low-power hardware discrete logic circuitry) can save power by activating the DSP only during bands where events (e.g., high-frequency) occur and / or only during bands near zero crossings (where arcing faults are more likely to occur). If activated in this way, the DSP 146 can extract frequency information (e.g., an indication by the number of high-frequency events occurring in the selected band) from simple data from the selected band.

[0042] The general-purpose processor 170 includes a memory 172 and executable instructions for implementing the fault detector 174. To save power, the general-purpose processor 170 can be activated during a selected period. For example, the general-purpose processor 170 can be activated in response to the activation of the DSP 146. The general-purpose processor 170 can also be activated at the opportune moment (“just in time”) to process the results of the DSP 146 (e.g., this saves power). Typically, the processor 170 can be activated in response to determining a transition to the next band or a transition to a specific band (e.g., a band near a zero-crossing).

[0043] A general-purpose processor 170 is configured to evaluate the number of high-frequency events associated with a band, the band number (e.g., the ordinal number of a specific band in a fundamental period), and frequency information (e.g., band information) determined by a DSP 146. In response to the determination, the general-purpose processor can generate real-time candidate fault features. These candidate fault features can be compared with parameters of known fault features (e.g., stored in a feature library 178) to determine the probability that the candidate fault feature is indeed a fault. Because the fault probability is determined in response to the band (e.g., indicating in which part of the wave the characteristic event occurs), the likelihood of false alarms (e.g., identifying a non-existent fault) and false negatives (e.g., identifying a non-existent fault when it is actually present) is reduced. Therefore, methods, systems, and apparatus for improving the accuracy of fault determination and saving power are described herein.

[0044] The analyzer 100 can be deployed as a subsystem of a larger system. For example, a general-purpose processor 170 includes an interface through which FIR data (described below), pulse sequence data (described below), and fault flags are used to protect external devices. Furthermore, the FIR data and pulse sequence data can be evaluated by an external system for characterization to determine actions to be taken (e.g., power decoupling) in response to an assertion by a fault flag. A "Spy-Bi-Wire" two-wire test interface 176 is available to simulate Joint Test Action Group (JTAG) commands for setting and reading internal registers of the analyzer 100. Additionally, the memory 172 of the general-purpose processor 170 can be updated (e.g., after deployment) to modify (or load) the feature library 178, allowing the use of new features to reduce false alarms (e.g., ignoring false alarm features caused by recently introduced technologies (e.g., LED-based illumination).

[0045] Figure 2 This is a data flow diagram for instance frequency-domain and time-domain processing of data derived from electrical monitoring signals from an instance line fault feature analyzer. Flowchart 200 includes a segmented representation 202 of a periodic waveform 201. The periodic waveform 201 may represent a sinusoidal voltage or current in the monitored power line (e.g., power line 110 described above). The periodic waveform 201 is typically not ideal and may contain noise and other interference (e.g., high-frequency information caused by line faults). The periodic waveform 201 is divided into eight equal segments, such as S1, S2, S3, S4, S5, S6, S7, and S8. More or fewer segments may be used to divide the periodic waveform 201.

[0046] The periodic waveform 201 includes zero-crossing points. When a band is adjacent to or contains a zero-crossing point, the band is close to the zero-crossing point. For example, bands close to the zero-crossing point include bands S1, S4, S5, and S8. Although other periodic signals can be used, the periodic waveform 201 is presented as a sine wave. In addition, the first band (e.g., S1) does not need to be close to the zero-crossing point.

[0047] An analog-to-digital converter (e.g., ADC 144) is arranged to generate a sample set during each band. The analog-to-digital converter can be arranged to generate samples continuously or on demand, for example, for bands close to zero crossings. Alternating storage banks 1 of memory 210 and storage banks 2 of memory 220 are used to store the sample set derived from the periodic waveform 201. Storage banks and storage locations can be allocated in response to phase angle correlation determination performed by a band determiner (e.g., band determiner 150), and samples can be started, stopped, grouped, and processed using FIR filtering.

[0048] For example, the analog-to-digital converter is arranged to store ADC data for each band: the sample set acquired during band S1 is stored in the first location of memory bank 1 of memory 210 as sample set ADC-T. n-3 (where n = 4, representing band S4, which is close to the zero crossing point); the sample set acquired during band S2 is stored in the first location of storage bank 2 of memory 220 as the sample set ADC-T. n-2 The sample set acquired during band S3 is stored in the second location of memory bank 1 of memory 210 as the sample set ADC-T. n-1 Furthermore, the sample set acquired during band S4 is stored in the second location of memory 220 as the sample set ADC-T. n .

[0049] Frequency domain operations are performed using memories 230 and 240. Memory 230 displays the ordering of data for FIR filtering operations used in continuous band alignment. For example, ADC data from the storage banks of memories 210 and 220 is moved to memory 230 for DSP access to perform FIR filter operations (or FFT operations): the sample set acquired during band S1 is stored in memory 230 during band S2 (as FIR-T). N-3 The sample set acquired during band S2 is stored in memory 230 during band S3 (as FIR-T). N-2 The sample set acquired during band S3 is stored in memory 230 during band S4 (as FIR-T). N-1 Furthermore, the sample set acquired during band S4 will be stored in memory 230 during band S5 (as FIR-T). N ).

[0050] The DSP (e.g., DSP 146) is arranged to selectively perform FIR filtering operations on a selected sample set: the sample set stored during band S2 is processed into an FIR operation FIR-T. N-3 And it is stored in memory 240 during band S3 (as DATA1-T). N-3 Furthermore, the sample set stored during band S3 is processed into an FIR operation, FIR-T. N-2 And it is stored in memory 240 during band S4 (as DATA1-T) N-2 ).

[0051] An FIR filter implemented by a DSP (e.g., by executing instructions stored in memory 148) typically contains at least two taps, and may contain one hundred or more taps. The number of taps can be determined by filter parameters, which can be bandpass filters, as referenced below. Figure 3As described, a bandpass filter effectively converts the time-domain information (of a sample set) into frequency-domain information. By setting the filter parameters according to the bandwidth, the DSP can search for and / or evaluate frequency information in the sampled electrical monitoring signal. For example, the frequency information processed by the DSP may be a sub-Nyquist frequency lower than the frequency transmitted by the high-pass filter 162.

[0052] To perform an instance FIR operation on all samples in the sample set, the number of consecutive samples (the last sample acquired during the previous band: “N-1”) equal to the number of filter taps (e.g., tap length 232) is preset into the sample set of the currently processed band (e.g., “N”). The preset samples are “prepared” using the preset samples by timing a number of clock cycles equal to the number of taps. Therefore, the entire sample set for the band can be processed without information loss. After evaluating the FIR output information (e.g., via a general-purpose processor such as general-purpose processor 170), further storage space is saved by reusing memory locations.

[0053] As described herein, the DSP can be woken up (or otherwise activated) to process frequency domain information stored in memory 230 in response to time domain information (e.g., counts exceeding a threshold during any band, or even before the end count is reached at the end of a band). Therefore, when a fault event is indicated, power can be saved (e.g.) by processing only the frequency domain information stored in memory 240. Furthermore, the DSP can be activated before the start of the next band, which mitigates or eliminates the processing time encountered when activating the DSP.

[0054] The frequency domain information stored in memory 240 is accessed and processed by general-purpose processor 290 (which is, for example, a processor of general-purpose processor 170) to determine whether a fault condition is indicated. In response to fault feature data stored in feature library 178, the frequency domain information stored in memory 240 and the time domain information stored in memory 260 (described below) are determined.

[0055] The time-domain information includes the number of high-frequency events counted by event counter 168 (where the memory of the event counter is memory 250). For example, the high-frequency event PT encountered in band S1. N-3 The pulse counts (e.g., terminal counts) of the pulse sequence are stored in memory 260 as DATA2-PT during band S2. N-3 High-frequency events PT encountered in band S2 N-2 The terminal count of the pulse sequence is stored in memory 260 as DATA2-PT during band S3. N-2 And the high-frequency event PT encountered in band S3 N-1The terminal count of the pulse sequence is stored in memory 260 as DATA2-PT during band S4. N-1 .

[0056] In the exemplary fault determination process used to determine whether a fault condition should be indicated for band S2, general-purpose processor 290 accesses frequency domain information stored in memory 240 during band S4, and accesses time domain information stored in memory 260 during band S4 (or possibly earlier, for example, by reading memory 250). Therefore, the determination regarding whether a fault condition should be indicated can be made using a waiting time of approximately the total duration of three bands, said waiting time being less than half a cycle of the line frequency.

[0057] The fault determination process can be performed synchronously or asynchronously. In a synchronous instance, DATA1-T is transmitted together. N-2 and DATA2-PT N-2 At the same time, FIR data (DATA1) and pulse count data (DATA2) can be transmitted together. In the asynchronous instance, the time domain analyzer can monitor the activity count (e.g., when the general-purpose processor 290 is inactive) and directly activate the DSP and the general-purpose processor 290 (or indirectly activate the general-purpose processor 290 on which the DSP can activate due to the detection of fault energy in the frequency band).

[0058] Figure 3 This is a frequency response plot illustrating the parameters of an example bandpass filter of example frequency domain analyzer 140. For example, a DSP (e.g., DSP 146) can be arranged to implement an FIR filter with a frequency response (e.g., the frequency response of frequency plot 300). Frequency response plot 300 includes a frequency response curve 302. Frequency response curve 302 can be characterized by a roll-off (e.g., shown by the “skirt” of frequency response curve 302, which can be measured in dB / octave) and the width of the passband 330. The width of the passband spans the frequency range between a -3 dB point 310 (at 15 kHz) and a -3 dB point 320 (at 65 kHz). The passband start frequency and width (or width and stop frequency) are software selectable, allowing selected electrical frequencies from benign electrical noise sources to be excluded from the output of FIR operation. Increasing the number of taps in the FIR filter increases the steepness of the roll-off.

[0059] Figure 4 This is a flowchart illustrating the operation of an example overlay memory for digitally sampled waveform information from an example line fault feature analyzer. For example, an analog-to-digital converter (e.g., ADC 144) and a DSP (e.g., DSP 146) may be arranged to share memory (e.g., memory 148) according to processing flow 400. Processing flow 400 begins in operation 410.

[0060] In operation 410, the shared memory is initialized. For example, the shared memory is organized into first and second memory blocks, such as memory blocks 406 and 408 (e.g., block A and block B). Both memory blocks A and B are independently addressable, allowing overlapping and / or simultaneous read and write operations to access both blocks A and B. In this example, the ADC can write to or read from the first memory block independently of the DSP, and the DSP can read from or write to the second memory block independently of the ADC. The address range 402 of block A extends from 0 to 511, while the address range 402 of block B extends from 512 to 1023. In operation 410, data 404 spanning memory range 402 is initialized with a value of zero (0). Processing flow 400 continues to operation 420.

[0061] In operation 420, the ADC is in the first waveform segment (e.g., T). N During the first band, the input waveform is sampled, and the sampled ADC values ​​are stored as data in block A. For example, the ADC continuously samples the low-pass filtered (e.g., low-frequency) electrical monitoring signal during the first band, and the samples are continuously used as data (e.g., ADC-T). N The data is stored in block A. Continuous sampling is aligned with the start and end of the selected band and can be controlled (e.g., aligned) in response to the output from the waveform segment determiner 150. Processing flow 400 continues with operation 430.

[0062] In operation 430, the ADC samples the input waveform during the second band. The second band is the new T... N (For example, the newly obtained sample in block B is called ADC-T) N The previously obtained samples were referred to as ADC-T. N-1 The DSP is arranged to read the ADC-T stored in block A. N-1 Value 432, to perform an FIR operation on block A data, and in the previously stored ADC-T N-1 Write the FIR result to the value.

[0063] To pre-set FIR input data (e.g., for filling filter taps with relevant data), a sequence 434 of stored ADC values ​​sampled during the bands sampled prior to the first band is retrieved by the DSP (e.g., before the previously sampled data is overwritten by new ADC samples acquired during the second band). The DSP is configured to read sequence 434 (e.g., at the start of operation 430), such that the old ADC-T N-1 The sample is read before it is replaced (e.g., near the end of operation 430). Overwriting the data with one or both of the DSP and ADC saves storage space, thereby reducing power dissipation. Processing flow 400 continues in operation 440.

[0064] In operation 440, the ADC samples the input waveform during the third band. The third band is the latest T... N This makes the newly obtained samples in block A called ADC-T. N The previously obtained samples are referred to as ADC-T. N-1 The preceding sample group (which is shown in a simplified form in data location 511 for simplicity) is referred to as ADC-T. N-2 The DSP is arranged to read the ADC-T stored in block B. N-1 and ADC-T N-2 Value 442, to perform FIR operation on block B data (e.g., previously sampled during the second band), and in the previously stored ADC-T N-1 The FIR result is written to the value. To preset the FIR input data (e.g., for filling filter taps with relevant data), the ADC-T stored before the second band is retrieved via the DSP. N-2 The sequence of values ​​(e.g., the initial portion of 442) (e.g., before previously sampled data is overwritten by new ADC samples obtained during the third band).

[0065] In instance processing flow 400, the ADC may be: activated in continuous operation; activated at least the end portion of each band; or activated at least the end portion of the selected band. This activation helps ensure that sequence 434 is available to populate the tap filter before processing the ADC data acquired during the selected band.

[0066] Figure 5 This is a waveform diagram of the frequency domain processing of an example FFT on analog-to-digital converter data from an example line fault characteristic analyzer. In the first example, waveform diagram 500 shows the electrical monitoring signal 510. The electrical monitoring signal 510 is approximately 12 volts between peaks and includes a portion of the fundamental periodic waveform at the line frequency and frequency-dependent noise (e.g., caused by electrical fault conditions) extending across the entire band. The noise (e.g., shown by the offset of the electrical monitoring signal 510 between nodes 512) is approximately 2 volts between peaks.

[0067] A DSP (e.g., DSP 146) can obtain the input sample set, where the number of samples is the number of samples within the period of the band. The FFT output is shown as curve 520, where the frequency-dependent noise is represented as energy 522. The energy of the frequency-dependent noise is converted to the frequency domain, where the energy 522 in the frequency domain is derived from the energy of the noise throughout the sample set.

[0068] In the second example, the electrical monitoring signal 530 is also a 12-volt peak-to-peak value and includes a portion of the basic periodic waveform at the line frequency and a smaller portion 532 extending only across the associated band, which is (e.g., the same) frequency-dependent noise (e.g., caused by an electrical fault condition). The noise is also approximately a 2-volt peak-to-peak value.

[0069] The DSP performs an FFT operation to transform the input sample set into frequency information, where the number of samples is the number of samples within the period of the band. The FFT output is displayed as sample set 540 (scaled up compared to curve 520). The frequency-dependent noise of the electrical monitoring signal 530 is displayed as energy 542.

[0070] The energy of the frequency-dependent noise is converted to the frequency domain, where the energy 522 in the frequency domain is derived from the energy of the noise across the entire sample set. The energy of the frequency-dependent noise of the electrical monitoring signal 530 is substantially less than that of the frequency-dependent noise of the electrical monitoring signal 510 because the frequency-dependent noise of the electrical monitoring signal 530 (e.g., only) spans a portion of the frequency-dependent noise extension of the electrical monitoring signal 530. The smaller energy is converted into a lower amplitude value. Therefore, due to the resulting lower amplitude value, it is more difficult to detect frequency-dependent noise of shorter durations using the FFT transform.

[0071] Figure 6 This is a waveform diagram of the instance fault signal information detected during a waveform segment of the period of the instance's basic periodic waveform. Waveform diagram 600 shows the input signal 601, frequency domain FIR data 602, and time domain pulse count data 603.

[0072] Input data 601 is a sinusoidal waveform 610, and its sample waveform (e.g., input data 601 sampled by an ADC) correlates with frequency domain FIR data 602. (The energy of the sinusoidal waveform of input signal 601 is reduced in frequency domain FIR data 602 because the sinusoidal waveform of input signal 602 has a fundamental frequency much lower than the lower cutoff frequency of the passband filter).

[0073] According to the above text about Figure 2 As described above, the fundamental period of the input signal 601 can be divided into eight segments (e.g., S1 to S8), where each sample set is associated with 256+1 (end-to-end) samples of the low-frequency electrical monitoring signal stored by the ADC. Therefore, 4K+1 samples (e.g., end-to-end) can be stored (as described above regarding...). Figure 2 and Figure 5 The reusable memory space is described above.

[0074] A processor (e.g., general-purpose processor 170) is arranged to evaluate (digital) frequency-domain FIR data 602. The frequency-domain FIR data 602 includes an offset 622. The offset 622 can be detected by comparing each value of the frequency-domain FIR data 602 to the average value of the frequency-domain FIR data 602 (e.g., such that the average value is used as a threshold). Additionally, each offset 622 within a specific band can be correlated with the number of events detected and recorded by a time-domain analyzer (e.g., time-domain analyzer 160).

[0075] The processor can correlate frequency domain information (associated with each offset 622) with time domain information (e.g., based on band counts). The correlation enhancement between the frequency domain information and the time domain information determines the appropriate probability (and within a time period of approximately two or three bands) of the existence of a fault condition. Additionally, the input signal 601, the frequency domain FIR data 602, and the time domain pulse count data 603 are correlated with specific time periods (e.g., associated with corresponding bands), which can be used to identify fault conditions occurring at or near the zero-crossing point of the input signal 601.

[0076] In response to executable instructions stored in memory, the processor can be configured as a fault detector. The fault detector is arranged to monitor the presence of a number of high-frequency events and the generated frequency band information, and generates a flag in response to the monitored indications of multiple high-frequency events and the generated frequency band information.

[0077] Time-domain information can be generated by a time-domain analyzer (e.g., time-domain analyzer 160). This information is generated by high-pass filtering the electrical monitoring signal and calculating the pulses generated when the high-frequency information of the electrical monitoring signal exceeds a threshold. The counted pulses are associated with events, indicating fault conditions.

[0078] For example, input signal 601 indicates event 612 superimposed on sine wave 610. The event occurs in band S. N-4 S N-3 S N and S N+1 (This refers to a band close to the zero-crossing point) during the period. In band S... N-4 Event 612, which occurred during this period, occurred in band S. N-3 During this period, it was detected in the time-domain pulse count data 603 (as terminal count 205) and in band S N-2 It was detected during this period in frequency domain FIR data 602 (as offset 622). In band S... N-3 Event 612, which occurred during this period, occurred in band S. N-2 During this period, it was detected in time-domain pulse count data 603 (as terminal count 18) and in band S N-1 It was detected during this period in frequency domain FIR data 602 (as offset 622). In band S... NEvent 612, which occurred during this period, occurred in band S. N+1 During this period, it was detected in time-domain pulse count data 603 (as terminal count 146) and in band S N+2 It was detected in the frequency domain FIR data 602 during this period (as offset 622).

[0079] In band S N The time-domain pulse count data 603 stored during this period indicates terminal count 8 and indicates benign noise. Terminal count 18 indicates benign noise because terminal count 8 responds to the signal in band S. N-1 This occurs due to noise that occurs during the period (which is not close to the zero-crossing point). Furthermore, terminal count 8 indicates benign noise because terminal count 18 is a relatively low value. Additionally, terminal count 8 indicates benign noise because terminal count 18 is not correlated with the energy shift in the frequency domain FIR data 602. A feature library (e.g., feature library 178) contains corresponding thresholds for determining fault conditions, which are used to distinguish between benign and fault conditions in response to comparisons involving proximity to the zero-crossing point, high-frequency energy detected in the time domain, and energy within a selected frequency band.

[0080] Figure 7 This is a waveform diagram of signal interference caused by an instance fault in a band of an instance period of the fundamental periodic waveform. Waveform diagram 700 includes waveform 710, which shows an instance electrical monitoring signal used to indicate the power transmitted across a power line (e.g., power line 110). As discussed above, arc faults and transient faults often occur during time periods associated with the zero-crossing points of the sinusoidal waveform of line power. Waveform 710 shows the interference caused by such faults during waveform segments S1, S4, S5, and S8.

[0081] Signal 720 is the average (e.g., truck average) signal of waveform 710. Signal 720 typically represents the fundamental sine wave of the basic periodic waveform. Furthermore, interference caused by arcing and transient faults is indicated by discontinuities in the running current or near zero crossings.

[0082] Within the scope of the claims, modifications are possible in the described embodiments, and other embodiments are also possible.

Claims

1. A system comprising: A sensor configured to be coupled to a line, wherein the sensor includes an output group to provide a sensor signal in response to power passing through the line, wherein the power has a base frequency; A low-pass filter, comprising: The input coupled to the output group of the sensor; and The output of a first filtered signal is provided based on the sensor signal; A high-pass filter, comprising: The input coupled to the output group of the sensor; and The output of a second filtered signal is provided based on the sensor signal; A comparator, which includes: The output of the high-pass filter is coupled to receive the first input of the second filtered signal; The threshold input for receiving the threshold signal; and The output of the comparison signal is provided based on the second filtered signal and the threshold signal; and Processor, comprising: An analog-to-digital converter, comprising an input coupled to the output of the low-pass filter, and comprising an output; and An event counter includes an input coupled to the output of the comparator and an output of a signal configured to generate a count representing a plurality of events having a frequency greater than the base frequency and an amplitude greater than a threshold. A digital signal processor, comprising an input coupled to the output of the analog-to-digital converter, and comprising an output; and Processing resources, which include: The first input coupled to the output of the event counter; A second input coupled to the output of the digital signal processor; as well as The output is configured to provide a fault signal based on the output of the event counter and a frequency domain signal provided at the output of the digital signal processor, wherein the frequency domain signal includes a frequency domain finite impulse response associated with the first filtered signal.

2. The system of claim 1, further comprising a level shifter that couples the output group of the sensor to the input of the low-pass filter and to the input of the high-pass filter.

3. The system of claim 1, wherein the digital signal processor is configured to provide the frequency domain signal at the output based on the output of the analog-to-digital converter.

4. The system of claim 3, wherein the processing resource comprises a fault feature library and is configured to: The frequency domain signal and the output of the event counter are compared with the fault feature library; and The fault signal is provided based on the comparison between the frequency domain signal and the output of the event counter and the fault feature library.

5. The system according to claim 1, wherein: The power passing through the line has a zero-crossing point; The system is configured to divide the power passing through the line into groups of time periods, the group of time periods including a first segment, the first segment including the zero crossing point; The digital signal processor includes a wake-up input to receive a wake-up signal; and The digital signal processor is configured to wake up in response to the wake-up signal indicating the first segment containing the zero-crossing point.

6. The system according to claim 5, wherein: The processing resources include a wake-up input to receive the wake-up signal; and The processing resources are configured to be woken up in response to the wake-up signal indicating the first segment containing the zero-crossing point.

7. The system according to claim 5, wherein: The event counter includes a reset input to receive the wake-up signal; and The event counter is configured to be reset in response to the wake-up signal indicating the first segment containing the zero-crossing.

8. The system of claim 1, wherein the sensor comprises at least one of a current transformer or a series shunt resistor.

9. The system according to claim 1, wherein: The comparator is configured to provide the comparison signal in response to one of the events having a frequency greater than the base frequency and an amplitude greater than the threshold.

10. The system of claim 1, wherein the processor includes the comparator.

11. A system comprising: A time-domain analyzer includes an input configured to be coupled to a sensor to receive a sensor signal in response to power passing through the line, wherein: The power passing through the line has a fundamental frequency; and The time-domain analyzer includes an output to provide a count of multiple events in the sensor signal, the multiple events having a frequency greater than the fundamental frequency and an amplitude greater than a threshold; A frequency domain analyzer, which includes: The input is configured to be coupled to the sensor to receive the sensor signal; and Based on the sensor signal, to provide the output of a frequency domain signal; and Processing resources, which include: Feature library; The first input is coupled to the output of the time-domain analyzer to receive the counts of the plurality of events; The output of the frequency domain analyzer is coupled to receive a second input of the frequency domain signal; and A fault signal is output in response to the comparison of the feature library with the counts of the plurality of events and the frequency domain signal, wherein the frequency domain signal includes a frequency domain finite impulse response associated with a first filtered signal from a low-pass filter of the frequency domain analyzer.

12. The system of claim 11, wherein the time-domain analyzer comprises: A high-pass filter, comprising: The input is configured to be coupled to the sensor to receive the sensor signal; and The output of a second filtered signal is provided based on the sensor signal; A comparator, which includes: The output of the high-pass filter is coupled to receive the first input of the second filtered signal; The threshold input for receiving the threshold signal; and The output of the comparison signal is provided based on the second filtered signal and the threshold signal; as well as An event counter, which includes: The input coupled to the output of the comparator; and Provides the output of the counts of the plurality of events.

13. The system of claim 12, wherein the low-pass filter of the frequency domain analyzer comprises: The input is configured to be coupled to the sensor to receive the sensor signal; and The first filtered signal is output based on the sensor signal; The frequency domain analyzer further includes: An analog-to-digital converter comprising: The output of the low-pass filter is coupled to receive the input of the first filtered signal; and Output; and Digital signal processor, comprising: The input coupled to the output of the analog-to-digital converter; and Provides the output of the frequency domain signal.

14. The system of claim 13, further comprising a processor including the analog-to-digital converter, the digital signal processor, the event counter, and the processing resources.

15. The system of claim 14, wherein the processor further comprises the comparator.

16. The system according to claim 13, wherein: The power passing through the line has a zero-crossing point; and The digital signal processor is configured to wake up in response to the zero crossing.

17. The system of claim 16, wherein the event counter is configured to be reset in response to the zero crossing.

18. The system of claim 13, wherein the digital signal processor is configured to wake up in response to the counting of the plurality of events.

19. The system according to claim 11, wherein: The power passing through the line has a zero-crossing point; and The processing resources are configured to be woken up in response to the zero crossing.

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