Apparatus, method and system for generating device signatures based on fine-tuning and redundant information

Abstract

The present disclosure describes an apparatus, method, and system for generating a device signature based on trim and redundancy information, the apparatus having a memory and a processor. The memory is configured to store integrated circuit trim and redundancy information. The processor is configured to extract bits from the integrated circuit trim and redundancy information, perform a hash function on the extracted bits to generate hashed bits, and output the hashed bits in response to statistical properties of the hashed bits satisfying one or more criteria. In some embodiments, the memory storing the integrated circuit trim and redundancy information can be different from other memory used by the apparatus for other operations (e.g., accessing user data and program data that have been written into system memory).

Description

Technical Field

[0001] Embodiments of this disclosure relate to an apparatus, method, and system for generating apparatus signatures based on fine-tuning and redundancy information. Background Technology

[0002] A physically unclonable function (PUF) uses the measurable intrinsic randomness of a physical device to establish a signature for those devices. PUFs can be used in integrated circuit (IC) devices, where repeated measurements of a given IC device with a PUF consistently result in the same (or very similar) PUF response. However, due to variations in manufacturing processes, PUF measurements of another IC device may produce significantly different PUF responses. These distinct PUF responses between IC devices can be used to create unique device signatures (or identifiers). Summary of the Invention

[0003] Embodiments of this disclosure include an apparatus for signing an IC based on tuning and redundancy information generation device signature, having a memory and a processor. The memory is configured to store IC tuning and redundancy information. The processor is configured to extract bits from the IC tuning and redundancy information, perform a hash function operation on the extracted bits to generate hash bits, and output the hash bits in response to the statistical properties of the hash bits satisfying one or more criteria.

[0004] Embodiments of this disclosure include a method for generating a device signature based on fine-tuning and redundancy information. The method stores fine-tuning and redundancy information associated with an integrated circuit; retrieves the fine-tuning and redundancy information to extract bits from it; and performs a hash function operation on the extracted bits to generate hash bits. The method further includes outputting hash bits in response to statistical properties of the hash bits satisfying one or more criteria.

[0005] Embodiments of this disclosure include a system based on a tuning and redundancy information generation device signature having a non-volatile memory device and physically non-cloning function (PUF) circuitry. The non-volatile memory device is configured to store integrated circuit tuning and redundancy information. The PUF circuitry is configured to: retrieve IC tuning and redundancy information from the non-volatile memory device; extract bits from the IC tuning and redundancy information; perform a hash function operation on the extracted bits to generate a hash bit; output the hash bit in response to the statistical properties of the hash bit satisfying one or more criteria; and repeat one or more of the following operations in response to the statistical properties of the hash bit not satisfying one or more criteria: extracting bits from the IC tuning and redundancy information, and performing a hash function operation on the extracted bits to generate a hash bit. Attached Figure Description

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will best convey the various aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of explanation.

[0007] Figure 1 This is an illustration of a memory device having a physically unclonable function (PUF) circuit according to some embodiments of the present disclosure.

[0008] Figure 2 This is an illustration of a method for generating a device signature via a PUF circuit based on IC fine-tuning and redundancy information, according to some embodiments of the present disclosure.

[0009] Figure 3 This is a diagram of a circuit architecture based on a linear feedback shift register (LFSR) that can be used to randomly extract bits from IC fine-tuning and redundancy information according to some embodiments of this disclosure.

[0010] Figure 4 This is an illustration of a first LFSR that can be implemented in an LFSR-based circuit architecture according to some embodiments of the present disclosure.

[0011] Figure 5 This is an illustration of a second LFSR that can be implemented in an LFSR-based circuit architecture according to some embodiments of the present disclosure.

[0012] Figure 6 This is a diagram of a multiplexer-based circuit architecture that can be used to randomly extract bits from IC fine-tuning and redundancy information, according to some embodiments of this disclosure.

[0013] Figure 7 This is an illustration of a first selection module that can be implemented in a multiplexer-based circuit architecture according to some embodiments of the present disclosure.

[0014] Figure 8 This is an illustration of a second selection module that can be implemented in a multiplexer-based circuit architecture according to some embodiments of the present disclosure.

[0015] Figure 9 This is an illustration of a third selection module that can be implemented in a multiplexer-based circuit architecture according to some embodiments of the present disclosure.

[0016] Figure 10 This is an illustration of a fourth selection module that can be implemented in a multiplexer-based circuit architecture according to some embodiments of the present disclosure.

[0017] Figure 11This is a diagram of a hash circuit that can be implemented in a PUF circuit according to some embodiments of the present disclosure.

[0018] Explanation of icon numbers

[0019] 100: Memory device;

[0020] 110: Physically Unclonable Function (PUF) Circuits;

[0021] 120: Line decoder;

[0022] 130: Input / output (I / O) circuit;

[0023] 140: Readout amplifier;

[0024] 150: Column decoder;

[0025] 160: Storage array;

[0026] 170: Non-volatile memory (NVM) module;

[0027] 200: Method;

[0028] 210, 220, 230, 240, 250: Operation;

[0029] 300, 600: Circuit architecture;

[0030] 310: Folding / Expanding Module;

[0031] 320: Counter;

[0032] 325, 430, 530: Clock signals;

[0033] 330, 400, 500, 930, 1030: Linear feedback shift registers;

[0034] 340, 610: Controller;

[0035] 420, 520: Reset signals;

[0036] 620, 700, 800, 900, 1000: Select module;

[0037] 1100: Hash circuit;

[0038] 1110: Register;

[0039] 1120: Hash function operation module;

[0040] 4100, 4101, 4102…, 410 11 410 12 410 13410 14 410 15 5100, 5101…510 15 510 16 510 17 510 18 510 19 …510 29 510 30 510 31 :enter;

[0041] 4400, 4401, 4402…, 440 11 440 12 440 13 440 14 440 15 5400, 5401…540 15 540 16 540 17 540 18 540 19 …540 29 540 30 540 31 7200, 7201, 7202…720 (n-3) 720 (n-2) 720 (n-1) 8200, 8201…820 (M-1) 9200, 9201, 9202…, 920 (n-3) 920 (n-2) 920 (n-1) 10200, 10201…1020 (M-1) Multiplexer;

[0042] 4500, 4501, 4502…, 450 11 450 12 450 13 450 14 450 15 5500, 5501…550 15 550 16 550 17 550 18 550 19 …550 29 550 30 550 31 : Shift register;

[0043] 4600, 4601, 4602, 5600, 5601, 5602: XOR devices;

[0044] 7100…710 (n-1) 8100, 8101…810 (M-1) 9400…940 (n-1) 10400, 10401…1040 (M-1) : Select signal;

[0045] 7300…730 (n-1) 8300…830 (n-1) 9100…910 (n-1) 9500…950 (n-1) 10100…1010 (M-1) 10500…1050 (n-1) Output. Detailed Implementation

[0046] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and, unless otherwise specified, does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0047] The following disclosure describes aspects of an integrated circuit (IC) device having physically unclonable function (PUF) circuitry. For purposes of explanation, the IC device described herein is a memory device such as a static random access memory (SRAM) device, dynamic RAM, resistive RAM, magnetoresistive RAM, and ferroelectric RAM. Certain memory device elements are disclosed to facilitate the description of different embodiments herein. Memory devices may include other circuit elements within the spirit and scope of this disclosure. Furthermore, the embodiments described herein are not limited to memory devices and are applicable to other IC devices (e.g., processors and application-specific integrated circuits (ASICs)). These other IC devices are within the spirit and scope of this disclosure.

[0048] In some embodiments, the PUF circuitry is configured to generate an output (also referred to herein as a “device signature”) based on unique tuning and redundancy information associated with the IC device. According to some embodiments, the IC tuning and redundancy information may be based on one or more of the following: input / output (I / O) circuit repair information, sense amplifier tuning information, physical addresses associated with repair word lines in the memory device, physical addresses associated with repair bit lines in the memory device, analog-to-digital converter tuning information, digital-to-analog tuning information, sensor tuning information, any other IC tuning and redundancy information, or combinations thereof. Based on the IC device’s tuning and redundancy information, a unique device signature (or identifier) ​​for the IC device can be generated. Among other benefits of the embodiments described herein is the lower overhead of the PUF circuitry, because the information used to generate the device signature is based on existing IC tuning and redundancy information unique to the IC device. Furthermore, existing circuit designs already incorporate readout reliability and repeatability of the information, as the information is critical to the correct operation of the IC device.

[0049] Figure 1 This is an illustration of a memory device 100 according to some embodiments of the present disclosure. In some embodiments, the memory device 100 may be an SRAM device, which includes a PUF circuit 110, a row decoder 120, an I / O circuit 130, a sense amplifier 140, a column decoder 150, a memory array 160, and a non-volatile memory (NVM) module 170.

[0050] The memory array 160 includes memory cells arranged in rows and columns, which are accessed using memory addresses—for example, for memory read and write operations. Based on the memory address, the row decoder 120 selects a row of memory cells for access. Furthermore, based on the memory address, the column decoder 150 selects a column of memory cells for access. For memory read operations, the sense amplifier 140 senses the voltage on the selected column (e.g., the select line of an SRAM array). I / O circuitry 130 provides access from the sense amplifier 140 to external circuitry (…). Figure 1 The sensed voltage (not shown in the diagram) is represented digitally. Other memory operations (e.g., memory write operations) can be performed using the row decoder 120, I / O circuitry 130, sense amplifier 140, column decoder 150, and memory array 160. These other memory operations are within the spirit and scope of this disclosure.

[0051] Semiconductor manufacturing processes can have variations that cause memory device 100 to operate differently from its design and / or cause parts of memory device 100 to be defective and inoperable. These semiconductor manufacturing process variations and defects can be detected during IC testing. For example, during IC testing, memory device 100 can receive various electrical test signals to compare the output signals of memory device 100 with expected values ​​and performance indicators. Testing can identify parts of memory device 100 that do not operate optimally and / or defective and inoperable parts of memory device 100.

[0052] In contrast to variations in semiconductor manufacturing processes, variations in layer deposition or curing processes can, in this case, cause certain layers of the memory device 100 to have higher or lower resistance than expected. Therefore, the operating characteristics (e.g., operating voltage and device performance) of the manufactured memory device 100 may differ from the intended design. To address these semiconductor manufacturing process variations, the memory device 100 may incorporate one or more trimmer circuits to adjust the operating characteristics of the memory device 100 after manufacturing.

[0053] In some embodiments, the sense amplifier 140 may include a trimming circuit (also referred to as a "sense amplifier trimming circuit"); Figure 1 (Not shown in the image). The sense amplifier tuning circuitry can be used to adjust the reference current used by the sense amplifier 140 by, for example, activating an additional current source transistor to increase the reference current. Therefore, the output of the sense amplifier 140 can be tuned to a desired operating point. According to some embodiments, the sense amplifier tuning information of the sense amplifier tuning circuitry can be stored as a sense amplifier tuning code in the NVM module 170.

[0054] although Figure 1 Not shown, but the memory device 100 may include other circuitry with fine-tuning circuitry. This other circuitry includes an analog-to-digital (A / D) converter, a digital-to-analog (D / A) converter, and sensors. The A / D converter can be used to convert the analog voltage used by the memory device 100 into a digital format. Conversely, the D / A converter can be used to convert the digital voltage used by the memory device 100 into an analog format. Additionally, the memory device 100 may use sensors to measure, for example, the temperature of the device, to ensure that the memory device 100 operates within a safe thermal range or to adjust temperature-dependent fine-tuning accordingly.

[0055] In some embodiments, the A / D converter, D / A converter, and sensor may include fine-tuning circuitry (also referred to herein as "A / D converter fine-tuning circuitry," "D / A converter fine-tuning circuitry," and "sensor fine-tuning circuitry," respectively). The fine-tuning circuitry can be used to tune the A / D converter, D / A converter, and sensor so that these circuits operate in an accurate manner. For example, the A / D converter and D / A converter may each include a resistor ladder network for generating digital and analog outputs. The A / D converter fine-tuning circuitry and D / A converter fine-tuning circuitry can be used to fine-tune the resistor ladder networks in the A / D converter and D / A converter, respectively, to improve accuracy. Regarding the sensor, the sensor fine-tuning circuitry can be used to compare the sensor's temperature measurement with a reference temperature for sensor calibration. According to some embodiments, the A / D converter fine-tuning information, D / A converter fine-tuning information, and sensor fine-tuning information may be stored as A / D converter fine-tuning codes, D / A converter fine-tuning codes, and sensor fine-tuning codes, respectively, in the NVM module 170.

[0056] The NVM module 170 may include, for example, non-volatile memory cells (e.g., flash memory cells, eFuse, etc.) to store sense amplifier tuning codes, A / D converter tuning codes, D / A converter tuning codes, and sensor tuning codes when the memory device 100 is powered on or off. In some embodiments, the memory device 100 may access the sense amplifier tuning codes, A / D converter tuning codes, D / A converter tuning codes, and / or sensor tuning codes in the NVM module 170 after power-on. In some embodiments, the NVM module 170 may be dedicated to storing tuning code information; for example, the NVM module 170 may be separate from and independent of the memory array 160.

[0057] Besides variations in semiconductor manufacturing processes, portions of the manufactured memory device 100 may be defective and / or inoperable. In some embodiments, the memory device 100 may include redundant circuitry to replace these defective portions without requiring the device to be discarded. For example, I / O circuitry 130 and memory array 160 may each include redundant circuitry. Figure 1(As shown in the diagram) to replace defective I / O circuits and word lines respectively. In some embodiments, when replacement I / O circuits and word lines are activated from redundant circuitry, the address mapping of memory device 100 is updated to be associated with the replacement I / O circuits and word lines. According to some embodiments, information associated with the updated address mapping may be stored in NVM module 170. In some embodiments, memory device 100 may access the updated address mapping information in NVM module 170 after power-on. In some embodiments, NVM module 170 may be dedicated to storing address mapping information and / or the fine-tuning code information described above, for example, NVM module 170 may be separate from and independent of memory array 160.

[0058] In some embodiments, to generate a unique device signature for memory device 100, PUF circuitry 110 may store trimming codes (e.g., sense amplifier trimming codes, A / D converter trimming codes, D / A converter trimming codes, and sensor trimming codes) and address mapping information (e.g., updated address mapping information for I / O circuitry and word lines) – collectively referred to herein as “IC trimming and redundancy information” – in NVM module 170. In some embodiments, IC trimming and redundancy information may be a combination of trimming codes and address mapping information, and may be represented by bits of any length, such as 64 bits, 128 bits, 256 bits, 512 bits, and 1024 bits. Due to the uniqueness of IC trimming and redundancy information, which depends on random physical factors introduced in the semiconductor manufacturing process, the output of PUF circuitry 110 can be highly unpredictable and serve as a unique device signature for memory device 100. This unique device signature may be used for security purposes, such as device authentication, to prove that memory device 100 can execute certain software and applications.

[0059] Figure 2 This is an illustration of a method 200 for generating a device signature via PUF circuit 110 based on IC fine-tuning and redundancy information, according to some embodiments. For illustrative purposes, reference will be made to... Figure 1 The operation of method 200 is described using memory device 100. The operation can be performed by other types of IC devices, such as processors and ASICs. Furthermore, the operations of method 200 can be performed in different orders, or some operations may be omitted depending on the specific application.

[0060] In operation 210, bits are randomly extracted from the IC tuning and redundancy information. In some embodiments, the IC tuning and redundancy information may be stored in the NVM module 170, where the PUF circuit 110 retrieves this information and performs operation 210. In some embodiments, to perform operation 210, the PUF circuit 110 may include one or more circuits having a design based on a linear feedback shift register (LFSR), a multiplexer-based design, or a combination thereof. References below Figures 3 to 5 The design based on LFSR is described below, with references to other sources. Figures 6 to 8 The design based on a multiplexer is described below, and references are provided below. Figure 9 and Figure 10 Describe the design based on a multiplexer / LFSR.

[0061] Figure 3 This is an illustration of an LFSR-based circuit architecture 300, according to some embodiments, which can be used to randomly extract bits from IC tuning and redundancy information. The LFSR-based circuit architecture 300 includes a folding / expansion module 310, a counter 320, an LFSR 330, and a controller 340. For ease of description of the LFSR-based circuit architecture 300, the IC tuning and redundancy information has 'k' bits. As discussed above, the IC tuning and redundancy information can be represented by bits of any length, where the value of 'k' can be 64, 128, 256, 512, 1024, or any other suitable number.

[0062] Folding / expansion module 310 and counter 320 from, for example Figure 1 The NVM module 170 receives IC tuning and redundancy information. In some embodiments, the folding / expansion module 310 converts 'k' bits in the IC tuning and redundancy information into 'n' bits. The value of 'n' may be less than the value of 'k', wherein the folding / expansion module 310 may execute a folding algorithm to implement the 'n' bits. Alternatively, the value of 'n' may be greater than the value of 'k', wherein the folding / expansion module 310 may execute an expansion algorithm to implement the 'n' bits. Folding and expansion algorithms are well known, and these algorithms are within the spirit and scope of this disclosure. The folding / expansion module 310 outputs the 'n' bits to the LFSR 330.

[0063] In some embodiments, counter 320 extracts 'm' bits from 'k' bits of IC tuning and redundancy information. According to some embodiments, the value of 'm' may be less than the value of 'k'. According to some embodiments, the value of 'm' may be a preset number or a number that changes over time. The value associated with the 'm' bits extracted from the IC tuning and redundancy information represents the count value of counter 320. For example, if the value of 'k' is 1024 and the value of 'm' is 512, then counter 320 extracts 512 bits from the 1024 bits of IC tuning and redundancy information. Counter 320 can extract 512 bits from IC tuning and redundancy information using various methods: (i) counter 320 can extract the first 512 bits from 1024 bits of IC tuning and redundancy information; (ii) counter 320 can extract the last 512 bits from 1024 bits of IC tuning and redundancy information; (iii) counter 320 can extract every other bit from 1024 bits of IC tuning and redundancy information, for a total of 512 bits; (iv) counter 320 can randomly extract 512 bits from 1024 bits of IC tuning and redundancy information; or (v) any other suitable extraction method. The numerical value corresponding to the extracted 512 bits is the count value of counter 320. According to some embodiments, controller 340 controls the bit extraction operation performed by counter 320.

[0064] According to some embodiments, the LFSR 330 receives 'n' bits as an initial or seed value from the folding / expansion module 310 and a clock signal 325 from the counter 320. After loading the 'n' bits into the LFSR 330, the LFSR 330 can be cyclically operated using the clock signal 325 based on the count value stored in the counter 320. For example, if the count value stored in the counter 320 is '64', then the 'n' bits loaded in the LFSR 330 are cyclically 64 times based on the clock signal 325. The LFSR 330 outputs the cyclically cyclically 'n' bits, which represent bits randomly extracted from the IC fine-tuning and redundancy information of operation 210. According to some embodiments, the controller 340 controls the cyclic operation performed by the LFSR 330. Figure 4 and Figure 5 This is a diagram of an example LFSR that can be implemented in an LFSR-based circuit architecture 300.

[0065] According to some embodiments, Figure 4 This is a diagram of a 16-bit LFSR 400 that can be implemented in an LFSR-based circuit architecture 300. The LFSR 400 includes inputs 4100 to 410. 15 Reset signal 420, clock signal 430, multiplexer 4400 to multiplexer 440 15 Shift register 4500 to shift register 450 15And XOR devices 4600 to 4602. In some embodiments, shift registers 4500 to 450... 15 Each of these can be a D flip-flop. Before loading LFSR 400 with an initial or seed value, the reset signal 420 can be used to move shift register 4500 to shift register 450. 15 Initialize (e.g., to a logic low value, such as 0 volts).

[0066] LFSR 400 can be accessed by entering 4100 to 410. 15 Receive 16 bits (e.g., 'n' bits from folding / expanding module 310) as an initial or seed value, and load the 16 bits into multiplexers 4400 to 4400 respectively. 15 The output of XOR device 4600 serves as the selection signal for multiplexer 4400. In some embodiments, if the output of XOR device 4600 is '1' (e.g., a logic high value, such as the power supply voltage of memory device 100, which may be, for example, 1.5 volts, 3.0 volts, or 5.0 volts), then the bit information on input 4100 (e.g., a logic high value or a logic low value) is passed to shift register 4500. Conversely, when shift register 4500 is cyclically operated based on clock signal 430, the bit information on input 4100 is passed to the output of shift register 4500. The output of shift register 4500 is received by multiplexer 4401 and serves as the selection signal for multiplexer (e.g., similar to the selection signal for multiplexer 4400). XOR device 4600 also receives the output of shift register 4500 as an input.

[0067] If the output of XOR device 4600 is '0' (e.g., a logic low value, such as 0 volts), then the bit information on input 4100 (e.g., a logic high or logic low value) is not passed to shift register 4500. Conversely, when shift register 4500 is cyclically operated based on clock signal 430, the initialization value in shift register 4500 is passed to the output of shift register 4500. Similarly, the output of shift register 4500 is received by multiplexer 4401 and functions as a select signal for the multiplexer (e.g., similar to the select signal for multiplexer 4400). XOR device 4600 also receives the output of shift register 4500 as an input.

[0068] Based on multiplexer 4400 to multiplexer 440 15 Shift register 4500 to shift register 450 15 And the inputs and outputs of XOR devices 4600 to 4602, and multiplexers 4401 to 4402. 15Shift registers 4501 to 450 15 XOR devices 4601 and 4602 operate in a similar manner to multiplexer 4400, shift register 4500, and XOR device 4600 described above. After each cycle, the last multiplexer in the multiplexer chain (e.g., multiplexer 450)... 15 Output bits (e.g., logic high or logic low values). This is done in the LFSR 400 with the values ​​stored... Figure 3 After the count value in counter 320 is associated with the number of cycles, LFSR 400 will output its cycle bit (e.g., the 'n' bit of the cycle), which represents a bit randomly extracted from the IC fine-tuning and redundancy information of operation 210.

[0069] Figure 5 This is an illustration of a 32-bit LFSR 500 implementable in an LFSR-based circuit architecture 300 according to some embodiments. The LFSR 500 includes inputs 5100 to 510. 31 520 reset signal, 530 clock signal, 5400 multiplexer to 540 multiplexer 31 Shift register 5500 to shift register 550 31 And XOR devices 5600 to XOR devices 5602. In some embodiments, shift registers 5500 to shift register 550 31 Each of these can be a D flip-flop. Before loading LFSR 500 with an initial or seed value, the reset signal 520 can be used to move shift register 5500 to shift register 550. 31 Initialize (e.g., to a logic low value, such as 0 volts).

[0070] Multiplexer 5400 to Multiplexer 540 31 Shift register 5500 to shift register 550 31 And each of the XOR devices 5600 to XOR devices 5602 is respectively coupled with the XOR device as described above. Figure 4 The described multiplexer 440, shift register 450, and XOR device 460 operate in a similar manner. For example, the LFSR 500 can be accessed via inputs 5100 to 510. 31 Receive 32 bits (e.g., 'n' bits from folding / expanding module 310) as an initial or seed value, and load the 32 bits into multiplexers 5400 to 540 respectively. 31 In China. Based on multiplexer 5400 to multiplexer 540 31 Shift register 5500 to shift register 550 31And the inputs and outputs of XOR devices 5600 to XOR devices 5602, and the data stored in the LFSR 500 are processed. Figure 3 After the counter value in counter 320 is associated with the number of cycles, LFSR 500 will output the cycle bit (e.g., the 'n' bit of the cycle), which represents a bit randomly extracted from the IC fine-tuning and redundancy information of operation 210.

[0071] Based on the description in this article, although Figure 4 and Figure 5 The diagrams illustrate 16-bit and 32-bit LFSR designs, but the number of bits used in the LFSR design is not limited to these values ​​and can have higher or lower LFSR bit designs, such as 4-bit LFSR designs, 64-bit LFSR designs, 128-bit LFSR designs, and 256-bit LFSR designs.

[0072] Figure 6 This is an illustration of a multiplexer-based circuit architecture 600, according to some embodiments, for randomly extracting bits from IC tuning and redundancy information. The multiplexer-based circuit architecture 600 includes a controller 610 and a selection module 620. For ease of description of the multiplexer-based circuit architecture 600, the IC tuning and redundancy information has 'k' bits. As discussed above, the IC tuning and redundancy information can be represented by bits of any length, where the value of 'k' can be 64, 128, 256, 512, 1024, or any other suitable number.

[0073] Controller 610 and selection module 620 from, for example Figure 1 The NVM module 170 receives IC tuning and redundancy information. Depending on the design of the multiplexer-based circuit architecture 600, the controller 610 can process a certain number of bits from the IC tuning and redundancy information and pass these bits to the selection module 620 for further processing. Figures 7 to 10 This is a diagram of an instance selection module that can be implemented in a multiplexer-based circuit architecture 600.

[0074] Figure 7 It is practicable according to some embodiments Figure 6 This diagram illustrates the selection module 700 in a multiplexer-based circuit architecture 600. The selection module 700 includes multiplexers 7200 to 720... (n-1) The number of multiplexers 'n' is related to Figure 6 The controller 610 outputs n bits with the same value. In some embodiments, multiplexer 7200 to multiplexer 720 (n-1) Each of the 'k' bits in the IC trimming and redundancy information subset receives 2 bits.

[0075] In some embodiments, controller 610 extracts 'n' bits from the 'k' bits of IC tuning and redundancy information. The value of 'n' may be less than the value of 'k', for example, half, one-third, and one-quarter of 'k' (e.g., 'k / 2', 'k / 3', and 'k / 4', respectively). For example, if the value of 'k' is 1024 and the value of 'n' is 341 (e.g., approximately 'k / 3'), then controller 610 extracts 341 bits from the 1024 bits of IC tuning and redundancy information. The controller 610 can extract 341 bits from the IC tuning and redundancy information using various methods: (i) the controller 610 can extract the first 341 bits from the 1024 bits of the IC tuning and redundancy information; (ii) the controller 610 can extract the last 341 bits from the 1024 bits of the IC tuning and redundancy information; (iii) the controller 610 can extract every two bits from the 1024 bits of the IC tuning and redundancy information, for a total of 341 bits; (iv) the controller 610 can randomly extract 341 bits from the 1024 bits of the IC tuning and redundancy information; or (v) any other suitable extraction method. The 'n' bits output by the controller 610 can be used as... Figure 7 Multiplexer 7200 to Multiplexer 720 (n-1) The selection signal. In some embodiments, the value of 'n' may be a preset number based on the design of the selection module 700.

[0076] According to some embodiments, the number of subsets of the 'k' bits of IC tuning and redundancy information can be twice the number of 'n' bits output by the controller 610. In some embodiments, the subset of the 'k' bits of IC tuning and redundancy information can be (i) randomly selected from the 'k' bits of IC tuning and redundancy information, (ii) the first [2·'n'] bits of the 'k' bits of IC tuning and redundancy information, (iii) the last [2·'n'] bits of the 'k' bits of IC tuning and redundancy information, or (iv) selected in any suitable manner. For example, if the value of 'k' is 1024 and the value of 'n' is 341, then the number of subsets of the 'k' bits of IC tuning and redundancy information can be 682. In this example, the 682 bits from the IC tuning and redundancy information can be (i) randomly selected from the 1024 bits of the IC tuning and redundancy information, (ii) the first 682 bits of the 1024 bits of the IC tuning and redundancy information, (iii) the last 682 bits of the 1024 bits of the IC tuning and redundancy information, or (iv) selected in any suitable manner.

[0077] In some embodiments, multiplexer 7200 to multiplexer 720 (n-1)Each of the multiplexers can receive a bit value associated with an even bit index (e.g., a logic high or low value at bit indices 0, 2, 4, 6, 8…682) from a subset of the 'k' bits of the IC tuning and redundancy information, and multiplexers 7200 to 720… (n-1) The second input of each of these components may receive a bit value associated with an odd-numbered bit index (e.g., a logic high or low value at bit indices 1, 3, 5, 7, 9…681) from a subset of the 'k' bits of the IC tuning and redundancy information. Based on the description herein, the subset of the 'k' bits of the IC tuning and redundancy information may be mapped to multiplexer 7200 to multiplexer 720 in any suitable manner. (n-1) The first and second inputs.

[0078] Additionally, in some embodiments, each of the 'n' bits output by controller 610 is compared with selection signals 7100 to 710... (n-1) Each corresponds to one of them. Based on selection signals 7100 to 710. (n-1) The value (e.g., logic high or logic low), multiplexer 7200 to multiplexer 720 (n-1) Output its first or second input as outputs 7300 to 730 respectively. (n-1) In some embodiments, outputs 7300 to 730 are... (n-1) This represents a bit randomly extracted from the IC fine-tuning and redundancy information of operation 210.

[0079] Figure 8 It is practicable according to some embodiments Figure 6 The diagram illustrates another selection module 800 in the multiplexer-based circuit architecture 600. In some embodiments, the number of 'k' bits of IC tuning and redundancy information can be much greater than twice the number of 'n' bits output by the controller 610 (e.g., 'k' >> [2·'n'], such as 3 times, 4 times, 5 times, or other magnitudes greater than twice the number of 'n' bits). In this case, the multiplexer architecture illustrated in selection module 800 can be used.

[0080] In some embodiments, the selection module 800 includes multiplexers 8200 to 820. (M-1)Here, 'M' represents the number of multiplexer rows and depends on the number of 'k' bits of the IC tuning and redundancy information and the number of 'n' bits of the controller 610 output. For example, the value of 'n' can be 64, and the value of 'k' can be 1024. Here, the value of 'M' can be 4, for example, 4 rows of multiplexers. In this example, the first row of multiplexers can have 512 multiplexers, where the first input of each multiplexer can receive a bit value associated with an even bit index (e.g., a logic high or low value at bit indices 0, 2, 4, 6, 8…1024) from the 'k' bits of the IC tuning and redundancy information, and the second input of each multiplexer can receive a bit value associated with an odd bit index (e.g., a logic high or low value at bit indices 1, 3, 5, 7, 9…1023) from the 'k' bits of the IC tuning and redundancy information. Based on the description herein, the 'k' bits of IC tuning and redundancy information can be mapped to the first and second inputs of the multiplexer in any suitable manner. The second row of the multiplexer can have 256 multiplexers, each receiving an output as input from the multiplexers in the first row. The third row of the multiplexer can have 128 multiplexers, each receiving an output as input from the multiplexers in the second row (e.g., similar to the multiplexer inputs in the second row). The fourth row of the multiplexer can have 64 multiplexers, each receiving an output as input from the multiplexers in the third row (e.g., similar to the multiplexer inputs in the third row).

[0081] refer to Figure 8 Multiplexer 8200 to Multiplexer 820 (M-1) The multiplexers in each row can be used separately from... Figure 6 The controller 610 receives the selection signal 8100 to the selection signal 810 (M-1) According to some embodiments, selection signals 8100 to 810 (M-1)The value can be mapped to a value (e.g., logic high and logic low values) associated with 'M' bits from the 'k' bits of IC tuning and redundancy information. In some embodiments, the 'M' bits can be (i) randomly selected from the 'k' bits of IC tuning and redundancy information, (ii) the first 'M' bits from the 'k' bits of IC tuning and redundancy information, (iii) the last 'M' bits from the 'k' bits of IC tuning and redundancy information, or (iv) selected in any suitable manner. Using the above example, where the value of 'M' is 4 and the value of 'k' is 1024, the 4 bits of selection signals 8100 to 8103 can be (i) randomly selected from 1024 bits of IC tuning and redundancy information, (ii) the first 4 bits of 1024 bits of IC tuning and redundancy information, (iii) the last 4 bits of 1024 bits of IC tuning and redundancy information, or (iv) selected in any suitable manner. Based on selection signals 8100 to 810 (M-1) The value (e.g., logic high or logic low), multiplexer 8200 to multiplexer 820 (M-1) Each row of the multiplexer outputs either its first or second input. Multiplexer 820 (m-1) The multiplexer output bit in the row is 'n', and in Figure 8 The output is represented as 8300 to 830. (n-1) The multiplexer output represents bits randomly extracted from the IC fine-tuning and redundancy information of operation 210.

[0082] Figure 9 It is practicable according to some embodiments Figure 6 The illustration shows another selection module 900 in the multiplexer-based circuit architecture. Selection module 900 includes multiplexers 9200 to 920... (n-1) And the LFSR 930. The number of multiplexers 'n' and Figure 6 The bit 'n' output by controller 610 has the same value. In some embodiments, multiplexer 9200 to multiplexer 920 (n-1) Each of the 'k' bits in the IC trimming and redundancy information subset receives 2 bits.

[0083] According to some embodiments, the number of subsets of the 'k' bits of IC tuning and redundancy information can be twice the number of 'n' bits output by the controller 610. In some embodiments, the subset of the 'k' bits of IC tuning and redundancy information can be: (i) randomly selected from the 'k' bits of IC tuning and redundancy information, (ii) the first [2·'n'] bits of the 'k' bits of IC tuning and redundancy information, (iii) the last [2·'n'] bits of the 'k' bits of IC tuning and redundancy information, or (iv) selected in any suitable manner. For example, if the value of 'k' is 1024 and the value of 'n' is 341, then the number of subsets of the 'k' bits of IC tuning and redundancy information can be 682. In this example, the 682 bits from the IC tuning and redundancy information can be (i) randomly selected from the 1024 bits of the IC tuning and redundancy information, (ii) the first 682 bits of the 1024 bits of the IC tuning and redundancy information, (iii) the last 682 bits of the 1024 bits of the IC tuning and redundancy information, or (iv) selected in any suitable manner.

[0084] In some embodiments, multiplexers 9200 to 920 (n-1) Each of the following can receive a bit value associated with an even bit index (e.g., a logic high or low value at bit indices 0, 2, 4, 6, 8…682) from a subset of the 'k' bits of IC tuning and redundancy information, and multiplexers 9200 to 920… (n-1) The second input to each of these components may receive a bit value associated with an odd-numbered bit index (e.g., a logic high or low value at bit indices 1, 3, 5, 7, 9…681) from a subset of the 'k' bits of the IC tuning and redundancy information. Based on the description herein, the subset of the 'k' bits of the IC tuning and redundancy information may be mapped to multiplexer 9200 to multiplexer 920 in any suitable manner. (n-1) The first and second inputs.

[0085] According to some embodiments, LFSR 930 may receive 'n' bits output by controller 610 (e.g., outputs 9100 to 910). (n-1) The 'n' bits are used as an initial or seed value. According to some embodiments, after loading the 'n' bits into the LFSR 930, the LFSR 930 can be made to cycle based on a predetermined number of cycles. The 'n' bits of the LFSR 930 output cycle are used as the input for multiplexer 9200 to multiplexer 920. (n-1) Selection signal 9400 to selection signal 940 (n-1) The above text is for reference only. Figure 4 16-bit LFSR400 and Figure 5The 32-bit LFSR 500 describes an example implementation of the LFSR 930. Other implementations of the LFSR 930 are within the spirit and scope of this disclosure.

[0086] Based on selection signal 9400 to selection signal 940 (n-1) Values ​​(e.g., logic high or logic low), multiplexer 9200 to multiplexer 920 (n-1) Output its first or second input as output 9500 to output 950 respectively. (n-1) In some embodiments, outputs 9500 to 950 (n-1) This represents a bit randomly extracted from the IC fine-tuning and redundancy information of operation 210.

[0087] Figure 10 It is practicable according to some embodiments Figure 6 The diagram illustrates another selection module 1000 in the multiplexer-based circuit architecture 600. In some embodiments, the number of 'k' bits of IC tuning and redundancy information can be much greater than twice the number of 'n' bits output by the controller 610 (e.g., 'k' >> [2·'n'], such as 3 times, 4 times, 5 times, or other magnitudes greater than twice the number of 'n' bits). In this case, the multiplexer architecture illustrated in the selection module 1000 can be used.

[0088] In some embodiments, the selection module 1000 includes multiplexers 10200 to 1020. (M-1)Here, 'M' represents the number of multiplexer rows and depends on the number of 'k' bits of the IC tuning and redundancy information and the number of 'n' bits of the controller 610 output. For example, the value of 'n' can be 64, and the value of 'k' can be 1024. Here, the value of 'M' can be 4, for example, 4 rows of multiplexers. In this example, the first row of multiplexers can have 512 multiplexers, where the first input of each multiplexer can receive a bit value associated with an even bit index (e.g., a logic high or low value at bit indices 0, 2, 4, 6, 8…1024) from the 'k' bits of the IC tuning and redundancy information, and the second input of each multiplexer can receive a bit value associated with an odd bit index (e.g., a logic high or low value at bit indices 1, 3, 5, 7, 9…1023) from the 'k' bits of the IC tuning and redundancy information. Based on the description herein, the 'k' bits of IC tuning and redundancy information can be mapped to the first and second inputs of the multiplexer in any suitable manner. The second row of the multiplexer can have 256 multiplexers, each receiving an output as input from a multiplexer in the first row (e.g., similar to the multiplexer inputs in the row of multiplexer 10201). The third row of the multiplexer can have 128 multiplexers, each receiving an output as input from a multiplexer in the second row (e.g., similar to the multiplexer inputs in the second row). The fourth row of the multiplexer can have 64 multiplexers, each receiving an output as input from a multiplexer in the third row (e.g., similar to the multiplexer inputs in the third row).

[0089] According to some embodiments, the LFSR 1030 can receive 'M' bits extracted from the 'k' bits of IC tuning and redundancy information as an initial value or seed value. The LFSR 1030 can receive from... Figure 6 The controller 610 receives the extracted 'M' bits (e.g., outputs 10100 to 1010). (M-1) The controller 610 can extract 'M' bits from the IC tuning and redundancy information using various methods: (i) extracting the first 'M' bits from the 'k' bits of the IC tuning and redundancy information; (ii) extracting the last 'M' bits from the 'k' bits of the IC tuning and redundancy information; (iii) randomly extracting 'M' bits from the 'k' bits of the IC tuning and redundancy information; or (iv) using any other suitable extraction method. According to some embodiments, after receiving the 'M' bits extracted from the 'k' bits of the IC tuning and redundancy information from the controller 610, the LFSR 1030 can be cycled based on a predetermined number of cycles. The LFSR 1030 outputs the cycled extracted bits to multiplexers 10200-1020 respectively.(M-1) The selection signal of the multiplexer in the line is 10400-1040. (M-1) The above text is for reference only. Figure 4 16-bit LFSR400 and Figure 5 The 32-bit LFSR 500 describes an example implementation of the LFSR 1030. Other implementations of the LFSR 1030 are described within the spirit and scope of this disclosure.

[0090] Based on selection signal 10400 to selection signal 1040 (M-1) The value (e.g., logic high or logic low), multiplexer 10200 to 1020 (M-1) Each row of the multiplexer outputs either its first or second input. Multiplexer 1020 (m-1) The multiplexer output bit in the row is 'n', and in Figure 10 The value is represented as output 10500 to output 1050. (n-1) The multiplexer output represents bits randomly extracted from the IC fine-tuning and redundancy information of operation 210.

[0091] refer to Figure 2 In operation 220, a hash function is performed on bits randomly extracted from IC fine-tuning and redundancy information to produce bits (hash bits) after the hash function operation. In some embodiments, the hash function may be a cryptographic hash function, such as a secure hash algorithm (SHA), SHA-2, SHA-3, XOR tree hash, and combinations thereof for randomly extracted bits.

[0092] Figure 11 It is practicable according to some embodiments Figure 1 A diagram of a hash circuit 1100 performing the hash function of operation 220 within a PUF circuit 110. The hash circuit 1100 includes a register 1110 and a hash function operation module 1120. In some embodiments, register 1110 receives and stores randomly extracted bits from IC fine-tuning and redundancy information (from operation 210). According to some embodiments, register 1110 may receive bits from... Figure 3 LFSR-based circuit architecture 300 or Figure 6The output of the multiplexer-based circuit architecture 600 receives bits randomly extracted from IC fine-tuning and redundancy information. The hash function operation module 1120 can perform a hash function, such as SHA, SHA-2, SHA-3, or XOR tree hash, on the randomly extracted bits, or perform a combination of these functions on information stored in register 1110 to produce hash bits. Other types of hash functions are also possible within the spirit and scope of this disclosure. In some embodiments, the type of hash function performed by the hash function operation module 1120 may depend on the security requirements of the IC implementing the PUF circuit 110.

[0093] refer to Figure 2 In operation 230, statistical analysis is performed on the hash bits. Figure 1 The PUF circuit 110 may include one or more processors to perform the statistical analysis of operation 230. In some embodiments, the statistical analysis includes Hamming weight analysis of hash bits, inter-Hamming distance (inter-HD) analysis of hash bits, inter-HD analysis of hash bits, autocorrelation operation of hash bits, or a combination thereof. According to some embodiments, Hamming weight analysis may be used to determine the percentage of 1s (e.g., logic high values) and 0s (e.g., logic low values) in the hash bits (from operation 220).

[0094] In some embodiments, when multiple challenges are issued to the PUF circuit 110, inter-HD analysis can be used to measure the randomness between hash bits (from operation 220). For example, if first IC tuning and redundancy information (e.g., the first challenge) is input to... Figure 1 In the PUF circuit 110, the PUF circuit 110 generates a first set of hash bits. If a second set of IC fine-tuning and redundancy information, different from the first IC fine-tuning and redundancy information, is input into the PUF circuit 110, the PUF circuit 110 generates a second set of hash bits. The first set of hash bits and the second set of hash bits can be compared with each other to determine the degree of randomness.

[0095] In some embodiments, when the same challenge is issued to PUF circuit 110, HD in-circuit analysis can be used to measure the randomness of the hash bits (from operation 220). For example, if the same first trimming and redundancy information (e.g., challenge) is input to PUF circuit 110 multiple times, then PUF circuit 110 should produce the same hash bits each time. If the hash bits are different at different times when the same first trimming and redundancy information is input to PUF circuit 110, then randomness can be determined.

[0096] In some embodiments, when two challenges are issued to the PUF circuit 110, an autocorrelation operation can be used to measure the similarity between the hash bits of the challenge (from operation 220) and the hash bits of a delayed version of the same challenge (from operation 220). For example, if first IC tuning and redundancy information (e.g., a challenge) are input to... Figure 1 In the PUF circuit 110, the PUF circuit 110 generates a first set of hash bits. If a second set of IC tuning and redundancy information (e.g., a challenged delayed version) is input to the PUF circuit 110, the PUF circuit 110 generates a second set of hash bits. In some embodiments, the delayed version of the first IC tuning and redundancy information may be represented by bit offsets of the first IC tuning and redundancy information (e.g., 2-bit offset, 4-bit offset, 16-bit offset, and 32-bit offset). The first set of hash bits and the second set of hash bits can be compared with each other to determine similarity.

[0097] refer to Figure 2 In operation 240, it is determined whether the statistical properties of the hash bits satisfy one or more criteria. Figure 1 The PUF circuit 110 may include one or more processors to perform the determination of operation 240. In some embodiments, operation 240 determines whether the hash bit satisfies one or more criteria associated with one or more of the Hamming weighted analysis of the hash bit, the inter-HD analysis of the hash bit, the intra-HD analysis of the hash bit, and the autocorrelation operation of the hash bit performed in operation 230.

[0098] In some embodiments, the criteria for Hamming weighted analysis of hash bits may be: whether the percentage of 1s (e.g., logic high values) in the hash bits is within a predetermined range, such as between 45% and 55%, between 40% and 60%, and between 35% and 65%. In some embodiments, the criteria for inter-HD analysis of hash bits may be: when comparing a first set of hash bits from a first challenge with a second set of hash bits from a second challenge—whether at least a predetermined percentage of bits (e.g., at least 50% of the bits) are flipped from '1' to '0' or from '0' to '1'. As discussed above, the first challenge and the second challenge are different from each other and are input to PUF circuit 110. In some embodiments, the criteria for intra-HD analysis of hash bits may be: whether a predetermined percentage of bits (e.g., 0% of the bits or no bits) are flipped when the same challenge is issued to PUF circuit 110. In some embodiments, the criterion for the autocorrelation operation on the hash bits may be whether a predetermined percentage of bits (e.g., 0% of the bits or no bits) are flipped when the first set of hash bits from the challenge is compared with the second set of hash bits from the delayed version of the challenge.

[0099] In some embodiments, if the statistical properties of the hash bits do not meet one or more criteria, then method 200 repeats operations 210, 220, 230, and 240 (e.g., ...). Figure 2 (As shown by the solid arrows in the diagram). For example, if the statistical properties of the hash bits are outside a predetermined percentage range for Hamming weighted analysis, below a predetermined percentage of bits flipped from between HDs, above a predetermined percentage of bits flipped from within HDs, and / or above a predetermined percentage of bits flipped from autocorrelation operations, then the hash bits do not meet one or more criteria. Alternatively, in some embodiments, if the statistical properties of the hash bits do not meet one or more criteria, then method 200 repeats operations 220, 230, and 240 (e.g., ...). Figure 2 (As shown by the dashed arrow in the image).

[0100] refer to Figure 2 If the statistical properties of the hash bits satisfy one or more criteria, then in operation 240, method 200 proceeds to operation 250. In operation 250, according to some embodiments, the hash bits are output by PUF circuit 110 to represent a device signature of memory device 100.

[0101] Embodiments of this disclosure describe an IC device having a PUF circuit. In some embodiments, the PUF circuit is configured to generate a device signature based on IC tuning and redundancy information. According to some embodiments, the IC tuning and redundancy information may be based on one or more of the following: I / O circuit repair information, sense amplifier tuning information, physical addresses associated with repair word lines in a memory device, physical addresses associated with repair bit lines in a memory device, A / D converter tuning information, D / A tuning information, sensor tuning information, any other IC tuning and redundancy information, or combinations thereof. Among other things, an advantage of the embodiments described herein is the lower overhead of the PUF circuit because the information used to generate the device signature is based on existing IC tuning and redundancy information unique to the IC device.

[0102] Embodiments of this disclosure include an apparatus for generating a signature based on tuning and redundancy information, having a memory and a processor. The memory is configured to store IC tuning and redundancy information. The processor is configured to extract bits from the IC tuning and redundancy information, perform a hash function on the extracted bits to generate hash bits, and output the hash bits in response to statistical properties of the hash bits satisfying one or more criteria. In some embodiments, the memory storing the IC tuning and redundancy information may be different from other memories used by the apparatus for other operations (e.g., accessing user data and program data written to system memory). In some embodiments, the IC tuning and redundancy information includes one or more of the following: a subset of input / output circuit repair information, a subset of sense amplifier tuning information, a subset of physical addresses associated with repair word lines in the memory device, a subset of physical addresses associated with repair bit lines in the memory device, a subset of analog-to-digital converter tuning information, a subset of digital-to-analog tuning information, and a subset of sensor tuning information. In some embodiments, to extract the bits from the integrated circuit tuning and redundancy information, the processor is further configured to: initialize a linear feedback shift register (LFSR) with a first subset of the integrated circuit tuning and redundancy information; cause the LFSR to cyclically operate based on values ​​associated with a second subset of the integrated circuit tuning and redundancy information, wherein the second subset is different from the first subset of the integrated circuit tuning and redundancy information; and output the contents of the cyclically operated LFSR to produce the extracted bits. In some embodiments, the processor is further configured to: input the first subset of the integrated circuit tuning and redundancy information into a plurality of multiplexer circuits; and select the output of each of the plurality of multiplexer circuits based on the second subset of the integrated circuit tuning and redundancy information to produce the extracted bits, wherein the number of bits in the second subset is half the number of bits in the first subset of the integrated circuit tuning and redundancy information. In some embodiments, the processor is further configured to: input a first subset of the integrated circuit tuning and redundancy information into a plurality of multiplexer circuits; initialize a linear feedback shift register with a second subset of the integrated circuit tuning and redundancy information, wherein the number of bits in the second subset is half the number of bits in the first subset of the integrated circuit tuning and redundancy information; cyclically operate the linear feedback shift register for a predetermined number of clock cycles; and select the output of each of the plurality of multiplexer circuits based on the output of the cyclically operating linear feedback shift register to generate the extracted bits. In some embodiments, in order to perform the hash function on the extracted bits, the processor is further configured to perform a cryptographic hash function on the extracted bits to generate the hash bits.In some embodiments, the cryptographic hash function includes one or more of the following: Secure Hash Algorithm (SHA), Secure Hash Algorithm-2, Secure Hash Algorithm-3, and XOR tree hashing performed on the extracted bits. In some embodiments, to output the hash bit, the processor is further configured to determine the statistical properties of the hash bit based on one or more of the following: Hamming weight analysis of the hash bit, inter-Hamming distance analysis of the hash bit, intra-Hamming distance analysis of the hash bit, and autocorrelation operation on the hash bit. In some embodiments, the processor is further configured to, in response to the statistical properties of the hash bit not satisfying one or more criteria, repeat one or more of the following operations: extracting bits from the integrated circuit fine-tuning and redundancy information, and performing the hash function on the extracted bits to produce the hash bit.

[0103] Embodiments of this disclosure include a method for generating an apparatus signature based on fine-tuning and redundancy information, the method storing fine-tuning and redundancy information associated with an integrated circuit; retrieving the fine-tuning and redundancy information to extract bits from the fine-tuning and redundancy information; and performing a hash function on the extracted bits to generate hash bits. The method further includes outputting hash bits in response to statistical properties of the hash bits satisfying one or more criteria. In some embodiments, the method further includes: in response to the statistical properties of the hash bits not satisfying the one or more criteria, repeating one or more of the following operations: retrieving the fine-tuning and redundancy information to extract the bits from the fine-tuning and redundancy information, and performing the hash function on the extracted bits to generate the hash bits. In some embodiments, retrieving the tuning and redundancy information to extract the bits includes: initializing a linear feedback shift register (LFSR) with a first subset of the tuning and redundancy information; cyclically operating the LFSR based on values ​​associated with a second subset of the tuning and redundancy information, wherein the second subset is different from the first subset of the tuning and redundancy information; and outputting the contents of the cyclically operating LFSR to produce the extracted bits. In some embodiments, retrieving the tuning and redundancy information to extract the bits includes: inputting a first subset of the tuning and redundancy information into a plurality of multiplexer circuits; and selecting the output of each of the plurality of multiplexer circuits based on a second subset of the tuning and redundancy information to produce the extracted bits, wherein the number of bits in the second subset is half the number of bits in the first subset of the integrated circuit tuning and redundancy information. In some embodiments, retrieving the tuning and redundancy information to extract the bit includes: inputting a first subset of the tuning and redundancy information into a plurality of multiplexer circuits; initializing a linear feedback shift register with a second subset of the tuning and redundancy information, wherein the number of bits in the second subset is half the number of bits in the first subset of the tuning and redundancy information; cyclically operating the linear feedback shift register for a predetermined number of clock cycles; and selecting the output of each of the plurality of multiplexer circuits based on the output of the cyclically operating linear feedback shift register to produce the extracted bit. In some embodiments, performing the hash function includes performing a cryptographic hash function operation on the extracted bit to produce the hash bit. In some embodiments, outputting the hash bit includes determining the statistical properties of the hash bit based on one or more of the following analyses: Hamming weight analysis of the hash bit, inter-Hamming distance (inter-HD) analysis of the hash bit, intra-Hamming distance analysis of the hash bit, and autocorrelation operation of the hash bit.

[0104] Embodiments of this disclosure include a system for signature-based fine-tuning and redundancy information generation apparatus having a non-volatile memory device and a physically unclonable function (PUF) circuit. The non-volatile memory device is configured to store integrated circuit (IC) fine-tuning and redundancy information. The PUF circuit is configured to: retrieve IC fine-tuning and redundancy information from the non-volatile memory device; extract bits from the IC fine-tuning and redundancy information; perform a hash function on the extracted bits to generate hash bits; output hash bits in response to statistical properties of the hash bits satisfying one or more criteria; and repeat one or more of the following operations in response to statistical properties of the hash bits not satisfying one or more criteria: extracting bits from the IC fine-tuning and redundancy information, and performing a hash function on the extracted bits to generate hash bits. In some embodiments, the non-volatile memory storing the IC fine-tuning and redundancy information may be different from other memory used by the system for other operations (e.g., accessing user data and program data written to system memory). In some embodiments, the physically unclonable function circuitry is further configured to: initialize a linear feedback shift register (LFSR) with a first subset of the integrated circuit tuning and redundancy information; cause the LFSR to cyclically operate based on values ​​associated with a second subset of the integrated circuit tuning and redundancy information, wherein the second subset is different from the first subset of the integrated circuit tuning and redundancy information; and output the contents of the cyclically operating LFSR to produce the extracted bits. In some embodiments, the physically unclonable function circuitry is further configured to: input the first subset of the integrated circuit tuning and redundancy information into a plurality of multiplexer circuits; and select the output of each of the plurality of multiplexer circuits based on the second subset of the integrated circuit tuning and redundancy information to produce the extracted bits, wherein the number of bits in the second subset is half the number of bits in the first subset of the integrated circuit tuning and redundancy information. In some embodiments, the physically unclonable function circuitry is further configured to: input a first subset of the integrated circuit tuning and redundancy information into a plurality of multiplexer circuits; initialize a linear feedback shift register with a second subset of the integrated circuit tuning and redundancy information, wherein the number of bits in the second subset is half the number of bits in the first subset of the integrated circuit tuning and redundancy information; cyclically operate the linear feedback shift register for a predetermined number of clock cycles; and select the output of each of the plurality of multiplexer circuits based on the output of the cyclically operating linear feedback shift register to produce the extracted bits.

[0105] It should be understood that the Description of Embodiments section, rather than the Abstract section, is intended to interpret the claims. The Abstract section may set forth one or more, but not all, possible embodiments of this disclosure as conceived by the inventors, and is therefore not intended to limit the appended claims in any way.

[0106] The foregoing disclosure outlines features of several embodiments, thereby enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An apparatus for generating a signature based on fine-tuning and redundancy information, comprising: One or more first circuit elements, including one or more of a sense amplifier, an analog-to-digital converter, a digital-to-analog converter, and a sensor; One or more second circuit elements, including one or more of input / output lines, word lines, and bit lines; A fine-tuning circuit configured to adjust one or more operating characteristics of the one or more first circuit components based on fine-tuning information, the fine-tuning information including one or more adjustment parameters of the adjusted one or more operating characteristics; A redundant circuit configured to replace one or more defective portions of the one or more second circuit elements based on redundancy information, the redundancy information including address mappings of the replaced one or more defective portions; as well as The processor is configured as follows: Extract bits from the fine-tuning and redundancy information; Perform a hash function operation on the extracted bits to produce hash bits; and The hash bit is output in response to the statistical properties of the hash bit satisfying one or more criteria.

2. The apparatus of claim 1, wherein the fine-tuning and redundancy information includes one or more of the following: a subset of input / output circuit repair information, a subset of sense amplifier fine-tuning information, a subset of physical addresses associated with repair word lines in the memory device, a subset of physical addresses associated with repair bit lines in the memory device, a subset of analog-to-digital converter fine-tuning information, a subset of digital-to-analog fine-tuning information, and a subset of sensor fine-tuning information.

3. The apparatus according to claim 1, wherein, In order to extract the bits from the fine-tuning and redundancy information, the processor is further configured to: The linear feedback shift register is initialized with a first subset of the fine-tuning and redundancy information; The linear feedback shift register is cyclically operated based on values ​​associated with a second subset of the fine-tuning and redundancy information, wherein the second subset is different from the first subset of the fine-tuning and redundancy information; as well as The contents of the linear feedback shift register of the loop are output to produce the extracted bits.

4. The apparatus according to claim 1, wherein, In order to extract the bits from the fine-tuning and redundancy information, the processor is further configured to: The first subset of the fine-tuning and redundancy information is input into multiple multiplexer circuits; as well as The output of each of the plurality of multiplexer circuits is selected based on a second subset of the fine-tuning and redundancy information to produce the extracted bits, wherein the number of bits in the second subset is half the number of bits in the first subset of the fine-tuning and redundancy information.

5. The apparatus according to claim 1, wherein, In order to extract the bits from the fine-tuning and redundancy information, the processor is further configured to: The first subset of the fine-tuning and redundancy information is input into multiple multiplexer circuits; The linear feedback shift register is initialized with a second subset of the fine-tuning and redundancy information, wherein the number of bits in the second subset is half the number of bits in the first subset of the fine-tuning and redundancy information. The linear feedback shift register is cyclically operated for a predetermined number of clock cycles; as well as The output of the linear feedback shift register that performs the cyclic operation is selected based on the output of each of the plurality of multiplexer circuits to produce the extracted bits.

6. The apparatus according to claim 1, wherein, In order to perform the hash function on the extracted bits, the processor is further configured to perform a cryptographic hash function on the extracted bits to generate the hash bits.

7. The apparatus according to claim 6, wherein the encrypted hash function comprises one or more of the following: a secure hash algorithm, a secure hash algorithm-2, a secure hash algorithm-3, and an XOR tree hash, performed on the extracted bits.

8. The apparatus according to claim 1, wherein, In order to output the hash bit, the processor is further configured to determine the statistical properties of the hash bit based on one or more of the following: Hamming weight analysis of the hash bit, Hamming distance analysis of the hash bit, Hamming distance analysis of the hash bit, and autocorrelation operation on the hash bit.

9. The apparatus of claim 1, wherein the processor is further configured to repeat one or more of the following operations in response to the statistical properties of the hash bit not satisfying the one or more criteria: extracting bits from the fine-tuning and redundancy information, and performing the hash function on the extracted bits to generate the hash bit.

10. A method for generating a device signature based on fine-tuning and redundancy information, comprising: Adjust an operational characteristic of the first circuit based on fine-tuning information; Replace a defective part of the second circuit based on redundant information; Extract bits from the fine-tuning and redundancy information; A hash function is performed on the extracted bits to produce hash bits; as well as The hash bit is output in response to the statistical properties of the hash bit satisfying one or more criteria.

11. The method of claim 10, further comprising: In response to the statistical properties of the hash bit not satisfying one or more criteria, one or more of the following operations are repeated: retrieving the fine-tuning and redundancy information to extract the bit from the fine-tuning and redundancy information, and performing the hash function on the extracted bit to produce the hash bit.

12. The method of claim 10, wherein extracting the bit comprises: The linear feedback shift register is initialized with a first subset of the fine-tuning and redundancy information; The linear feedback shift register is cyclically operated based on values ​​associated with a second subset of the fine-tuning and redundancy information, wherein the second subset is different from the first subset of the fine-tuning and redundancy information; as well as The contents of the linear feedback shift register that performs the cyclic operation are output to generate the extracted bits.

13. The method of claim 10, wherein extracting the bit comprises: The first subset of the fine-tuning and redundancy information is input into multiple multiplexer circuits; as well as The output of each of the plurality of multiplexer circuits is selected based on a second subset of the fine-tuning and redundancy information to produce the extracted bits, wherein the number of bits in the second subset is half the number of bits in the first subset of the fine-tuning and redundancy information.

14. The method of claim 10, wherein extracting the bit comprises: The first subset of the fine-tuning and redundancy information is input into multiple multiplexer circuits; The linear feedback shift register is initialized with a second subset of the fine-tuning and redundancy information, wherein the number of bits in the second subset is half the number of bits in the first subset of the fine-tuning and redundancy information. The linear feedback shift register is cyclically operated for a predetermined number of clock cycles; as well as The output of the linear feedback shift register that performs the cyclic operation is selected based on the output of each of the plurality of multiplexer circuits to produce the extracted bits.

15. The method of claim 10, wherein performing the hash function comprises performing a cryptographic hash function operation on the extracted bits to generate the hash bits.

16. The method of claim 10, wherein outputting the hash bit comprises determining the statistical properties of the hash bit based on one or more of the following analyses: Hamming weight analysis of the hash bit, Hamming distance analysis between the hash bits, Hamming distance analysis within the hash bits, and autocorrelation operation on the hash bit.

17. A system for signature based on a fine-tuning and redundancy information generation device, comprising: First circuit; Second circuit; A fine-tuning circuit is configured to adjust an operating characteristic of the first circuit based on fine-tuning information; A redundant circuit is configured to replace a defective portion of the second circuit based on redundant information. as well as A physically non-clonable function circuit is configured as follows: Extract bits from the fine-tuning and redundancy information; A hash function is performed on the extracted bits to produce hash bits; The hash bit is output in response to the statistical properties of the hash bit satisfying one or more criteria; as well as In response to the statistical properties of the hash bit not satisfying one or more criteria, one or more of the following operations are repeated: extracting bits from the fine-tuning and redundancy information, and performing the hash function on the extracted bits to produce the hash bit.

18. The system of claim 17, wherein the physically unclonable function circuitry is further configured to: The linear feedback shift register is initialized using a first subset of the fine-tuning and redundancy information; The linear feedback shift register is cyclically operated based on values ​​associated with a second subset of the fine-tuning and redundancy information, wherein the second subset differs from the first subset of the fine-tuning and redundancy information; and The contents of the linear feedback shift register that performs the cyclic operation are output to generate the extracted bits.

19. The system of claim 17, wherein the physically unclonable function circuit is further configured to: The first subset of the fine-tuning and redundancy information is input into multiple multiplexer circuits; and The output of each of the plurality of multiplexer circuits is selected based on a second subset of the fine-tuning and redundancy information to produce the extracted bits, wherein the number of bits in the second subset is half the number of bits in the first subset of the fine-tuning and redundancy information.

20. The system of claim 17, wherein the physically unclonable function circuit is further configured to: The first subset of the fine-tuning and redundancy information is input into multiple multiplexer circuits; The linear feedback shift register is initialized with a second subset of the fine-tuning and redundancy information, wherein the number of bits in the second subset is half the number of bits in the first subset of the fine-tuning and redundancy information. The linear feedback shift register is cyclically operated for a predetermined number of clock cycles; as well as The output of the linear feedback shift register that performs the cyclic operation is selected based on the output of each of the plurality of multiplexer circuits to produce the extracted bits.

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