A semiconductor structure and a method for preparing an active region thereof

Abstract

The present application relates to a semiconductor structure and a method for preparing an active region of the semiconductor structure. The method for preparing an active region of a semiconductor structure comprises: depositing amorphous silicon on a semiconductor substrate with etched trenches to form an amorphous silicon layer from the bottom to the top of the trench; in-situ low-temperature oxidation of the amorphous silicon layer; the temperature of the in-situ low-temperature oxidation is 600-700 DEG C, and the oxidation gas is a mixture of H2 and O2 with a volume ratio of 1:2-10; and depositing an oxide layer on the trench after the in-situ low-temperature oxidation. The present application can avoid the problem of amorphous silicon residue when depositing an oxide layer by performing low-temperature oxidation of the amorphous silicon after depositing the amorphous silicon and before depositing the oxide layer, thereby avoiding device defects caused by the problem and saving the process of oxidizing the amorphous silicon after depositing the oxide layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating its active region. Background Technology

[0002] With the miniaturization of electronic devices, Dynamic Random Access Memory (DRAM) has become a crucial component. During its active fabrication process, if active sidewall oxidation is performed directly after trench etching, it can lead to thinning of the active region, resulting in defects in subsequent processes, such as reduced contact area on the active region. To mitigate this issue, methods such as... Figures 1 to 3 As shown, after etching the trenches, amorphous silicon is deposited, followed by a subsequent oxidation process to prevent thinning at the top of the active region. Figure 1 The cross-sectional morphology after trench etching; Figure 2 For the cross-sectional morphology after deposition of amorphous silicon and Figure 3 This image shows the cross-sectional morphology after an oxide layer has been deposited using atomic layer deposition (ALD). In this process, the step coverage of the oxide layer is crucial. Step coverage refers to the ratio of the film thickness deposited at the bottom of the trench to the film thickness deposited on the horizontal surface of the step at the top of the trench. Insufficient step coverage will result in amorphous silicon residue at the bottom of the trench, leading to device defects. Summary of the Invention

[0003] The main objective of this invention is to provide a method for preparing an active region in a semiconductor structure. This method involves performing low-temperature oxidation on the amorphous silicon after deposition and before deposition of an oxide layer, which can avoid the problem of amorphous silicon residue during oxide deposition, thereby avoiding device defects caused by amorphous silicon residue, and eliminating the step of oxidizing amorphous silicon after oxide deposition.

[0004] Another object of the present invention is to provide a semiconductor active region structure that is free from amorphous silicon residual defects.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A method for fabricating an active region in a semiconductor structure includes:

[0007] Amorphous silicon is deposited on a semiconductor substrate with etched trenches to form an amorphous silicon layer from the bottom to the top of the trench;

[0008] The amorphous silicon layer is subjected to in-situ low-temperature oxidation; the temperature of the in-situ low-temperature oxidation is 600℃~700℃, and the oxidizing gas is a mixture of H2 and O2 in a volume ratio of 1:2~1:10.

[0009] An oxide layer is deposited on the trench after the in-situ low-temperature oxidation.

[0010] In contrast, existing technologies typically oxidize amorphous silicon after depositing an oxide layer to address the problem of residual amorphous silicon. This method cannot achieve in-situ oxidation due to the intermediate oxide layer deposition process, and the oxide layer's obstruction places higher demands on the oxidation process for residual amorphous silicon.

[0011] In summary, this invention not only solves the problem of amorphous silicon residue, but also improves process efficiency.

[0012] The present invention also provides a semiconductor active region structure, including a semiconductor substrate; trenches are etched on the semiconductor substrate, and an amorphous silicon layer and an oxide deposition layer are sequentially disposed on the surface of the trenches from bottom to bottom, wherein the surface layer of the amorphous silicon layer is a silicon oxide layer.

[0013] The present invention also provides a semiconductor device comprising the above-described active semiconductor region structure.

[0014] The semiconductor device includes, but is not limited to, DRAM, 2D NAND, 3D NAND, or logic devices.

[0015] The active region in the aforementioned semiconductor device can be formed using the fabrication method described above.

[0016] Compared with the prior art, the present invention achieves the following technical effects:

[0017] (1) It eliminates the problem of amorphous silicon defects caused by insufficient step coverage;

[0018] (2) Compared with the process of oxidizing residual amorphous silicon defects after depositing an oxide layer, the present invention can be carried out in situ, saving time and energy consumption and improving process efficiency.

[0019] (3) The process of oxidizing residual amorphous silicon after depositing the oxide layer is eliminated. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0021] Figure 1 The cross-sectional morphology after trench etching;

[0022] Figure 2 for Figure 1 Morphology of the surface after amorphous silicon deposition;

[0023] Figure 3 for Figure 2 Topographic image of a cross section after surface oxide layer deposition;

[0024] Figure 4 To improve the process of existing methods for handling amorphous silicon residues;

[0025] Figure 5 This invention improves the process of the method for removing amorphous silicon residue. Detailed Implementation

[0026] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0027] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0028] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0029] To address the issue of insufficient step coverage during oxidation leading to amorphous silicon residue, existing technologies typically oxidize the amorphous silicon after depositing an oxide layer. The process for forming the active region is as follows: Figure 4 As shown. This method cannot achieve in-situ oxidation because of the intermediate oxide layer deposition process, and the oxide layer also makes the process requirements for oxidizing residual amorphous silicon more stringent.

[0030] In contrast, the present invention provides the following preparation method:

[0031] A method for fabricating an active region in a semiconductor structure, such as Figure 5 As shown, it includes:

[0032] Step 1: Etch trenches on the semiconductor substrate;

[0033] The second step is to deposit amorphous silicon on a semiconductor substrate with etched trenches to form an amorphous silicon layer from the bottom to the top of the trenches.

[0034] The third step is to perform in-situ low-temperature oxidation on the amorphous silicon layer; the temperature of the in-situ low-temperature oxidation is 600-700℃, and the oxidation gas is a mixture of H2 and O2 in a volume ratio of 1:2 to 1:10.

[0035] The fourth step is to deposit an oxide layer on the trench after the in-situ low-temperature oxidation.

[0036] The method of the present invention performs low-temperature oxidation on amorphous silicon after deposition of amorphous silicon and before deposition of oxide layer, which improves the step coverage during the oxidation process, avoids the problem of amorphous silicon residue during oxide layer deposition, thereby avoiding device defects caused by amorphous silicon residue, while reducing the requirement for step coverage during oxide layer deposition, and eliminating the step of oxidizing amorphous silicon after oxide layer deposition.

[0037] The semiconductor substrate mentioned above can be any semiconductor structure that requires the deposition of amorphous silicon films. Taking DRAM as an example, the semiconductor substrate includes a region for forming memory cells and a region for forming core / periphery. Trenches can be formed on the semiconductor substrate through an etching process. Active regions are formed between the trenches. The trenches include a top surface and a bottom surface, where the top surface constitutes the top of the active region.

[0038] In the above methods, the deposition technique and silicon source are not limited when depositing amorphous silicon. Deposition techniques include, but are not limited to, typical CVD, ALD, or LPCVD. Silicon sources include, but are not limited to, typical: diisopropylaminosilane (DIPAS), bis(tert-butylamino)silane (BTBAS), bis(diethylamino)silane (BDEAS), hexachlorosilane (HCDS), tris(dimethylamino)silane (TDMAS), butylaminosilane (BAS), diethylaminosilane (DEAS), dipropylaminosilane (DPAS), hexaethylaminosilane, etc.

[0039] In the above method, the in-situ low-temperature oxidation temperature is any temperature between 600 and 700°C. In some embodiments, the oxidation temperature is 600°C, 620°C, 630°C, 650°C, 670°C, 690°C, or 700°C, etc. In some preferred embodiments, the oxidation temperature is 600 to 650°C.

[0040] In the above method, the volume ratio of H2 to O2 in the oxidizing gas is arbitrary within the range of 1:2 to 1:10. In some embodiments, the volume ratio of H2 to O2 is 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9 or 1:10, etc. In some preferred embodiments, the volume ratio is 1:5 to 1:8.

[0041] The above method is applicable to the thickness of amorphous silicon layers. Its advantages are obvious, especially in terms of thickness. The amorphous silicon layer.

[0042] The method of oxide layer deposition is not limited to the above methods, including but not limited to the typical atomic layer deposition (ALD) method.

[0043] Any of the embodiments described above are applicable to the formation of active region structures of any semiconductor device, including but not limited to DRAM, 2D NAND, 3D NAND, or logic devices.

[0044] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for fabricating an active region in a semiconductor structure, characterized in that, include: Amorphous silicon is deposited on a semiconductor substrate with etched trenches to form an amorphous silicon layer from the bottom to the top of the trench; The amorphous silicon layer is subjected to in-situ low-temperature oxidation at a temperature of 600℃~700℃, and the oxidizing gas is a mixture of H2 and O2 in a volume ratio of 1:2~1:10; the thickness of the amorphous silicon layer is ≤50Å. Deposited oxide layer; After the deposition of the amorphous silicon layer and before the deposition of the oxide layer, the amorphous silicon layer is subjected to in-situ low-temperature oxidation.

2. The preparation method according to claim 1, characterized in that, The in-situ low-temperature oxidation temperature is 600℃~650℃.

3. The preparation method according to claim 1, characterized in that, The oxide layer was deposited using atomic layer deposition.

4. The preparation method according to claim 1, characterized in that, The thickness of the amorphous silicon layer is ≤30Å.

5. The preparation method according to any one of claims 1-4, characterized in that, The oxidizing gas used in the in-situ low-temperature oxidation process is a mixture of H2 and O2 in a volume ratio of 1:5 to 1:

8.

6. A semiconductor active region structure prepared by the method according to any one of claims 1-5, characterized in that, Including semiconductor substrates; A trench is etched on the semiconductor substrate, and an amorphous silicon layer and an oxide deposition layer are sequentially disposed on the surface of the trench from bottom to top, and the surface layer of the amorphous silicon layer is a silicon oxide layer.

7. A semiconductor device comprising the semiconductor active region structure of claim 6.

8. The semiconductor device according to claim 7, characterized in that, It can be DRAM, 2D NAND, 3D NAND, or a logic device.

9. The method for fabricating the semiconductor device according to claim 7 or 8, characterized in that, The active region in the semiconductor device is formed using the fabrication method described in any one of claims 1-5.

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