Power-ground arrangement in a package structure

Abstract

Power-ground arrangements in package structures are disclosed. One structure includes a redistribution structure including a bottom layer and a plurality of upper layers above the bottom layer. The redistribution structure also includes a power-ground macro extending from a topmost layer of the plurality of upper layers to a bottommost layer of the plurality of upper layers, and a metal pad in the bottom layer and overlapping the power-ground macro. The metal pad is electrically disconnected from the power-ground macro.

Description

Technical Field

[0001] This disclosure generally relates to power-ground arrangements in package structures. Background Technology

[0002] In the fabrication of integrated circuit components, power and ground (VDD and VSS) networks are designed along with signal lines. Power and ground networks can include pre-designed macros (standard cells) that are selected and placed at desired locations in the layout of the integrated circuit component. While macros offer convenience and efficiency, they sacrifice design flexibility. For example, when designing the layout of a redistribution structure for an integrated fan-out (InFO) package, because a macro is used for VDD or VSS, the entire macro (characterized by a distribution from solder area to metal bumps on the opposite side of the redistribution structure) is attached to VDD or VSS. The entire chip area occupied by the macro cannot be used for routing other features. Summary of the Invention

[0003] According to a first aspect of this disclosure, a semiconductor structure is provided, comprising: a device die; an encapsulant therein encapsulating the device die; and a redistribution structure on and electrically connected to the device die, wherein the redistribution structure includes a bottom layer and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: a first power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; a second power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; at least one first conductive feature in the bottom layer overlapping the first power-ground macro; and at least one second conductive feature in the bottom layer overlapping the second power-ground macro, wherein the pattern of the at least one first conductive feature is different from that of the at least one second conductive feature.

[0004] According to a second aspect of this disclosure, a semiconductor structure is provided, comprising: a redistribution structure including a bottom layer and a plurality of upper layers above the bottom layer, wherein the redistribution structure includes: a first power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a first metal pad in the bottom layer and overlapping with the first power-to-ground macro, wherein the first metal pad is electrically disconnected from the first power-to-ground macro.

[0005] According to a third aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: placing a device die on a carrier; encapsulating the device chip in a sealant; planarizing the sealant to expose metal pads in the device chip; and forming a redistribution structure on the device die and the sealant, wherein the redistribution structure includes a bottom layer in contact with the device die and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: a first power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a first metal pad in the bottom layer and overlapping with the first power-to-ground macro, wherein the first metal pad is electrically disconnected from the first power-to-ground macro. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and 5B Cross-sectional and top views are shown in the design of a power-to-ground (PG) redistribution network according to some embodiments.

[0008] Figure 6 and Figure 7 A cross-sectional view of a PG redistribution network designed using a shortest path scheme according to some embodiments is shown.

[0009] Figure 8A A cross-sectional view of a package including a PG redistribution network according to some embodiments is shown.

[0010] Figures 8B to 8E A cross-sectional view is shown of an intermediate stage in the fabrication of a packaged assembly including a PG redistribution network according to some embodiments.

[0011] Figure 9 A process flow for designing and manufacturing a package including a PG network, according to some embodiments, is shown.

[0012] Figure 10 A process flow for manufacturing a package including a PG network, according to some embodiments, is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0015] A method for designing and arranging a power-to-ground (PG) network for a redistribution structure, and the resulting packaged assembly, are provided. According to some embodiments of this disclosure, the redistribution structure includes a PG network and signal redistribution lines. The redistribution structure includes an upper layer and a lower layer below the upper layer. Multiple PG macros (pre-designed and stored in a cell library) are selected and placed in the layout of the redistribution structure. The PG macros are in the upper layer and do not extend into the lower layer. The PG network in the lower layer is designed, laid out, and connected to the macros to complete the layout of the power network. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0016] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and 5BCross-sectional and top views of intermediate stages in the design and layout of a PG network according to some embodiments of the present disclosure are shown. Corresponding processes are also schematically reflected in, for example... Figure 9 The process flow shown is 200.

[0017] refer to Figure 5A A cross-sectional view of the layout of the redistributed structure 100 designed using the design process of this disclosure is shown. It can be understood that... Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B The design process shown is in the design phase and is not performed on physical entities such as wafers, dielectric materials, metals, etc. Therefore, when the features in these layers are referred to as (metal) lines / pads / boards, these features are actually patterns of these features in the layout, and the corresponding features are manufactured as physical entities after the design and layout are completed.

[0018] According to some embodiments of this disclosure, the layout of the redistributed structure 100 may be in Graphics Data System (GDS) format or any other applicable format. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B In the illustrated process, a computer can be used to design and lay out the redistributed structure 100. After the layout is completed, the layout of the redistributed structure 100 is saved to a storage device such as a hard disk, then taped out and implemented as a physical package, such as... Figure 8A The example is shown in the image.

[0019] like Figure 5AAs shown, the redistribution structure 100 includes multiple metal layers, and metal lines and metal plates (metal surfaces) are formed in these multiple metal layers. The multiple metal layers also include a lower layer and an upper layer above the lower layer. According to some embodiments of this disclosure, the lower layer is referred to as a PG-free macro layer because PG macros do not extend into these layers. The upper layer is referred to as a PG-containing macro layer because PG macros extend into each of these layers. According to some embodiments of this disclosure, the lower layer includes at least two layers, namely layer 1 and layer 2. Layer 1, also referred to as a bottom (electrical) connector layer or bump layer, includes metal bumps, metal pads, etc., which are used for electrical connection to (and can be coupled to) other package components, such as interposers, package substrates, printed circuit boards, etc. Layer 2 is a metal layer including metal features (patterns), such as metal lines, metal plates, metal pads, etc. The lower layer includes at least two layers and may include more layers, such as 3, 4, 5, or more metal layers. The power board and power lines in the lower layer are laid out without the use of PG macros.

[0020] The macro layer (upper layer) may include multiple metal layers, such as two, three, four, or more. The upper layer may also include a top connector layer, which includes electrical connectors such as metal pillars, solder areas, metal pads, and under-bump metallurgies. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B The example shown uses two lower layers and four upper layers, and different numbers of lower and upper layers are also within the scope of this disclosure. It should also be understood that the accompanying drawings primarily depict the power network, with signal lines also arranged in the same layer as the PG network. However, the layout of the signal lines is not shown in detail.

[0021] Before the layout process, PG macros can be designed and stored in a library, and can be stored on a hard drive or other types of storage devices. Multiple macro designs are possible to suit different design requirements. For example, the dimensions, number of vias, etc., included in the design macro can differ from one another in different PG macros. Some PG macro designs for VDD may be the same as or different from some PG macro designs for VSS. There can also be multiple different designs for PG macros for VDD, and multiple different designs for PG macros for VSS. A PG macro VDD can also be called a power macro VDD, and a PG macro VSS can also be called a ground macro VSS.

[0022] exist Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B The diagram shows a redistribution structure 100 for design and layout. Figure 5A The layout and process of ( ). Reference Figure 1A-1B In the initial stage of the placement process, multiple PG macros are selected from the library and placed in the placement. At this stage, the placement can be a blank placement or it can already include some placements (such as signal lines). The corresponding process... Figure 9 The process flow 200 shown is designated as process 202. The pre-designed PG macros include PG macro MVDD (which is a macro for VDD (positive power supply)) and PG macro MVSS (which can be a macro for electrical ground). PG macros can also be identified using numbers such as "1", "2", etc., to distinguish individual PG macros. In the example shown, PG macros MVDD and MVSS extend into layers 3-5 and the top connector layer. In other words, the design of PG macros MVDD and MVSS includes the design of the pattern of metal features in layers 3-5 and the top connector layer (layer 6), but does not include the design of metal features in the lower layers (i.e., layers 1 and 2 in the example shown). This also means that when PG macros MVDD and MVSS are placed in certain chip areas of the redistributed structure, the upper layer of the corresponding chip area in the macro layer is occupied by the already designed features. However, the chip area directly below the macro layer can still be used to lay out other features.

[0023] like Figure 1A As shown, some PG macros are the same as (or different from) each other. Furthermore, some PG macro MVDDs may be the same as (or different from) other PG macro MVDDs, and may be the same as some PG macro MVSSs. The same structure can be used to identify the presence of PG macros from physical packaged components manufactured by implementing the appropriate layout.

[0024] According to some embodiments, a PG macro MVDD (and MVSS) includes multiple metal plates, each in one of the upper layers. The top view shape and size of the metal plates of the same PG macro in different metal layers can be identical to each other (e.g., all having the same square or rectangular shape, such as...). Figure 1B (As shown), or they may differ from each other. Vias are formed to interconnect metal plates in adjacent layers. It is understood that vias in a via layer are vertically offset from the vias immediately above and below, because design rules may require vias in two adjacent via layers to have a certain lateral spacing.

[0025] Figure 1B A top view of multiple placements of macros MVDD and MVSS according to some embodiments is shown. Figure 1A The cross-sectional view shown illustrates Figure 1B Reference section 1A-1A is shown. The top view shown illustrates a portion of the macro placed in one of metal layers 3, 4, and / or 5. Figure 1B Several rectangular macros are shown as examples; these are PG macros MVDDs or MVSSs. According to some embodiments of this disclosure, the placed PG macros MVDDs or MVSSs are surrounded by a large chip area and spaced apart from each other. According to some embodiments of this disclosure, some of the PG macros MVDDs or MVSSs are portions of a composite macro (e.g., a composite macro CM as shown). The composite macro CM may include one or more PG macros MVDDs or MVSSs. The composite macro CM may also include vent holes DH, which are formed as holes in the respective metal plates to reduce pattern loading effects that occur during the electroplating process of the manufacturing stage when forming the respective metal layers.

[0026] exist Figure 1B In the diagram, each of the PG macros MVDD or MVSS includes four vias, each via shown as a circular pattern at the corner of the corresponding PG macro. It is understood that the number of vias in each of the PG macros MVDD or MVSS may differ from what is shown. For example, each of the PG macros MVDD or MVSS may include two to dozens of rows and two to dozens of columns of vias. The vias may also be arranged in an array or in a honeycomb (hexagonal) pattern.

[0027] Additionally, within the illustrated chip area, there may be several metal traces (MTs). These MTs can be laid out before or after the PG macro MVDD or MVSS. The patterns of the metal traces (MTs) in different metal layers may differ from those in other metal layers, but they can also be identical within a given chip area.

[0028] like Figure 1B As shown, there are also some metal pads (MPADs) that are elongated with circular patterns at opposite ends, where the circular patterns represent metal vias. Each metal pad is used to connect two vias, one via located at one end and used to connect to the metal feature above, and the other via located at the other end and used to connect to the metal feature below.

[0029] Figure 2A The layout process for placing the metal plate MP1 into the metal layer 2 and the electrical connector ECB into the metal layer 1 are illustrated. The corresponding processes are described in... Figure 9 The process flow 200 is shown as processes 204 and 206. According to some embodiments of this disclosure, the metal plate MP1 is a metal plate extending to a chip region overlapping with multiple PG macros MVDD and MVSS. For example, in Figure 2AIn the middle, the metal plate MP1 extends continuously to (and may extend beyond) the left edge of the leftmost PG macro MVDD, and extends to (and may extend beyond) the right edge of the rightmost PG macro MVSS. Figure 2B A top view of a metal plate MP1 is shown, which is a blank plate without holes. According to some embodiments of this disclosure, such as... Figure 1B The entire area shown is as follows Figure 2B Above the continuous metal plate MP1 shown. The metal plate MP1 can also be larger than... Figure 1B The area shown in the diagram, and can extend beyond the boundary of the area shown in one or all lateral directions.

[0030] Return to reference Figure 2A Multiple electrical connector ECBs (which may be metal pads, metal posts, etc.) are added to layer 1. These ECBs include some that overlap with the PG macro MVDD and MVSS, and others that are vertically offset from the PG macro MVDD and MVSS. It is understood that while some PG macro MVDDs and MVSSs are identical to each other, the patterns, positions, and dimensions of the ECBs directly beneath these PG macros have design freedom and can be identical or different from each other. Therefore, the patterns, positions, total number, connections, and dimensions of the ECBs overlapping one PG macro can differ from (or be identical to) the corresponding patterns, positions, total number, connections, and dimensions of the ECBs beneath another identical PG macro. According to some embodiments, all ECBs overlapping a PG macro can be electrically disconnected from the PG macro.

[0031] It is understood that in embodiments where the macro-free layer includes more (one or more) metal layers above layer 2, a metal plate may be added for each metal layer in the macro-free layer. The metal plates of different macro-free layers (lower layers) may or may not have the same top view shape and may or may not have the same top view dimensions.

[0032] Figure 3A The diagram shows a cross-sectional view of the redistributed structure after the metal plate MP1 has been patterned (cut) to form different patterns, some of which are connected to the PG macro MVDD, and others are connected to the PG macro MVSS. There may also be patterns used for signal routing. The corresponding processes are described in... Figure 9 The process flow 200 shown is referred to as process 208.

[0033] Figure 3B A top view of the cut metal plate MP1 is shown. It can be understood that, although... Figure 3B The PG macros MVDD and MVSS are shown, but the PG macros MVDD and MVSS shown actually override... Figure 3B The metal plate is on the layer shown (e.g., layer 2), not in it. Therefore, the location with the PG macros MVDD and MVSS shown is actually the metal plate. Furthermore, the metal plate in layer 2 may have the same pattern as or a different pattern than the metal plate in the corresponding overlying PG macro.

[0034] like Figure 3B As shown, Figure 2B The large metal plate MP1 shown is patterned into multiple smaller metal plates MPVDD and MPVSS. Metal plate MPVDD carries the power supply voltage VDD, and metal plate MPVSS carries the ground potential. Within the large metal plate MPVDD, there can be one or more smaller metal plates MPVSS, and within the large metal plate MPVSS, there can be one or more smaller metal plates MPVDD. Therefore, Figure 2B The metal plate MP1 shown is divided into several larger and smaller metal plates. Some features are labeled MVSS / MPVSS, indicating that these portions of the metal plate in metal layer 2 are MPVSS, which are below (and will connect to) the overlying PG macro MVSS. Furthermore, although the patterns of the metal plate MPVSS (marked with dashed squares) and its overlying PG macro MVSS are shown to be the same, they can also be different from each other. Similarly, some features are labeled MVDD / MPVDD, indicating that this portion of the metal plate in metal layer 2 is MPVDD, which are below (and will connect to) the overlying PG macro MVDD. Furthermore, although the patterns of the metal plate MPVDD (marked with dashed squares) and its overlying PG macro MVDD are shown to be the same, they can also be different from each other.

[0035] Metal plates MPVDD are physically separated from adjacent metal plates MPVSS. Adjacent metal plates MPVDD are merged to form a larger metal plate when there are no metal plates MPVSS separating them. For example, in Figure 3B In the middle, there exists a large metal plate MPVDD. In the example embodiment, the large metal plate carries the power supply voltage VDD. Inside the metal plate MPVDD, there may be some dashed features marked MVDD. These are patterns of the overlying PG macro MVDD, which are in the upper metal layer and electrically connected to the metal plate MPVDD via vias. The metal plate MPVSS inside the larger metal plate MPVDD is electrically connected to the overlying PG macro MVSS. The smaller metal plate MPVSS is spaced apart from and electrically isolated from the large metal plate MPVDD it surrounds. The pattern, position, and size of the metal plate MPVSS can be related to the overlying PG macro MVSS ( Figure 1B )different.

[0036] Similarly, there are some larger metal plate MPVSS (e.g., Figure 3BThe left-hand side has a larger metal plate (MPVSS), and inside the larger MPVSS is a smaller metal plate (MPVDD). The smaller metal plate (MPVDD) is spaced apart from and electrically isolated from the larger metal plate (MPVSS) it surrounds. Inside the MPVSS, there may be some dashed features marked MVSS. These are patterns of the PG macro MVSS, which are in the upper metal layer and electrically connected to the MPVSS via vias. The smaller metal plate (MPVSS) inside the larger metal plate (MPVDD) is electrically connected to the overlying PG macro MVSS. The pattern, position, and size of the smaller metal plate (MPVDD) can be related to the overlying PG macro MVSS. Figure 1B )different.

[0037] Through such Figure 2A , Figure 2B , Figure 3A and Figure 3B The fabrication scheme shown uses large metal plates for MPVDD and MPVSS (instead of thin metal wires) for VDD and VSS power supplies. Therefore, the power supply impedance is reduced compared to power supply schemes that use relatively thin metal traces.

[0038] Figure 4A This illustrates adding a metal feature MIF layout to, for example... Figure 3A In the macro-layers shown (e.g., layers 3-5), the metallic feature MIF interconnects adjacent PG macro MVDDs and adjacent PG macro MVSSs. The corresponding process is... Figure 9 The process flow 200 shown is designated as process 210. It can be understood that... Figure 4A In the diagram, the added metallic feature MIF is shown as forming an interface with the original PG macros MVDD and MVSS. However, these interfaces are used to show where the boundaries of the PG macros MVDD and MVSS are located, and these interfaces do not actually exist in the layout or in the final physical package manufactured.

[0039] Figure 4B It shows Figure 4A A top view. This top view represents one of the macro layers (e.g., layers 3, 4, and / or 5). Compared to the power grid, after adding the metal interconnect feature MIF, as... Figure 1B The isolated PG macro MVDD and MVSS shown become part of the power plane, and these parts have large metal plates MPVDD and MPVSS for carrying power and electrical grounding.

[0040] refer to Figure 5A Metal vias MV are used to connect the electrical connector ECB to the overlying metal plates MPVDD and MPVSS. The corresponding process is as follows: Figure 9The process flow 200 shown is referred to as process 212. Some electrical connectors ECB are connected to the metal plate MPVDD and are designated as electrical connector ECBVDD. Some other electrical connectors ECB are connected to the metal plate MPVSS and are designated as electrical connector ECBVSS.

[0041] Figure 5B It shows Figure 5A The diagram shows a top view of the structure. This top view represents one of the macro layers (e.g., layer 2). (Compared to...) Figure 3B Compared to the top view shown, multiple vent holes (DH) are formed to reduce the density of the metal pads MPVDD and MPVSS. Due to the high density of the power network region (compared to the chip region primarily used for signal routing), pattern loading effects are more likely to occur, and features in the chip region with higher metal density may be thinner than features in the chip region with lower metal density. By forming vent holes, the pattern loading effects are reduced.

[0042] According to alternative embodiments, it is possible to Figure 3A and Figure 3B The vent hole DH is formed in the same process shown, but not in a step after the formation of metal plates MPVDD and MPVSS. In other words, the vent hole DH is also formed in metal plates MPVDD and MPVSS in the same step of patterning metal plate MP1 to form metal plates MPVDD and MPVSS.

[0043] Return to reference Figure 4B Vent holes (DH) are also formed in the macrolayer, allowing the corresponding metallic features in the macrolayer (e.g., layers 3-5) to also exhibit reduced pattern loading effects. Metal interconnect features (MIF) Figure 4B The vent holes in DH and the vent holes in MPVDD and MPVSS of the metal plate can be formed in the same layout modification step or in a separate layout modification step.

[0044] Return to reference Figure 5A According to some embodiments of this disclosure, redundant vias MV1, MV2, MV3, etc., are laid out. The corresponding processes are as follows: Figure 9 The process flow 200 is shown as process 214. Some redundant vias (e.g., MV1) are used to connect the metal features MPVDD and MPVSS to the overlying MP macros MVSS and MVDD. Some other redundant vias (e.g., MV2) are added in the upper layer and outside the PG macros MVDD and MVSS, and are used for electrical interconnection of the PG macros MVDD and MVSS. Redundant vias may or may not be added inside the PG macros MVDD and MVSS. Figure 5A Some examples of redundant vias MV3 are shown, which are added inside the PG macros MVDD and MVSS, provided that it does not violate design rules.

[0045] Redundant vias can be added in the same layout step as adding other vias to interconnect metal features in different layers. Alternatively, redundant vias can be added in the layout step after the existing vias have been added. In this embodiment, the layout software checks for locations where redundant vias can be added without violating design rules and then adds them. Redundant vias serve to reduce the resistance of the power distribution network.

[0046] It is understood that the aforementioned process includes multiple processes, such as adding metal features in macro layers 3, 4, and 5, placing electrical connectors (ECBs), placing vias (MVs), and adding redundant vias. These processes can be performed in any order, and some of these process steps can be performed simultaneously.

[0047] Figure 6 The illustration shows the layout of electrical connectors ECT1 and ECT2 at the top connector layer according to some embodiments of this disclosure. ECT1 may be a VDD connector or a signal connector for carrying electrical signals. ECT2 may be a VSS connector or a signal connector for carrying signals. Electrical connectors ECT1 and ECT2 are not part of the PG macro. Therefore, the metal lines in layers 1 to 5, electrical connectors ECT1 and ECT2, and corresponding vias are laid out separately without needing to be selected and placed from a library. The shortest path scheme is used when laying out the individual metal features. For example, Figure 6 Some features are shown drawn with dashed boxes, representing metal features laid out using a conventional layout scheme. Figure 6 The dashed metal feature is shown extending in the same direction (e.g., to the left) from the bottom to the top. This results in the electrical path being away from the electrical connector ECT1 at metal layer 5, and a long connecting wire CON1 must be used to connect to the top electrical connector ECT1. The overlay vias are not laid out to overlap with the underlay vias because design rules may require a minimum lateral spacing between vias overlaying the metal feature and vias located below the same metal feature.

[0048] According to some embodiments of this disclosure, the shortest path scheme can be used to implement the layout of metal wires / boards and vias. For example, in Figure 6In the diagram, metal line / pad ML1 has left and right ends. Via MV1 below it connects to the left end of metal line / pad ML1, and via MV2 above it connects to the right end of metal line / pad ML1. The lateral spacing S1 between vias MV1 and MV2 can be equal to or greater than the minimum spacing allowed by the design rules. Metal line / pad ML2 also has left and right ends. Via MV2 below it connects to the right end of metal line / pad ML2, and via MV3 above it connects to the left end of metal line / pad ML2. The lateral spacing S2 between vias V2 and V3 can be equal to or slightly greater than the minimum spacing allowed by the design rules. With this staggered layout, the bottom electrical connector ECB can be connected to the overlying top electrical connector ECT1 without having a long lateral metal line / pad, and the total resistance between the bottom electrical connector ECB and the top electrical connector ECT1 is reduced. Electrical connector ECT2 can also be connected to the bottom connector ECB using the shortest path scheme.

[0049] Figure 7 The shortest path scheme according to some embodiments is shown, wherein the total number of macro layers without macro layers is greater than two, for example, the macro layers without macro layers include metal layers 1, 2, 3 and 4. The shortest path scheme can also be used to connect the bottom electrical connector ECB to the overlying PG macro, which can be the PG macro MVDD or MVSS.

[0050] After the layout is completed, the redistributed structure is rolled off the production line, and manufacturing processes are executed to form the physical packaged components. The corresponding processes are as follows: Figure 9 The process flow 200 shown is referred to as process 216. Figure 8A A redistributed structure according to some embodiments of the implementation layout is illustrated. It is understood that the illustrated structure includes an integrated fan-out package 102, wherein the redistributed structure 100 extends laterally beyond the opposite edge of the underlying device die 20, allowing for the formation of a top electrical connector (ETC) with a larger pitch for electrical connection to an electrical connector in the device die 20. It is understood that the PG network and the corresponding redistributed structure 100 can be used in other package components, including but not limited to package substrates, inserters, etc.

[0051] like Figure 8A As shown, the device die 20 includes a plurality of electrical connectors 22 located on its top surface. The electrical connectors 22 may include metal pillars, metal pads, etc. The electrical connectors 22 may be located within a dielectric layer 24, which may be formed of, or include, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. The device die 20 may be encapsulated in a sealant 26, which may be a molding compound, epoxy resin, resin, etc. The top surfaces of the device die 20 and the sealant 26 may be coplanar.

[0052] Figures 8B to 8EIt shows the manufacturing process as follows Figure 8A The intermediate stage of the integrated fan-out package 102 (which is a physical and tangible entity) is shown. A brief process is discussed in this paper. It can be understood that other processes can be employed because the PG redistribution network can be used for package components other than the fan-out package.

[0053] refer to Figure 8B The device die 20 is placed on a carrier 60, which can be a glass carrier. The corresponding process is as follows: Figure 10 The process flow 300 is shown as process 302. A release film 62, which may be a light-to-heat-conversion (LTHC) film, is coated on the carrier 60. The device die 20 can be adhered to the release film 62 via a die attachment film 64, which may be an adhesive layer. Although one device die 20 is shown, multiple identical device dies, identical to device die 20, can be placed on the carrier 60.

[0054] refer to Figure 8C The sealant 26 is dispensed and cured to seal the device die 20. The corresponding process is as follows: Figure 10 The process flow 300 shown is referred to as process 304. The sealant 26 may include molding compounds, epoxy resins, resins, etc. Next, as... Figure 8D As shown, planarization processes such as chemical mechanical polishing (CMP) or mechanical polishing are performed to expose the electrical connector 22 in the device die 20. The corresponding processes are as follows: Figure 10 The process flow 300 shown is referred to as process 306.

[0055] refer to Figure 8E A redistribution structure 100 is formed on the device die 20 and the sealant 26. The corresponding process is as follows: Figure 10The process flow 300 shown is designated as process 308. This forms an integrated fan-out package 102. Dielectric layers 30, 31, 34, 40, 48, and 54 can be formed of organic materials, such as polymers like PBO, polyimide, and BCB. Alternatively, dielectric layers 30, 31, 34, 40, 48, and 54 can be formed of inorganic materials such as SiO2, SiN, SiOC, SiOCN, and SiON. Redistribution lines and vias ETB, 36, 38, 42, 44, 50, 52, 60, and 62 can be formed of copper or copper alloys and may include other materials such as Ti, TiN, Ta, TaN, nickel, etc. The formation process may include electroplating. Metal lines 38, 44, 52, and 62 can be formed in the same electroplating process as their corresponding underlying vias 36, 42, 50, and 60, so there may be no distinguishable interface between them. According to some embodiments, the formation of the electrical connector ECB and redistribution lines may include depositing a metal seed layer, forming a patterned plating mask (not shown) on the metal seed layer, plating the electrical connector ECB in openings in the plating mask and on exposed portions of the metal seed layer, removing the plating mask, and etching the metal seed layer previously covered by plating features. The ETC may also include metal pillars and solder areas. The layout of the redistribution structure 100 is as discussed with reference to the foregoing embodiments. Metal layers 1-6 are also labeled. Features in the metal layers may correspond to... Figure 5A and Figure 5B The corresponding features in [the diagram]. For example, electrical connectors ECB and ETC respectively have [the following characteristics]. Figure 5A The diagram shows the ECB and ECT electrical connectors.

[0056] Then the integrated fan-out package 102 is debonded from the carrier 60. The corresponding process is as follows: Figure 10 The process flow 300 shown is referred to as process 310. According to some embodiments, the process is performed as follows: a laser beam is projected onto the LTHC 62, causing the LTHC 62 to decompose under the heat of the laser beam, and the integrated fan-out package 102 can be peeled off from the carrier 60. A polishing process can be performed on the back side of the device die 20 to remove the die-attached film 64. Figure 8A The resulting structure is shown.

[0057] In the above discussion of forming the redistribution structure 100, the redistribution structure 100 is formed layer by layer directly above the device die 20 and the sealant 26. According to other embodiments, the redistribution structure 100 can also be formed separately and then bonded to the device die 20 or another type of package assembly, such as a package, inserter, package substrate, printed circuit board, etc.

[0058] In such Figure 8AIn the structure shown, PG macro MVDDs and MVSSs are formed within the redistributed structure 100. According to some embodiments, no redundant vias are formed within the PG macro MVDDs and MVSSs. Therefore, multiple PG macro MVDDs and MVSSs (e.g., Figure 8A MVSS1 and MVSS2 in the PG macros can be identical to each other in terms of structure, size, and shape. These PG macros MVDD and MVSS can therefore be identified for the same structure they extend into multiple metal layers. It should also be noted that PG macros MVDD and MVSS in one or more metal layers can be parts of a continuous metal plate with no distinguishable interface between them.

[0059] The embodiments of this disclosure have several advantageous features. By designing a PG macro that extends into the upper layer of the redistributed structure and leaving the lower layer of the redistributed structure for other features, the chip region directly below the PG macro and in the lower layer can be freely used for design. This provides design flexibility because the chip region is independent of the PG macro. This chip region can be used to place features with potential-related properties other than the overlying PG macro, or it can be used to route signals. Furthermore, redundant vias are formed to reduce the resistance of the power path. A shortest path scheme is also employed to reduce the resistance of the power path. The shortest path scheme can be used in the layer directly below the PG macro and can extend into the layer above the PG macro, thus achieving both design flexibility and reduced resistance.

[0060] According to some embodiments of this disclosure, a structure includes: a device die; an encapsulant encapsulating the device die therein; and a redistribution structure on and electrically connected to the device die, wherein the redistribution structure includes a bottom layer and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: a first power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; a second power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; at least one first conductive feature in the bottom layer overlapping the first power-ground macro; and at least one second conductive feature in the bottom layer overlapping the second power-ground macro, wherein the pattern of the at least one first conductive feature is different from that of the at least one second conductive feature. In one embodiment, the at least one first conductive feature includes a first plurality of conductive features, the at least one second conductive feature includes a second plurality of conductive features, and a first total number of the first plurality of conductive features is different from a second total number of the second plurality of conductive features. In one embodiment, the at least one first conductive feature includes a first metal pad electrically isolated from the first power-ground macro. In one embodiment, the top layer includes a solder region. In one embodiment, the bottom layer contacts the metal pads in the device die. In one embodiment, both the first power-to-ground macro and the second power-to-ground macro are VDD macros. In one embodiment, both the first power-to-ground macro and the second power-to-ground macro are VSS macros. In one embodiment, the first power-to-ground macro includes a plurality of metal plates and a plurality of vias, each metal plate being in one of a plurality of upper layers, the plurality of vias being in each of the plurality of upper layers, and wherein the plurality of metal plates in the first power-to-ground macro have the same pattern, position, and size as the corresponding metal plates in the plurality of metal plates in the second power-to-ground macro. In one embodiment, the first power-to-ground macro includes a plurality of metal plates, and the edges of the plurality of metal plates are vertically aligned. In one embodiment, the redistribution structure further includes an additional layer above the bottom layer and below the plurality of upper layers, and wherein the redistribution structure further includes metal pads located in the additional layer, and the metal pads overlap with and are electrically disconnected from the first power-to-ground macro.

[0061] According to some embodiments of this disclosure, a structure includes: a redistribution structure including a bottom layer and a plurality of upper layers above the bottom layer, wherein the redistribution structure includes: a first power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a first metal pad in the bottom layer overlapping with the first power-to-ground macro, wherein the first metal pad is electrically disconnected from the first power-to-ground macro. In one embodiment, the structure further includes: a second metal pad in the bottom layer overlapping with the first power-to-ground macro, wherein the second metal pad is electrically connected to the first power-to-ground macro. In one embodiment, the structure further includes: a device die overlapping with the first power-to-ground macro, wherein the device die further includes a second metal pad physically bonded to the first metal pad. In one embodiment, the structure further includes: a second power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers, wherein the second power-to-ground macro is identical to the first power-to-ground macro; and a second metal pad in the bottom layer overlapping with the second power-to-ground macro, wherein the second metal pad is electrically connected to the second power-to-ground macro. In one embodiment, the first total number of metal pads in the bottom layer that overlap with the first power-ground macro is different from the second total number of metal pads in the bottom layer that overlap with the second power-ground macro.

[0062] According to some embodiments of this disclosure, a method includes: placing a device die on a carrier; encapsulating a device chip in a sealant; planarizing the sealant to expose metal pads in the device chip; and forming a redistribution structure on the device die and the sealant, wherein the redistribution structure includes a bottom layer in contact with the device die and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: a first power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a first metal pad in the bottom layer overlapping with the first power-ground macro, wherein the first metal pad is electrically disconnected from the first power-ground macro. In one embodiment, the redistribution structure further includes: a second power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a second metal pad in the bottom layer overlapping with the second power-ground macro, wherein the second metal pad is electrically connected to the second power-ground macro. In one embodiment, forming the first power-ground macro includes forming a solder region in the topmost of the plurality of upper layers. In one embodiment, the method further includes decoupling the carrier from the device die and the sealant. In one embodiment, the plurality of upper layers includes four layers.

[0063] According to some embodiments of this disclosure, a method includes: placing a plurality of power-to-ground macros in a layout of a redistribution structure, wherein the redistribution structure includes: a plurality of upper layers, wherein the plurality of power-to-ground macros extend into the plurality of upper layers; and a first lower layer below the plurality of upper layers; distributing a metal plate in the first lower layer, wherein the metal plate extends directly below the plurality of power-to-ground macros; patterning the metal plate to form a pattern of a plurality of metal features; and distributing a pattern of metal vias connecting the plurality of power-to-ground macros to the plurality of metal features directly below the plurality of power-to-ground macros. In one embodiment, the method further includes: manufacturing a physical package assembly implementing the layout of the redistribution structure. In one embodiment, the power-to-ground macros are copied from a cell library. In one embodiment, placing the plurality of power-to-ground macros includes placing VDD macros and VSS macros, wherein the VDD macros and VSS macros have the same structure. In one embodiment, the method further includes: distributing a bottom electrical connector in a second lower layer below the first lower layer, wherein the bottom electrical connector overlaps with a first macro among the plurality of power-to-ground macros, and the bottom electrical connector is electrically connected to a second macro among the plurality of power-to-ground macros. In one embodiment, the first macro is a VDD macro, and the second macro is a VSS macro. In one embodiment, the method further includes: positioning a top electrical connector in a redistributed structure layout; positioning a bottom electrical connector in a redistributed structure layout; and positioning a plurality of metal lines and vias to electrically connect the bottom electrical connector to the top electrical connector, wherein the plurality of metal lines and vias are positioned using a shortest path scheme. In one embodiment, the method further includes: positioning redundant vias to further connect the plurality of power-to-ground macros to a multi-metal feature directly below the plurality of power-to-ground macros. In one embodiment, the method further includes: positioning redundant vias within the plurality of power-to-ground macros.

[0064] According to some embodiments of this disclosure, a method includes: placing a first power-to-ground macro in a layout of a redistribution structure, wherein the first power-to-ground macro extends into a plurality of upper layers of the redistribution structure; arranging a bottom electrical connector directly below the first power-to-ground macro; forming a pattern of metallic features above the bottom electrical connector and below the first power-to-ground macro; arranging a first pattern of a first via connecting the bottom electrical connector to the pattern of metallic features; and arranging a second pattern of a second via connecting the pattern of metallic features to the first power-to-ground macro. In one embodiment, forming the pattern of metallic features includes: arranging a continuous metal plate extending laterally beyond an edge of the first power-to-ground macro; and patterning the continuous metal plate to form the pattern of metallic features. In one embodiment, the patterned continuous metal plate forms the pattern of metallic features and an additional pattern of additional metallic features, wherein the pattern of the additional metallic features is surrounded by the pattern of metallic features. In one embodiment, the first power-to-ground macro is a VDD macro, and the method further includes: placing a second power-to-ground macro in the layout of the redistribution structure, wherein a pattern of additional metallic features is directly below the second power-to-ground macro, and the second power-to-ground macro is a VSS macro; and laying out a third pattern of a third via, the third pattern of the third via connecting the pattern of the additional metallic features to the second power-to-ground macro. In one embodiment, the method further includes: placing a plurality of power-to-ground macros in the layout of the redistribution structure, wherein each of the plurality of power-to-ground macros is confined in a plurality of upper layers. In one embodiment, the method further includes: laying out a metal plate in one of the plurality of upper layers, wherein the metal plate incorporates the plurality of power-to-ground macros into the power-to-ground macro.

[0065] According to some embodiments of this disclosure, a method includes: providing a layout of a redistributed structure, wherein the redistributed structure includes a plurality of upper layers and a lower layer below the upper layers; placing a plurality of power macros and a plurality of ground macros, wherein bottom portions of the plurality of power macros and the plurality of ground macros are located in the bottom layer of the plurality of upper layers; laying out a pattern of a plurality of conductive features, wherein the pattern of the plurality of conductive features overlaps with the plurality of power macros and the plurality of ground macros; and laying out vias connecting the plurality of conductive features to the plurality of power macros and the plurality of ground macros. In one embodiment, each of the plurality of power macros and the plurality of ground macros includes a top connector layer and at least two metal layers below the top connector layer. In one embodiment, the layout of the redistributed structure is part of a fan-out package. In one embodiment, the method further includes: manufacturing a package, wherein the layout of the redistributed structure is implemented in the package. In one embodiment, the plurality of power macros and the plurality of ground macros are copied from a cell library.

[0066] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0067] Example

[0068] Example 1. A semiconductor structure comprising: a device die; an encapsulant therein encapsulating the device die; a redistribution structure on and electrically connected to the device die, wherein the redistribution structure includes a bottom layer and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: a first power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; a second power-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; at least one first conductive feature in the bottom layer overlapping the first power-ground macro; and at least one second conductive feature in the bottom layer overlapping the second power-ground macro, wherein the pattern of the at least one first conductive feature is different from that of the at least one second conductive feature.

[0069] Example 2. The semiconductor structure according to Example 1, wherein the at least one first conductive feature includes a first plurality of conductive features, the at least one second conductive feature includes a second plurality of conductive features, and the first total number of the first plurality of conductive features is different from the second total number of the second plurality of conductive features.

[0070] Example 3. The semiconductor structure according to Example 1, wherein the at least one first conductive feature includes a first metal pad separated from the first power-ground macrocurrent.

[0071] Example 4. The semiconductor structure according to Example 1, wherein the top layer includes a solder region.

[0072] Example 5. The semiconductor structure according to Example 1, wherein the bottom layer is in contact with metal pads in the device die.

[0073] Example 6. The semiconductor structure according to Example 1, wherein the first power-to-ground macro and the second power-to-ground macro are both VDD macros.

[0074] Example 7. The semiconductor structure according to Example 1, wherein the first power-to-ground macro and the second power-to-ground macro are both VSS macros.

[0075] Example 8. The semiconductor structure according to Example 1, wherein the first power-to-ground macro includes a plurality of metal plates and a plurality of vias, each metal plate being in one of the plurality of upper layers, the plurality of vias being in each of the plurality of upper layers, and wherein the plurality of metal plates in the first power-to-ground macro have the same pattern, position and size as the corresponding metal plates in the plurality of metal plates in the second power-to-ground macro.

[0076] Example 9. The semiconductor structure according to Example 1, wherein the first power-to-ground macro comprises a plurality of metal plates and the edges of the plurality of metal plates are vertically aligned.

[0077] Example 10. The semiconductor structure according to Example 1, wherein the redistribution structure further includes an additional layer above the bottom layer and below the plurality of upper layers, and wherein the redistribution structure further includes metal pads located in the additional layer, and the metal pads overlap with and are electrically disconnected from the first power-ground macro.

[0078] Example 11. A semiconductor structure comprising: a redistribution structure including a bottom layer and a plurality of upper layers above the bottom layer, wherein the redistribution structure includes: a first power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a first metal pad in the bottom layer and overlapping with the first power-to-ground macro, wherein the first metal pad is electrically disconnected from the first power-to-ground macro.

[0079] Example 12. The semiconductor structure according to Example 11 further includes: a second metal pad, in the underlying layer and overlapping with the first power-ground macro, wherein the second metal pad is electrically connected to the first power-ground macro.

[0080] Example 13. The semiconductor structure according to Example 11 further includes: a device die overlapping the first power-ground macro, wherein the device die further includes a second metal pad substantially bonded to the first metal pad.

[0081] Example 14. The semiconductor structure according to Example 11 further includes: a second power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers, wherein the second power-to-ground macro is the same as the first power-to-ground macro; and a second metal pad in the bottom layer and overlapping with the second power-to-ground macro, wherein the second metal pad is electrically connected to the second power-to-ground macro.

[0082] Example 15. The semiconductor structure according to Example 14, wherein the first total number of metal pads overlapping the first power-ground macro in the underlying layer is different from the second total number of metal pads overlapping the second power-ground macro in the underlying layer.

[0083] Example 16. A method for forming a semiconductor structure, comprising: placing a device die on a carrier; encapsulating the device die in a sealant; planarizing the sealant to expose metal pads in the device die; and forming a redistribution structure on the device die and the sealant, wherein the redistribution structure includes a bottom layer in contact with the device die and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: a first power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a first metal pad in the bottom layer and overlapping the first power-to-ground macro, wherein the first metal pad is electrically disconnected from the first power-to-ground macro.

[0084] Example 17. The method according to Example 16, wherein the redistribution structure further includes: a second power-to-ground macro extending from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and a second metal pad in the bottom layer and overlapping the second power-to-ground macro, wherein the second metal pad is electrically connected to the second power-to-ground macro.

[0085] Example 18. The method according to Example 16, wherein forming the first power-ground macro includes forming a solder region in the topmost of the plurality of upper layers.

[0086] Example 19. The method according to Example 16 further includes detaching the carrier from the device die and the sealant.

[0087] Example 20. The method according to Example 16, wherein the plurality of upper layers includes four layers.

Claims

1. A semiconductor structure, comprising: Device die; An encapsulating agent is used to encapsulate the device die therein; A redistribution structure is disposed on and electrically connected to the device die, wherein the redistribution structure includes a bottom layer and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: The first power supply-ground macro extends from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; The second power supply-ground macro extends from the topmost layer of the plurality of upper layers to the bottommost layer of the plurality of upper layers; At least one first conductive feature, in the underlying layer and overlapping with the first power-to-ground macro, wherein the at least one first conductive feature includes a first metal pad electrically isolated from the first power-to-ground macro; and At least one second conductive feature, in the underlying layer and overlapping with the second power-ground macro, wherein the pattern of the at least one first conductive feature is different from that of the at least one second conductive feature.

2. The semiconductor structure according to claim 1, wherein, The at least one first conductive feature includes a first plurality of conductive features, the at least one second conductive feature includes a second plurality of conductive features, and the first total number of the first plurality of conductive features is different from the second total number of the second plurality of conductive features.

3. The semiconductor structure according to claim 1, wherein, The top layer includes the solder area.

4. The semiconductor structure according to claim 1, wherein, The bottom layer is in contact with the metal pads in the die of the device.

5. The semiconductor structure according to claim 1, wherein, Both the first power-to-ground macro and the second power-to-ground macro are VDD macros.

6. The semiconductor structure according to claim 1, wherein, Both the first power-to-ground macro and the second power-to-ground macro are VSS macros.

7. The semiconductor structure according to claim 1, wherein, The first power-to-ground macro includes a plurality of metal plates and a plurality of vias, each metal plate being in one of the plurality of upper layers, the plurality of vias being in each of the plurality of upper layers, and wherein the plurality of metal plates in the first power-to-ground macro have the same pattern, position and size as the corresponding metal plates in the plurality of metal plates in the second power-to-ground macro.

8. The semiconductor structure according to claim 1, wherein, The first power-to-ground macro includes multiple metal plates, and the edges of the multiple metal plates are vertically aligned.

9. The semiconductor structure according to claim 1, wherein, The redistribution structure further includes an additional layer above the bottom layer and below the plurality of upper layers, wherein the redistribution structure further includes metal pads located in the additional layer, and the metal pads overlap with and are electrically disconnected from the first power-ground macro.

10. A semiconductor structure comprising: A redistributed structure includes a bottom layer and multiple upper layers above the bottom layer, wherein the redistributed structure includes: A first power supply-ground macro extends from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and A first metal pad is located in the bottom layer and overlaps with the first power-ground macro, wherein the first metal pad is electrically disconnected from the first power-ground macro.

11. The structure according to claim 10, further comprising: A second metal pad is located in the bottom layer and overlaps with the first power-ground macro, wherein the second metal pad is electrically connected to the first power-ground macro.

12. The structure according to claim 10, further comprising: The device die overlaps with the first power-to-ground macro, wherein the device die also includes a second metal pad that is physically bonded to the first metal pad.

13. The structure according to claim 10, further comprising: A second power-to-ground macro extends from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers, wherein the second power-to-ground macro is identical to the first power-to-ground macro; and A second metal pad is located in the bottom layer and overlaps with the second power-ground macro, wherein the second metal pad is electrically connected to the second power-ground macro.

14. The structure according to claim 13, wherein, The first total number of metal pads in the underlying layer that overlap with the first power-ground macro is different from the second total number of metal pads in the underlying layer that overlap with the second power-ground macro.

15. A method for forming a semiconductor structure, comprising: Place the device die on the carrier; The device die is encapsulated in a sealant; Planarize the sealant to expose the metal pads in the device die; as well as A redistribution structure is formed on the device die and the sealant, wherein the redistribution structure includes a bottom layer in contact with the device die and a plurality of upper layers above the bottom layer, and wherein the redistribution structure includes: A first power supply-ground macro extends from the topmost of the plurality of upper layers to the bottommost of the plurality of upper layers; and A first metal pad is located in the bottom layer and overlaps with the first power-ground macro, wherein the first metal pad is electrically disconnected from the first power-ground macro.

16. The method according to claim 15, wherein, The redistribution structure also includes: A second power supply-ground macro extends from the topmost layer of the plurality of upper layers to the bottommost layer of the plurality of upper layers; and A second metal pad is located in the bottom layer and overlaps with the second power-ground macro, wherein the second metal pad is electrically connected to the second power-ground macro.

17. The method according to claim 15, wherein, Forming the first power-ground macro includes forming a solder region in the topmost layer of the plurality of upper layers.

18. The method of claim 15, further comprising detaching the carrier from the device die and the sealant.

19. The method according to claim 15, wherein, The multiple upper layers include four layers.

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