Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. In one embodiment, a device includes a first channel region; a second channel region; and a gate structure surrounding the first channel region and the second channel region, the gate structure including a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more specifically to semiconductor devices and methods of manufacturing thereof. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a first channel region; a second channel region; and a gate structure surrounding the first channel region and the second channel region, the gate structure comprising: a gate dielectric layer; a first p-type work function metal located on the gate dielectric layer, the first p-type work function metal comprising fluorine and aluminum; a second p-type work function metal located on the first p-type work function metal, the fluorine concentration and aluminum concentration of the second p-type work function metal being lower than the fluorine concentration and aluminum concentration of the first p-type work function metal; and a filler layer located on the second p-type work function metal.

[0005] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a channel region; an interface layer located on the channel region; a high-k gate dielectric layer located on the interface layer; a first work function adjustment layer located on the high-k gate dielectric layer, the first work function adjustment layer comprising a first p-type work function metal, aluminum in the first p-type work function metal, and fluorine in the first p-type work function metal; a second work function adjustment layer located on the first work function adjustment layer, the second work function adjustment layer comprising a second p-type work function metal, the second work function adjustment layer being free of fluorine and aluminum; an adhesion layer located on the second work function adjustment layer; and a filler layer located on the adhesion layer.

[0006] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: depositing a gate dielectric layer on a channel region; depositing a first p-type work function metal on the gate dielectric layer; performing an aluminum treatment on the first p-type work function metal; performing a fluorine treatment on the first p-type work function metal after performing the aluminum treatment; and depositing a second p-type work function metal on the first p-type work function metal after performing the fluorine treatment. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanostructured FET) is shown in a three-dimensional view according to some embodiments.

[0009] Figures 2 to 22B This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments.

[0010] Figure 23 This is a flowchart of an example method for forming a replacement gate for a nanostructured FET, according to some embodiments.

[0011] Figure 24 This is a view of a nanostructured FET according to some other embodiments.

[0012] Figures 25A to 26 This is a view of a FinFET (Fin Field-Effect Transistor) according to some embodiments.

[0013] Figure 27 and Figure 28 This is a view of a device according to some embodiments.

[0014] Figure 29 and Figure 30 This is a view of a device according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, spatially related terms (e.g., "below," "under," "down," "above," "upper," etc.) may be used herein to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover devices in use or operation in orientations other than those shown in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0017] According to various embodiments, the gate structure for the transistor is formed as a fluorine-treated work function metal (WFM) layer. For example, the fluorine treatment may include performing fluorine impregnation on the WFM layer, or it may allow fluorine to diffuse into the underlying gate dielectric (e.g., a high-k gate dielectric). An aluminum treatment is performed on the WFM layer prior to the fluorine treatment to increase its effectiveness. As a result, the flat-band voltage (V0) of the resulting transistor is improved. FB By increasing the band edge of the metal in the WFM layer, the threshold voltage of the resulting transistor can be reduced, and the device performance can be improved.

[0018] Embodiments of dies including nanostructured FETs are described in a specific context. However, various embodiments may be applied to dies including other types of transistors (e.g., FinFETs, planar transistors, etc.) in place of or in combination with nanostructured FETs.

[0019] Figure 1 Examples of nanostructured FETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1This is a 3D view; for clarity, some features of the nanostructure FET have been omitted. Nanostructure FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), etc.

[0020] The nanostructured FET includes nanostructures 66 (e.g., nanosheets, nanowires, etc.) on a substrate 50 (e.g., a semiconductor substrate) above fins 62, wherein the nanostructures 66 serve as channel regions for the nanostructured FET. The nanostructures 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 70 (e.g., shallow trench isolation (STI) regions) are disposed between adjacent fins 62, and the fins 62 may protrude above the isolation regions 70 between adjacent isolation regions 70. Although the isolation regions 70 are described / illustrated as independent of the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fins 62 is illustrated as being of a single continuous material with the substrate 50, the bottom portion of the fins 62 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 62 refers to the portion extending above the isolation regions 70 between adjacent isolation regions 70.

[0021] Gate dielectric 122 is located above the top surface of fin 62 and along the top, sidewalls, and bottom surface of nanostructure 66. Gate electrode 124 is located above gate dielectric 122. Epitaxial source / drain regions 98 are disposed on fin 62 on opposite sides of gate dielectric 122 and gate electrode 124. These epitaxial source / drain regions 98 can be shared between fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, for example, by joining these epitaxial source / drain regions 98 through epitaxial growth, or by coupling these epitaxial source / drain regions 98 to the same source / drain contact.

[0022] Figure 1 Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 124 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section B-B' is along the longitudinal axis of the nanostructure 66 and in a direction, for example, the current flow direction between the epitaxial source / drain regions 98 of the nanostructure FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 98 of the nanostructure FET. These reference cross sections are referenced in subsequent figures for clarity.

[0023] Some of the embodiments discussed herein are discussed in the context of forming nanostructured FETs using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices (e.g., planar FETs) or in FinFETs.

[0024] Figures 2 to 22B This is a view of an intermediate stage in the fabrication of a nanostructured FET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 It is a 3D view, showing the relationship with Figure 1 A similar 3D view. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20A , Figure 21A and Figure 22A It shows Figure 1 The reference section A-A' shown is different in that it shows two fins. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 20B , Figure 21B and Figure 22B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 9C and Figure 9D It shows Figure 1 The reference section C-C' shown is different in that it shows two fins.

[0025] exist Figure 2The diagram provides a substrate 50 for forming a nanostructured FET. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc.), which can be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0026] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices such as NMOS transistors, for example, n-type nanostructure FETs, and the p-type region 50P can be used to form p-type devices such as PMOS transistors, for example, p-type nanostructure FETs. The n-type region 50N can be physically independent of the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0027] The substrate 50 can be lightly doped with p-type or n-type impurities. A reverse through-hole (APT) implantation can be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, a dopant can be implanted into the substrate 50. The dopant can have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region can extend below the source / drain regions in the nanostructured FET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region can be approximately 10. 18 cm -3 To about 10 19 cm -3 Within the range.

[0028] A multilayer stack 52 is formed on the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. Each semiconductor material can be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three first semiconductor layers 54 and three second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56.

[0029] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed, and the second semiconductor layer 56 is patterned to form channel regions for the nanostructured FET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity according to the etching of the second semiconductor layer 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for the channel regions of both the n-type and p-type nanostructured FETs, such as silicon.

[0030] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanostructured FET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for a nanostructured FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be suitable for a p-type nanostructured FET, such as silicon germanium (e.g., Si...). x Ge 1-x The second semiconductor material of the second semiconductor layer 56 can be suitable for n-type nanostructure FETs, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc., where x can be in the range of 0 to 1.

[0031] Each layer of the multilayer stack 52 can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE) and deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can have a small thickness, for example, in the range of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layer 56) are formed to be thinner than other layers (e.g., the first semiconductor layer 54). For example, in an embodiment where the first semiconductor layer 54 is a sacrificial layer (or dummy layer) and the second semiconductor layer 56 is patterned to form a channel region for a nanostructured FET, the first semiconductor layer 54 can have a first thickness T1 and the second semiconductor layer 56 can have a second thickness T2, wherein the second thickness T2 is about 30% to about 60% smaller than the first thickness T1. Forming the second semiconductor layer 56 to a smaller thickness allows the channel region to be formed at a greater density.

[0032] exist Figure 3 In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form fins 62, a first nanostructure 64, and a second nanostructure 66. Fins 62 are semiconductor strips patterned in substrate 50. The first nanostructure 64 and the second nanostructure 66 respectively comprise the remainder of the first semiconductor layer 54 and the remainder of the second semiconductor layer 56. The trenches can be patterned using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0033] Fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, fins 62 and nanostructures 64, 66 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the created patterns to have spacing that is, for example, smaller than that obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can subsequently be used as masks to pattern fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on nanostructures 64, 66.

[0034] The widths of fins 62 and nanostructures 64, 66 can each range from about 8 nm to about 40 nm. In the illustrated embodiment, fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, fins 62 and nanostructures 64, 66 in one region (e.g., n-type region 50N) are wider or narrower than those in another region (e.g., p-type region 50P).

[0035] exist Figure 4 In this embodiment, an STI region 70 is formed on the substrate 50 and between adjacent fins 62. The STI region 70 is configured to surround at least a portion of the fin 62, such that nanostructures 64, 66 protrude from between adjacent STI regions 70. In the illustrated embodiment, the top surface of the STI region 70 is coplanar with the top surface of the fin 62 (within the range of process variations). In some embodiments, the top surface of the STI region 70 is higher or lower than the top surface of the fin 62. The STI region 70 separates features of adjacent devices.

[0036] The STI regions 70 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride (e.g., silicon nitride), or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process (e.g., high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof). Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although each of the STI regions 70 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64, 66. Subsequently, a filler material, such as the filler material described above, can be formed on the liner.

[0037] Then, a removal process is applied to the insulating material to remove excess insulating material on top of the nanostructures 64, 66. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back processes, combinations thereof, etc., may be utilized. In embodiments where the mask remains on the nanostructures 64, 66, the planarization process can expose or remove the mask. After the planarization process, the top surface of the insulating material is coplanar (within the process variation range) with the top surface of the mask (if present) or the nanostructures 64, 66. Thus, the top surface of the mask (if present) or the nanostructures 64, 66 is exposed through the insulating material. In the illustrated embodiment, no mask is retained on the nanostructures 64, 66. The insulating material is then recessed to form the STI region 70. The insulating material is recessed such that at least a portion of the nanostructures 64, 66 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 70 may have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof, as shown. The top surface of the STI region 70 can be formed into a flat, convex, and / or concave shape through appropriate etching. Acceptable etching processes can be used to recess the insulating material, such as material-selective etching processes (e.g., selectively etching the insulating material of the STI region 70 at a faster rate than that used for the fins 62 and nanostructures 64, 66). For example, oxide removal can be performed using diluted hydrofluoric acid (dHF).

[0038] The processes described above are merely one example of how the fins 62 and nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64, 66. The epitaxial structure may include the alternating semiconductor materials described previously, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing the epitaxial structure, the material to be epitaxially grown can be doped in situ during growth, which can avoid prior and / or subsequent implantation; however, in-situ doping and implantation doping can also be used together.

[0039] Furthermore, suitable wells (not shown separately) can be formed in the substrate 50, fins 62, and / or nanostructures 64, 66. In some embodiments, a p-type well can be formed in an n-type region 50N, and an n-type well can be formed in a p-type region 50P. In some embodiments, either a p-type well or an n-type well is formed in both the n-type region 50N and the p-type region 50P.

[0040] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be implemented using a mask such as a photoresist (not shown separately). For example, a photoresist can be formed over the fins 62, nanostructures 64, 66, and STI region 70 in the n-type region 50N. The photoresist can be patterned to expose the p-type region 50P. The photoresist can be formed using a spin-coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in the region, with a concentration of about 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0041] Before or after implantation into the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the fins 62, nanostructures 64, 66, and STI region 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurity implantation into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in the region, at a concentration of approximately 10. 13 cm -3 To about 10 14 cm -3 Within the specified range. After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0042] Following implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments of epitaxial growth of fins 62 and / or nanostructures 64, 66, the grown material can be in-situ doped during growth, which avoids implantation; however, in-situ doping and implantation doping can also be used together.

[0043] exist Figure 5In this process, a dummy dielectric layer 72 is formed on fins 62 and nanostructures 64 and 66. The dummy dielectric layer 72 can be formed from dielectric materials such as silicon oxide, silicon nitride, or combinations thereof, which can be deposited or thermally grown using acceptable techniques. A dummy gate layer 74 is formed on the dummy dielectric layer 72, and a mask layer 76 is formed on the dummy gate layer 74. The dummy gate layer 74 can be deposited on the dummy dielectric layer 72 and then planarized, for example, by CMP. The mask layer 76 can be deposited on the dummy gate layer 74. The dummy gate layer 74 can be formed from conductive or non-conductive materials, such as amorphous silicon, polysilicon, poly-SiGe, metals, metal nitrides, metal silicides, metal oxides, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 74 can be formed from one or more materials with high etch selectivity based on the etching of the insulating material (e.g., STI region 70 and / or dummy dielectric layer 72). The mask layer 76 can be formed from a dielectric material such as silicon nitride or silicon oxynitride. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the fins 62, nanostructures 64, 66, and STI region 70 such that the dummy dielectric layer 72 extends above STI region 70 between the dummy gate layer 74 and STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and nanostructures 64, 66.

[0044] exist Figure 6 In this process, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 is then transferred to dummy gate layer 74 using acceptable etching techniques to form dummy gate 84. Optionally, the pattern of mask 86 can be further transferred to dummy dielectric layer 72 using acceptable etching techniques to form dummy dielectric 82. Dummy gate 84 covers portions of nanostructures 64, 66, which will be exposed in subsequent processing to form channel regions. Specifically, dummy gate 84 extends along portions of nanostructure 66, which will be patterned to form channel regions 68. The pattern of mask 86 can be used to physically separate adjacent dummy gates 84. Furthermore, the longitudinal direction of dummy gate 84 can be substantially perpendicular to the longitudinal direction of fin 62 (within the range of process variations). Mask 86 can optionally be removed after patterning, for example, by acceptable etching techniques.

[0045] Figures 7A to 22B Various additional steps in manufacturing the embodiment device are shown. Figures 7A to 13B and Figures 20A to 22BThe characteristics of either n-type region 50N or p-type region 50P are shown. For example, the structure shown can be applied to both n-type region 50N and p-type region 50P. Differences (if any) in the structure of n-type region 50N and p-type region 50P are described in the text accompanying each figure.

[0046] exist Figure 7A and Figure 7B In this embodiment, gate spacers 90 are formed on nanostructures 64, 66, and on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 90 can be formed by conformally depositing one or more dielectric materials and subsequently etching one or more dielectric materials. Acceptable dielectric materials include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; combinations thereof, such as silicon oxynitride, silicon oxycarbonate, silicon carbonitride, or silicon carbonitride; and so on. Dielectric materials can be formed by conformal deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. In the illustrated embodiment, each gate spacer 90 includes multiple layers, such as a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-y (where x and y are in the range of 0 to 1) are formed. For example, the first spacer layer 90A may be formed of a composition of silicon carbonitride similar to or different from that of the second spacer layer 90B. Acceptable etching processes, such as dry etching, wet etching, or combinations thereof, may be performed to pattern the (one or more) dielectric materials. The etching may be anisotropic. The (one or more) dielectric materials, when etched, have portions remaining on the sidewalls of the dummy gate 84 (thus forming the gate spacer 90). After etching, the gate spacer 90 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately). As will be described in more detail later, the (one or more) dielectric materials, when etched, may also have portions remaining on the sidewalls of the fins 62 and / or nanostructures 64, 66 (thus forming fin spacers).

[0047] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation for wells previously described, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurity can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity described above, and the p-type impurity can be any p-type impurity described above. During implantation, the channel region 68 remains covered by the dummy gate 84, ensuring that the channel region 68 is essentially free of impurities implanted to form the LDD region. The impurity concentration in the LDD region can be approximately 10. 15 cm -3 To about 10 19 cm -3 Within the specified range. Annealing can be used to repair injected material damage and activate injected impurities.

[0048] Note that the previous disclosures generally describe the process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different step sequences may be used, additional spacers may be formed and removed, and so on. Furthermore, different structures and steps may be used to form n-type and p-type devices.

[0049] exist Figure 8A and Figure 8BIn the illustrated embodiment, source / drain recesses 94 are formed in nanostructures 64, 66. In this embodiment, the source / drain recesses 94 extend through nanostructures 64, 66 and into fin 62. The source / drain recesses 94 may also extend into the substrate 50. In various embodiments, the source / drain recesses 94 may extend to the top surface of the substrate 50 without etching the substrate 50; the fin 62 may be etched such that the bottom surface of the source / drain recesses 94 is set below the top surface of the STI region 70; and so on. The source / drain recesses 94 can be formed by etching nanostructures 64, 66 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process used to form the source / drain recesses 94, the gate spacer 90 and the dummy gate 84 jointly mask portions of the fin 62 and / or nanostructures 64, 66. A single etching process may be used to etch each of the nanostructures 64, 66, or multiple etching processes may be used to etch the nanostructures 64, 66. The time-controlled etching process can be used to stop etching the source / drain recess 94 after it has reached the desired depth.

[0050] Optionally, internal spacers 96 are formed on the sidewalls of the remaining portion of the first nanostructure 64 (e.g., those sidewalls exposed by the source / drain recesses 94). As will be described in more detail later, source / drain regions are then formed in the source / drain recesses 94, and the first nanostructure 64 is subsequently replaced by a corresponding gate structure. The internal spacers 96 act as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 96 can be used to substantially prevent subsequent etching processes (e.g., etching processes for the subsequent removal of the first nanostructure 64) from damaging the subsequently formed source / drain regions.

[0051] As an example of forming the internal spacer 96, the source / drain recess 94 can be extended laterally. Specifically, portions of the sidewalls of the first nanostructure 64 exposed by the source / drain recess 94 can be recessed. Although the sidewalls of the first nanostructure 64 are illustrated as straight, the sidewalls can be concave or convex. The sidewalls can be recessed by an acceptable etching process, such as an etching process selective for the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate than for the material of the second nanostructure 66). The etching can be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process can be a dry etching using a fluorine-based gas (e.g., hydrogen fluoride (HF) gas). In some embodiments, the same etching process can be performed continuously to form the source / drain recess 94 and to recess the sidewalls of the first nanostructure 64. The internal spacer 96 can then be formed by conformally forming an insulating material and subsequently etching it. The insulating material can be silicon nitride or silicon oxynitride, however any suitable material can be used, such as a low-k material with a k-value less than about 3.5. The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. Although the outer sidewalls of the internal spacer 96 are illustrated as flush with the sidewalls of the gate spacer 90, the outer sidewalls of the internal spacer 96 can extend beyond or be recessed from the sidewalls of the gate spacer 90. In other words, the internal spacer 96 can partially fill, completely fill, or overfill the sidewall recesses. Furthermore, although the sidewalls of the internal spacer 96 are illustrated as straight, the sidewalls of the internal spacer 96 can be concave or convex.

[0052] exist Figure 9A and Figure 9B In this process, epitaxial source / drain regions 98 are formed in the source / drain recesses 94. The epitaxial source / drain regions 98 are formed in the source / drain recesses 94 such that each dummy gate 84 (and its corresponding channel region 68) is disposed between corresponding adjacent pairs of epitaxial source / drain regions 98. In some embodiments, gate spacers 90 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84, and internal spacers 96 are used to separate the epitaxial source / drain regions 98 from the first nanostructure 64 by an appropriate lateral distance, such that the epitaxial source / drain regions 98 do not short-circuit with the subsequently formed gate of the resulting nanostructure FET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel regions 68, thereby improving performance.

[0053] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P. The epitaxial source / drain region 98 in the n-type region 50N is then epitaxially grown in the source / drain recess 94 in the n-type region 50N. The epitaxial source / drain region 98 can include any acceptable material suitable for an n-type nanostructure FET. For example, the epitaxial source / drain region 98 in the n-type region 50N can include a material that applies tensile strain to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 98 in the n-type region 50N can have surfaces protruding from the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have facets.

[0054] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N. The epitaxial source / drain region 98 in the p-type region 50P is then epitaxially grown in the source / drain recess 94 in the p-type region 50P. The epitaxial source / drain region 98 can include any acceptable material suitable for a p-type nanostructure FET. For example, the epitaxial source / drain region 98 in the p-type region 50P can include a material that applies compressive strain to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The surface of the epitaxial source / drain region 98 in the p-type region 50P can have a protrusion higher than the surfaces of the corresponding fins 62 and nanostructures 64, 66, and can have small facets.

[0055] Epitaxial source / drain regions 98, nanostructures 64, 66, and / or fins 62 can be implanted with dopants to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19 cm -3 To about 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any impurities previously described. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0056] As a result of the epitaxial process used to form the epitaxial source / drain region 98, the upper surface of the epitaxial source / drain region has small planes that extend laterally outward beyond the sidewalls of the fins 62 and nanostructures 64, 66. In some embodiments, such as Figure 9C As shown, these small planes cause adjacent epitaxial source / drain regions 98 to merge. In some embodiments, such as Figure 9DAs shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 98 remain separated. In the illustrated embodiment, the spacer etching for forming the gate spacer 90 is adjusted to also form fin spacers 92 on the sidewalls of fins 62 and / or nanostructures 64, 66. The fin spacers 92 are formed to cover portions of the sidewalls of fins 62 that extend above the STI region 70, thereby blocking epitaxial growth. In another embodiment, the spacer layer etching for forming the gate spacer layer 90 is adjusted not to form a fin spacer layer, so as to allow the epitaxial source / drain regions 98 to extend to the surface of the STI region 70.

[0057] The epitaxial source / drain region 98 may include one or more semiconductor material layers. For example, each epitaxial source / drain region 98 may include a liner layer 98A, a main layer 98B, and a finishing layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 98. Each of the liner layer 98A, the main layer 98B, and the finishing layer 98C may be formed of different semiconductor materials and may be doped with different dopant concentrations. In some embodiments, the dopant concentration of the liner layer 98A may be less than that of the main layer 98B, and the dopant concentration of the finishing layer 98C may be greater than that of the liner layer 98A and less than that of the main layer 98B. In an embodiment where the epitaxial source / drain region 98 includes three semiconductor material layers, a liner layer 98A may be grown in the source / drain recess 94, a main layer 98B may be grown on the liner layer 98A, and a trimming layer 98C may be grown on the main layer 98B.

[0058] exist Figure 10A and Figure 10B In this configuration, the first ILD 104 is deposited over the epitaxial source / drain region 98, the gate spacer 90, the mask 86 (if present), or the dummy gate 84. The first ILD 104 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0059] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain region 98, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84. The CESL 102 can be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which have high etch selectivity according to the etching of the first ILD 104. The CESL 102 can be formed by any suitable method, such as CVD, ALD, etc.

[0060] exist Figure 11A and Figure 11B In this process, a removal process is performed to make the top surface of the first ILD 104 flush with the top surface of the mask 86 (if present) or dummy gate 84. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84, as well as portions of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the gate spacer 90, the first ILD 104, CESL 102, and the mask 86 (if present) or dummy gate 84 are coplanar (within the process variation range). Therefore, the top surface of the mask 86 (if present) or dummy gate 84 is exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process makes the top surface of the first ILD 104 flush with the top surface of the mask 86.

[0061] exist Figure 12A and Figure 12B In the etching process, the mask 86 (if present) and the dummy gate 84 are removed to form the recess 110. A portion of the dummy dielectric 82 in the recess 110 is also removed. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 84 at a faster rate than for the first ILD 104 or the gate spacer 90. During removal, the dummy dielectric 82 may serve as an etch stop layer while the dummy gate 84 is etched. The dummy dielectric 82 is then removed. Each recess 110 exposes and / or covers a portion of the channel region 68. A portion of the second nanostructure 66 serving as the channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 98.

[0062] The remaining portion of the first nanostructure 64 is then removed to extend the recess 110. The remaining portion of the first nanostructure 64 can be removed by an acceptable etching process that selectively etches the material of the first nanostructure 64 at a faster rate than that for the material of the second nanostructure 66. The etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon-germanium and the second nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portion of the second nanostructure 66. Figures 14 to 19 As shown more clearly in the diagram (and described in more detail later), the remainder of the second nanostructure 66 may have rounded corners.

[0063] exist Figure 13A and Figure 13B In the recess 110, a gate dielectric layer 112 is formed. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers used to replace the gate, and each layer encloses all (e.g., four) sides of the second nanostructure 66.

[0064] A gate dielectric layer 112 is disposed on the sidewalls and / or top surface of the fin 62; on the top surface, sidewalls, and bottom surface of the second nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric layer 112 may also be formed on the top surface of the first ILD 104 and the gate spacer 90. The gate dielectric layer 112 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric layer 112 may include dielectric materials with a k-value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in Figure 13A and Figure 13B A single-layer gate dielectric layer 112 is shown, but as will be described in more detail later, the gate dielectric layer 112 may include an interface layer and a main layer.

[0065] The gate electrode layer 114 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although in Figure 13A and Figure 13B The diagram shows a single gate electrode layer 114, but as will be described in more detail later, the gate electrode layer 114 may include any number of work function adjustment layers, any number of adhesive layers, and filler materials.

[0066] The formation of the gate dielectric layer 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 112 in each region is formed of the same material, and the formation of the gate electrode layer 114 can occur simultaneously, such that the gate electrode layer 114 in each region is formed of the same material. In some embodiments, the gate dielectric layer 112 in each region can be formed by different processes, such that the gate dielectric layer 112 can be made of different materials and / or have different numbers of layers, and / or the gate electrode layer 114 in each region can be formed by different processes, such that the gate electrode layer 114 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions. In the following description, the gate electrode layer 114 in the n-type region 50N and the gate electrode layer 114 in the p-type region 50P are formed separately.

[0067] Figures 14 to 19 The process of forming a gate dielectric layer 112 and a gate electrode layer 114 for replacing the gate in a recess 110 of a p-type region 50P is shown. (The text also mentions a process with...) Figure 13A Features in regions similar to 50R. Figure 23 This is a flowchart of an example method 200 for forming a replacement gate layer in a p-type region 50P according to some embodiments. (In conjunction with...) Figure 23 Describe together Figures 14 to 19 The gate electrode layer 114 includes a fluorinated WFM layer. The processing involves impregnating the WFM layer in an aluminum-containing precursor and then impregnating the WFM layer in a fluorinated precursor. As a result of the fluorinated treatment, the flat-band voltage (VFB) of the resulting transistor tends to increase towards the metal band edge of the WFM layer, the threshold voltage of the resulting transistor can be reduced, and device performance can be improved. The n-type region 50N can be masked at least when the gate electrode layer 114 is formed in the p-type region 50P.

[0068] exist Figure 14 In step 202 of neutralization method 200, a gate dielectric layer 112 is deposited in the recess 110 of the p-type region 50P. The gate dielectric layer 112 can be formed by methods including molecular beam deposition (MBD), ALD, PECVD, etc. The gate dielectric layer 112 encapsulates all (e.g., four) sides of the second nanostructure 66. In the illustrated embodiment, the gate dielectric layer 112 is multilayered, including a first gate dielectric layer 112A (e.g., an interface layer) and an overlying second gate dielectric layer 112B (e.g., a high-k dielectric layer). The first gate dielectric layer 112A may be formed of silicon oxide, and the second gate dielectric layer 112B may be formed of hafnium oxide.

[0069] exist Figure 15In step 204 of method 200, a first conductive material layer 114A is conformally deposited on the gate dielectric layer 112 in the p-type region 50P. The first conductive material 114A is a p-type work function metal (PWFM), such as titanium nitride, tantalum nitride, silicon titanium nitride, tungsten nitride, molybdenum nitride, etc., which can be deposited by CVD, ALD, PECVD, PVD, etc. Therefore, the first conductive material layer 114A can be referred to as a work function adjustment layer. The thickness of the first conductive material 114A can be approximately... to approximately Within the range, a first conductive material 114A may be deposited to surround each of the second nanostructures 66. After depositing the first conductive material 114A, an opening 116 may be retained in the region 50I between the second nanostructures 66.

[0070] exist Figure 16 In step 206 of method 200, a processing step is performed on the exposed surface of the first conductive material 114A. This processing step includes an aluminum treatment 118 and a fluorine treatment 120. The fluorine treatment 120 incorporates fluorine into the first conductive material 114A and the second gate dielectric layer 112B (optionally). As will be described in more detail later, the aluminum treatment 118 increases the effectiveness of the fluorine treatment 120, such that more fluorine is incorporated into the second gate dielectric layer 112B and / or the first conductive material 114A compared to other processing steps.

[0071] In step 208 of method 200, an aluminum treatment 118 is applied to a first conductive material 114A. In some embodiments, the aluminum treatment 118 is a deposition process (e.g., ALD and CVD processes, etc.) that includes flowing an aluminum-containing precursor over the surface of the first conductive material 114A. Specifically, the aluminum treatment 118 can be performed by placing a substrate 50 in a deposition chamber and dispensing the aluminum-containing precursor into the deposition chamber. In some embodiments, the aluminum-containing precursor is an organoaluminum, such as triethylaluminum (TEA) (Al2(C2H5)6), trimethylaluminum (TMA) (Al2(CH3)6), etc. During the aluminum treatment 118, aluminum dissociates from the aluminum-containing precursor and is incorporated into the first conductive material 114A, while another group bonded to aluminum (e.g., ethyl, methyl, etc.) dissociates from the aluminum-containing precursor and is discharged from the deposition chamber. As a result of the aluminum treatment 118, the first conductive material 114A may include aluminum at a concentration ranging from about 0.5 at.% to about 25 at.%.

[0072] The aluminum treatment 118 can be performed at a temperature ranging from about 250°C to about 475°C, for example, by maintaining the deposition chamber at a temperature within this range. Performing the aluminum treatment 118 at temperatures within this range incorporates the required amount of aluminum into the first conductive material 114A to create a sufficient number of fluorine bonding sites. Performing the aluminum treatment 118 at temperatures outside this range may not incorporate the required amount of aluminum into the first conductive material 114A. When the temperature of the aluminum treatment 118 is below 250°C, the aluminum-containing precursor does not dissociate properly and a sufficient number of fluorine bonding sites are not created in the first conductive material 114A. When the temperature of the aluminum treatment 118 is above 475°C, the amount of aluminum dissociated from the aluminum-containing precursor may be too large to be precisely controlled.

[0073] The aluminum treatment 118 can be performed for a duration ranging from about 1 second to about 15 minutes, for example, by flowing an aluminum-containing precursor in a deposition chamber within this range. Performing the aluminum treatment 118 within this range incorporates the required amount of aluminum into the first conductive material 114A to create a sufficient number of fluorine-bonding sites. Performing the aluminum treatment 118 outside this range may not incorporate the required amount of aluminum into the first conductive material 114A. When the aluminum treatment 118 is performed for less than about 1 second, the number of fluorine-bonding sites 114A created in the first conductive material is insufficient. When the aluminum treatment 118 is performed for more than about 15 minutes, excess aluminum is introduced into the device, thereby undesirably altering the threshold voltage of the resulting transistor.

[0074] In some embodiments, aluminum treatment 118 is a deposition process that uses a single chemical (e.g., TEA, TMA, etc.) without using another chemical that would trigger a reduction-oxidation reaction. Therefore, aluminum treatment 118 does not deposit a continuous film on the first conductive material 114A. However, as will be described in more detail later, discrete pockets of aluminum residue can be formed on the top surface of the first conductive material 114A.

[0075] In other embodiments, residues from aluminum treatment 118 may not form on the first conductive material 114A. For example, Figure 24 An embodiment is shown in which no aluminum residue is formed. Instead, aluminum can diffuse into the first conductive material 114A.

[0076] In some embodiments, the aluminum treatment 118 does not cause aluminum to diffuse into the underlying gate dielectric layer 112, such that the underlying gate dielectric layer 112 (e.g., the second gate dielectric layer 112B) is aluminum-free. In another embodiment, the aluminum treatment 118 may further cause aluminum to diffuse into the underlying gate dielectric layer 112 (e.g., the second gate dielectric layer 112B), and aluminum may be observed in the second gate dielectric layer 112B using X-ray photoelectron spectroscopy analysis.

[0077] Fluorine readily bonds to aluminum. Incorporating aluminum into the second gate dielectric layer 112B and / or the first conductive material 114A during aluminum treatment 118 increases the number of sites to which fluorine can bond during fluorine treatment 120. Therefore, performing aluminum treatment 118 increases the effectiveness of fluorine treatment 120.

[0078] In step 210 of method 200, a fluorine treatment 120 is applied to the first conductive material 114A. In some embodiments, the fluorine treatment 120 is a deposition process (e.g., ALD and CVD processes) that includes flowing a fluorine-containing precursor over the surface of the first conductive material 114A. Specifically, the fluorine treatment 120 can be performed by placing a substrate 50 in a deposition chamber and dispensing the fluorine-containing precursor into the deposition chamber. In some embodiments, the fluorine-containing precursor is WF. x NF x TiF x TaF x HfF x And so on, where x is an integer in the range of 1 to 6. For example, the fluorinated precursor may be WF6 and / or NF3. During fluorination treatment 120, fluorine dissociates from the fluorinated precursor and is incorporated into the first conductive material 114A, bonding with aluminum previously incorporated into the first conductive material 114A. As a result of fluorination treatment 120, the first conductive material 114A may include fluorine at a concentration in the range of about 2.5 at.% to about 30 at.%.

[0079] Fluorine treatment 120 can be performed at temperatures ranging from about 250°C to about 475°C, for example, by maintaining the deposition chamber at temperatures within this range. Performing fluorine treatment 120 at temperatures within this range produces the desired changes in the first conductive material 114A and / or its underlying layer. Performing fluorine treatment 120 at temperatures outside this range may not produce the desired changes in the first conductive material 114A and / or its underlying layer. When the temperature of fluorine treatment 120 is below 250°C, the fluorinated precursor dissociates inappropriately and does not produce the desired changes in the first conductive material 114A and / or its underlying layer. When the temperature of fluorine treatment 120 is above 475°C, the amount of fluorine dissociated from the fluorinated precursor may be too large to be precisely controlled.

[0080] The fluorine treatment 120 can be performed for a duration ranging from about 1 second to about 15 minutes, for example, by allowing a fluorine-containing precursor to flow in a deposition chamber within this range. Performing the fluorine treatment 120 within this range will adjust the threshold voltage of the resulting transistor by a desired amount. Performing the fluorine treatment 120 outside this range may not adjust the threshold voltage of the resulting transistor by the desired amount. When the duration of the fluorine treatment 120 is less than about 1 second, the amount of fluorine introduced by the process may be insufficient to adjust the threshold voltage of the resulting transistor. When the fluorine treatment 120 is performed for more than about 15 minutes, excess fluorine may be introduced into the device, resulting in a capacitance equivalent thickness (CET) penalty (e.g., regrowth of the first gate dielectric layer 112A).

[0081] In some embodiments, fluorine treatment 120 is a deposition process using a single chemical (e.g., WF6, NF3, etc.) without using another chemical that would trigger a reduction-oxidation reaction. Therefore, fluorine treatment 120 does not deposit a continuous film on the first conductive material 114A. In other embodiments where the fluorine-containing precursor also includes a metal, discrete metal capsules of metal residue may be formed on the top surface of the first conductive material 114A. In embodiments where the fluorine-containing precursor used during fluorine treatment 120 is WF6, the residue may be tungsten residue formed on the first conductive material 114A. The process can therefore form residues 114B of one or more metals, including residual aluminum (e.g., unbonded aluminum) from an aluminum-containing precursor used during aluminum treatment 118 and / or residual metal (e.g., tungsten when the fluorine-containing precursor is WF6) from a fluorine-containing precursor used during fluorine treatment 120. Each capsule of residue 114B may be separate from other capsules of residue 114B and does not form a continuous film on the first conductive material 114A. Residue 114B may be formed on the exposed surface of the first conductive material 114A, including in region 50I of the gate structure between the second nanostructures 66. In some embodiments where residue 114B comprises aluminum and tungsten residues and the second gate dielectric layer 112B comprises hafnium oxide, the aluminum to hafnium ratio in region 50I may be less than about 0.1 (e.g., in the range of about 0.005 to about 0.1) or less than about 0.005, and the tungsten to hafnium ratio in region 50I may be less than about 0.1 (e.g., in the range of about 0.005 to about 0.1) or less than about 0.005. When the tungsten to hafnium ratio or the aluminum to hafnium ratio in region 50I is greater than about 0.1, the resulting device may not have the desired threshold voltage (e.g., the threshold voltage may be too high).

[0082] In other embodiments where the fluorinated precursor does not include a metal (e.g., the fluorinated precursor is NF3), no residue from the fluorine treatment 120 is formed on the first conductive material 114A. For example, Figure 24An example is shown where no metal residue is formed and the fluorinated precursor used during fluorine treatment 120 is NF3.

[0083] In some embodiments, the fluorine treatment 120 may further result in fluorine diffusion into the underlying gate dielectric layer 112 (e.g., the second gate dielectric layer 112B), and fluorine may be observed in the second gate dielectric layer 112B using X-ray photoelectron spectroscopy analysis. For example, in embodiments where the second gate dielectric layer 112B comprises hafnium oxide, as a result of the fluorine treatment 120, the fluorine to hafnium ratio in region 50I (e.g., in the second gate dielectric layer 112B) may be in the range of about 0.015 to about 0.2. When the fluorine to hafnium ratio in region 50I is less than about 0.015, the amount of fluorine may be insufficient to adjust the threshold voltage of the resulting transistor. When the fluorine to hafnium ratio in region 50I is greater than about 0.2, excess fluorine may have been introduced into the second gate dielectric layer 112B, resulting in CET penalty (e.g., regrowth of the first gate dielectric layer 112A). As a result of the fluorine treatment 120, the second gate dielectric layer 112B may include fluorine in a concentration ranging from about 2.5 at.% to about 30 at.%.

[0084] As described above, incorporating aluminum into the first conductive material 114A during aluminum treatment 118 increases the number of sites to which fluorine can bond during fluorine treatment 120. Furthermore, Al-F bonds are more stable than Ti-F bonds, therefore the amount of fluorine incorporated into the first conductive material 114A remains more stable and decreases less over time compared to other treatment processes. For example, in experimental data, the embodiment treatment applying TEA impregnation prior to WF6 impregnation increased the fluorine concentration of the first conductive material 114A by up to 10.8 at.%, allowing a positive effective work function shift greater than approximately 50 mV.

[0085] In some embodiments, aluminum treatment 118 and fluorine treatment 120 are performed in situ (e.g., in the same deposition chamber) without disrupting the vacuum in the deposition chamber between aluminum treatment 118 and fluorine treatment 120. For example, performing the process may include: placing substrate 50 in the deposition chamber; allowing an aluminum-containing precursor to flow into the deposition chamber (thus performing aluminum treatment 118); removing the aluminum-containing precursor from the deposition chamber; allowing a fluorine-containing precursor to flow into the deposition chamber (thus performing fluorine treatment 120); removing the fluorine-containing precursor from the deposition chamber; and removing substrate 50 from the deposition chamber. In various embodiments, aluminum treatment 118 and fluorine treatment 120 are performed at the same temperature and for the same duration; aluminum treatment 118 and fluorine treatment 120 are performed at the same temperature but for different durations; aluminum treatment 118 and fluorine treatment 120 are performed at different temperatures but for the same duration; or aluminum treatment 118 and fluorine treatment 120 are performed at different temperatures but for different durations.

[0086] Therefore, as described above, a fluorinated WFM layer (e.g., a first conductive material 114A) is formed in various embodiments, and during the formation of the fluorinated WFM layer, fluorine can diffuse into the underlying gate dielectric layer 112 (e.g., a second gate dielectric layer 112B). As a result, the flat-band voltage (VFB) of the resulting transistor can tend to increase towards the band edge of the metal of the WFM layer, the threshold voltage of the resulting device can be reduced, and the device performance can be improved. For example, in experimental data, the fluorinated treatment in the embodiment with WF6 impregnation resulted in a positive effective work function shift of approximately 15 mV to approximately 130 mV on the metal oxide semiconductor capacitor after gas annealing.

[0087] exist Figure 17 In step 212 of method 200, a layer of the second conductive material 114C is conformally deposited on the residue 114B (if present) and / or the first conductive material 114A. The second conductive material 114C is a p-type work function metal (PWFM), such as titanium nitride, tantalum nitride, silicon titanium nitride, tungsten nitride, molybdenum nitride, etc., which can be deposited by CVD, ALD, PECVD, PVD, etc. Therefore, the layer of the second conductive material 114C can be referred to as a work function adjustment layer. The thickness of the second conductive material 114C can be approximately... to approximately Within the range. Because the second conductive material 114C is deposited after the aluminum treatment 118 and the fluorine treatment 120, the second conductive material 114C may be free of fluorine and aluminum, or at least may have a lower concentration of fluorine and aluminum than the first conductive material 114A.

[0088] In some embodiments, the first conductive material 114A is different from the second conductive material 114C. For example, the first conductive material 114A may be titanium nitride, and the second conductive material 114C may be tantalum nitride. In some embodiments, the first conductive material 114A and the second conductive material 114C may be the same. For example, both the first conductive material 114A and the second conductive material 114C may be titanium nitride.

[0089] The second conductive material 114C can fill the remaining portion of region 50I between the second nanostructures 66 (e.g., fill the opening 116, see...). Figure 15 and Figure 16 For example, the second conductive material 114C may be deposited on the first conductive material 114A until they merge and bond together, and in some embodiments, the interface 114I may be formed by contacting a first portion of the second conductive material 114C (e.g., a portion of the second conductive material 114C surrounding a portion of the second nanostructure 66) in region 50I with a second portion of the second conductive material 114C (e.g., a portion of the second conductive material 114C surrounding an adjacent portion of an adjacent second nanostructure 66).

[0090] exist Figure 18 In step 214 of method 200, the remaining portion of the gate electrode layer 114 is deposited in the p-type region 50P to fill the remaining portion of the recess 110. Specifically, a fill layer 114E is deposited on the second conductive material 114C. Optionally, an adhesion layer 114D is formed between the fill layer 114E and the second conductive material 114C. After formation, the gate electrode layer 114 in the p-type region 50P includes a first conductive material 114A, a residue 114B (if present), a second conductive material 114C, an adhesion layer 114D, and a fill layer 114E.

[0091] The adhesion layer 114D can be conformally deposited on the second conductive material 114C. The adhesion layer 114D can be formed of conductive materials, such as titanium nitride, tantalum nitride, etc., which can be deposited by CVD, ALD, PECVD, PVD, etc. The adhesion layer 114D can be alternatively referred to as the adhesive layer, and improves the adhesion between the second conductive material 114C and the filler layer 114E.

[0092] A filler layer 114E is deposited on top of the adhesion layer 114D. In some embodiments, the filler layer 114E may be formed of a conductive material, such as cobalt, ruthenium, aluminum, tungsten, or combinations thereof, which may be deposited by CVD, ALD, PECVD, PVD, etc. In the p-type region 50P, the filler layer 114E fills the remaining portion of the recess 110.

[0093] In the p-type region 50P, the gate dielectric layer 112 (e.g., a first gate dielectric layer 112A and a second gate dielectric layer 112B) and the gate electrode layer 114 (e.g., a first conductive material 114A, a residue 114B (if present), a second conductive material 114C, an adhesion layer 114D, and a filler layer 114E) can all be formed on the top surface, sidewalls, and bottom surface of the second nanostructure 66. The residue 114B can be formed at the interface between the first conductive material 114A and the second conductive material 114C, and the metal element of the residue 114B can be different from the metal element of the first conductive material 114A and / or the metal element of the second conductive material 114C.

[0094] Figure 19 A gate dielectric layer 112 and a gate electrode layer 114 for replacing the gate are shown, formed in a recess 110 in an n-type region 50N. Figure 13AFeatures in regions similar to region 50R are shown. In some embodiments, gate dielectric layers 112 in both n-type region 50N and p-type region 50P can be formed simultaneously. Furthermore, at least a portion of the gate electrode layer 114 in n-type region 50N can be formed before or after the formation of the gate electrode layer 114 in p-type region 50P (see [link to documentation]). Figures 14 to 18 Furthermore, at least a portion of the gate electrode layer 114 in the n-type region 50N can be formed when the p-type region 50P is masked. Therefore, the gate electrode layer 114 in the n-type region 50N can include a material different from the gate electrode layer 114 in the p-type region 50P. For example, the gate electrode layer 114 in the n-type region 50N can include a third conductive material layer 114F. The third conductive material 114F is an n-type work function metal (NWFM), such as aluminum titanium, aluminum titanium carbide, aluminum tantalum, tantalum carbide, combinations thereof, etc., which can be deposited by CVD, ALD, PECVD, PVD, etc. Therefore, the third conductive material layer 114F can be referred to as a work function adjustment layer. Because the third conductive material 114F is deposited after aluminum treatment 118 and fluorine treatment 120, the third conductive material 114F can be free of fluorine and aluminum, or at least can have a lower fluorine and aluminum concentration than the first conductive material 114A. The gate electrode layer 114 in the n-type region 50N may further include an adhesion layer 114D and a fill layer 114E. The adhesion layer 114D in the n-type region 50N may have the same (or different) material composition as the adhesion layer 114D in the p-type region 50P and may (or may not) be deposited simultaneously with the adhesion layer 114D in the p-type region 50P. The fill layer 114E in the n-type region 50N may have the same (or different) material composition as the fill layer 114E in the p-type region 50P and may (or may not) be deposited simultaneously with the fill layer 114E in the p-type region 50P.

[0095] In some embodiments, the third conductive material 114F is different from the first conductive material 114A and the second conductive material 114C. For example, the first conductive material 114A and the second conductive material 114C can both be titanium nitride or tantalum nitride, while the third conductive material 114F is aluminum nitride.

[0096] exist Figure 20A and Figure 20BIn this process, a removal process is performed to remove excess material from the gate dielectric layer 112 and the gate electrode layer 114, which lie above the top surfaces of the first ILD 104 and the gate spacer 90, thereby forming the gate dielectric layer 122 and the gate electrode 124. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., may be utilized. When planarization is performed, the gate dielectric layer 112 has a portion remaining in the recess 110 (thus forming the gate dielectric 122). When planarization is performed, the gate electrode layer 114 has a portion remaining in the recess 110 (thus forming the gate electrode 124). Gate spacer 90; CESL 102; first ILD 104; gate dielectric 122 (e.g., first gate dielectric layer 112A and second gate dielectric layer 112B, see Figure 18 ); and gate electrode 124 (e.g., first conductive material 114A, second conductive material 114C, adhesive layer 114D, filler layer 114E and third conductive material 114F, see Figure 18 and Figure 19 The top surfaces of the gate dielectric 122 and gate electrode 124 are coplanar (within the range of process variations). The gate dielectric 122 and gate electrode 124 form the replacement gate of the resulting nanostructure FET. Each pair of corresponding gate dielectric 122 and gate electrode 124 may be collectively referred to as a “gate structure”. Each gate structure extends along the top surface, sidewalls and bottom surface of the channel region 68 of the second nanostructure 66.

[0097] exist Figure 21A and Figure 21B In this configuration, the second ILD 134 is deposited over the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 134 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD.

[0098] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. The ESL 132 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which have high etch selectivity according to the etching of the second ILD 134.

[0099] exist Figure 22A and Figure 22BIn this configuration, a gate contact 142 and a source / drain contact 144 are formed to contact the gate electrode 124 and the epitaxial source / drain region 98, respectively. The gate contact 142 is physically and electrically coupled to the gate electrode 124, and the source / drain contact 144 is physically and electrically coupled to the epitaxial source / drain region 98.

[0100] As an example of forming the gate contact 142 and the source / drain contact 144, the opening of the gate contact 142 is formed through the second ILD 134 and ESL 132, and the opening of the source / drain contact 144 is formed through the second ILD 134, ESL 132, the first ILD 104, and CESL 102. Acceptable photolithography and etching techniques can be used to form the openings. A liner (not shown separately), such as a diffusion barrier layer or an adhesion layer, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., CMP) can be performed to remove excess material from the surface of the second ILD 134. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 in the openings. The gate contact 142 and the source / drain contact 144 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 142 and the source / drain contact 144 can be formed in different cross sections to avoid short circuits.

[0101] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 98 and the source / drain contact 144. The metal-semiconductor alloy region 146 may be: a silicide region formed of metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon-germanide silicon region formed of both metal silicides and metal germanides, etc. The metal-semiconductor alloy region 146 can be formed before one or more materials of the source / drain contact 144 by depositing metal in the opening of the source / drain contact 144 and then performing a thermal annealing process. The metal may be any metal capable of reacting with the semiconductor material of the epitaxial source / drain region 98 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metal can be deposited using deposition processes (e.g., ALD, CVD, PVD, etc.). Following a thermal annealing process, a cleaning process (e.g., wet cleaning) can be performed to remove any residual metal from the openings of the source / drain contact 144, for example, from the surface of the metal-semiconductor alloy region 146. One or more materials of the source / drain contact 144 can then be formed on the metal-semiconductor alloy region 146.

[0102] Figure 24 This is a view of a nanostructured FET according to some other embodiments. This embodiment is related to... Figure 18 The embodiments described are similar, except that no residue 114B is formed between the first conductive material 114A and the second conductive material 114C. This is because all the aluminum in the aluminum-containing precursor used during aluminum treatment 118 is bonded to fluorine during fluorine treatment 120 (see...). Figure 16 This can be achieved when the fluorinated precursor used during fluorination 120 does not contain metal. For example, in embodiments where the fluorinated precursor is NF3 and all aluminum is bonded to fluorine, no residue 114B may be formed.

[0103] As described above, some embodiments are considered for use in planar devices such as planar FETs or fin field-effect transistors (FinFETs). Figures 25A to 26 This is a view of a FinFET according to some embodiments. Figure 25A and Figure 25B Showing with Figure 22A and Figure 22B Similar views, and Figure 26 Showing with Figure 18A similar view, except that it is a FinFET instead of a nanostructure FET. In the illustrated embodiment, fin 62 includes a channel region 68, and a gate structure extends along the sidewalls and top surface of fin 62. Figure 26 One embodiment is shown in which the gate structure includes residue 114B, but residue 114B can be configured similarly to previously targeted... Figure 24 Similar methods described have been omitted.

[0104] Some embodiments consider omitting a specific work function adjustment layer. Figure 27 and Figure 28 This is a view of a device according to some embodiments. Figure 27 With Figure 18 A similar view shows a nanostructured FET, and Figure 28 With Figure 26 A similar view illustrates the FinFET. In these embodiments, a first conductive material 114A is processed, but the second conductive material 114C is omitted. Manufacturing complexity can be reduced by eliminating the second conductive material 114C.

[0105] Some embodiments consider fluorine treatment of other work function adjustment layers. Figure 29 and Figure 30 This is a view of a device according to some embodiments. Figure 29 With Figure 18 A similar view shows a nanostructured FET, and Figure 30 With Figure 26 A similar view illustrates a FinFET. In these embodiments, both a first conductive material 114A and a second conductive material 114C are included, but the second conductive material 114C is treated instead of the first conductive material 114A. Therefore, residue 114B can form on the second conductive material 114C instead of the first conductive material 114A. Treating the second conductive material 114C instead of the first conductive material 114A allows for the formation of devices with other desired threshold voltages.

[0106] The embodiments achieve various advantages. A fluorine treatment 120 is performed to form a gate stack with a fluorine-treated WFM layer. For example, the fluorine treatment may include performing fluorine impregnation on the WFM layer, or it may allow fluorine to diffuse into the underlying gate dielectric (e.g., a high-k gate dielectric). An aluminum treatment 118 is performed to increase the effectiveness of the fluorine treatment 120, allowing more fluorine to be incorporated into the WFM layer. As a result, the flat-band voltage of the resulting transistor can tend to increase towards the band edge of the metal of the WFM layer, the threshold voltage of the resulting transistor can be reduced, and device performance can be improved.

[0107] In one embodiment, a device includes: a first channel region; a second channel region; and a gate structure surrounding the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal located on the gate dielectric layer, the first p-type work function metal comprising fluorine and aluminum; a second p-type work function metal located on the first p-type work function metal, the fluorine and aluminum concentrations of the second p-type work function metal being lower than the fluorine and aluminum concentrations of the first p-type work function metal; and a filler layer located on the second p-type work function metal. In some embodiments of the device, a first region of the gate structure is disposed between the first channel region and the second channel region, and the fluorine to aluminum ratio in the first region of the gate structure is in the range of 0.005 to 0.1. In some embodiments of the device, the gate structure further includes: a metal residue located at the interface between the first p-type work function metal and the second p-type work function metal, the metal residue comprising aluminum and tungsten. In some embodiments of the device, a first region of the gate structure is disposed between the first channel region and the second channel region, and the fluorine to tungsten ratio in the first region of the gate structure is in the range of 0.005 to 0.1. In some embodiments of the device, the gate dielectric layer comprises fluorine and hafnium. In some embodiments of the device, a first region of the gate structure is disposed between the first channel region and the second channel region, and the fluorine to hafnium ratio in the first region of the gate structure is in the range of 0.015 to 0.2.

[0108] In one embodiment, a device includes: a channel region; an interface layer located on the channel region; a high-k gate dielectric layer located on the interface layer; a first work function adjustment layer located on the high-k gate dielectric layer, the first work function adjustment layer comprising a first p-type work function metal, aluminum in the first p-type work function metal, and fluorine in the first p-type work function metal; a second work function adjustment layer located on the first work function adjustment layer, the second work function adjustment layer comprising a second p-type work function metal, the second work function adjustment layer being free of fluorine and aluminum; an adhesion layer located on the second work function adjustment layer; and a filler layer located on the adhesion layer. In some embodiments of the device, the high-k gate dielectric layer comprises fluorine and hafnium, and the high-k gate dielectric layer is free of aluminum. In some embodiments of the device, the first work function adjustment layer and the second work function adjustment layer are titanium nitride. In some embodiments of the device, the first work function adjustment layer is titanium nitride and the second work function adjustment layer is tantalum nitride.

[0109] In one embodiment, a method includes: depositing a gate dielectric layer on a channel region; depositing a first p-type work function metal on the gate dielectric layer; performing an aluminum treatment on the first p-type work function metal; performing a fluorine treatment on the first p-type work function metal after performing the aluminum treatment; and depositing a second p-type work function metal on the first p-type work function metal after performing the fluorine treatment. In some embodiments of the method, the aluminum treatment incorporates aluminum into the first p-type work function metal, and the fluorine treatment incorporates fluorine into the first p-type work function metal, wherein the fluorine incorporated during the fluorine treatment is bonded to the aluminum incorporated during the aluminum treatment. In some embodiments of the method, the aluminum treatment represents a first deposition process exposing the surface of the first p-type work function metal to an aluminum-containing precursor, and the fluorine treatment represents a second deposition process exposing the surface of the first p-type work function metal to a fluorine-containing precursor. In some embodiments of the method, the fluorine-containing precursor is WF. x NF x TiF x TaF x or HfF x And where x is an integer in the range of 1 to 6. In some embodiments of the method, the aluminum-containing precursor is triethylaluminum or trimethylaluminum. In some embodiments of the method, the first deposition process and the second deposition process are performed in the same deposition chamber. In some embodiments of the method, the first deposition process and the second deposition process are performed at the same temperature. In some embodiments of the method, the first deposition process and the second deposition process are performed at different temperatures. In some embodiments of the method, no aluminum diffuses into the gate dielectric layer during the aluminum treatment. In some embodiments of the method, fluorine diffuses into the gate dielectric layer during the fluorine treatment.

[0110] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0111] Example 1. A semiconductor device, comprising:

[0112] First trench area;

[0113] The second trench area; and

[0114] A gate structure, surrounding the first channel region and the second channel region, the gate structure comprising:

[0115] Gate dielectric layer;

[0116] A first p-type work function metal is located on the gate dielectric layer, and the first p-type work function metal includes fluorine and aluminum;

[0117] A second p-type work function metal is located on top of the first p-type work function metal, wherein the fluorine and aluminum concentrations of the second p-type work function metal are lower than those of the first p-type work function metal; and

[0118] A filling layer is located on the second p-type work function metal.

[0119] Example 2. The device according to Example 1, wherein a first region of the gate structure is disposed between the first channel region and the second channel region, and wherein the ratio of fluorine to aluminum in the first region of the gate structure is in the range of 0.005 to 0.1.

[0120] Example 3. The device according to Example 1, wherein the gate structure further includes:

[0121] Metal residues are located at the interface between the first p-type work function metal and the second p-type work function metal, and the metal residues include aluminum and tungsten.

[0122] Example 4. The device according to Example 3, wherein a first region of the gate structure is disposed between the first channel region and the second channel region, and wherein the ratio of fluorine to tungsten in the first region of the gate structure is in the range of 0.005 to 0.1.

[0123] Example 5. The device according to Example 1, wherein the gate dielectric layer comprises fluorine and hafnium.

[0124] Example 6. The device according to Example 5, wherein a first region of the gate structure is disposed between the first channel region and the second channel region, and wherein the ratio of fluorine to hafnium in the first region of the gate structure is in the range of 0.015 to 0.2.

[0125] Example 7. A semiconductor device comprising:

[0126] Channel area;

[0127] An interface layer is located on the channel region;

[0128] A high-k gate dielectric layer is located on the interface layer;

[0129] The first work function adjustment layer is located on the high-k gate dielectric layer, and the first work function adjustment layer includes a first p-type work function metal, aluminum in the first p-type work function metal, and fluorine in the first p-type work function metal;

[0130] The second work function adjustment layer is located on the first work function adjustment layer. The second work function adjustment layer includes a second p-type work function metal and does not contain fluorine or aluminum.

[0131] An adhesion layer is located on the second work function adjustment layer; and

[0132] A filler layer is located on the adhesive layer.

[0133] Example 8. The device according to Example 7, wherein the high-k gate dielectric layer comprises fluorine and hafnium, and the high-k gate dielectric layer does not contain aluminum.

[0134] Example 9. The device according to Example 7, wherein the first work function adjustment layer and the second work function adjustment layer are titanium nitride.

[0135] Example 10. The device according to Example 7, wherein the first work function adjustment layer is titanium nitride and the second work function adjustment layer is tantalum nitride.

[0136] Example 11. A method of manufacturing a semiconductor device, comprising:

[0137] Deposit a gate dielectric layer on the channel region;

[0138] A first p-type work function metal is deposited on the gate dielectric layer;

[0139] Aluminum treatment is performed on the first p-type work function metal;

[0140] After performing the aluminum treatment, a fluorine treatment is performed on the first p-type work function metal; and

[0141] After the fluorine treatment is performed, a second p-type work function metal is deposited on the first p-type work function metal.

[0142] Example 12. The method according to Example 11, wherein the aluminum treatment incorporates aluminum into the first p-type work function metal, wherein the fluorine treatment incorporates fluorine into the first p-type work function metal, wherein the fluorine incorporated during the fluorine treatment is bonded to the aluminum incorporated during the aluminum treatment.

[0143] Example 13. The method according to Example 11, wherein the aluminum treatment is a first deposition process that exposes the surface of the first p-type work function metal to an aluminum-containing precursor, and wherein the fluorine treatment is a second deposition process that exposes the surface of the first p-type work function metal to a fluorine-containing precursor.

[0144] Example 14. The method according to Example 13, wherein the fluorinated precursor is WFx, NFx, TiFx, TaFx or HfFx, and wherein x is an integer in the range of 1 to 6.

[0145] Example 15. The method according to Example 13, wherein the aluminum-containing precursor is triethylaluminum or trimethylaluminum.

[0146] Example 16. The method according to Example 13, wherein the first deposition process and the second deposition process are performed in the same deposition chamber.

[0147] Example 17. The method according to Example 13, wherein the first deposition process and the second deposition process are performed at the same temperature.

[0148] Example 18. The method according to Example 13, wherein the first deposition process and the second deposition process are performed at different temperatures.

[0149] Example 19. The method according to Example 11, wherein no aluminum diffuses into the gate dielectric layer during the aluminum treatment.

[0150] Example 20. The method according to Example 11, wherein fluorine diffuses into the gate dielectric layer during the fluorine treatment.

Claims

1. A semiconductor device, comprising: First trench area; Second trench area; as well as A gate structure, surrounding the first channel region and the second channel region, the gate structure comprising: Gate dielectric layer; A first p-type work function metal is located on the gate dielectric layer, and the first p-type work function metal includes fluorine and aluminum; A second p-type work function metal is located on top of the first p-type work function metal, wherein the fluorine and aluminum concentrations of the second p-type work function metal are lower than those of the first p-type work function metal; and A filling layer is located on the second p-type work function metal.

2. The semiconductor device according to claim 1, wherein, The first region of the gate structure is disposed between the first channel region and the second channel region, and wherein the ratio of fluorine to aluminum in the first region of the gate structure is in the range of 0.005 to 0.

1.

3. The semiconductor device according to claim 1, wherein, The gate structure further includes: Metal residues are located at the interface between the first p-type work function metal and the second p-type work function metal, and the metal residues include aluminum and tungsten.

4. The semiconductor device according to claim 3, wherein, The first region of the gate structure is disposed between the first channel region and the second channel region, and wherein the ratio of fluorine to tungsten in the first region of the gate structure is in the range of 0.005 to 0.

1.

5. The semiconductor device according to claim 1, wherein, The gate dielectric layer comprises fluorine and hafnium.

6. The semiconductor device according to claim 5, wherein, The first region of the gate structure is disposed between the first channel region and the second channel region, and wherein the ratio of fluorine to hafnium in the first region of the gate structure is in the range of 0.015 to 0.

2.

7. A semiconductor device, comprising: Channel area; An interface layer is located on the channel region; A high-k gate dielectric layer is located on the interface layer; The first work function adjustment layer is located on the high-k gate dielectric layer, and the first work function adjustment layer includes a first p-type work function metal, aluminum in the first p-type work function metal, and fluorine in the first p-type work function metal; The second work function adjustment layer is located on the first work function adjustment layer. The second work function adjustment layer includes a second p-type work function metal and does not contain fluorine or aluminum. An adhesion layer is located on the second work function adjustment layer; as well as A filler layer is located on the adhesive layer.

8. The semiconductor device according to claim 7, wherein, The high-k gate dielectric layer comprises fluorine and hafnium, and the high-k gate dielectric layer does not contain aluminum.

9. The semiconductor device according to claim 7, wherein, The first work function adjustment layer and the second work function adjustment layer are titanium nitride.

10. The semiconductor device according to claim 7, wherein, The first work function adjustment layer is titanium nitride and the second work function adjustment layer is tantalum nitride.

11. A method for manufacturing a semiconductor device, comprising: Deposit a gate dielectric layer on the channel region; A first p-type work function metal is deposited on the gate dielectric layer; Aluminum treatment is performed on the first p-type work function metal; After performing the aluminum treatment, a fluorine treatment is performed on the first p-type work function metal; and After the fluorine treatment is performed, a second p-type work function metal is deposited on the first p-type work function metal.

12. The method according to claim 11, wherein, The aluminum treatment incorporates aluminum into the first p-type work function metal, wherein the fluorine treatment incorporates fluorine into the first p-type work function metal, wherein the fluorine incorporated during the fluorine treatment is bonded to the aluminum incorporated during the aluminum treatment.

13. The method according to claim 11, wherein, The aluminum treatment is a first deposition process that exposes the surface of the first p-type work function metal to an aluminum-containing precursor, and the fluorine treatment is a second deposition process that exposes the surface of the first p-type work function metal to a fluorine-containing precursor.

14. The method according to claim 13, wherein, The fluorine-containing precursor is WFx, NFx, TiFx, TaFx or HfFx, where x is an integer in the range of 1 to 6.

15. The method according to claim 13, wherein, The aluminum-containing precursor is triethylaluminum or trimethylaluminum.

16. The method according to claim 13, wherein, The first deposition process and the second deposition process are performed in the same deposition chamber.

17. The method according to claim 13, wherein, The first deposition process and the second deposition process are performed at the same temperature.

18. The method according to claim 13, wherein, The first deposition process and the second deposition process are performed at different temperatures.

19. The method according to claim 11, wherein, No aluminum diffuses into the gate dielectric layer during the aluminum processing.

20. The method according to claim 11, wherein, During the fluorine treatment, fluorine diffuses into the gate dielectric layer.

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