Gate structure of semiconductor device and method of forming the same

Abstract

This application relates to gate structures for semiconductor devices and methods for forming the same. A semiconductor device and method for forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged alternately over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and more specifically to the gate structure of a semiconductor device and a method for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor device is provided, comprising: a gate stack over an active region of a substrate, wherein the gate stack includes: a gate dielectric layer; and a first work function layer over the gate dielectric layer, the first work function layer including a plurality of first layers and a plurality of second layers arranged alternately over the gate dielectric layer, the plurality of first layers including a first material, and the plurality of second layers including a second material different from the first material.

[0005] According to a second aspect of this disclosure, a semiconductor device is provided, comprising: a gate stack over an active region of a substrate, wherein the gate stack includes: a gate dielectric layer; a p-type work function layer over the gate dielectric layer, the p-type work function layer including paired layers repeated two or more times, the paired layers including a first layer and a second layer, the first layer including a first metal nitride material, and the second layer including a second metal nitride material different from the first metal nitride material; and an n-type work function layer over the p-type work function layer.

[0006] According to a third aspect of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a sacrificial gate over an active region of a substrate; removing the sacrificial gate to form a recess; and forming a replacement gate in the recess, wherein forming the replacement gate comprises: forming a gate dielectric layer in the recess; and forming a first work function layer over the gate dielectric layer, wherein forming the first work function layer comprises forming paired layers two or more times, the paired layers comprising a first layer and a second layer, the first layer comprising a first metal nitride material, and the second layer comprising a second metal nitride material different from the first metal nitride material. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1-11 and Figures 15-18 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device according to some embodiments.

[0009] Figure 12 This is a flowchart illustrating a method for forming a function layer according to some embodiments.

[0010] Figure 13 This is a flowchart illustrating an atomic layer deposition process according to some embodiments.

[0011] Figure 14 This is a flowchart illustrating an atomic layer deposition process according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to facilitate the description of the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0014] Embodiments will be described with reference to a specific context (i.e., the gate structure of a semiconductor device and methods of its formation). The various embodiments presented herein are discussed in the context of planar field-effect transistor (FET) devices formed using a gate-last process. In other embodiments, a gate-first process may be used. However, various embodiments can be applied to dies including other types of transistors (e.g., FinFETs, gate-all-around (GAA) transistors, etc.) as alternatives to or in combination with planar FETs. The various embodiments discussed herein allow for the formation of gate structures including a work function layer whose work function can be adjusted according to the design requirements of the semiconductor device. In some embodiments, the work function layer comprises two different metal nitride materials (e.g., a nitride of a first metal and a nitride of a second metal different from the first metal) disposed in a plurality of alternating layers. The work function of the work function layer can be adjusted by adjusting the ratio of the first metal to the second metal within the work function layer.

[0015] Figures 1-11 and Figures 15-18 This is a cross-sectional view of an intermediate stage in the manufacturing of a semiconductor device 100 according to some embodiments. Figure 1A substrate 102 is provided. The substrate 102 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 102 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate that is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 102 includes silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0016] Substrate 102 has region 100N and region 100P. Region 100N can be used to form an n-type device, such as an n-type transistor. Region 100P can be used to form a p-type device, such as a p-type transistor. Region 100N can be physically separated from region 100P (as shown by separator 104), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between region 100N and region 100P.

[0017] Substrate 102 includes an active region 106. In some embodiments, when the semiconductor device 100 is a planar FET device, the active region 106 includes an upper planar portion of the substrate 102. In other embodiments, when the semiconductor device 100 is a planar FET device, the active region 106 is a semiconductor layer formed on the substrate 102, such that the semiconductor layer and the substrate 102 comprise different semiconductor materials. In some embodiments, when the semiconductor device 100 is a FinFET device, the active region 106 includes one or more semiconductor strips. Semiconductor strips may also be referred to as fins. In some embodiments, the semiconductor strips and the substrate 102 comprise the same semiconductor material. In other embodiments, the semiconductor strips and the substrate 102 comprise different semiconductor materials. In some embodiments, when the semiconductor device 100 is a GAA device, the active region 106 includes one or more nanostructures. Nanostructures may include nanosheets, nanowires, etc. In some embodiments, the nanostructures and the substrate 102 comprise the same semiconductor material. In other embodiments, the nanostructures and the substrate 102 comprise different semiconductor materials.

[0018] exist Figure 2In this process, an isolation region 108 is formed in a substrate 102. In some embodiments, the process steps for forming the isolation region 108 include: forming a plurality of recesses in the substrate 102, and depositing an insulating material in the recesses and on the substrate 102. The recesses can be formed by patterning the substrate 102 using appropriate photolithography and etching processes. The etching process can include, for example, a dry etching process. The etching process can be anisotropic.

[0019] The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert the deposited material into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) can be formed first along the sidewalls and bottom of the recess and over the active region 106 of the substrate 102. Then, a filler material (e.g., those discussed above) can be formed over the liner.

[0020] In some embodiments, a removal process is applied to the insulating material to remove excess portions of the overfilled recesses. The remaining portion of the insulating material forms the isolation region 108. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, or combinations thereof, may be utilized. The planarization process exposes the top surface of the active region 106 of the substrate 102 such that the top surface of the active region 106 and the top surface of the isolation region 108 are substantially coplanar or flush after the planarization process is completed (within process variations of the planarization process).

[0021] Further in Figure 2In this process, suitable wells (not shown) can be formed in the active region 106 of the substrate 102. In some embodiments, a P-well can be formed in region 100N and an N-well can be formed in region 100P. In some embodiments, either a P-well or an N-well is formed in both region 100N and region 100P. In embodiments with different well types, different implantation steps for regions 100N and 100P can be implemented using photoresist or other masks (not shown). For example, a first photoresist can be formed on the active region 106 and the isolation region 108 of the substrate 102 in both regions 100N and 100P. The first photoresist is patterned to expose region 100P. The first photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the first photoresist is patterned, n-type impurity implantation is performed in region 100P, while the remaining portion of the first photoresist serves as a mask to substantially prevent n-type impurities from being implanted into region 100N. The n-type impurity can be phosphorus, arsenic, antimony, or combinations thereof. After implantation, the first photoresist is removed, for example, by an acceptable ashing process followed by a wet cleaning process.

[0022] After implantation into region 100P, a second photoresist is formed on the active region 106 and isolation region 108 of substrate 102 in both regions 100P and 100N. The second photoresist is patterned to expose region 100N. The second photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the second photoresist is patterned, p-type impurity implantation can be performed in region 100N, while the remaining portion of the second photoresist serves as a mask to substantially prevent p-type impurities from being implanted into region 100P. The p-type impurity can be boron, BF2, indium, combinations thereof, etc. After implantation, the second photoresist can be removed, for example, by an acceptable ashing process followed by a wet cleaning process. After implantation into regions 100N and 100P, an annealing process can be performed to activate the implanted p-type and / or n-type impurities.

[0023] exist Figure 3In this process, a dummy dielectric layer 110 is formed over the active region 106 and the isolation region 108 of the substrate 102. The dummy dielectric layer 110 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 112 is formed over the dummy dielectric layer 110, and a mask layer 114 is formed over the dummy gate layer 112. The dummy gate layer 112 can be deposited over the dummy dielectric layer 110 and then planarized using, for example, a CMP process. The mask layer 114 can be deposited over the dummy gate layer 112. The dummy gate layer 112 can be a conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 112 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art for depositing conductive materials. The dummy gate layer 112 may be made of a material having higher etch selectivity than that of the isolation region 108. The mask layer 114 may include, for example, one or more layers of silicon oxide, SiN, SiON, or combinations thereof. In some embodiments, the mask layer 114 may include a silicon nitride layer and a silicon oxide layer on top of the silicon nitride layer. In some embodiments, a single dummy dielectric layer 110, a single dummy gate layer 112, and a single mask layer 114 are formed across both region 100N and region 100P. In other embodiments, a first dummy dielectric layer, a first dummy gate layer, and a first mask layer are formed in region 100N, and a second dummy dielectric layer, a second dummy gate layer, and a second mask layer are formed in region 100P, such that the first and second dummy dielectric layers comprise different materials, the first and second dummy gate layers comprise different materials, and the first and second mask layers comprise different materials.

[0024] exist Figure 4 In this process, acceptable photolithography and etching techniques can be used to process mask layer 114 (see...). Figure 3 The mask 118 is patterned to form a mask 118. In some embodiments, the etching technique may include one or more anisotropic etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, etc. The pattern of the mask 118 can then be transferred to the dummy gate layer 112 (see [link to documentation]). Figure 3A dummy gate 116N is formed in region 100N and a dummy gate 116P is formed in region 100P. In some embodiments, the pattern of mask 118 can also be transferred to the dummy dielectric layer 110 by an acceptable etching technique. As described in more detail below, dummy gates 116N and 116P are sacrificial gates and are subsequently replaced by replacement gates. Therefore, dummy gates 116N and 116P can also be referred to as sacrificial gates. In other embodiments, some of dummy gates 116N and 116P are not replaced and remain in the final structure of semiconductor device 100.

[0025] Further in Figure 4 In this process, a gate sealing spacer 120N can be formed on the exposed surfaces of the dummy gate 116N and the corresponding mask 118, and a gate sealing spacer 120P can be formed on the exposed surfaces of the dummy gate 116P and the corresponding mask 118. Thermal oxidation or deposition followed by anisotropic etching can form the gate sealing spacers 120N and 120P. The gate sealing spacers 120N and 120P can include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, combinations thereof, etc. In some embodiments, the gate sealing spacers 120N and 120P comprise the same material. In other embodiments, the gate sealing spacers 120N and 120P comprise different materials. In some embodiments, the gate sealing spacers 120N and 120P have the same width. In other embodiments, the gate sealing spacers 120N and 120P have different widths.

[0026] After forming the gate sealing spacers 120N and 120P, implantation can be performed for the lightly doped source / drain (LDD) regions (not explicitly shown). In embodiments with different device types, similar to the above... Figure 2 The implantation discussed herein can involve forming a mask (e.g., photoresist) over region 100N while exposing region 100P, and implanting an impurity of an appropriate type (e.g., p-type) into the active region 106 of the substrate 102 in region 100P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over region 100P while exposing region 100N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the active region 106 of the substrate 102 in region 100N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. Annealing can be used to activate the implanted impurity.

[0027] exist Figure 5In this embodiment, a gate spacer 122N is formed on a gate sealing spacer 120N in region 100N along the sidewalls of the dummy gate 116N and the mask 118, and a gate spacer 122P is formed on a gate sealing spacer 120P in region 100P along the sidewalls of the dummy gate 116P and the mask 118. The gate spacers 122N and 122P can be formed by blanket or conformal deposition of an insulating material followed by anisotropic etching of the insulating material. The insulating material of the gate spacers 122N and 122P may include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, combinations thereof, etc. In some embodiments, each of the gate spacers 122N and 122P may include multiple layers (not shown) such that these layers comprise different materials. In some embodiments, the gate spacers 122N and 122P comprise the same material. In other embodiments, the gate spacers 122N and 122P comprise different materials. In some embodiments, gate spacers 122N and 122P have the same width. In other embodiments, gate spacers 122N and 122P have different widths.

[0028] Note that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and different step sequences can be employed (e.g., gate sealing spacers 120N and 120P can be left unetched before forming gate spacers 122N and 122P respectively, resulting in "L-shaped" gate sealing spacers; spacers can be formed and removed, etc.). Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region for an n-type device in region 100N can be formed before forming gate sealing spacer 120N, while the LDD region for a p-type device in region 100P can be formed after forming gate sealing spacer 120P.

[0029] exist Figure 6In the active regions 106 of regions 100N and 100P, epitaxial source / drain regions 124N and 124P are formed respectively to apply stress in the corresponding channel regions, thereby improving device performance. Each dummy gate 116N is disposed between adjacent pairs of epitaxial source / drain regions 124N. Each dummy gate 116P is disposed between adjacent pairs of epitaxial source / drain regions 124P. Gate spacers 122N are used to separate the epitaxial source / drain regions 124N and dummy gates 116N by an appropriate lateral distance, such that the epitaxial source / drain regions 124N do not short-circuit the gate of the subsequently formed semiconductor device 100. Gate spacers 122P are used to separate the epitaxial source / drain regions 124P and dummy gates 116P by an appropriate lateral distance, such that the epitaxial source / drain regions 124P do not short-circuit the gate of the subsequently formed semiconductor device 100.

[0030] The epitaxial source / drain region 124N in region 100N can be formed by masking region 100P and etching active region 106 to form a recess in active region 106. Then, the epitaxial source / drain region 124N is epitaxially grown in the recess. The epitaxial source / drain region 124N can include any acceptable material, such as that suitable for n-type devices. For example, if active region 106 includes silicon, the epitaxial source / drain region 124N can include a material that applies tensile strain to the channel region, such as silicon, SiC, SiCP, SiP, combinations thereof, etc. The epitaxial source / drain region 124N can have a small facet.

[0031] The epitaxial source / drain region 124P in region 100P can be formed by masking region 100N and etching active region 106 to form a recess in active region 106. Then, the epitaxial source / drain region 124P is epitaxially grown in the recess. The epitaxial source / drain region 124P can include any acceptable material, such as that suitable for p-type devices. For example, if active region 106 comprises silicon, the epitaxial source / drain region 124P can include a material for applying compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, combinations thereof, etc. The epitaxial source / drain region 124P can have a facet.

[0032] The epitaxial source / drain regions 124N and 124P can be implanted with n-type and p-type dopants, respectively, to form the source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The n-type and p-type impurities used for the epitaxial source / drain regions 124N and 124P, respectively, can be any impurities discussed previously. In some embodiments, the epitaxial source / drain regions 124N and 124P can be doped in situ during growth.

[0033] exist Figure 7 In the middle, interlayer dielectric (ILD) 126 is deposited in Figure 6 The structure shown is overlaid. ILD 126 can be formed of a dielectric material and can be deposited by any suitable method (e.g., CVD, plasma-enhanced CVD (PECVD), FCVD, combinations thereof, etc.). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate-phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable method may also be used. In some embodiments, a contact etch stop layer (CESL) 124 is disposed between ILD 126 and epitaxial source / drain regions 124N and 124P, mask 118, gate spacers 122N and 122P, and isolation region 108. CESL 124 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, etc., having an etch rate different from that of the material overlaid on ILD 126.

[0034] exist Figure 8 In this process, planarization processes such as CMP can be performed to make the top surface of ILD 126 aligned with dummy gates 116N and 116P or mask 118 (see...). Figure 7 The top surfaces of the dummy gates 116N and 116P are flush with each other. In some embodiments, the planarization process may further remove the mask 118 on the dummy gates 116N and 116P, and portions of the gate sealing spacers 120N and 120P and gate spacers 122N and 122P along the sidewalls of the mask 118. After the planarization process, the top surfaces of the dummy gates 116N and 116P, the top surfaces of the gate sealing spacers 120N and 120P, the top surfaces of the gate spacers 122N and 122P, and the top surface of the ILD 126 are substantially coplanar or flush with each other (within process variations of the planarization process). Thus, the top surfaces of the dummy gates 116N and 116P are exposed through the ILD 126. In some embodiments, the mask 118 may be retained, in which case the planarization process flushes the top surface of the ILD 126 with the top surface of the mask 118.

[0035] exist Figure 9 In the middle, dummy gates 116N and 116P are set (see Figure 8 ) and mask 118 (see Figure 7The dummy dielectric layer 110 is removed in one or more etching steps, thereby forming openings 128N and 128P in regions 100N and 100P, respectively. In some embodiments, portions of the dummy dielectric layer 110 in openings 128N and 128P may also be removed. In other embodiments, only dummy gates 116N and 116P are removed, and the dummy dielectric layer 110 remains exposed through openings 128N and 128P. In some embodiments, the dummy dielectric layer 110 is removed from openings 128N and 128P in a first region of the die (e.g., a core logic region), and the dummy dielectric layer 110 remains in openings 128N and 128P in a second region of the die (e.g., an input / output region).

[0036] In some embodiments, dummy gates 116N and 116P are removed by a suitable etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gates 116N and 116P without etching ILD 126, CESL 124, gate sealing spacers 120N and 120P, and gate spacers 122N and 122P. Each opening 128N and 128P exposes a channel region of the corresponding active region 106. During removal, the dummy dielectric layer 110 may be used as an etch stop layer while the dummy gates 116N and 116P are being etched. The dummy dielectric layer 110 may then be optionally removed after the dummy gates 116N and 116P have been removed.

[0037] Figure 10 , Figure 11 and Figures 15-17 According to some embodiments, in openings 128N and 128P (see...) Figure 9 ) fabricating gate stacks 146N and 146P (see Figure 17 A cross-sectional view of the intermediate stage of ). For clarity, Figure 10 , Figure 11 and Figures 15-17 It shows Figure 9 Enlarged view of regions 130N and 130P shown. Figure 10An interface layer 132 is formed in openings 128N and 128P. The interface layer 132 may include silicon oxide and can be formed using a chemical deposition process (e.g., atomic layer deposition (ALD), CVD, etc.) or an oxidation process. In some embodiments, when the interface layer 132 is formed using a deposition process, the interface layer 132 extends along the exposed surfaces of the active region 106, the dummy dielectric layer 110, and the gate sealing spacers 120N and 120P. In some embodiments, when the interface layer 132 is formed using an oxidation process, the interface layer 132 extends along the exposed surface of the active region 106 and does not extend along the exposed surfaces of the dummy dielectric layer 110 and the gate sealing spacers 120N and 120P. In some embodiments, the thickness of the interface layer 132 is approximately... With the agreement between.

[0038] After forming the interface layer 132, a gate dielectric layer 134 is formed over the interface layer 132 in the openings 128N and 128P. In some embodiments, the gate dielectric layer 134 may include silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 134 may include a high-k dielectric material, and in these embodiments, the gate dielectric layer 134 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. In some embodiments, ALD, CVD, or a combination thereof may be used to form the gate dielectric layer 134. In some embodiments, the thickness of the gate dielectric layer 134 is approximately With the agreement between.

[0039] Further in Figure 10 In this configuration, a work function layer 136 is formed above the gate dielectric layer 134 in openings 128N and 128P. The work function layer 136 may also be referred to as a p-type work function layer. In some embodiments, the work function layer 136 includes, for example... Figure 11 The multiple layers 136A and 136B shown, Figure 11 It shows Figure 10 The enlarged portion of region 138 is shown. In some embodiments, the work function layer 136 includes a plurality of first layers 136A and a plurality of second layers 136B arranged in an alternating manner. In some embodiments, the top layer of the plurality of first layers 136A is the top layer of the work function layer 136. In other embodiments, the top layer of the plurality of second layers 136B is the top layer of the work function layer 136.

[0040] In some embodiments, a plurality of first layers 136A comprise TiN, and a plurality of second layers 136B comprise TaN. In other embodiments, a plurality of first layers 136A comprise TaN, and a plurality of second layers 136B comprise TiN. In some embodiments, the plurality of first layers 136A have the same width. In other embodiments, the plurality of first layers 136A have different widths. In some embodiments, the plurality of second layers 136B have the same width. In other embodiments, the plurality of second layers 136B have different widths. In some embodiments, the plurality of first layers 136A are included between layers 1 and 3. In some embodiments, the plurality of second layers 136B are included between layers 1 and 3. In some embodiments, the plurality of first layers 136A have the same width as the plurality of second layers 136B. In other embodiments, the plurality of first layers 136A have a different width than the plurality of second layers 136B. In some embodiments, each of the plurality of first layers 136A has a width of approximately With the agreement The thickness T1 between them. In some embodiments, each of the plurality of second layers 136B has a thickness T1 between them. With the agreement The thickness T2 is between [thickness T1 and thickness T2]. In some embodiments, the ratio of thickness T1 to thickness T2 (T1 / T2) is between about 0.3 and about 3. In some embodiments, the work function layer 136 has a thickness T2 between [thickness T1 and thickness T2]. With the agreement The thickness T3 between them.

[0041] In some embodiments, the ratio of Ti in the work function layer 136 is between about 7 at% and about 40 at%. In some embodiments, the ratio of Ta in the work function layer 136 is between about 7 at% and about 40 at%. In some embodiments, the ratio of Ta to Ti in the work function layer 136 can be adjusted from about 0.5 to about 0.95. In some embodiments, the ratio of Ta to Ti in the work function layer 136 can be adjusted, for example, by adjusting the thickness T1 of the plurality of first layers 136A and the thickness T2 of the plurality of second layers 136B. In some embodiments, the ratio of Ta to Ti in the work function layer 136 can be adjusted, for example, by adjusting the ratio of Ti or Ta in the plurality of first layers 136A and by adjusting the ratio of Ti or Ta in the plurality of second layers 136B. By adjusting the ratio of Ta to Ti in the work function layer 136, the work function of the work function layer 136 can be adjusted. In some embodiments, a high ratio of Ta to Ti in the work function layer 136 results in a low work function. In some embodiments, a low ratio of the ratio of Ta to Ti in the work function layer 136 produces a high work function.

[0042] Figure 12 This illustrates the formation function layer 136 according to some embodiments (see [link]). Figure 10 and Figure 11 The flowchart of method 1200 is shown. Method 1200 begins with step 1202, where a first metal nitride layer (e.g., ...) is formed over the gate dielectric layer 134. Figure 10 and Figure 11 (The first of the plurality of first layers 136A shown). In step 1204, a second metal nitride layer is formed on top of the first metal nitride layer (e.g., Figure 10 and Figure 11 (The first of a plurality of second layers 136B shown). The second metal nitride layer is different from the first metal nitride layer. In some embodiments, the first metal nitride layer comprises TiN and the second metal nitride layer comprises TaN. In other embodiments, the first metal nitride layer comprises TaN and the second metal nitride layer comprises TiN. In some embodiments, steps 1202 and 1204 are performed in the same process chamber. In other embodiments, steps 1202 and 1204 are performed in different process chambers. In some embodiments, steps 1202 and 1204 are repeated N1 times. In some embodiments, N1 is between 1 and 50.

[0043] Figure 13 This illustrates method 1200 according to some embodiments (see...) Figure 12 A flowchart of step 1202. In some embodiments, step 1202 includes an ALD process and includes performing one or more ALD cycles 1302. In some embodiments, ALD cycle 1302 is performed N2 times. In some embodiments, N2 is between 1 and 50. In some embodiments, ALD cycle 1302 is performed at a temperature between about 250°C and about 550°C. In some embodiments, ALD cycle 1302 includes performing step 1304, wherein a first metal-containing precursor is introduced onto substrate 102 (see...). Figure 10 and Figure 11 In some embodiments, the first metal-containing precursor is adsorbed in a space formed by openings 128N and 128P (see...). Figure 10 On the exposed surface. In some embodiments, when the first metal nitride layer comprises TiN, the first metal-containing precursor may comprise TiCl4, tetrakis(dimethylamino)titanium (TDMAT), combinations thereof, etc. In some embodiments, when the first metal nitride layer comprises TaN, the first metal-containing precursor may comprise TaCl5, pentapenta(dimethylamino)tantalum (PDMAT), combinations thereof, etc. In some embodiments, the first metal-containing precursor is introduced over a time between about 0.1 seconds and about 20 seconds. In some embodiments, the flow rate of the first metal-containing precursor is between about 200 sccm and about 5000 sccm.

[0044] In step 1306, a non-reactive gas (e.g., N2, Ar, combinations thereof) is used to purge the unadsorbed portion of the first metal-containing precursor. In some embodiments, the purging is performed for a time between 0.1 seconds and about 20 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0045] In step 1308, a first nitrogen-containing precursor is introduced onto the adsorption portion of a first metal-containing precursor. The first nitrogen-containing precursor reacts with the adsorption portion of the first metal-containing precursor to form a first metal nitride material. In some embodiments, when the first metal-containing precursor comprises TiCl4, TaCl5, or PDMAT, the first nitrogen-containing precursor comprises NH3. In some embodiments, when the first metal-containing precursor comprises TDMAT, the first nitrogen-containing precursor comprises N2. In some embodiments, the first nitrogen-containing precursor is introduced over a time period between 0.1 seconds and approximately 20 seconds. In some embodiments, the flow rate of the first nitrogen-containing precursor is between approximately 200 sccm and approximately 5000 sccm.

[0046] In step 1310, a non-reactive gas (e.g., N2, Ar, combinations thereof) is used to purge the reaction byproducts of step 1308. In some embodiments, the purging is performed for a period between 0.1 seconds and 20 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0047] In some embodiments, the thickness of the first metal nitride layer can be adjusted by changing the number of cycles N2. In some embodiments, the ratio of Ti or Ta in the first metal nitride layer can be adjusted by adjusting the flow rates of the first metal-containing precursor and the first nitrogen-containing precursor.

[0048] Figure 14 This illustrates method 1200 according to some embodiments (see...) Figure 12 The flowchart of step 1204 is shown below. In some embodiments, step 1204 includes an ALD process and includes performing one or more ALD cycles 1402. In some embodiments, ALD cycle 1402 is performed N3 times. In some embodiments, N3 is between 1 and 50. In some embodiments, ALD cycle 1402 is performed at a temperature between about 250°C and about 550°C. In some embodiments, ALD cycle 1402 includes performing step 1404, wherein a second metal-containing precursor is introduced onto substrate 102. The second metal-containing precursor is different from the first metal-containing precursor. In some embodiments, the second metal-containing precursor is adsorbed onto a surface formed by openings 128N and 128P (see [link to documentation]). Figure 10On the exposed surface. In some embodiments, when the second metal nitride layer comprises TiN, the second metal-containing precursor may comprise TiCl4, tetrakis(dimethylamino)titanium (TDMAT), combinations thereof, etc. In some embodiments, when the second metal nitride layer comprises TaN, the second metal-containing precursor may comprise TaCl5, pentapenta(dimethylamino)tantalum (PDMAT), combinations thereof, etc. In some embodiments, the second metal-containing precursor is introduced over a time between about 0.1 seconds and about 20 seconds. In some embodiments, the flow rate of the second metal-containing precursor is between about 200 sccm and about 5000 sccm.

[0049] In step 1406, a non-reactive gas (e.g., N2, Ar, combinations thereof) is used to purge the unadsorbed portion of the second metal-containing precursor. In some embodiments, the purging is performed for a time between 0.1 seconds and about 20 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0050] In step 1408, a second nitrogen-containing precursor is introduced onto the adsorption portion of a second metal-containing precursor. The second nitrogen-containing precursor reacts with the adsorption portion of the second metal-containing precursor to form a second metal nitride material different from the first metal nitride material. In some embodiments, when the second metal-containing precursor comprises TiCl4, TaCl5, or PDMAT, the second nitrogen-containing precursor comprises NH3. In some embodiments, when the second metal-containing precursor comprises TDMAT, the second nitrogen-containing precursor comprises N2. In some embodiments, the second nitrogen-containing precursor is introduced over a time period between 0.1 seconds and approximately 20 seconds. In some embodiments, the flow rate of the second nitrogen-containing precursor is between approximately 200 sccm and approximately 5000 sccm.

[0051] In step 1410, a non-reactive gas (e.g., N2, Ar, combinations thereof) is used to purge the reaction byproducts of step 1408. In some embodiments, the purging is performed for a period between 0.1 seconds and 20 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0052] In some embodiments, the thickness of the second metal nitride layer can be adjusted by changing the number of cycles N3. In some embodiments, the ratio of Ti or Ta in the second metal nitride layer can be adjusted by adjusting the flow rates of the second metal-containing precursor and the second nitrogen-containing precursor.

[0053] exist Figure 15In this process, after forming the work function layer 136, a first portion of the work function layer 136 is removed from the opening 128N in region 100N, while a second portion of the work function layer 136 remains in the opening 128P in region 100P. In some embodiments, a mask (e.g., photoresist) is formed over region 100P, while exposing region 100N. Subsequently, the first portion of the work function layer 136 in region 100N is removed, for example, by using a suitable etching process. In some embodiments, the suitable etching process is selective for the material of the work function layer 136. In some embodiments, the suitable etching process is performed using an etchant, such as HF, including solutions of H2O, NH4OH, and H2O2, combinations thereof, etc. After the removal process, the photoresist is removed, for example, by an acceptable ashing process followed by a wet cleaning process.

[0054] exist Figure 16 In the middle, at openings 128N and 128P (see...) Figure 15 A work function layer 140 is formed in the middle. The work function layer 140 can also be referred to as an n-type work function layer. The work function layer 140 may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multiple layers thereof, etc., and can be formed using PVD, CVD, ALD, combinations thereof, etc. In some embodiments, the thickness of the work function layer 140 is approximately... With the agreement between.

[0055] After forming the function layer 140, at openings 128N and 128P (see...) Figure 15 A binder layer 142 is formed on top of the work function layer 140 in the process. The binder layer 142 may include TiN, TaN, TiSiN, TiAlN, combinations thereof, multilayers thereof, etc., and may be formed using PVD, CVD, ALD, combinations thereof, etc. In some embodiments, the thickness of the binder layer 142 is approximately [missing information]. With the agreement between.

[0056] After forming adhesive layer 142, at openings 128N and 128P (see...) Figure 15 A conductive filler layer 144 is formed in the [structure / process]. In some embodiments, the conductive filler layer 144 overfills the openings 128N and 128P. In some embodiments, the conductive filler layer 144 may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, multilayers thereof, etc., and may be formed using PVD, CVD, ALD, electroplating, combinations thereof, etc.

[0057] exist Figure 17In the middle, the openings 128N and 128P are filled with conductive filling layer 144 (see...). Figure 15 Afterwards, a planarization process (e.g., CMP process) can be performed to remove excess portions of the interface layer 132, gate dielectric layer 134, work function layers 136 and 140, adhesive layer 142, and conductive filler layer 144, which are located in ILD 126. Figure 9 Above the top surface of the interface layer 132, gate dielectric layer 134, work function layer 140, adhesive layer 142, and the remainder of conductive fill layer 144 are in the opening 128N in region 100N (see Figure 9 A gate stack 146N is formed in the region 100P. The remaining portions of the interface layer 132, gate dielectric layer 134, work function layers 136 and 140, adhesive layer 142, and conductive filler layer 144 are formed in an opening 128P in region 100P (see [link to documentation]). Figure 9 Gate stack 146P is formed in the process. After planarization, the top surfaces of gate stacks 146N and 146P, the top surfaces of gate sealing spacers 120N and 120P, the top surfaces of gate spacers 122N and 122P, and ILD 126 (see...) are formed. Figure 9 The top surfaces of the gate stacks are substantially coplanar or flush with each other (within the process variations of the planarization process). Gate stacks 146N and 146P can also be referred to as replacement gate stacks.

[0058] exist Figure 18 In this process, after forming gate stacks 146N and 146P, the gate stacks 146N and 146P are recessed, and gate masks 148N and 148P are formed in the recesses, respectively. Gate masks 148N and 148P may comprise one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, combinations thereof, etc., and can be formed using CVD, ALD, combinations thereof, etc. In some embodiments, the material of gate masks 148N and 148P is filled in the recesses, followed by a planarization process (e.g., CMP process) to remove the dielectric material in ILD 126 ( Figure 9 The excess portion extending above. In some embodiments, gate mask 148N and gate mask 148P comprise the same material. In other embodiments, gate mask 148N and gate mask 148P comprise different materials. After the planarization process, the top surfaces of gate masks 148N and 148P, the top surfaces of gate sealing spacers 120N and 120P, the top surfaces of gate spacers 122N and 122P, and ILD 126 (see Figure 9 The top surfaces of the planes are basically coplanar or flush with each other (within the process variations of planarization).

[0059] After forming gate masks 148N and 148P, ILD 150 is deposited on ILD 126 and gate masks 148N and 148P. In some embodiments, ILD 150 is constructed using the methods described above. Figure 7 The materials and methods used to form ILD 126 are similar to those described herein and will not be repeated here. In some embodiments, ILD 126 and ILD 150 comprise the same material. In other embodiments, ILD 126 and ILD 150 comprise different materials.

[0060] Further in Figure 18 In the design, source / drain contacts 154N and gate contacts 156N are formed in region 100N, and source / drain contacts 154P and gate contacts 156P are formed in region 100P. Openings for source / drain contacts 154N and 154P are formed through CESL 124 and ILDs 126 and 150. Openings for gate contacts 156N and 156P are formed through ILD 150 and gate masks 148N and 148P, respectively. Acceptable photolithography and etching techniques can be used to form the openings.

[0061] After forming openings for source / drain contacts 154N and 154P, silicide layers 152N and 152P are formed through the openings in regions 100N and 100P, respectively. In some embodiments, metallization material is deposited in the openings for source / drain contacts 154N and 154P. The metallization material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, combinations thereof, etc., and may be formed using PVD, sputtering, combinations thereof, etc. Subsequently, an annealing process is performed to form silicide layers 152N and 152P. In some embodiments, the annealing process causes the metallization material to react with the semiconductor material of the epitaxial source / drain regions 124N and 124P to form silicide layers 152N and 152P, respectively. After forming silicide layers 152N and 152P, an appropriate removal process (e.g., an appropriate etching process) is used to remove the unreacted portions of the metallization material.

[0062] Subsequently, a liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the openings for the source / drain contacts 154N and 154P and in the openings for the gate contacts 156N and 156P. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc. The conductive material may include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, combinations thereof, etc. A planarization process (e.g., CMP process) may be performed to remove excess material from the top surface of the ILD 150. The remaining portion of the liner and conductive material forms the source / drain contacts 154N and 154P and the gate contacts 156N and 156P in the respective openings. The source / drain contacts 154N and 154P are electrically coupled to the epitaxial source / drain regions 124N and 124P, respectively. The gate contacts 156N and 156P are electrically coupled to the gate stacks 146N and 146P, respectively.

[0063] In some embodiments, the source / drain contact 154N and gate contact 156N in region 100N comprise the same material as the source / drain contact 154P and gate contact 156P in region 100P. In other embodiments, the source / drain contact 154N and gate contact 156N in region 100N comprise a different material than the source / drain contact 154P and gate contact 156P in region 100P. Although shown as being formed in the same cross-section, it should be understood that each source / drain contact 154N and gate contact 156N in region 100N may be formed in a different cross-section, which can prevent short circuits of the contacts. Although shown as being formed in the same cross-section, it should be understood that each source / drain contact 154P and gate contact 156P in region 100P may be formed in a different cross-section, which can prevent short circuits of the contacts.

[0064] The embodiments can achieve advantages. The various embodiments discussed herein allow for the formation of gate structures including a work function layer whose work function can be adjusted according to the design requirements of the semiconductor device. In some embodiments, the work function layer includes two different metal nitride materials (e.g., a nitride of a first metal and a nitride of a second metal different from the first metal) disposed in a plurality of alternating layers. In some embodiments, the work function of the work function layer can be adjusted by adjusting the ratio of the first metal to the second metal within the work function layer. In some embodiments, a high ratio of the first metal to the second metal in the work function layer produces a low work function. In some embodiments, a low ratio of the first metal to the second metal in the work function layer produces a high work function.

[0065] According to an embodiment, a device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged alternately over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

[0066] The embodiments may include one or more of the following features: In this device, the first material is a first metal nitride material. In this device, the first metal nitride material includes TaN or TiN. In this device, the second material is a second metal nitride material. In this device, the second metal nitride material includes TaN or TiN. In this device, the gate stack further includes a second work function layer above the first work function layer, the second work function layer including a third material different from the first and second materials. In this device, the first work function layer is a p-type work function layer, and the second work function layer is an n-type work function layer.

[0067] According to another embodiment, a device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer, a p-type work function layer over the gate dielectric layer, and an n-type work function layer over the p-type work function layer. The p-type work function layer includes paired layers repeated two or more times. The paired layers include a first layer and a second layer, the first layer including a first metal nitride material, and the second layer including a second metal nitride material different from the first metal nitride material.

[0068] The embodiments may include one or more of the following features: In the device, the first metal nitride material includes TaN or TiN. In the device, the second metal nitride material includes TaN or TiN. In the device, the ratio of Ta to Ti in the p-type work function layer is from about 0.5 to about 0.95. In the device, the gate stack further includes a binder layer above the n-type work function layer and a conductive layer above the binder layer. In the device, the first thickness of the first layer is different from the second thickness of the second layer.

[0069] According to another embodiment, a method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming a gate dielectric layer in the recess and forming a first work function layer over the gate dielectric layer. Forming the first work function layer includes forming paired layers two or more times. The paired layers include a first layer and a second layer, the first layer comprising a first metal nitride material, and the second layer comprising a second metal nitride material different from the first metal nitride material.

[0070] Embodiments may include one or more of the following features. In this method, forming paired layers includes performing a first atomic layer deposition (ALD) process to form a first layer, and performing a second ALD process to form a second layer, the second ALD process being different from the first ALD process. In this method, the first metal nitride material includes TaN or TiN. In this method, the second metal nitride material includes TaN or TiN. In this method, forming a replacement gate further includes forming a second work function layer over the first work function layer, the material of the second work function layer being different from the first and second metal nitride materials. In this method, forming a replacement gate further includes forming a binder layer over the second work function layer, and filling the recess with a conductive layer. In this method, the first thickness of the first layer is the same as the second thickness of the second layer.

[0071] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0072] Example

[0073] Example 1. A semiconductor device comprising: a gate stack over an active region of a substrate, wherein the gate stack includes: a gate dielectric layer; and a first work function layer over the gate dielectric layer, the first work function layer including a plurality of first layers and a plurality of second layers arranged alternately over the gate dielectric layer, the plurality of first layers including a first material, and the plurality of second layers including a second material different from the first material.

[0074] Example 2. The semiconductor device according to Example 1, wherein the first material is a first metal nitride material.

[0075] Example 3. The semiconductor device according to Example 2, wherein the first metal nitride material comprises TaN or TiN.

[0076] Example 4. The semiconductor device according to Example 2, wherein the second material is a second metal nitride material.

[0077] Example 5. The semiconductor device according to Example 4, wherein the second metal nitride material comprises TaN or TiN.

[0078] Example 6. The semiconductor device according to Example 1, wherein the gate stack further includes a second work function layer above the first work function layer, the second work function layer comprising a third material different from the first material and the second material.

[0079] Example 7. The semiconductor device according to Example 6, wherein the first work function layer is a p-type work function layer, and wherein the second work function layer is an n-type work function layer.

[0080] Example 8. A semiconductor device comprising: a gate stack over an active region of a substrate, wherein the gate stack includes: a gate dielectric layer; a p-type work function layer over the gate dielectric layer, the p-type work function layer including paired layers repeated two or more times, the paired layers including a first layer and a second layer, the first layer including a first metal nitride material, and the second layer including a second metal nitride material different from the first metal nitride material; and an n-type work function layer over the p-type work function layer.

[0081] Example 9. The semiconductor device according to Example 8, wherein the first metal nitride material comprises TaN or TiN.

[0082] Example 10. The semiconductor device according to Example 9, wherein the second metal nitride material comprises TaN or TiN.

[0083] Example 11. The semiconductor device according to Example 10, wherein the ratio of Ta to Ti in the p-type work function layer is from about 0.5 to about 0.95.

[0084] Example 12. The semiconductor device according to Example 8, wherein the gate stack further includes: an adhesive layer on the n-type work function layer; and a conductive layer on the adhesive layer.

[0085] Example 13. The semiconductor device according to Example 8, wherein the first thickness of the first layer is different from the second thickness of the second layer.

[0086] Example 14. A method for forming a semiconductor device, comprising: forming a sacrificial gate over an active region of a substrate; removing the sacrificial gate to form a recess; and forming a replacement gate in the recess, wherein forming the replacement gate comprises: forming a gate dielectric layer in the recess; and forming a first work function layer over the gate dielectric layer, wherein forming the first work function layer comprises forming paired layers two or more times, the paired layers comprising a first layer and a second layer, the first layer comprising a first metal nitride material, and the second layer comprising a second metal nitride material different from the first metal nitride material.

[0087] Example 15. The method according to Example 14, wherein forming the paired layers comprises: performing a first atomic layer deposition (ALD) process to form the first layer; and performing a second ALD process to form the second layer, the second ALD process being different from the first ALD process.

[0088] Example 16. The method according to Example 14, wherein the first metal nitride material comprises TaN or TiN.

[0089] Example 17. The method according to Example 16, wherein the second metal nitride material comprises TaN or TiN.

[0090] Example 18. The method according to Example 14, wherein forming the replacement gate further includes: forming a second work function layer on top of the first work function layer, the material of the second work function layer being different from the first metal nitride material and the second metal nitride material.

[0091] Example 19. The method according to Example 18, wherein forming the replacement gate further includes: forming an adhesive layer over the second work function layer; and filling the recess with a conductive layer.

[0092] Example 20. The method according to Example 14, wherein the first thickness of the first layer is the same as the second thickness of the second layer.

Claims

1. A semiconductor device, comprising: A gate stack, situated above an active region of a substrate, wherein the gate stack comprises: Gate dielectric layer; and A first work function layer is disposed above the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged alternately above the gate dielectric layer. The plurality of first layers include a first material, and the plurality of second layers include a second material different from the first material. The first thickness of the first layer is different from the second thickness of the second layer.

2. The semiconductor device according to claim 1, wherein, The first material is a first metal nitride material.

3. The semiconductor device according to claim 2, wherein, The first metal nitride material includes TaN or TiN.

4. The semiconductor device according to claim 2, wherein, The second material is a second metal nitride material.

5. The semiconductor device according to claim 4, wherein, The second metal nitride material includes TaN or TiN.

6. The semiconductor device according to claim 1, wherein, The gate stack further includes a second work function layer, which is above the first work function layer, and the second work function layer includes a third material that is different from the first material and the second material.

7. The semiconductor device according to claim 6, wherein, The first work function layer is a p-type work function layer, and the second work function layer is an n-type work function layer.

8. A semiconductor device, comprising: A gate stack, situated above an active region of a substrate, wherein the gate stack comprises: Gate dielectric layer; A p-type work function layer, above the gate dielectric layer, comprising paired layers repeated two or more times, the paired layers comprising a first layer and a second layer, the first layer comprising a first metal nitride material, and the second layer comprising a second metal nitride material different from the first metal nitride material, wherein a first thickness of the first layer is different from a second thickness of the second layer; and The n-type work function layer is located above the p-type work function layer.

9. The semiconductor device according to claim 8, wherein, The first metal nitride material includes TaN or TiN.

10. The semiconductor device according to claim 9, wherein, The second metal nitride material includes TaN or TiN.

11. The semiconductor device according to claim 10, wherein, The ratio of Ta to Ti in the p-type work function layer ranges from 0.5 to 0.

95.

12. The semiconductor device according to claim 8, wherein, The gate stack further includes: Adhesive layer, on top of the n-type work function layer; and A conductive layer is placed on top of the adhesive layer.

13. A method for forming a semiconductor device, comprising: A sacrificial gate is formed on the active region of the substrate; Remove the sacrificial gate to form a recess; as well as A replacement gate is formed in the recess, wherein forming the replacement gate includes: A gate dielectric layer is formed in the recess; and A first work function layer is formed on the gate dielectric layer, wherein forming the first work function layer includes forming paired layers two or more times, the paired layers including a first layer and a second layer, the first layer including a first metal nitride material, and the second layer including a second metal nitride material different from the first metal nitride material, wherein the first thickness of the first layer is different from the second thickness of the second layer.

14. The method according to claim 13, wherein, Forming the paired layers includes: Perform a first atomic layer deposition (ALD) process to form the first layer; and A second atomic layer deposition (ALD) process is performed to form the second layer, which is different from the first atomic layer deposition (ALD) process.

15. The method according to claim 13, wherein, The first metal nitride material includes TaN or TiN.

16. The method according to claim 15, wherein, The second metal nitride material includes TaN or TiN.

17. The method according to claim 13, wherein, Forming the replacement gate further includes forming a second work function layer on top of the first work function layer, wherein the material of the second work function layer is different from the first metal nitride material and the second metal nitride material.

18. The method according to claim 17, wherein, Forming the replacement gate further includes: A glue layer is formed on top of the second work function layer; and The recess is filled with a conductive layer.

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