Display substrate and manufacturing method thereof, and display device

Abstract

The present disclosure provides a display substrate and a method for preparing the same, and a display device. The display substrate includes a plurality of pixel light-emitting areas and a plurality of pixel spacing areas between adjacent pixel light-emitting areas; in a plane perpendicular to the display substrate, the display substrate includes a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light-emitting structure layer at least includes a pixel definition layer and at least one hole neutralization layer, the pixel definition layer is provided with a pixel opening in the pixel light-emitting area, the hole neutralization layer is provided in the pixel spacing area, and the hole neutralization layer is configured to neutralize hole-type carriers propagating laterally. The present disclosure eliminates lateral leakage by providing a hole neutralization layer in the pixel spacing area, and effectively solves the lateral crosstalk problem.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Micro Organic Light-Emitting Diode (Micro-OLED) is a micro display that has been developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED can not only realize active addressing of pixels, but also realize the preparation of pixel driving circuits and other structures on silicon-based substrates, which is conducive to reducing the system volume and achieving lightweight. Silicon-based OLED is prepared using mature complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) integrated circuit technology. It has the advantages of small size, high resolution (Pixels Per Inch, PPI), high refresh rate, etc., and is widely used in virtual reality (VR) or augmented reality (AR) near-eye display fields.

[0003] Currently, existing OLED display devices have a lateral crosstalk problem, which reduces the display quality. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a preparation method thereof, and a display device, so as to solve the lateral crosstalk problem existing in the existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, wherein in a plane parallel to the display substrate, the display substrate includes a plurality of pixel light-emitting areas and a plurality of pixel spacing areas located between adjacent pixel light-emitting areas; in a plane perpendicular to the display substrate, the display substrate includes a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the light-emitting structure layer includes at least a pixel definition layer and at least one hole neutralization layer, the pixel definition layer is provided with a pixel opening in the pixel light-emitting area, the hole neutralization layer is arranged in the pixel spacing area, and the hole neutralization layer is configured to neutralize laterally propagating hole-type carriers.

[0007] In an exemplary embodiment, an orthographic projection of the hole neutralization layer on the substrate does not overlap with an orthographic projection of the pixel opening on the substrate.

[0008] In an exemplary embodiment, the hole neutralization layer is disposed on a side of the pixel definition layer away from the substrate.

[0009] In an exemplary embodiment, the pixel definition layer is provided with a groove in the pixel spacing region, and the hole neutralization layer is provided in the groove.

[0010] In an exemplary embodiment, the depth of the groove is 30% to 80% of the thickness of the pixel definition layer.

[0011] In an exemplary embodiment, the hole neutralization layer is embedded within the pixel definition layer.

[0012] In an exemplary embodiment, the hole neutralization layer is formed by performing a doping process on the pixel definition layer.

[0013] In an exemplary embodiment, a surface of the hole neutralization layer at a side remote from the substrate is flush with a surface of the pixel definition layer at a side remote from the substrate.

[0014] In an exemplary embodiment, the conductivity of the hole neutralization layer is greater than the conductivity of the pixel definition layer.

[0015] In an exemplary embodiment, the material of the hole neutralization layer includes an N-doped material.

[0016] In an exemplary embodiment, a material of the hole neutralization layer includes N-doped silicon nitride or N-doped polysilicon.

[0017] In an exemplary embodiment, the width of the hole neutralization layer is 30% to 80% of an opening pitch, which is a distance between two adjacent pixel openings.

[0018] In an exemplary embodiment, a distance between a surface of the hole neutralization layer away from the substrate and the substrate is smaller than a distance between a surface of the anode in the light emitting structure layer away from the substrate and the substrate.

[0019] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0020] In another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate comprises a plurality of pixel light-emitting regions and a plurality of pixel spacing regions located between adjacent pixel light-emitting regions in a plane parallel to the display substrate; the preparation method comprises:

[0021] forming a driving circuit layer on the substrate;

[0022] A light-emitting structure layer is formed on the driving circuit layer, wherein the light-emitting structure layer at least includes a pixel definition layer and a hole neutralization layer, wherein the pixel definition layer is provided with a pixel opening in the pixel light-emitting area, and the hole neutralization layer is provided in the pixel spacing area, and the hole neutralization layer is configured to neutralize laterally propagating hole-type carriers.

[0023] The present disclosure provides a display substrate and a preparation method thereof, and a display device. By arranging a hole neutralization layer in a pixel spacing region, lateral leakage is eliminated, the lateral crosstalk problem is effectively solved, the color gamut of the display device is improved, and the display quality is improved.

[0024] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0026] Figure 1 It is a structural schematic diagram of a silicon-based OLED display device;

[0027] Figure 2 It is a schematic diagram of the planar structure of a silicon-based OLED display device;

[0028] Figure 3 is an equivalent circuit diagram of a pixel driving circuit;

[0029] Figure 4 It is a schematic diagram of the cross-sectional structure of a silicon-based OLED display device;

[0030] Figure 5 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 6 A schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 7 It is a schematic diagram after forming the substrate and the driving circuit layer patterns according to the exemplary embodiment of the present disclosure;

[0033] Figure 8 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming an anode conductive layer pattern;

[0034] Fig. 9 A schematic diagram of an exemplary embodiment of the present disclosure after forming a pixel definition layer pattern;

[0035] Fig.10 A schematic diagram of an exemplary embodiment of the present disclosure after forming a hole neutralization layer pattern;

[0036] Fig.11 It is a schematic diagram of an exemplary embodiment of the present disclosure after forming an organic light-emitting layer pattern;

[0037] Fig.12 A schematic diagram of an exemplary embodiment of the present disclosure after a cathode pattern is formed;

[0038] Fig.13 A schematic diagram showing a lateral crosstalk problem on a display substrate;

[0039] Fig.14 A schematic diagram of solving the lateral leakage problem of an exemplary embodiment of the present disclosure;

[0040] Fig.15a , Fig.15b and Fig.15c is a schematic diagram of simulation results of an exemplary embodiment of the present disclosure;

[0041] Fig.16 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0042] Fig.17 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0043] Fig.18 The figure is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure.

[0044] Description of reference numerals:

[0045] 10—substrate; 11—first insulating layer; 12—second insulating layer;

[0046] 13—third insulating layer; 14—fourth insulating layer; 20—driving circuit layer;

[0047] 30—light emitting structure layer; 31—anode; 32—pixel definition layer;

[0048] 33—hole neutralization layer; 34—organic light emitting layer; 35—cathode;

[0049] 36—pixel opening; 37—groove; 40—first encapsulation layer;

[0050] 50—color film structure layer; 60—second encapsulation layer; 70—cover plate layer;

[0051] 80—Leakage path. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0053] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0054] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0055] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0056] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0057] In this specification, a transistor refers to an element including at least three terminals, namely, a gate electrode, a second stage, and a first stage. The transistor has a channel region between the second stage (second stage terminal, drain region, or second stage) and the first stage (first terminal, source region, or first stage), and current can flow through the second stage, the channel region, and the first stage. Note that in this specification, the channel region refers to a region through which current mainly flows.

[0058] In this specification, the first pole may be the second level, the second pole may be the first pole, or the first pole may be the first pole and the second pole may be the second level. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "first pole" and the "second level" are sometimes interchanged. Therefore, in this specification, the "first pole" and the "second level" may be interchanged.

[0059] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0060] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0061] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0062] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0063] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0064] Figure 1 Schematic diagram of the structure of a silicon-based OLED display device. Figure 1As shown, the silicon-based OLED display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using a clock signal, and apply a data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of sub-pixel rows, where n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next level circuit under the control of a clock signal, and m may be a natural number. The sub-pixel array may include a plurality of pixel sub-PXij. Each pixel sub-PXij may be connected to a corresponding data signal line and a corresponding scan signal line, and i and j may be natural numbers. The sub-pixel PXij may refer to a sub-pixel in which a transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0065] Figure 2 Schematic diagram of the planar structure of a silicon-based OLED display device. Figure 2 As shown, the display device may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, and the three sub-pixels each include a pixel driving circuit and a light-emitting device, the pixel driving circuit in the sub-pixel is respectively connected to the scanning signal line and the data signal line, the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line, and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0066] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel emitting red (R) light, the second sub-pixel P2 may be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 may be a green sub-pixel emitting green (G) light. In an exemplary embodiment, the shape of the sub-pixels may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and may be arranged in a horizontal parallel, a vertical parallel, a herringbone, etc., which is not limited in the present disclosure.

[0067] In an exemplary embodiment, the pixel unit may include four sub-pixels, such as a red sub-pixel, a blue sub-pixel, a green sub-pixel, and a white (W) sub-pixel, which is not limited in the present disclosure.

[0068] Figure 3 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 3 As shown, the pixel driving circuit can be a 3T1C structure, including three transistors (a first transistor T1 to a third transistor T3) and a storage capacitor C. The pixel driving circuit is connected to five signal lines (a scanning signal line S, a data signal line D, a compensation signal line SE, a first power line VDD and a second power line VSS). The first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The first node N1 and the second node N2 are the meeting points of related electrical connections in the circuit diagram.

[0069] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1, and a second end of the storage capacitor C may be connected to the second node N2, or may be connected to a ground line (GND).

[0070] In an exemplary embodiment, a control electrode of the first transistor T1 is connected to the scan signal line S, a first electrode of the first transistor T1 is connected to the data signal line D, and a second electrode of the first transistor T1 is connected to the first node N1.

[0071] In an exemplary embodiment, a control electrode of the second transistor T2 is connected to the first node N1 , a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2 .

[0072] In an exemplary embodiment, a control electrode of the third transistor T3 is connected to the scan signal line S, a first electrode of the third transistor T3 is connected to the compensation signal line SE, and a second electrode of the third transistor T3 is connected to the second node N2.

[0073] In an exemplary embodiment, a first electrode of the light emitting device XL is connected to the second node N2 , and a second electrode of the light emitting device XL is connected to the second power line VSS.

[0074] In an exemplary embodiment, the first transistor T1 is configured to receive the data voltage transmitted by the data signal line D under the control of the signal of the scan signal line S, store the data voltage in the storage capacitor C, and provide the data voltage to the control electrode of the second transistor T2. The second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by its control electrode. The second transistor T2 is configured to provide the signal of the first power line VDD to the second node N2 under the control of the third transistor T3 to drive the display light-emitting device XL to emit light. The third transistor T3 is configured to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth. The storage capacitor C is configured to store the potential of the control electrode of the second transistor T2, and the light-emitting device XL is configured to emit light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0075] In an exemplary embodiment, the signal of the first power line VDD may be a high level signal that is continuously provided, and the signal of the second power line VSS may be a low level signal that is continuously provided.

[0076] In an exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be P-type transistors. In another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In another exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may include a P-type transistor and an N-type transistor. For example, the first transistor T1 and the third transistor T3 may be P-type metal oxide semiconductor transistors (PMOS), and the second transistor T2 may be an N-type metal oxide semiconductor transistor (NMOS).

[0077] In an exemplary embodiment, the light emitting device XL may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0078] Figure 4 This is a schematic diagram of the cross-sectional structure of a silicon-based OLED display device, illustrating a structure that uses white light + color film to achieve full color. Figure 4As shown, the silicon-based OLED display device may include: a silicon substrate 10, a driving circuit layer 20 disposed on the silicon substrate 10, a light emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the silicon substrate 10, a first encapsulation layer 40 disposed on the side of the light emitting structure layer 30 away from the silicon substrate 10, a color film structure layer 50 disposed on the side of the first encapsulation layer 40 away from the silicon substrate 10, a second encapsulation layer 60 disposed on the side of the color film structure layer 50 away from the silicon substrate 10, and a cover layer 70 disposed on the side of the second encapsulation layer 60 away from the silicon substrate 10. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in the present disclosure.

[0079] In an exemplary embodiment, the silicon substrate 10 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 20 may be prepared on the silicon substrate 10 by a silicon semiconductor process (e.g., a CMOS process). The driving circuit layer 20 may include a plurality of circuit units, at least one of which may include a pixel driving circuit, the pixel driving circuits are respectively connected to the scanning signal lines and the data signal lines, and at least one of which may include a plurality of transistors and storage capacitors. Figure 3 In the example, the pixel driving circuit includes only one transistor. The transistor may include a control electrode G, a first electrode S, and a second electrode D. The control electrode G, the first electrode S, and the second electrode D may be connected to corresponding connection electrodes through vias filled with tungsten metal (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as wiring, etc.) through the connection electrodes.

[0080] In an exemplary embodiment, the light-emitting structure layer 30 may include a plurality of light-emitting devices, and the light-emitting devices may include at least an anode, an organic light-emitting layer and a cathode. The anode may be connected to the second electrode D of the transistor through a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light when driven by the anode and the cathode.

[0081] In an exemplary embodiment, the light emitting structure layer 30 may further include a pixel definition layer, and a pixel opening is disposed on the pixel definition layer of each sub-pixel, and the pixel opening exposes the anode, so that the organic light emitting layer is connected to the anode through the pixel opening.

[0082] In an exemplary embodiment, since the organic light-emitting layer emits light in the pixel opening area defined by the pixel definition layer, the sub-pixel may include a light-emitting area and a non-light-emitting area, the pixel opening area is the light-emitting area, the area outside the pixel opening is the non-light-emitting area, and the non-light-emitting area is located at the periphery of the light-emitting area. In the present disclosure, the light-emitting area of ​​each sub-pixel is referred to as a pixel light-emitting area, and the non-light-emitting area of ​​each sub-pixel is referred to as a pixel spacing area. For example, the area between the pixel light-emitting area of ​​the first sub-pixel and the pixel light-emitting area of ​​the second sub-pixel is a pixel spacing area. In this way, the display substrate may include a plurality of pixel light-emitting areas arranged periodically, and a plurality of pixel spacing areas located between adjacent pixel light-emitting areas.

[0083] In an exemplary embodiment, the first encapsulation layer 40 and the second encapsulation layer 60 can adopt a thin film encapsulation (Thin Film Encapsulation, referred to as TFE) method to ensure that external water vapor cannot enter the light-emitting structure layer. The cover layer 70 can be made of glass, or a plastic colorless polyimide with flexible properties.

[0084] In an exemplary embodiment, the color film structure layer 50 may include a black matrix (BM) and a color filter (CF), the color filters are respectively arranged in the red sub-pixel, the green sub-pixel and the blue sub-pixel, and the white light emitted by the light-emitting device is filtered into red (R) light, green (G) light and blue (B) light, and the black matrix may be located between adjacent color filters.

[0085] In an exemplary embodiment, the organic light-emitting layer is configured to emit white light and may be prepared by evaporation. The organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0086] The resolution of silicon-based OLED is relatively high, about greater than 1500, and the size of a single sub-pixel is small, about less than 10μm, or even about 5μm, and the organic light-emitting layer is a whole continuous film layer, so some of the film layers in the organic light-emitting layer have lateral leakage, and there is lateral crosstalk between adjacent sub-pixels. At present, the prior art has proposed a variety of solutions to the problem of lateral crosstalk. For example, one solution is to set an undercut partition structure and use the partition structure to cut off the lateral leakage. For another example, another solution is to set a groove on the image definition layer, and use the groove to increase the transmission distance of the carrier to reduce the lateral leakage. For another example, another solution is to use an organic light-emitting material with low lateral conductivity. The inventors of this application have found that the first two solutions not only have limited effects in cutting off lateral leakage, but also have high process requirements and are difficult to achieve mass production. The third solution will affect the efficiency and voltage of the light-emitting device, and the brightness loss is large.

[0087] In order to solve the problems of lateral crosstalk in existing OLED display devices, the present disclosure provides a display substrate. In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate includes a plurality of pixel light-emitting areas and a plurality of pixel spacing areas between adjacent pixel light-emitting areas; in a plane perpendicular to the display substrate, the display substrate includes a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the light-emitting structure layer at least includes a pixel definition layer and a hole neutralization layer, the pixel definition layer is provided with a pixel opening in the pixel light-emitting area, the hole neutralization layer is disposed in the pixel spacing area, and the hole neutralization layer is configured to neutralize hole-type carriers propagating laterally.

[0088] In an exemplary embodiment, the conductivity of the hole neutralization layer is greater than the conductivity of the pixel definition layer.

[0089] In example embodiments, the material of the hole neutralization layer may include an N-dopant material.

[0090] In example embodiments, the N-doped material may include N-doped silicon nitride (N-dopant SiNx) or N-doped polysilicon (N-dopant poly-Si).

[0091] In an exemplary embodiment, a content of the boron element in the hole neutralization layer is greater than a content of the boron element in the pixel definition layer.

[0092] In an exemplary embodiment, the width of the hole neutralization layer may be approximately 30% to 80% of an opening pitch, which is a distance between two adjacent pixel openings.

[0093] In an exemplary embodiment, a distance between a surface of the hole neutralization layer away from the substrate and the substrate is smaller than a distance between a surface of the anode in the light emitting structure layer away from the substrate and the substrate.

[0094] In exemplary embodiments, the hole neutralization layer may have a thickness of about 10 nm to 200 nm.

[0095] In an exemplary embodiment, the hole neutralization layer is disposed on a side of the pixel definition layer away from the substrate.

[0096] In another exemplary embodiment, the pixel definition layer is provided with a groove in the pixel spacing region, and the hole neutralization layer is provided in the groove.

[0097] In yet another exemplary embodiment, the hole neutralization layer is embedded in the pixel definition layer, and the hole neutralization layer is formed by performing a doping process on the pixel definition layer.

[0098] Figure 5 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 6 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure. Figure 5 A cross-sectional view taken along the AA direction. On a plane parallel to the display substrate, the display substrate may include a plurality of pixel units arranged in a matrix, at least one pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence, in a first direction X, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in alignment, in a second direction Y, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in a staggered manner, and the first direction X and the second direction Y intersect.

[0099] In an exemplary embodiment, the area where the pixel unit is located may be divided into a pixel light emitting area PA and a pixel spacing area PK, the pixel light emitting area PA may be located in the middle area of ​​each sub-pixel, and the pixel spacing area PK may be located between the pixel light emitting areas PA of adjacent sub-pixels. In an exemplary embodiment, the pixel light emitting area PA may be a pixel opening area of ​​each sub-pixel, and the pixel spacing area PK may be an area outside the pixel opening of each sub-pixel.

[0100] like Figure 5 and Figure 6As shown, on a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving circuit layer 20 disposed on the substrate 10, and a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate, and the light emitting structure layer 30 may include an anode 31, a pixel definition layer 32, a hole neutralization layer 33, an organic light emitting layer 34, and a cathode 35. In an exemplary embodiment, the anode 31 may be disposed on a side of the driving circuit layer 20 away from the substrate, the pixel definition layer 32 may be disposed on a side of the anode 31 away from the substrate, a pixel opening 36 may be disposed on the pixel definition layer 32 of each sub-pixel, the pixel definition layer in the pixel opening 36 is removed, exposing the surface of the anode 31, and the pixel opening 36 is configured to form a pixel light emitting area PA in each sub-pixel, and to form a pixel spacing area PK between adjacent sub-pixels. In an exemplary embodiment, at least one hole neutralization layer 33 may be disposed on a side of the pixel definition layer 32 away from the substrate, in the region where the pixel spacing area PK is located. The organic light-emitting layer 34 may include at least a plurality of stacked light-emitting sublayers. The organic light-emitting layer 34 located in the pixel light-emitting area PA is connected to the anode 31 through the pixel opening 36. The organic light-emitting layer 34 located in the pixel spacing area PK is arranged in the hole and on the side of the layer 33 away from the substrate. The cathode 35 may be arranged on the side of the organic light-emitting layer 34 away from the substrate.

[0101] In an exemplary embodiment, the orthographic projection of the hole neutralization layer 33 on the substrate does not overlap with the orthographic projection of the pixel opening 36 on the substrate.

[0102] In an exemplary embodiment, the orthographic projection of the hole neutralization layer 33 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate to avoid generation of parasitic capacitance between the hole neutralization layer 33 and the anode 31 .

[0103] In an exemplary embodiment, the width L2 of the hole neutralization layer 33 may be approximately 30% to 60% of the opening pitch L1. For example, the width L2 of the hole neutralization layer 33 may be approximately 40% of the opening pitch L1.

[0104] In an exemplary embodiment, a distance M1 between a surface of the hole neutralization layer 33 away from the substrate 10 and the surface of the substrate 10 may be smaller than a distance M2 between a surface of the anode 31 of the light emitting structure layer 30 away from the substrate 10 and the surface of the substrate 10 .

[0105] In exemplary embodiments, the thickness H of the hole neutralization layer may be about 10 nm to 200 nm.

[0106] In an exemplary embodiment, on a plane parallel to the display substrate, the shape of the hole neutralization layer 33 can be a closed ring structure surrounding the pixel light-emitting area PA. The hole neutralization layer 33 with a closed ring structure can block the propagation of hole-type carriers in any lateral direction, thereby avoiding lateral crosstalk.

[0107] In an exemplary embodiment, the hole neutralization layers 33 disposed in the plurality of pixel spacing regions PK are connected to each other to form a grid on the display substrate, which can effectively improve the effect of the hole neutralization layer in blocking the lateral propagation of hole-type carriers.

[0108] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0109] In an exemplary embodiment, taking three sub-pixels of a display substrate as an example, the preparation process of the display substrate may include the following operations.

[0110] (1) Forming a substrate and a driving circuit layer pattern. In an exemplary embodiment, forming a substrate and a driving circuit layer pattern may include:

[0111] A silicon material is provided to form a substrate 10. The silicon material may be a semiconductor material such as single crystal silicon or polycrystalline silicon. For example, the silicon material may be a P-type silicon material, which may be used as a channel region of an N-type transistor. For another example, the silicon material may be an N-type silicon material, which may be used as a channel region of a P-type transistor.

[0112] A first insulating film and a polysilicon film are sequentially deposited on a substrate 10, and the polysilicon film and the first insulating film are first patterned by a patterning process, and a first insulating layer 11 and a polysilicon layer disposed on the first insulating layer 11 are formed on the silicon substrate, and then a doping process is performed using the polysilicon layer pattern as a shield, and the doped polysilicon layer forms a first conductive layer, and the doped silicon substrate forms a first region and a second region of an active layer, and a channel region is located between the first region and the second region. In an exemplary embodiment, the first conductive layer may include gate electrodes of a plurality of transistors.

[0113] A second insulating film is deposited, and the second insulating film is patterned by a patterning process to form a second insulating layer 12 covering the first conductive layer pattern, wherein a plurality of first via holes are disposed on the second insulating layer 12 .

[0114] A first metal film is deposited and patterned through a patterning process to form a first metal layer on the second insulating layer 12. The first metal layer may include at least a scanning signal line, a first electrode and a second electrode of a transistor. The scanning signal line is connected to the gate electrode of the transistor through a metal (such as tungsten) filled in a via hole, the first electrode of the transistor is connected to the first area of ​​the active layer through the metal filled in the first via hole, and the second electrode of the transistor is connected to the second area of ​​the active layer through the metal filled in the first via hole.

[0115] A third insulating film is deposited and patterned by a patterning process to form a third insulating layer 13 covering the first metal layer pattern, wherein a plurality of second via holes are disposed on the third insulating layer 13 .

[0116] A second metal film is deposited and patterned by a patterning process to form a second metal layer on the third insulating layer 13. The second metal layer may include at least a connecting electrode, which is connected to the second electrode of the transistor through the metal filled in the second via hole.

[0117] A fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer 14 covering the second metal layer pattern, and a plurality of third via holes are disposed on the fourth insulating layer 14 .

[0118] At this point, the pattern of the driving circuit layer 20 is prepared on the substrate 10, such as Figure 7 In an exemplary embodiment, the driving circuit layer 20 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 7 In the figure, it is only taken as an example that the pixel driving circuit includes a transistor 20A, and the transistor 20A may include an active layer, a gate electrode, a first electrode and a second electrode.

[0119] In an exemplary embodiment, the first insulating layer, the second insulating layer and the third insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first insulating layer may be referred to as a gate insulating (GI) layer, the second insulating layer may be referred to as an interlayer insulating (ILD) layer, and the third insulating layer may be referred to as a passivation (PVX) layer. The fourth insulating layer may be made of an organic material, such as a resin, etc., and the fourth insulating layer may be referred to as a flat layer. The first metal layer and the second metal layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as an aluminum neodymium alloy (AlNd) or a molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc.

[0120] In an exemplary embodiment, the driving circuit layer 20 may further include structures such as power lines, which are not limited in the present disclosure.

[0121] (2) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate formed with the aforementioned pattern, patterning the anode conductive film through a patterning process to form an anode conductive layer pattern, wherein the anode conductive layer pattern includes at least an anode 31 located in each sub-pixel, and the anode 31 is connected to the connection electrode through the metal filled in the third via hole, such as Figure 8 shown.

[0122] In an exemplary embodiment, the anode conductive layer may be made of a metal material or a transparent conductive material, the metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, and the transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the anode conductive layer may be a single-layer structure, or a multi-layer composite structure, such as ITO / Al / ITO, etc.

[0123] (3) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: depositing a pixel definition film on a substrate formed with the aforementioned pattern, patterning the pixel definition film through a patterning process, and forming a pixel definition layer 32 pattern, such as Fig. 9 shown.

[0124] In an exemplary embodiment, the pixel definition layer 32 in each sub-pixel is provided with a pixel opening 36 , and the pixel definition layer in the pixel opening 36 is removed to expose the surface of the anode 31 .

[0125] In an exemplary embodiment, the pixel opening 36 forms a pixel light emitting area PA within each sub-pixel and forms a pixel spacing area PK between adjacent sub-pixels.

[0126] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the pixel opening 36 of each sub-pixel may include any one or more of the following: triangle, square, rectangle, pentagon, hexagon, circle and ellipse. In a plane perpendicular to the substrate, the cross-sectional shape of the pixel opening 36 of each sub-pixel may be an inverted trapezoidal shape, which is not limited in the present disclosure.

[0127] In an exemplary embodiment, the pixel definition layer may use any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.

[0128] (4) Forming a hole neutralization layer pattern. In an exemplary embodiment, forming a hole neutralization layer pattern may include: depositing a hole neutralization film on the substrate formed with the aforementioned pattern, patterning the hole neutralization film through a patterning process, and forming a hole neutralization layer 33 pattern on the pixel definition layer 32, such as Fig.10 shown.

[0129] In an exemplary embodiment, the hole neutralization layer 33 is disposed in a pixel spacing region PK between adjacent sub-pixels, the orthographic projection of the hole neutralization layer 33 on the substrate does not overlap with the orthographic projection of the pixel opening 36 on the substrate, the orthographic projection of the hole neutralization layer 33 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate, and the hole neutralization layer 33 is configured to neutralize laterally propagating hole-type carriers.

[0130] In an exemplary embodiment, the material of the hole neutralization layer 33 may be an N-type doped (N-dopant) material, which may be referred to as an N-type doped narrow fence (NNF) structure.

[0131] In example embodiments, the N-type doping material may include N-type doped silicon nitride (N-dopant SiNx) or N-type doped polysilicon (N-dopant poly-Si).

[0132] In an exemplary embodiment, the content of the boron element in the hole neutralization layer 33 is greater than the content of the boron element in the pixel definition layer 32 .

[0133] In some possible implementations, the material of the hole neutralization layer 33 may be a metal material with a lower work function, such as magnesium (Mg), and the content of the metal element (such as magnesium) in the hole neutralization layer 33 is greater than the content of the metal element (such as magnesium) in the pixel definition layer 32.

[0134] In an exemplary embodiment, the width L2 of the hole neutralization layer 33 can be approximately 30% to 60% of the opening spacing L1, and the opening spacing L1 can be the distance between the pixel openings of two adjacent sub-pixels, that is, for the adjacent first sub-pixel and the second sub-pixel, the opening spacing L1 is the minimum distance between the edge of the pixel opening of the first sub-pixel close to the pixel opening of the second sub-pixel and the edge of the pixel opening of the second sub-pixel close to the pixel opening of the first sub-pixel.

[0135] In an exemplary embodiment, a surface of the hole neutralization layer 33 away from the substrate 10 has a distance M1 from the surface of the substrate 10, and a surface of the anode 31 away from the substrate 10 has a distance M2 from the surface of the substrate 10, and M1 may be smaller than M2, that is, the height of the upper surface in the hole neutralization layer is lower than the height of the upper surface in the anode, so as to ensure that the hole-type carriers in the organic light-emitting layer propagate into the hole neutralization layer (downward), thereby improving the effect of eliminating lateral crosstalk.

[0136] In exemplary embodiments, the thickness H of the hole neutralization layer 33 may be about 10 nm to 200 nm.

[0137] (5) Forming an organic light-emitting layer pattern. In an exemplary embodiment, forming an organic light-emitting layer pattern may include: forming an organic light-emitting layer 34 pattern by evaporation or inkjet printing, wherein the organic light-emitting layer 34 of each sub-pixel is connected to the anode 31 of the sub-pixel through the pixel opening 36, such as Fig.11 shown.

[0138] In an exemplary embodiment, the organic light-emitting layer 34 may include a plurality of light-emitting sublayers, which are connected in series to emit white light. For example, the organic light-emitting layer 34 may include a first light-emitting sublayer 34-1, a first charge generation layer 34-2, a second light-emitting sublayer 34-3, a second charge generation layer 34-4, and a third light-emitting sublayer 34-5, wherein the first light-emitting sublayer 34-1 is configured to emit a first color light, the second light-emitting sublayer 34-3 is configured to emit a second color light, the third light-emitting sublayer 34-5 is configured to emit a third color light, and the first charge generation layer 34-2 and the second charge generation layer 34-4 are configured to transfer carriers.

[0139] In an exemplary embodiment, each light-emitting sublayer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron-hole neutralization layer (EBL), a hole-hole neutralization layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0140] In an exemplary embodiment, the light-emitting layer may include a host material and a guest material doped in the host material, and the doping ratio of the guest material in the light-emitting layer is 1% to 20%. Within the doping ratio range, on the one hand, the host material of the light-emitting layer can effectively transfer the exciton energy to the guest material of the light-emitting layer to excite the guest material of the light-emitting layer to emit light, and on the other hand, the host material of the light-emitting layer "dilutes" the guest material of the light-emitting layer, effectively improving the mutual collision between the molecules of the guest material of the light-emitting layer, and the fluorescence quenching caused by the mutual collision between the energy, thereby improving the luminous efficiency and the life of the device. In an exemplary embodiment, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, that is, the mass percentage. In an exemplary embodiment, the host material and the guest material can be co-evaporated by a multi-source evaporation process, so that the host material and the guest material are uniformly dispersed in the light-emitting layer, and the doping ratio can be regulated by controlling the evaporation rate of the guest material during the evaporation process, or by controlling the evaporation rate ratio of the host material and the guest material. In an exemplary embodiment, the thickness of the light-emitting layer can be about 10nm to 50nm.

[0141] In an exemplary embodiment, the hole injection layer may be made of an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide or manganese oxide, or may be made of a p-type dopant of a strong electron-withdrawing system and a dopant of a hole transport material. In an exemplary embodiment, the hole injection layer may have a thickness of about 5 nm to 20 nm.

[0142] In an exemplary embodiment, the hole transport layer may be made of a material with high hole mobility, such as an aromatic amine compound, whose substituent group may be carbazole, methylfluorene, spirofluorene, dibenzothiophene or furan, etc. In an exemplary embodiment, the thickness of the hole transport layer may be about 40 nm to 150 nm.

[0143] In an exemplary embodiment, the hole neutralization layer and the electron transport layer may be made of aromatic heterocyclic compounds, such as imidazole derivatives such as benzimidazole derivatives, imidazopyridine derivatives, benzimidazolephenanthridine derivatives; oxazine derivatives such as pyrimidine derivatives and triazine derivatives; compounds containing nitrogen-containing six-membered ring structures such as quinoline derivatives, isoquinoline derivatives, and phenanthroline derivatives (including compounds having phosphine oxide-based substituents on heterocyclic rings), etc. In an exemplary embodiment, the hole neutralization layer may have a thickness of about 5 nm to 15 nm, and the electron transport layer may have a thickness of about 20 nm to 50 nm.

[0144] In an exemplary embodiment, the electron injection layer may be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg) or calcium (Ca), or a compound of these alkali metals or metals. In an exemplary embodiment, the thickness of the electron injection layer may be about 0.5 nm to 2 nm.

[0145] In some possible implementations, the organic light-emitting layer may include an organic light-emitting layer that emits a first color light and an organic light-emitting layer that emits complementary light of the first color light. The two organic light-emitting layers are stacked in sequence to emit white light as a whole. The present disclosure does not limit this.

[0146] (6) Forming a cathode pattern. In an exemplary embodiment, forming a cathode pattern may include: forming a cathode 35 pattern by evaporation or deposition, and the cathode 35 is disposed on a side of the organic light emitting layer 34 away from the substrate, such as Fig.12 shown.

[0147] In an exemplary embodiment, the cathode may be made of a metal material or a transparent conductive material, the metal material may include any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or alloy materials of the above metals, and the transparent conductive material may include indium zinc oxide (IZO). In an exemplary embodiment, the cathode may be a single-layer structure, or a multi-layer composite structure, such as Mg / Ag, etc.

[0148] In an exemplary embodiment, an optical coupling layer pattern can be formed after forming a cathode pattern. The optical coupling layer is disposed on the cathode. The refractive index of the optical coupling layer can be greater than the refractive index of the cathode, which is beneficial to light extraction and increases the light extraction efficiency. The material of the optical coupling layer can be organic material, or inorganic material, or both organic material and inorganic material, and can be a single layer, a multi-layer or a composite layer, which is not limited in the present disclosure.

[0149] At this point, the pattern of the light emitting structure layer 30 is completed. The light emitting structure layer 30 may include an anode 31 , a pixel definition layer 32 , a hole neutralization layer 33 , an organic light emitting layer 34 and a cathode 35 . The organic light emitting layer 34 emits light under the drive of the anode 31 and the cathode 35 .

[0150] Subsequent preparation may include processes such as forming a first encapsulation layer, a color film structure layer, a second encapsulation layer, and laminating a cover plate, which will not be described in detail here.

[0151] Fig.13 Schematic diagram of a display substrate having a lateral crosstalk problem. Fig.13As shown, taking the hole injection layer in the organic light-emitting layer as an example, in order to improve the hole injection effect, the hole injection layer usually uses a P-type doping (P-dopant) material or HATCN with good injection ability. Since the P-type doping material or HATCN has good conductivity and the hole injection layer is a whole continuous film layer, a leakage path 80 will be formed between adjacent sub-pixels, such as Fig.13 As shown by the dashed line in the middle, hole-type carriers of one sub-pixel can be laterally transferred to another adjacent sub-pixel along the leakage path 80, resulting in a lateral crosstalk problem.

[0152] In an exemplary embodiment, the film layer forming the leakage path includes but is not limited to the hole injection layer, and other layers in the organic light-emitting layer may also form a leakage path. For example, since the first charge generation layer and the second charge generation layer have good charge conduction characteristics, the first charge generation layer and the second charge generation layer may form a leakage path between adjacent sub-pixels.

[0153] Fig.14 This is a schematic diagram of a display substrate for solving the lateral leakage problem in an exemplary embodiment of the present disclosure. The present disclosure can effectively solve the lateral crosstalk problem by setting a hole neutralization layer 33 between adjacent sub-pixels. Fig.14 As shown, taking the hole injection layer in the organic light-emitting layer as an example, when the hole-type carriers of a sub-pixel are laterally transmitted to the hole neutralization layer along the leakage path 80, since the hole injection layer as a hole-type functional layer is a hole-rich layer, and the hole neutralization layer as an electron-type functional layer is an electron-rich layer, an electric field is formed between the hole injection layer and the hole neutralization layer due to the potential difference. Under the action of the electric field, the hole-type carriers will move toward the hole neutralization layer and recombine in the hole neutralization layer, that is, the hole neutralization layer neutralizes the laterally propagating hole-type carriers, so the lateral propagation path of the hole-type carriers is blocked, and the hole-injected carriers will not continue to be transmitted to the adjacent sub-pixels, thereby eliminating lateral leakage and effectively solving the lateral crosstalk problem.

[0154] Fig.15a , Fig.15b and Fig.15c Schematic diagram of simulation results of eliminating lateral crosstalk in an exemplary embodiment of the present disclosure. Fig.15a is the simulation result of red light spectrum, Fig.15b is the simulation result of blue light spectrum, Fig.15c : is the simulation result of the green light spectrum. The solid line in the figure is the spectrum with the hole neutralization layer set, and the dotted line in the figure is the spectrum without the hole neutralization layer set. Fig.15a , Fig.15b and Fig.15cAs shown, when the hole neutralization layer is not provided, due to the lateral leakage between adjacent sub-pixels, both the red light and the green light have a large intensity in the wavelength range of 430nm to 480nm, that is, the monochromatic red light and the monochromatic green light cross-talk to the monochromatic blue light due to the lateral leakage. The present disclosure not only reduces the cross-talk of red and green light in the wavelength range of 430nm to 480nm, but also eliminates the cross-talk of blue light in the wavelength range of 480nm to 530nm by providing a hole neutralization layer that neutralizes the laterally propagating hole-type carriers, effectively solving the lateral crosstalk problem, improving the color gamut, and improving the display quality.

[0155] Table 1 is the color gamut simulation result of eliminating lateral crosstalk in an exemplary embodiment of the present disclosure. As shown in Table 1, the simulation results show that when the hole neutralization layer is not set, the NTSC color gamut of the display device is 26.6%, and after the hole neutralization layer is set, the NTSC color gamut of the display device is 60%. The NTSC color gamut is a color range specified by the NTSC (National Television System Committee) standard, which refers to the sum of the colors that the display device can display under the NTSC standard in the entire color space. CIE-x is the color coordinate x of the CIE color system, and CIE-y is the color coordinate y of the CIE color system. The present disclosure improves the color gamut and the display quality by setting a hole neutralization layer that neutralizes the laterally propagating hole-type carriers.

[0156] Table 1: Color gamut comparison with and without a hole neutralization layer

[0157]

[0158]

[0159] From the structure and preparation process of the display substrate described above, it can be seen that the display substrate provided by the present disclosure, by setting a hole neutralization layer in the pixel spacing area, makes the hole-type carriers propagating laterally absorbed by the electric field there, the electron holes are neutralized, the lateral propagation path of the hole-type carriers is blocked, the hole-type carriers will not be transmitted to the adjacent sub-pixels, the lateral leakage is eliminated, the lateral crosstalk problem is effectively solved, the color gamut of the display device is improved, and the display quality is improved. The preparation process of the display substrate of the exemplary embodiment of the present disclosure has good process compatibility, simple process realization, easy implementation, high production efficiency, and low production cost.

[0160] Fig.16 FIG. 2 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure. Fig.16As shown, on a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving circuit layer 20 disposed on the substrate 10, and a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate, and the light emitting structure layer 30 may include an anode 31, a pixel definition layer 32, a hole neutralization layer 33, an organic light emitting layer 34, and a cathode 35. The anode 31 is disposed on a side of the driving circuit layer 20 away from the substrate, the pixel definition layer 32 is disposed on a side of the anode 31 away from the substrate, a pixel opening 36 is disposed on the pixel definition layer 32, the pixel definition layer in the pixel opening 36 is removed, and the surface of the anode 31 is exposed, and the pixel opening 36 is configured to form a pixel light emitting area PA in each sub-pixel and to form a pixel spacing area PK between adjacent sub-pixels. Different from the aforementioned exemplary embodiment, the pixel spacing area PK is provided with two hole neutralization layers 33, the two hole neutralization layers 33 are disposed at intervals, and the two hole neutralization layers 33 are configured to neutralize hole-type carriers propagating laterally. The organic light-emitting layer 34 may include at least a plurality of stacked light-emitting sublayers. The organic light-emitting layer 34 located in the pixel light-emitting area PA is connected to the anode 31 through the pixel opening 36. The organic light-emitting layer 34 located in the pixel spacing area PK is arranged on the side of the hole layer 33 away from the substrate, and the cathode 35 is arranged on the side of the organic light-emitting layer 34 away from the substrate.

[0161] In an exemplary embodiment, the sum of the widths of the two hole neutralizing layers 33 may be approximately 30% to 80% of the opening pitch.

[0162] In an exemplary embodiment, the pixel spacing region PK may be provided with a plurality of hole neutralizing layers, and the plurality of hole neutralizing layers are spaced apart.

[0163] This exemplary embodiment not only eliminates lateral leakage and effectively solves the lateral crosstalk problem by providing multiple hole neutralization layers, but also effectively increases the contact area between the hole neutralization layer and the organic light-emitting layer, thereby improving the efficiency of eliminating lateral crosstalk.

[0164] Fig.17 FIG. 2 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure. Fig.17As shown, on a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving circuit layer 20 disposed on the substrate 10, and a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate, and the light emitting structure layer 30 may include an anode 31, a pixel definition layer 32, a hole neutralization layer 33, an organic light emitting layer 34, and a cathode 35. The anode 31 is disposed on a side of the driving circuit layer 20 away from the substrate, and the pixel definition layer 32 is disposed on a side of the anode 31 away from the substrate. Different from the aforementioned exemplary embodiment, a pixel opening 36 and a groove 37 are disposed on the pixel definition layer 32. The pixel definition layer in the pixel opening 36 is removed to expose the surface of the anode 31, and the pixel opening 36 is configured to form a pixel light emitting area PA in each sub-pixel and to form a pixel spacing area PK between adjacent sub-pixels. The groove 37 is located in the pixel spacing area PK, and a portion of the thickness of the pixel definition layer in the groove 37 is removed, and the groove 37 is configured to accommodate the hole neutralization layer 33. The hole neutralization layer 33 is disposed in the groove 37 of the pixel spacing area PK, and is configured to neutralize the hole-type carriers propagating laterally. The organic light-emitting layer 34 may include at least a plurality of stacked light-emitting sublayers, the organic light-emitting layer 34 located in the pixel light-emitting area PA is connected to the anode 31 through the pixel opening 36, the organic light-emitting layer 34 located in the pixel spacing area PK is disposed on the side of the hole neutralization layer 33 away from the substrate, and the cathode 35 is disposed on the side of the organic light-emitting layer 34 away from the substrate.

[0165] In an exemplary embodiment, the depth of the groove 72 may be approximately 30% to 80% of the thickness of the pixel definition layer 32 .

[0166] The preparation process of the display substrate of this exemplary embodiment is basically similar to the preparation process of the aforementioned embodiment. The difference is that when forming the pixel definition layer pattern, a pixel opening 36 is formed in the pixel light emitting area PA, a groove 37 is formed in the pixel spacing area PK, and then a hole neutralization layer 33 is formed, and the hole neutralization layer 33 is arranged in the groove 37.

[0167] This exemplary embodiment provides a groove on the pixel definition layer in the pixel spacing area, and the hole neutralization layer is provided in the groove, which not only eliminates lateral leakage and effectively solves the lateral crosstalk problem, but also reduces the height of the upper surface of the hole neutralization layer, which is conducive to ensuring that hole-type carriers propagate into the hole neutralization layer (downward), thereby improving the effect of eliminating lateral crosstalk. In addition, by providing a groove on the pixel definition layer, the step difference between the upper surface of the hole neutralization layer and the upper surface of the pixel definition layer can also be reduced, which is conducive to the close fit between the organic light-emitting layer and the hole neutralization layer, thereby improving the efficiency of eliminating lateral crosstalk.

[0168] Fig.18 FIG. 2 is a schematic cross-sectional structure diagram of another display substrate according to an exemplary embodiment of the present disclosure. Fig.18As shown, on a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving circuit layer 20 disposed on the substrate 10, and a light emitting structure layer 30 disposed on a side of the driving circuit layer 20 away from the substrate, and the light emitting structure layer 30 may include an anode 31, a pixel definition layer 32, a hole neutralization layer 33, an organic light emitting layer 34, and a cathode 35. The anode 31 is disposed on a side of the driving circuit layer 20 away from the substrate, the pixel definition layer 32 is disposed on a side of the anode 31 away from the substrate, and a pixel opening 36 may be disposed on the pixel definition layer 32. Different from the aforementioned exemplary embodiment, the hole neutralization layer 33 is formed by doping the pixel definition layer 32, that is, the hole neutralization layer 33 is embedded in the pixel definition layer 32, the hole neutralization layer 33 and the pixel definition layer 32 are an integral structure connected to each other, and the hole neutralization layer 33 is configured to neutralize hole-type carriers propagating laterally. The organic light-emitting layer 34 may include at least a plurality of stacked light-emitting sublayers. The organic light-emitting layer 34 located in the pixel light-emitting area PA is connected to the anode 31 through the pixel opening 36. The organic light-emitting layer 34 located in the pixel spacing area PK is arranged on the side of the hole layer 33 away from the substrate, and the cathode 35 is arranged on the side of the organic light-emitting layer 34 away from the substrate.

[0169] In an exemplary embodiment, the width of the hole neutralization layer 33 may be approximately 60% to 80% of the opening pitch.

[0170] In an exemplary embodiment, a surface of the hole neutralization layer 33 on a side away from the substrate is flush with a surface of the pixel definition layer 32 on a side away from the substrate.

[0171] The preparation process of the display substrate of this exemplary embodiment is basically similar to the preparation process of the aforementioned embodiment. The difference is that after the pixel definition layer pattern is formed, the pixel definition layer is doped using a mask plate to form a hole neutralization layer in the pixel spacing area PK, forming a structure in which the hole neutralization layer is embedded in the pixel definition layer, that is, the hole neutralization layer and the pixel definition layer are an interconnected integrated structure.

[0172] This exemplary embodiment forms a hole neutralization layer by doping the pixel definition layer, which not only eliminates lateral leakage and effectively solves the lateral crosstalk problem, but also minimizes the height of the upper surface of the hole neutralization layer and eliminates the step difference between the hole neutralization layer and the pixel definition layer, which is beneficial to increase the width of the hole neutralization layer and can effectively improve the efficiency of eliminating lateral crosstalk.

[0173] The exemplary embodiments of the present disclosure also provide a method for preparing a display substrate. In an exemplary embodiment, in a plane parallel to the display substrate, the display substrate includes a plurality of pixel light-emitting areas and a plurality of pixel spacing areas located between adjacent pixel light-emitting areas; the preparation method may include:

[0174] forming a driving circuit layer on the substrate;

[0175] A light-emitting structure layer is formed on the driving circuit layer, wherein the light-emitting structure layer at least includes a pixel definition layer and at least one hole neutralization layer, wherein the pixel definition layer is provided with a pixel opening in the pixel light-emitting area, and the hole neutralization layer is provided in the pixel spacing area, and the hole neutralization layer is configured to neutralize laterally propagating hole-type carriers.

[0176] The present disclosure also provides a display device, including the display substrate of the above embodiment. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

[0177] Although the embodiments disclosed in the present disclosure are as above, the contents described are only embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any technician in the field to which the present disclosure belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present disclosure, but the scope of patent protection of this application shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: In a plane parallel to the display substrate, the display substrate includes a plurality of pixel light-emitting areas and a plurality of pixel spacing areas between adjacent pixel light-emitting areas; in a plane perpendicular to the display substrate, the display substrate includes a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the light-emitting structure layer includes at least a pixel definition layer and at least one hole neutralization layer, the pixel definition layer is provided with a pixel opening in the pixel light-emitting area, the hole neutralization layer is arranged in the pixel spacing area, and the hole neutralization layer is configured to neutralize laterally propagating hole-type carriers.

2. The display substrate according to claim 1, characterized in that: An orthographic projection of the hole neutralization layer on the substrate does not overlap with an orthographic projection of the pixel opening on the substrate.

3. The display substrate according to claim 1, characterized in that: The hole neutralization layer is arranged on a side of the pixel definition layer away from the substrate.

4. The display substrate according to claim 1, characterized in that: The pixel definition layer is provided with a groove in the pixel spacing region, and the hole neutralization layer is provided in the groove.

5. The display substrate according to claim 4, characterized in that: The depth of the groove is 30% to 80% of the thickness of the pixel definition layer.

6. The display substrate according to claim 1, characterized in that: The hole neutralization layer is embedded in the pixel definition layer.

7. The display substrate according to claim 6, characterized in that: The hole neutralization layer is formed by performing a doping process on the pixel definition layer.

8. The display substrate according to claim 6, characterized in that: The surface of the hole neutralization layer away from the substrate is flush with the surface of the pixel definition layer away from the substrate.

9. The display substrate according to any one of claims 1 to 8, characterized in that: The conductivity of the hole neutralization layer is greater than the conductivity of the pixel definition layer.

10. The display substrate according to claim 9, characterized in that: The material of the hole neutralization layer includes N-doped material.

11. The display substrate according to claim 9, characterized in that: The material of the hole neutralization layer includes N-doped silicon nitride or N-doped polysilicon.

12. The display substrate according to any one of claims 1 to 8, characterized in that: The width of the hole neutralization layer is 30% to 80% of the opening pitch, and the opening pitch is the distance between two adjacent pixel openings.

13. The display substrate according to any one of claims 1 to 8, characterized in that: The distance between the surface of the hole neutralization layer away from the substrate and the substrate is smaller than the distance between the surface of the anode in the light emitting structure layer away from the substrate and the substrate.

14. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 13.

15. A method for preparing a display substrate, characterized in that: In a plane parallel to the display substrate, the display substrate includes a plurality of pixel light-emitting areas and a plurality of pixel spacing areas located between adjacent pixel light-emitting areas; the preparation method includes: forming a driving circuit layer on the substrate; A light-emitting structure layer is formed on the driving circuit layer, wherein the light-emitting structure layer at least includes a pixel definition layer and at least one hole neutralization layer, wherein the pixel definition layer is provided with a pixel opening in the pixel light-emitting area, and the hole neutralization layer is provided in the pixel spacing area, and the hole neutralization layer is configured to neutralize laterally propagating hole-type carriers.

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