Superconducting integrated circuit with NbN SNS Josephson junction and preparation method thereof

Abstract

The present invention provides a superconducting integrated circuit with a NbN SNS Josephson junction and a preparation method thereof, wherein the superconducting integrated circuit comprises a substrate, a functional layer, a first isolation layer, a first wiring portion, a second wiring portion, a second isolation layer, a first grounding material layer and a second grounding material layer, wherein the substrate comprises a base layer and a buffer layer, the functional layer is located on the upper surface of the buffer layer and comprises a stacked bottom electrode, a junction barrier layer and a top electrode, the first isolation layer covers the upper surface of the buffer layer and the exposed surface of the functional layer and is provided with a first contact hole and a second contact hole filled with a first wiring portion and a second wiring portion, the second isolation layer covers the upper surface of the first isolation layer and the exposed surface of the first wiring portion and the second wiring portion and is provided with a first through hole and a second through hole, and the first and second grounding material layers fill the first through hole and the second through hole respectively. The present invention adopts a thicker junction barrier layer, improves the barrier layer coverage, does not require an external parallel resistor, and improves the circuit integration.

Description

Technical Field

[0001] The invention belongs to the field of superconducting electronics and relates to a superconducting integrated circuit with a NbN SNS Josephson junction and a preparation method thereof. Background Art

[0002] The superconducting single flux quantum (SFQ) circuit was discovered. It mainly uses superconducting Josephson junctions as switches, and the presence of a single flux quantum in the superconducting loop represents logical information. It has the advantages of high speed and low power consumption. Superconducting digital integrated circuits are multi-layer structures with Josephson junctions as core units. The scale of their circuits is highly dependent on factors such as the area occupied by the Josephson junctions, the uniformity of the junctions, and the area of ​​the transmission lines. To realize the application of large-scale integrated circuits such as supercomputers, the circuits of superconducting chips need to be integrated at the order of millions of Josephson junctions or even higher.

[0003] At present, the mainstream of superconducting integrated circuits is based on superconducting Nb materials and Nb / Al-AlOx / Nb Josephson junctions with external parallel resistors. However, the small inductance, energy gap and bypass resistance of Nb limit the circuit integration and high-frequency applications.

[0004] Silicon is a common semiconductor material with low cost, mature processing technology, high surface flatness, good uniformity, and very low loss in the high frequency band. However, since the NbN film grown on the silicon substrate is a polycrystalline structure with large interface fluctuations, the critical current density, junction array uniformity and repeatability of the Josephson junction on the silicon substrate are difficult to control, making it unsuitable as a substrate for high-quality Josephson junction units.

[0005] Therefore, there is an urgent need to develop a Josephson junction unit that is highly integrated and can be stably formed on a silicon substrate. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a superconducting integrated circuit with a NbN SNS Josephson junction and a preparation method thereof, so as to solve the problems in the prior art that superconducting digital integrated circuits have low integration and are difficult to stably form on a silicon substrate.

[0007] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction, comprising the following steps:

[0008] Providing a substrate, and forming a functional material layer including a NbN bottom film, a metal barrier layer and a NbN top film in order from bottom to top on the substrate, wherein the substrate includes a base layer and a buffer layer located on the base layer;

[0009] Etching the functional material layer to form a functional layer including a bottom electrode, a junction barrier layer and a top electrode, and forming a first isolation layer covering the exposed surface of the functional layer and the upper surface of the buffer layer;

[0010] forming a first contact hole whose bottom exposes the top electrode and a second contact hole whose bottom exposes the bottom electrode in the first isolation layer, and forming a wiring layer covering the upper surface of the first isolation layer and filling the first contact hole and the second contact hole;

[0011] Etching the wiring layer to form a first wiring portion filling the first contact hole and a second wiring portion filling the second contact hole, and forming a second isolation layer on the exposed surfaces of the first wiring portion and the second wiring portion and the upper surface of the first isolation layer;

[0012] forming a first through hole whose bottom exposes the first wiring portion and a second through hole whose bottom exposes the second wiring portion in the second isolation layer, and forming a grounding material layer covering the upper surface of the second isolation layer and filling the first through hole and the second through hole;

[0013] The grounding material layer is etched to form a first grounding material layer filling the first through hole and a second grounding material layer filling the second through hole.

[0014] Optionally, the material of the base layer includes silicon, and the material of the buffer layer includes silicon dioxide.

[0015] Optionally, the material of the metal barrier layer includes TiN x 、TaN x 、NbN x At least one of , wherein x is an atomic component of the N element, and 1>x>0.

[0016] Optionally, the NbN top film, the metal barrier layer and the NbN bottom film are first etched in one step to obtain the bottom electrode, and then the NbN top film and the metal barrier layer are etched in one step to obtain the junction barrier layer and the top electrode.

[0017] Optionally, the shape of the junction barrier layer includes a circle, and the thickness of the junction barrier layer ranges from 5 nm to 30 nm.

[0018] The present invention also provides a superconducting integrated circuit having a NbN SNS Josephson junction, comprising.

[0019] A substrate, comprising a base layer and a buffer layer located on the base layer;

[0020] A functional layer, located on the upper surface of the buffer layer and comprising a bottom electrode, a junction barrier layer and a top electrode stacked upward, wherein the material of the bottom electrode comprises NbN, the junction barrier layer comprises a metal barrier layer, and the material of the top electrode comprises NbN;

[0021] a first isolation layer, covering the upper surface of the buffer layer and the exposed surface of the functional layer, and having a first contact hole for exposing the top electrode and a second contact hole for exposing the bottom electrode;

[0022] a first wiring portion and a second wiring portion, wherein the first wiring portion fills the first contact hole, and the second wiring portion fills the second contact hole;

[0023] a second isolation layer covering the upper surface of the first isolation layer and the exposed surfaces of the first wiring portion and the second wiring portion, and the second isolation layer is provided with a first through hole for exposing the first wiring portion and a second through hole for exposing the second wiring portion;

[0024] A first grounding material layer and a second grounding material layer, wherein the first grounding material layer is located on the upper surface of the second isolation layer and fills the first through hole, and the second grounding material layer is located on the upper surface of the second isolation layer and fills the second through hole.

[0025] Optionally, the material of the base layer includes silicon, and the material of the buffer layer includes silicon dioxide.

[0026] Optionally, the bottom electrode, the junction barrier layer and the top electrode form an over-damped NbN SNS Josephson junction.

[0027] Optionally, the material of the junction barrier layer includes TiN x 、TaN x 、NbN x At least one of , wherein x is an atomic component of the N element, and 1>x>0.

[0028] Optionally, the thickness range of the bottom electrode is 150nm~250nm, the thickness range of the junction barrier layer is 5nm~30nm, the diameter range of the junction barrier layer is 1.6μm~3.0μm, the thickness range of the top electrode is 150nm~250nm, the thickness range of the first isolation layer is 200nm~300nm, and the thickness range of the second isolation layer is 500nm~600nm.

[0029] As described above, the superconducting integrated circuit with NbN SNS Josephson junction of the present invention and its preparation method form the substrate by forming the buffer layer on the silicon base layer, and then growing the functional material layer on the substrate, and the thickness of the metal barrier layer in the functional material layer is in the range of 5nm to 30nm, avoiding the film boundary fluctuation in the functional material layer directly formed on the silicon substrate, and the obtained functional material layer has high quality, and the coverage and repeatability of the metal barrier layer are improved. Nitride is used as the metal barrier layer, which avoids the formation of compounds at the interface between the layers in the functional layer, which is conducive to obtaining the functional layer with a clear interface. In addition, the superconducting integrated circuit with NbN SNS Josephson junction does not require parallel resistance, which improves the integration of the circuit, and uses NbN material with high transition temperature and high dynamic inductance as the top electrode and the bottom electrode of the superconducting integrated circuit with NbN SNS Josephson junction and the microstrip line of the circuit, which increases the operating temperature, saves the area of ​​the microstrip line, reduces the circuit power consumption and further improves the integration of the circuit, and has a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The flowchart is a method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction according to the present invention.

[0031] Figure 2 The cross-sectional structure schematic diagram of the substrate provided in the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction of the present invention is shown.

[0032] Figure 3 It is a schematic diagram of the cross-sectional structure after forming the functional layer material layer in the method for preparing the superconducting integrated circuit with NbN SNS Josephson junction of the present invention.

[0033] Figure 4 It is a schematic diagram of the cross-sectional structure after forming the bottom electrode in the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction of the present invention.

[0034] Figure 5 It is a schematic diagram of the cross-sectional structure after forming the functional layer of the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction of the present invention.

[0035] Figure 6 It is a schematic diagram of the cross-sectional structure after forming the first isolation layer in the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction of the present invention.

[0036] Figure 7It is a schematic cross-sectional structure diagram of the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction according to the present invention after forming a first contact hole and a second contact hole.

[0037] Figure 8 It is a schematic diagram showing the cross-sectional structure after forming the wiring layer in the method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction according to the present invention.

[0038] Fig. 9 It is a schematic cross-sectional structure diagram showing the method for manufacturing a superconducting integrated circuit having a NbN SNS Josephson junction according to the present invention after forming a first wiring portion and a second wiring portion.

[0039] Fig.10 It is a schematic cross-sectional structure diagram of the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction according to the present invention after forming a first through hole and a second through hole.

[0040] Fig.11 It is a schematic cross-sectional structure diagram of the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction according to the present invention after forming a grounding material layer.

[0041] Fig.12 It is a schematic cross-sectional structure diagram of the method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction according to the present invention after forming a first grounding material layer and a second grounding material layer.

[0042] Component number description

[0043] 1 Substrate

[0044] 11. Basal layer

[0045] 12 Buffer layer

[0046] 2 Functional material layer

[0047] 21 NbN base film

[0048] 22 Metal barrier layer

[0049] 23 NbN top film

[0050] 24 Functional Layer

[0051] 241 bottom electrode

[0052] 242 Junction barrier layer

[0053] 243 Top electrode

[0054] 3. First isolation layer

[0055] 31 First contact hole

[0056] 32 Second contact hole

[0057] 4 Wiring layer

[0058] 41 First wiring layer

[0059] 42 Second wiring layer

[0060] 5 Second isolation layer

[0061] 51 First through hole

[0062] 52 Second through hole

[0063] 6 Ground material layer

[0064] 61 First grounding material layer

[0065] 62 Second ground material layer DETAILED DESCRIPTION

[0066] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0067] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0068] Embodiment 1

[0069] This embodiment provides a method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction, such as Figure 1 As shown, it is a flow chart of the preparation method of forming the NbN SNS Josephson junction, which includes the following steps:

[0070] S1: providing a substrate, and forming a functional material layer including a NbN bottom film, a metal barrier layer and a NbN top film in order from bottom to top on the substrate, wherein the substrate includes a base layer and a buffer layer located on the base layer;

[0071] S2: etching the functional material layer to form a functional layer including a bottom electrode, a junction barrier layer and a top electrode, and forming a first isolation layer covering the exposed surface of the functional layer and the upper surface of the buffer layer;

[0072] S3: forming a first contact hole whose bottom exposes the top electrode and a second contact hole whose bottom exposes the bottom electrode in the first isolation layer, and forming a wiring layer covering the upper surface of the first isolation layer and filling the first contact hole and the second contact hole;

[0073] S4: etching the wiring layer to form a first wiring portion filling the first contact hole and a second wiring portion filling the second contact hole, and forming a second isolation layer on the exposed surfaces of the first wiring portion and the second wiring portion and the upper surface of the first isolation layer;

[0074] S5: forming a first through hole whose bottom exposes the first wiring portion and a second through hole whose bottom exposes the second wiring portion in the second isolation layer, and forming a grounding material layer covering the upper surface of the second isolation layer and filling the first through hole and the second through hole;

[0075] S6: Etching the grounding material layer to form a first grounding material layer filling the first through hole and a second grounding material layer filling the second through hole.

[0076] See also Figures 2 to 3 , perform the step S1: provide a substrate 1, and form a functional material layer 2 on the substrate, which includes a NbN bottom layer film 21, a metal barrier layer 22 and a NbN top layer film 23 from bottom to top, wherein the substrate 1 includes a base layer 11 and a buffer layer 12 located on the base layer 11.

[0077] As an example, Figure 2 As shown, a schematic diagram of the cross-sectional structure of the substrate 1 is provided. The material of the base layer 11 includes silicon or other suitable materials, and the material of the buffer layer 12 includes silicon dioxide or other suitable materials to be suitable for semiconductor processes.

[0078] Specifically, since the performance of the Josephson junction is related to the resistivity of the barrier layer material and the interface flatness of the superconducting material layer / normal metal material barrier layer, the substrate 1 needs to ensure that the interface fluctuation in the functional material layer grown on the substrate 1 is small to ensure the quality of the Josephson junction.

[0079] Specifically, the thickness of the substrate 1 can be selected according to actual conditions and is not limited here. The buffer layer 12 is used to reduce the undulation of the interface in the functional material layer formed on the base layer 11. Its thickness can be adjusted as needed and is not limited here. In this embodiment, the thickness of the substrate 1 is selected to be 0.625 mm to meet the needs of subsequent process equipment.

[0080] Specifically, Figure 3, which is a schematic diagram of the cross-sectional structure after the functional material layer 2 is formed, wherein the functional material layer 2 includes the NbN bottom film 21, the metal barrier layer 22 and the NbN top film 23 stacked upward.

[0081] Specifically, the NbN bottom layer 21, the metal barrier layer 22 and the NbN top layer 23 stacked upward are formed by direct current reactive magnetron sputtering or other suitable methods.

[0082] Specifically, the thickness of the NbN bottom film 21 is in the range of 150 nm to 250 nm, and the thickness of the NbN top film 23 is in the range of 150 nm to 250 nm. Preferably, the thickness of the NbN bottom film 21 is 200 nm, and the thickness of the NbN top film 23 is 200 nm.

[0083] Specifically, the thickness of the metal barrier layer 22 is in the range of 5 nm to 30 nm. The thicker metal barrier layer 22 avoids the fluctuation of the interface in the functional material layer 2 and ensures the quality of the functional material layer 2 .

[0084] As an example, the material of the metal barrier layer 22 includes TiN x 、TaN x 、NbN x At least one of them may also be other suitable materials, wherein x is an atomic component of the N element, and 1>x>0, so that the metal barrier layer 22 is metallic at low temperature.

[0085] Specifically, the metal barrier layer 22 , the NbN bottom film 21 and the NbN top film 23 are all nitrides, which avoids the formation of compounds at the superconducting metal / normal metal interface and is conducive to obtaining the functional material layer 2 with a clear interface.

[0086] Specifically, the NbN bottom film 21 and the NbN top film 23 have low-temperature superconducting properties, and the metal barrier layer 22 has low-temperature metal properties. In this embodiment, the NbN bottom film 21, the metal barrier layer 22 and the NbN top film 23 are stacked up in sequence by a DC reactive magnetron sputtering method, wherein when forming the NbN bottom film 21 and the NbN top film 23, the ratio of Nb to N in the NbN bottom film 21 and the NbN top film 23 is controlled to obtain the NbN bottom film 21 and the NbN top film 23 having low-temperature superconducting properties, and when forming the metal barrier layer 22, the ratio of each component in the metal barrier layer 22 is controlled to make the metal barrier layer 22 have low-temperature metal properties. For example, when the material of the metal barrier layer 22 is metal nitride TiN x 、TaN x or NbNx When the process parameters are adjusted, an active gas (N2) is mixed into the inert protective gas, and the amount of the active gas mixed is controlled so that the stoichiometric ratio of the metal elements in the metal barrier layer 22 is higher than the stoichiometric ratio of the N element.

[0087] Specifically, the NbN bottom film 21 and the NbN top film 23 both have a high superconducting transition temperature (T c ~16.5K), large superconducting energy gap (Δ~3meV) and large inductance superconducting films are beneficial to improving the integration of circuits, reducing the energy consumption of circuits and increasing the characteristic frequency of circuits.

[0088] Please see again Figures 4 to 8 , perform step S2 and step S3: etch the functional material layer 2 to form a functional layer 24 including a bottom electrode 241, a junction barrier layer 242 and a top electrode 243, and form a first isolation layer 3 covering the exposed surface of the functional layer 24 and the upper surface of the buffer layer 12; form a first contact hole 31 with the top electrode 243 exposed at the bottom and a second contact hole 32 with the bottom exposed at the bottom of the bottom electrode 241 in the first isolation layer 3, and form a wiring layer 4 covering the upper surface of the first isolation layer 3 and filling the first contact hole 31 and the second contact hole 32.

[0089] As an example, the NbN top film 23 , the metal barrier layer 22 and the NbN bottom film 21 are first etched in one step to obtain the bottom electrode 241 , and then the NbN top film 23 and the metal barrier layer 22 are etched in one step to obtain the junction barrier layer 242 and the top electrode 243 .

[0090] Specifically, Figure 4 As shown, it is a schematic diagram of the cross-sectional structure after etching the functional material layer 2 to obtain the bottom electrode 241. The functional material layer 2 is synchronously etched by step exposure and inductively coupled plasma etching or other suitable methods to form the bottom electrode 241, and the etching gas can be CF4 and Ar.

[0091] Specifically, Figure 5 As shown, it is a schematic diagram of the cross-sectional structure after the junction barrier layer 242 and the top electrode 243 are formed. The NbN top film 23 and the metal barrier layer 22 are synchronously etched by step exposure and inductively coupled plasma etching or other suitable methods to form the top electrode 243 and the junction barrier layer 242, which ensures the steepness and uniformity of the side walls of the top electrode 243 and the junction barrier layer 242, and effectively avoids the uneven distribution of the top electrode 243 and the junction barrier layer 242 in the vertical direction, and the etching gas can be CF4 and Ar.

[0092] As an example, the shape of the junction barrier layer 242 includes a circle or other suitable shapes, and the thickness of the junction barrier layer 242 ranges from 5 nm to 30 nm.

[0093] Specifically, the bottom electrode 241, the junction barrier layer 242 and the top electrode 243 constitute a superconductor / normal metal / superconductor (SNS) Josephson junction, and the Josephson junction is an intrinsically damped SNS Josephson junction, which does not require an external parallel resistor, thereby reducing the planar area of ​​the Josephson junction.

[0094] Specifically, Figure 6 , which is a schematic diagram of the cross-sectional structure after the first isolation layer 3 is formed, and the material of the first isolation layer 3 includes silicon dioxide, silicon nitride or other suitable insulating materials.

[0095] Specifically, the first isolation layer 3 is formed by physical vapor deposition, chemical vapor deposition or other suitable methods.

[0096] Specifically, Figure 7 , which is a schematic diagram of the cross-sectional structure after the first contact hole 31 and the second contact hole 32 are formed, is formed by step exposure and reactive ion etching or other suitable methods.

[0097] Specifically, the opening diameter of the first contact hole 31 is 1.2 μm to 2.6 μm, and the opening diameter of the second contact hole 32 is 1.2 μm to 2.6 μm.

[0098] Specifically, the top electrode 243 is exposed at the bottom of the first contact hole 31 for leading out the top electrode 243 , and the bottom of the second contact hole 32 is exposed at the bottom electrode 241 for leading out the bottom electrode 241 .

[0099] Specifically, Figure 8 , which is a schematic diagram of the cross-sectional structure after forming the wiring layer 4, the material of the wiring layer 4 includes NbN superconducting material or other suitable conductive materials. In this embodiment, the wiring layer 4 uses NbN low-temperature superconducting material to reduce the energy consumption of the circuit.

[0100] Specifically, the method for forming the wiring layer 4 includes DC reactive magnetron sputtering or other suitable methods, the wiring layer 4 fills the first contact hole 31 and the second contact hole 32, and the wiring layer 4 contacts the upper surface of the top electrode 243 through the first contact hole 31, and the wiring layer 4 contacts the upper surface of the bottom electrode 241 through the second contact hole 31.

[0101] Specifically, the thickness of the wiring layer 4 is in the range of 300 nm to 400 nm. Preferably, the thickness of the wiring layer is 350 nm.

[0102] Please see again Figures 9 and 10 , perform step S4 and step S5: etch the wiring layer 4 to form a first wiring portion 41 filling the first contact hole 31 and a second wiring portion 42 filling the second contact hole 32, and form a second isolation layer 5 on the exposed surfaces of the first wiring portion 41 and the second wiring portion 42 and the upper surface of the first isolation layer 3; form a first through hole 51 with the first wiring portion 41 exposed at the bottom and a second through hole 52 with the second wiring portion 42 exposed at the bottom in the second isolation layer 5, and form a grounding material layer covering the upper surface of the second isolation layer 5 and filling the first through hole 51 and the second through hole 52.

[0103] Specifically, Fig. 9 , which is a schematic diagram of the cross-sectional structure after the first wiring portion 41 and the second wiring portion 42 are formed. The method of forming the first wiring portion 41 and the second wiring portion 42 includes step exposure and inductively coupled plasma etching or other suitable methods.

[0104] As an example, the first wiring portion 41 is electrically connected to the top electrode 243 through the first contact hole 31 , and the second wiring portion 42 is electrically connected to the bottom electrode 241 through the second contact hole 32 .

[0105] Specifically, the second isolation layer 5 is formed by chemical vapor deposition, physical vapor deposition or other suitable methods.

[0106] Specifically, the material of the second isolation layer 5 includes silicon dioxide, silicon nitride or other suitable insulating materials.

[0107] Specifically, the thickness of the second isolation layer 5 is in the range of 400 nm to 500 nm. Preferably, the thickness of the second isolation layer 5 is 450 nm.

[0108] Specifically, Fig.10 , which is a schematic diagram of the cross-sectional structure after the first through hole 51 and the second through hole 52 are formed, the second isolation layer 5 is etched by step exposure and inductively coupled plasma etching or other suitable methods to form the first through hole 51 and the second through hole 52.

[0109] Specifically, the first through hole 51 and the first through hole 52 are used to lead out the first wiring portion 41 and the second wiring portion 42 .

[0110] Specifically, the grounding material layer 6 is formed by DC reactive magnetron sputtering or other suitable methods.

[0111] Specifically, the thickness of the grounding material layer 6 is in the range of 500 nm to 600 nm. Preferably, the thickness of the grounding material layer 6 is 550 nm.

[0112] Specifically, the grounding material layer 6 is made of low-temperature superconducting NbN or other suitable conductive materials.

[0113] Please see again Fig.11 , perform the step 6: etch the grounding material layer 6 to form a first grounding material layer 61 filling the first through hole 51 and a second grounding material layer 62 filling the second through hole 52 .

[0114] Specifically, the grounding material layer 6 is etched by step exposure and inductively coupled plasma etching or other suitable methods to form the first grounding material layer 61 and the second grounding material layer 62 .

[0115] As an example, the first grounding material layer 61 is electrically connected to the first wiring portion 41 through the first through hole 51 , and the second grounding material layer 62 is electrically connected to the second wiring portion 42 through the second through hole 52 .

[0116] The method for preparing a superconducting integrated circuit with a NbN SNS Josephson junction of this embodiment adopts the substrate 1 composed of a silicon base layer and the buffer layer 11, thereby avoiding the film boundary fluctuation in the functional material layer 2 formed directly on the silicon substrate. The obtained functional material layer 2 has high quality and is compatible with the mature process of preparing semiconductor devices on a silicon substrate, which is conducive to reducing the area occupied by the Josephson junction and then improving the integration of the circuit. The low-temperature superconducting NbN material with a high transition temperature and large inductance is used as the top electrode 243 and the bottom electrode 241 of the superconducting integrated circuit with the NbN SNS Josephson junction, which increases the operating temperature and reduces the power consumption of the circuit. In addition, the junction barrier layer 242 of nitride is used as the barrier layer of the Josephson junction, which avoids the formation of compounds at the interface between the junction barrier layer 242 and the top electrode 243 and the bottom electrode 241, which is conducive to obtaining the functional layer 24 with a clear interface.

[0117] Embodiment 2

[0118] This embodiment provides a superconducting integrated circuit having a NbN SNS Josephson junction, such as Fig.11, which is a schematic diagram of the cross-sectional structure of the superconducting integrated circuit with NbN SNS Josephson junction, wherein the superconducting integrated circuit with NbN SNS Josephson junction comprises a substrate 1, a functional layer 24, a first isolation layer 3, a first wiring portion 41, a second wiring portion 42, a second isolation layer 5, a first grounding material layer 61 and a second grounding material layer 62, wherein the substrate 1 comprises a base layer 11 and a buffer layer 12 located on the base layer 11, the functional layer 24 is located on the upper surface of the buffer layer 12 and comprises a bottom electrode 241, a junction barrier layer 242 and a top electrode 243 stacked upward, the material of the bottom electrode 241 comprises NbN, the junction barrier layer 242 comprises a metal barrier layer, the material of the top electrode 243 comprises NbN, the first isolation layer 3 covers the upper surface of the buffer layer 12 and the exposed surface of the functional layer 24, and the first isolation layer 3 covers the upper surface of the buffer layer 12 and the exposed surface of the functional layer 24, and the first isolation layer 3 covers the upper surface of the buffer layer 12 and the exposed surface of the functional layer 24. The isolation layer 3 is provided with a first contact hole 31 exposing the top electrode 243 and a second contact hole 32 exposing the bottom electrode 241, the first wiring portion 41 fills the first contact hole 31, and the second wiring portion 41 fills the second contact hole 32, the second isolation layer 5 covers the upper surface of the first isolation layer 3 and the exposed surfaces of the first wiring portion 41 and the second wiring portion 42, and the second isolation layer 5 is provided with a first through hole 51 exposing the first wiring portion 41 and a second through hole 52 exposing the second wiring portion 42, the first grounding material layer 61 is located on the upper surface of the second isolation layer 5 and fills the first through hole 51, and the second grounding material layer 62 is located on the upper surface of the second isolation layer 5 and fills the second through hole 52.

[0119] As an example, the material of the base layer 11 includes silicon or other suitable materials, and the material of the buffer layer 12 includes silicon dioxide or other suitable materials.

[0120] As an example, the bottom electrode 241 , the junction barrier layer 242 , and the top electrode 243 form an overdamped NbNSNS Josephson junction.

[0121] As an example, the material of the junction barrier layer 242 includes TiN x 、TaN x 、NbN x At least one of , wherein x is an atomic component of the N element, and 1>x>0.

[0122] Specifically, the superconducting integrated circuit with the NbN SNS Josephson junction does not need to be connected in parallel with an external resistor, thereby reducing the junction area and improving the integration of the circuit.

[0123] As an example, the thickness range of the bottom electrode 241 is 150nm~250nm, the thickness range of the junction barrier layer 242 is 5nm~30nm, the diameter range of the junction barrier layer 242 is 1.6μm~3.0μm, the thickness range of the top electrode 243 is 150nm~250nm, the thickness range of the first isolation layer 3 is 200nm~300nm, and the thickness range of the second isolation layer 5 is 500nm~600nm.

[0124] Specifically, the first grounding material layer 61 and the second grounding material layer 62 are used to reduce interference between signals and shield external magnetic field noise.

[0125] Specifically, the thicker junction barrier layer 242 as the barrier layer of the Josephson junction is beneficial to improving the coverage and repeatability of the barrier layer.

[0126] Specifically, the low-temperature superconducting NbN material is the microstrip line of the superconducting integrated circuit, which saves the area of ​​the microstrip line and further improves the integration of the circuit.

[0127] The superconducting integrated circuit with NbN SNS Josephson junction of this embodiment uses the intrinsically damped NbNSNS Josephson junction unit as the basic unit of the circuit, without external resistance, reducing the area occupied by the Josephson junction and improving the integration of the superconducting integrated circuit. The thicker junction barrier layer 242 is used as the barrier layer of the Josephson junction, which improves the coverage and repeatability of the barrier layer in the Josephson junction. The low-temperature superconducting NbN material is used as the microstrip line of the superconducting integrated circuit, which saves the area of ​​the microstrip line and further improves the integration of the circuit.

[0128] In summary, the superconducting integrated circuit with NbN SNS Josephson junction of the present invention and its preparation method form a buffer layer on the silicon base layer, and then form a functional material layer on the buffer layer, so as to form a high-quality functional material layer on the silicon substrate, and realize the compatibility of the preparation process with the mature process of preparing semiconductor devices on silicon substrates, which is conducive to reducing the area occupied by the Josephson junction, and then improving the integration of the circuit. At the same time, the low-temperature superconducting NbN material is used as the top electrode and bottom electrode of the Josephson junction and the microstrip line of the superconducting integrated circuit, which increases the operating temperature, reduces the power consumption of the circuit, saves the area of ​​the microstrip line, and further improves the integration of the circuit. In addition, the use of nitride as the junction barrier layer avoids the formation of compounds at the interface in the functional layer, which is conducive to obtaining a functional layer with a clear interface. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0129] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction, characterized in that: The following steps are involved: A substrate is provided, and a functional material layer is formed on the substrate, which includes a NbN bottom film, a metal barrier layer and a NbN top film in order from bottom to top, wherein the metal barrier layer is formed by a DC reactive magnetron sputtering method, the substrate includes a base layer and a buffer layer located on the base layer, and the material of the metal barrier layer includes TiN x 、TaN x 、NbN x At least one of , wherein x is an atomic component of element N, and 1>x>0; Etching the functional material layer to form a functional layer including a bottom electrode, a junction barrier layer and a top electrode, and forming a first isolation layer covering the exposed surface of the functional layer and the upper surface of the buffer layer, wherein the thickness of the junction barrier layer is in the range of 5 nm to 30 nm; forming a first contact hole whose bottom exposes the top electrode and a second contact hole whose bottom exposes the bottom electrode in the first isolation layer, and forming a wiring layer covering the upper surface of the first isolation layer and filling the first contact hole and the second contact hole; Etching the wiring layer to form a first wiring portion filling the first contact hole and a second wiring portion filling the second contact hole, and forming a second isolation layer on the exposed surfaces of the first wiring portion and the second wiring portion and the upper surface of the first isolation layer; forming a first through hole whose bottom exposes the first wiring portion and a second through hole whose bottom exposes the second wiring portion in the second isolation layer, and forming a grounding material layer covering the upper surface of the second isolation layer and filling the first through hole and the second through hole; The grounding material layer is etched to form a first grounding material layer filling the first through hole and a second grounding material layer filling the second through hole.

2. The method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction according to claim 1, characterized in that: The material of the base layer includes silicon, and the material of the buffer layer includes silicon dioxide.

3. The method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction according to claim 1, characterized in that: The NbN top film, the metal barrier layer and the NbN bottom film are first etched in one step to obtain the bottom electrode, and then the NbN top film and the metal barrier layer are etched in one step to obtain the junction barrier layer and the top electrode.

4. The method for preparing a superconducting integrated circuit having a NbN SNS Josephson junction according to claim 1, characterized in that: The junction barrier layer has a shape including a circle.

5. A superconducting integrated circuit having a NbN SNS Josephson junction, characterized in that: include: A substrate, comprising a base layer and a buffer layer located on the base layer; The functional layer is located on the upper surface of the buffer layer and includes a bottom electrode, a junction barrier layer and a top electrode stacked upward, the material of the bottom electrode includes NbN, the junction barrier layer includes a metal barrier layer, the material of the top electrode includes NbN, the thickness of the junction barrier layer ranges from 5nm to 30nm, the metal barrier layer is formed by a DC reactive magnetron sputtering method, and the material of the metal barrier layer includes TiN x 、TaN x 、NbN x At least one of , wherein x is an atomic component of element N, and 1>x>0; a first isolation layer, covering the upper surface of the buffer layer and the exposed surface of the functional layer, and having a first contact hole for exposing the top electrode and a second contact hole for exposing the bottom electrode; a first wiring portion and a second wiring portion, wherein the first wiring portion fills the first contact hole, and the second wiring portion fills the second contact hole; a second isolation layer covering the upper surface of the first isolation layer and the exposed surfaces of the first wiring portion and the second wiring portion, and the second isolation layer is provided with a first through hole for exposing the first wiring portion and a second through hole for exposing the second wiring portion; A first grounding material layer and a second grounding material layer, wherein the first grounding material layer is located on the upper surface of the second isolation layer and fills the first through hole, and the second grounding material layer is located on the upper surface of the second isolation layer and fills the second through hole.

6. The superconducting integrated circuit having a NbN SNS Josephson junction according to claim 5, characterized in that: The material of the base layer includes silicon, and the material of the buffer layer includes silicon dioxide.

7. The superconducting integrated circuit having a NbN SNS Josephson junction according to claim 5, characterized in that: The bottom electrode, the junction barrier layer and the top electrode form an overdamped NbN SNS Josephson junction.

8. The superconducting integrated circuit having a NbN SNS Josephson junction according to claim 5, characterized in that: The thickness of the bottom electrode ranges from 150nm to 250nm, the diameter of the junction barrier layer ranges from 1.6μm to 3.0μm, the thickness of the top electrode ranges from 150nm to 250nm, the thickness of the first isolation layer ranges from 200nm to 300nm, and the thickness of the second isolation layer ranges from 500nm to 600nm.

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