Analog-to-digital converter arrangement, sensor system and method for analog-to-digital conversion

Abstract

Embodiments of the present disclosure relate to an analog-to-digital converter device, a sensor system and a method for analog-to-digital conversion. A device and a method for analog-to-digital conversion are provided as well as a corresponding system with a sensor and such a device. Here, the demodulation is performed without variable preamplification, followed by an analog-to-digital conversion which is also continuous over time at least in a time segment, the analog-to-digital conversion also using chopper technology.

Description

Technical Field

[0001] This application relates to an apparatus for analog-to-digital conversion, a sensor system having such an apparatus for converting analog signals output by a sensor, and a corresponding method. Background Technology

[0002] In many applications, analog signals are converted into digital signals and then further processed digitally. One example is sensor applications, where physical variables such as velocity and position are acquired using sensors, the sensors output corresponding analog signals, which are then converted into digital signals for further processing.

[0003] In some cases, the analog signal to be converted can have a relatively high dynamic range, such as with respect to the voltage of the signal. An example of a sensor that can have such a high dynamic range in its output signal is an inductive motion sensor. In this sensor, a high-frequency magnetic field is generated by feeding an excitation signal to an excitation coil. The magnetic field is measured using multiple acquisition coils. The magnetic coupling between the excitation coil and the acquisition coil depends on, for example, the position of a rotor equipped with inductance. The excitation signal can have a frequency in the range of 3.5 MHz. For example, the voltage output by the receiving coil can be in the range of 4 to 120 mV, corresponding to a factor of 30 between the lowest and highest voltages. Along with the high frequency (e.g., 3.5 MHz), this presents challenges for subsequent demodulation (converting the sensor signal to a lower frequency) and analog-to-digital conversion.

[0004] Traditional methods use one or more variable gain controlled (AGC) amplifiers. The variable gain is adjusted based on the level of the input signal to provide a signal with a reduced dynamic range, which is ultimately converted by an analog-to-digital converter. Such amplifiers are typically combined with low-pass filters to suppress signal convolution effects (aliasing) and filter out unwanted high-frequency components. These low-pass filters require a corresponding chip area. Variable gain amplifiers also require sufficient chip space and increase current consumption.

[0005] Other conventional methods require channel filters to filter out frequencies outside the useful frequency range (e.g., the mentioned 3.5MHz) and / or require buffers in front of the analog-to-digital converter circuitry, which can lead to offset errors and additional current consumption. Summary of the Invention

[0006] Analog-to-digital converter apparatus, systems, and methods according to the present invention are provided.

[0007] According to an embodiment, an apparatus for analog-to-digital conversion is provided, comprising: A demodulator is used to demodulate an input signal with a demodulation frequency without requiring a variable preamplifier. A chopper modulator, connected downstream of the demodulator, is used to chop the signal. An analog-to-digital converter, connected downstream of a chopper modulator and operating continuously over time, at least for a given time period, and A chopper demodulator is used to chop signals.

[0008] According to another embodiment, an apparatus for analog-to-digital conversion is provided, comprising: An analog-to-digital converter, operating continuously over time at least during a time period, the analog-to-digital converter having: At least one integrator capacitor, said at least one integrator capacitor depending on the chopper signal connected to the remaining analog-to-digital converter, wherein the chopper signal has a frequency equal to the demodulation frequency used to demodulate the input signal of the device, and A chopper demodulator is used to chop a signal.

[0009] According to a further embodiment, a system is provided, comprising: Sensors, and The apparatus for analog-to-digital conversion described above is used to process signals from the sensor.

[0010] According to yet another embodiment, an analog-to-digital conversion method is provided, comprising: Direct demodulation of the input signal without the need for a variable preamplifier, and

[0011] At least during the time period, the demodulated input signal is subjected to time-continuous analog-to-digital conversion using chopper modulation and chopper demodulation with chopper frequency.

[0012] According to another embodiment, a method for analog-to-digital conversion is provided, comprising performing time-continuous analog-to-digital conversion on an input signal at least over a time period, wherein the time-continuous analog-to-digital conversion at least over the time period includes the operation of an integrator capacitor based on a chopping signal, wherein the chopping signal has a chopping frequency equal to the demodulation frequency used to demodulate the input signal to be converted.

[0013] The above overview represents only a brief summary of some embodiments and should not be construed as limiting. In particular, other embodiments may have features other than those described above. Attached Figure Description

[0014] Figure 1 This is a block diagram of the system according to an embodiment.

[0015] Figure 2 This is a diagram of the system according to an embodiment.

[0016] Figure 3 This is a circuit diagram of the system according to an embodiment.

[0017] Figure 4 Example signals are shown to illustrate the working principle of some embodiments.

[0018] Figure 5 Example signals are shown to illustrate the working principle of some embodiments.

[0019] Figure 6 A schematic circuit diagram is shown to illustrate a time-continuous analog-to-digital converter for explaining some embodiments.

[0020] Figure 7 It was shown as Figure 6 A simplified circuit diagram of an analog-to-digital converter with a switched input capacitor is provided as a comparative example.

[0021] Figure 8 A circuit diagram of a system according to an embodiment is shown.

[0022] Figure 9 A circuit diagram of a system according to an embodiment is shown.

[0023] Figure 10 A circuit diagram of a system according to an embodiment is shown.

[0024] Figure 11 A circuit diagram of a system according to an embodiment is shown.

[0025] Figure 12 A diagram with signals is shown to illustrate some embodiments.

[0026] Figure 13 It is a graph used to illustrate the prediction of the next starting value.

[0027] Figure 14 This is a flowchart illustrating a method according to some embodiments.

[0028] Figure 15A This is a circuit diagram of the system according to an embodiment.

[0029] Figure 15B It shows Figure 15A Voltage / current converter.

[0030] Figure 15C It is used for explanation Figure 15A A diagram of the system.

[0031] Figure 16A This is a circuit diagram of the system according to an embodiment.

[0032] Figure 16B It shows Figure 16A Operational amplifier.

[0033] Figures 17A to 17CVarious embodiments for synchronization signals are shown.

[0034] Figures 18 to 22 These are circuit diagrams of systems according to various embodiments. Detailed Implementation

[0035] Various embodiments are explained in detail below. These embodiments should not be construed as limiting, but are for illustrative purposes only. For example, some embodiments are described as having multiple features (components, apparatus, method steps, processes, etc.). In other embodiments, some of these features may be omitted or replaced by alternative features. Features of different embodiments may be combined. Variations and modifications or special parts of the apparatus described for one embodiment may also be applied to other embodiments, and therefore will not be explained again.

[0036] Unless otherwise stated, connection and coupling refer to electrical connection and coupling. Such connection or coupling can be modified, for example by adding components or removing parts, as long as the basic function of the connection or coupling, such as providing voltage, transmitting electrical signals, or transmitting information, is not significantly affected.

[0037] In addition to the features explicitly shown, other features may be provided, such as those commonly used in sensor systems and corresponding circuits.

[0038] Figure 1 A block diagram of a system having an analog-to-digital converter device 11 according to an embodiment is shown.

[0039] Figure 1 The system has a signal source 10 that outputs an analog signal si. The analog signal si may have a relatively high frequency, such as greater than 1 MHz, greater than 3 MHz, or, for example, about 3.5 MHz, but is not limited thereto. In some embodiments, the signal source 10 may be a sensor. In particular, the signal source 10 may be an inductive sensor, as will be referred to later. Figure 2 Explanation.

[0040] In some embodiments, the signal si may have a large dynamic range, for example, at least 10 times or at least 20 times between the minimum amplitude (e.g., minimum voltage) and the maximum amplitude (e.g., maximum voltage).

[0041] The signal si is directly fed to the demodulator 12 in device 11. In this case, "direct" means that no variable preamplification is performed to accommodate or reduce the dynamic range of the signal si. However, fixed amplification or other signal processing may be performed, for example, within the signal source 10. The demodulator mixes the signal si with the demodulation frequency fdemod to obtain a signal in a lower frequency band. This demodulation technique is known from the demodulation of communication signals, where, for example, a high-frequency signal is converted to a baseband signal by a demodulator. The frequency fdemod may correspond to the average frequency of the signal si. The demodulator 12 may be a passive demodulator.

[0042] Downstream of demodulator 12 is a time-continuous analog-to-digital converter 14, which has a chopper modulator 13 at its input and a chopper demodulator 15 at its output. The chopper modulator and demodulator chop the signal according to a chopping frequency fchop. This chopping technique is specifically used for offset compensation of the analog-to-digital converter 14. For simplicity, fchop and fdemod are used below to represent the signal and the signal frequency, respectively. The frequency fchop can be adapted to the demodulation frequency fdemod. Therefore, the frequency fdemod can be an integer multiple of the frequency fchop, wherein optionally, the pulse, rising edge, etc., of the signal fdemod can also coincide with one of the pulses, rising edges, etc., of the signal fchop. Furthermore, the frequency fdemod can be synchronized with the clock frequency fclock (corresponding to the sampling frequency fs) used by the analog-to-digital converter 14, such that fclock is an integer multiple of fdemod. This helps to avoid frequency discrepancies.

[0043] In the context of this application, a continuous-time analog-to-digital converter (ADC) is an analog-to-digital converter that does not operate based on a single sample value at its input, but rather continuously processes the signal present at its input, at least for some time intervals. "At least for some time intervals" in this context means that, in some embodiments explained later, different inputs are processed alternately by means of multiplexing, where a signal from one input is processed only during certain time intervals, but can be continuously converted within those intervals. In this case, a continuous-time ADC is also called an incremental converter. Hereinafter, for simplicity, the term continuous-time ADC will be used primarily, where it can be understood that it can also be a converter that operates continuously over time only during certain time intervals, i.e., an incremental converter, for example.

[0044] In some embodiments, an inherent low-pass filter is achieved by using a passive demodulator and / or a continuous-time analog-to-digital converter, utilizing chopping through chopper modulator 13 and chopper demodulator 15, thus eliminating the need for an additional low-pass filter. Furthermore, the combination of continuous-time analog-to-digital converter 14 and demodulator 12 enables a sufficiently large dynamic range to process the signal, thus eliminating the need for an amplifier with variable gain. The reason for this will be explained in more detail later.

[0045] Device 11 then outputs a digital signal sdig, which can be further processed by subsequent circuitry. If the signal source 10 is, for example, a sensor, then the signal sdig characterizes the physical variables acquired by the sensor, and by evaluating the signal sdig, a control or regulation process can then be performed, for example, based on the physical variables.

[0046] This analog-to-digital converter device can be used, for example, in sensor systems that utilize inductive sensors. According to an embodiment, such a sensor system... Figure 2 As shown in the image.

[0047] Figure 2 The system's inductive sensor has an excitation coil 20, a moving inductor 21, and three receiving coils 22A, 22B, and 22C. The moving inductor 21 can be implemented, for example, by a slotted metal disk fixed to the element whose movement is to be measured. Figure 2 An example of a system could be a rotor of an electric motor, to which inductor 21 is attached.

[0048] The output currents Inu, Inv, and Inw of the receiving coils 22A, 22B, and 22C are received by the controller 23, and therein, by means of the analog-to-digital converter device of the controller 23 according to the embodiment, for example, by means of... Figure 1 The analog-to-digital converter device 11 or one of the analog-to-digital converter devices described below is digitized. Furthermore, the controller 23 has a digital signal processor (DSP), which can be used to further process the digitized signal if needed. Additionally, the controller 23 has an oscillator (not shown) that outputs signals LCIop and LCIun to supply the excitation coil 22. Signals LCIop and LCIun are signals with relatively high frequencies, for example, greater than 1 MHz or greater than 3 MHz, such as approximately 3.5 MHz. As shown, the leads of the excitation coil 20 are grounded via capacitors 24A and 24B. The controller 23 is powered by a power supply voltage 25 and coupled to ground (gnd).

[0049] During operation, high-frequency signals LCIop and LCIun are supplied to the excitation coil 20 and coupled to the receiving coils 22A, 22B, and 22C via inductive coupling (i.e., through the action of the magnetic field generated by the excitation coil 20 on the receiving coils 22A, 22B, and 22C). The coupling strength varies depending on the position of the inductor 21, for example, depending on the rotation angle of the rotor to which the inductor 21 is attached. This generates time-varying signals Inu, Inv, and Inw, from which the position of the inductor 21 can be deduced, and thus the position of the moving element, such as the rotor. The corresponding output signal sdig represents the position of the moving element, such as the angular position of the rotor.

[0050] The changing coupling leads to, for example Figure 2 The sensors shown have relatively large dynamic ranges for signals Inu, Inv, and Inw, which can then generate voltage signals, for example, in the range of 4 to 120 mV, through corresponding input resistors.

[0051] In several of the following embodiments, this inductive sensor is used as an example. However, this should not be construed as limiting, and other types of signal sources besides inductive sensors may also be used in the embodiments described below.

[0052] Figure 3 A system according to another embodiment is shown.

[0053] exist Figure 3 In this embodiment, the device for analog-to-digital conversion according to the embodiment receives signals from the receiving coil 30 at input pads 31A, 31B. The receiving coil 30 may be, for example, Figure 2 One of the receiving coils 22A, 22B, and 22C. The signal from the receiving coil 30 is fed to the demodulator 30 via input resistors 32A and 32B, which mixes the input signal with the frequency fdemod and thus demodulates it. The frequency fdemod can be the excitation coil used (such as...). Figure 2 The excitation frequency of the excitation coil 20 is synchronized with and / or corresponds to it. Specifically, fdemod can correspond to the frequency fLC. fLC is the resonant frequency of the LC oscillator circuit, determined by the excitation coil used (such as...). Figure 2 The excitation coil 20 and an external capacitor (e.g., 3.5MHz) on the circuit board are combined to form the resonant frequency. In various embodiments, this resonant frequency is also used for demodulation, i.e., fLC = fdemod. For this purpose, in various embodiments, the voltage zero-crossing of the sinusoidal LC oscillation of the LC resonant circuit is used to switch the digital fdemod frequency so that the frequency and phase are matched with the demodulation.

[0054] Input resistors 32A and 32B may have resistance values, for example, between 100Ω and 1MΩ, such as between 300Ω and 500Ω, such as approximately 400Ω.

[0055] The voltage value corresponding to the demodulated input signal is then applied to capacitor 34 and averaged there over time. If the input amplitude of the signal received by receiving coil 30 does not change, a DC average value plus a superimposed AC residual voltage is established at capacitor 34 because the filtering at twice the modulation frequency (after rectification) is not particularly high. Instead, the input signal is actually integrated at capacitors 310A and 310B, which will be discussed further below.

[0056] Capacitors 35A and 35B characterize capacitance to ground, including parasitic capacitance. Figure 3 In the embodiments, with Figure 1 Similar to the previous embodiment, demodulation is performed without gain, and in particular without variable gain. Input resistors 32A and 32B, together with capacitor 34, form an RC filter with low-pass characteristics. Therefore, no additional low-pass filter is needed, as low-pass filtering for filtering out high-frequency interference signals can be achieved in this way.

[0057] The signal demodulated in this way is then fed to a chopper modulator 36 operating at frequency fchop, as referenced above. Figure 1 As already explained, this frequency is synchronized with the frequency fdemod. For example, fdemod can be an integer multiple of fchop. Alternatively, fdemod can be the same as the frequency fLC mentioned above.

[0058] Therefore, a chopper input voltage Vin is provided for the time-continuous Σ-Δ analog-to-digital converter (CT-Σ-Δ-ADC) 37. Any conventional implementation of a continuous-time Σ-Δ converter can be used here. Figure 3 In this embodiment, the time-continuous Σ-Δ analog-to-digital converter 37 has an integrator using capacitors 310A and 310B. These capacitors 310A and 310B are connected to the rest of the converter via a chopper 39, which also operates at the chopper frequency fchop. For example, capacitors 310A and 310B integrate the current integrated through the voltage-to-current conversion in the input stage of the analog-to-digital converter 37. This means that the DC input voltage at the input of the analog-to-digital converter 37 would result in an infinitely increasing integrated voltage at capacitor 310. However, the digital-to-analog converter included in the Σ-Δ analog-to-digital converter prevents this from happening through negative feedback, which will be described in detail later, because the voltage sign in the comparator determines the direction of integration in each analog-to-digital conversion.

[0059] The signal output from the time-continuous Σ-Δ analog-to-digital converter 37 is also demodulated in the chopper demodulator 38 at the chopper frequency fchop, which in the digital case corresponds to multiplication with alternating +1 and -1.

[0060] In some embodiments, as will be referred to later Figure 8 To explain in more detail, time-continuous Σ-Δ analog-to-digital converters have relatively high input impedances, such as >100Ω, for example in the 250Ω range, and typically have a feedback loop, as in Σ-Δ converters.

[0061] For example, a 6-bit signal with an output frequency of 10MHz can be output as an output signal, where other bit widths and frequencies are also possible.

[0062] Now refer to Figure 4 and 5 Explain the working principle of demodulator 33 and capacitor 34.

[0063] Figure 4 The input signal of the chopper modulator 36 for various filter adjustments of the low-pass filter formed by resistors 32A, 32B and capacitor 34 is shown. The modulation frequency of the input signal (corresponding to...) Figure 2 The frequency of the signal LCiop, LCion transmitted by the excitation coil 20 is assumed to be 3.5MHz.

[0064] Curve 40 shows the signal without capacitor 34, i.e., without low-pass filtering. Curve 41 shows the signal with a low-pass filter angular frequency of 3.5 MHz, and curve 42 shows an example signal with an angular frequency of 1 MHz. It is assumed that the signal amplitude from receiving coil 30 is constant. It can be seen that during filtering, the signal stabilizes near a fixed value corresponding to the value of the signal to be converted.

[0065] Demodulation is also available Figure 5 As shown in [the image]. Figure 5 In the diagram, curve 51 shows an example of the input signal for demodulator 33, namely the signal provided by receiving coil 30. Curve 52 shows an example of a signal with frequency fdemod being fed to demodulator 33. Curve 50 shows the input signal for chopper 36, which is generated by demodulation using filtering through capacitor 34 and resistors 32A and 32B.

[0066] The following describes the use of continuous-time analog-to-digital converters (such as...) Figure 3 The advantages and effects of the continuous-time Σ-Δ analog-to-digital converter (37) compared to the following analog-to-digital converter, which uses switched capacitors to sample the input signal and therefore cannot operate continuously, are explained below. Figure 6A schematic circuit diagram of the input stage of a continuous-time analog-to-digital converter is shown, while Figure 7 A schematic circuit diagram of the input stage of an analog-to-digital converter with a switched input capacitor is shown.

[0067] exist Figure 6 In this diagram, voltage source 62 represents the generation of the input voltage Vs used in the converter. This input voltage is supplied to input amplifier 60, which has a transconductance gm. Input amplifier 60 is characterized by transistor pairs 63A and 63B, current sources 64A and 64B that generate current Id respectively, current source 65, and current source 66 for the output signal of output amplifier 60. This characterization should be understood as illustrative only. The output signal is integrated into integrator capacitor 67 with a value Cint.

[0068] To generate low noise, the inverse transconductance must be 1 / gm < the resistance value Rs of the input resistor 61. Therefore, for example, a noise figure NF of +1 dB is required, such that the transconductance of the input stage satisfies the following relationship:

[0069] .

[0070] To optimize noise, transistors 63A and 63B must operate with weak inversion to obtain the best possible ratio of gm to current Id. In this case, 1 / gm becomes , In this equation, n, a technically relevant factor for the transistor's operation below the threshold (i.e., weak inversion), is set to 1.4; Id is the current through transistors 63A and 63B; k is the Boltzmann constant; T is the absolute temperature; and q is the elementary charge. For the expression on the right, the temperature T is assumed to be room temperature. For an input resistance of 1 kΩ Rs, Id must be greater than approximately 110 μA, which can be relatively easily achieved with proper design for the input stage of a continuous-time Σ-Δ analog-to-digital converter or amplifier.

[0071] Figure 7 The input stage of an analog-to-digital converter with input capacitor 73 is shown. The input voltage Vs is provided by voltage source 79 via input resistor 71. In a first operating phase, transistor switches 72A and 72B are closed by signal Ph1, causing input capacitor 73 to charge depending on the input voltage, while transistor switches 74A and 74B are opened by signal Ph2. In a second phase, transistor switches 72A and 72B are then opened, and transistor switches 74A and 74B are also opened, so that charge is transferred to the input of amplifier 70 in this way. Amplifier 70 is similar to... Figure 6Amplifier 60 has input transistor pairs 76A and 76B, each with its own current source 77A, 77B, and 78. The output signal of amplifier 70 is further processed (not shown) and fed back to the input of amplifier 70 via capacitor 75. Similarly, Figure 7 The illustrations in this document should be understood as illustrative only.

[0072] In this converter, designing the size of the input capacitor 73, Cin, is challenging due to conflicting requirements. On one hand, a sufficiently small Cin must be chosen to ensure converter stability. On the other hand, to satisfy the Nyquist criterion, the sampling frequency fs corresponding to the clock frequency fclock on which signals Ph1 and Ph2 are based must be much larger than the bandwidth of the signal to be converted. To ensure proper stability within the sampling time interval, the time constant τ = Rs x Cin must be a multiple of the time span Ts / 2, where Ts is the reciprocal of the clock signal fclock used (as mentioned above, it is equal to the sampling frequency fs, i.e., Ts is also the reciprocal of the sampling frequency fs), and Rs is the resistance value of the input resistor 71. For example, for 12-bit precision, 8.4τ is required within Ts / 2, and for 8-bit, 5.6τ is required. This makes... 8,4RsCin ≤ ½ Ts =1 / (2fclock) Cint ≤ 1 / (2×fclock Rs) Rnoise_equi = 1 / (fclock Cint) ≥ 16.8 Rs.

[0073] Here, Cint is Figure 7 The capacitance value of capacitor 75. This makes the noise contribution of the capacitor impedance 16.8 times higher, regardless of the clock frequency or the power supply of input transistors 76A and 76B.

[0074] The noise figure NF for 12-bit signals is limited to .

[0075] This means that by using a time-continuous analog-to-digital converter (such as the one used in the embodiments), three to four times lower noise can be achieved compared to converters that operate using switched capacitors.

[0076] Furthermore, processing using a continuous-time analog-to-digital converter may be affected by signal convolution (aliasing), for example, when using... Figure 7This can occur in analog-to-digital converters with switched-capacitor sampling, as shown. This can be mitigated by signal convolution to reduce noise and image frequencies, and to increase dynamic range for smaller amplitude signals. Image frequencies occur when signals at frequencies outside the useful frequency range are undesirably reflected within the useful frequency range. For example, an input interference signal of 3 x fdemod + 4 kHz will become an additional unwanted 4 kHz signal after demodulation. This effect can be reduced in the embodiments.

[0077] As mentioned above, a continuous-time analog-to-digital converter does not require a multiple of the aforementioned time τ within Ts / 2 to stabilize. This reduces the bandwidth required for stabilization, and consequently reduces noise and power requirements, because a larger bandwidth requires more electrical power to achieve the speed needed for stabilization.

[0078] Combining a chopper with a continuous-time analog-to-digital converter can further reduce the offset by one to three orders of magnitude. Furthermore, this combination can reduce flicker noise, which increases at lower frequencies and is caused by active electronics and chopper resistors. In some embodiments, it can even reduce harmonic distortion.

[0079] As will be explained further below, in time-continuous Σ-Δ converters, the dynamic range can also be increased by multi-bit feedback for compensating for offset ripple or by a feedback loop. Due to the increased dynamic range in various embodiments, an amplifier with variable gain is not required, and it can be utilized without such a variable amplifier. Figure 1 Demodulator 12 or Figure 3 The demodulator 32 performs direct passive demodulation. In some embodiments, this can reduce offset that may be caused by such an amplifier, reduce stability problems, and / or reduce noise in some embodiments.

[0080] Furthermore, in some embodiments, the combination of input resistors 32A, 32B and capacitor 34 can be used as an electromagnetic interference (EMC) filter and can avoid intermodulation problems caused by the nonlinearity of active switches (such as gain). Input resistors 32A, 32B can also be used to prevent electrostatic discharge (ESD protection). Therefore, in a continuous-time converter, the input resistance can be well adapted to noise conditions, and signal processing can easily adapt to demanding noise figures, such as an increase of only +1dB as described above.

[0081] As explained, on the one hand, the low-pass characteristic of the continuous-time converter can be used to reduce... Figure 4 The vibration shown is illustrated. Oscillations still occur at higher low-pass frequencies, and their frequency is primarily determined by subtracting the aforementioned frequency fLC from the analog-to-digital converter's clock frequency fclock.

[0082] This oscillation can also be reduced if the frequency fADC is synchronized with fLC.

[0083] Figure 8 Another embodiment of the apparatus according to the embodiment is shown. (Referring to...) Figure 3 The components described herein have the same reference numerals and will not be described in detail again. Figure 8 In particular, it shows Figure 3 Non-limiting examples of the construction of a time-continuous ∑-Δ analog-to-digital converter 37.

[0084] Figure 8 The analog-to-digital converter (ADC) in the circuit includes a voltage-to-current converter 80 (e.g., a transconductance amplifier), and the feedback signal from the ADC is fed back to the voltage-to-current converter via an input resistor 81. The output current of the voltage-to-current converter 80 is integrated analogically using capacitors 310A and 310B. In this case, for example, capacitors 310A and 310B can be implemented using gate oxide.

[0085] The current signal integrated in this manner is fed to comparator 82. The comparator's output is fed to chopper demodulator 38, which, in this case, is arranged within the loop of the Σ-Δ converter, but also in this arrangement, chopping and demodulation of the output signal are also performed. The output signal of comparator 82, corresponding to +1 or -1, is fed to digital integrator 83. This corresponds to a counter that increments the count when the output signal of comparator 82 corresponds to +1 and decrements the count when the output signal of comparator 82 corresponds to -1.

[0086] Furthermore, with the aid of counter 85, the +1 output signal of comparator 82 is added to the output signal of integrator 83 in adder 84. Adder 84 is a digital summing point that adds the digital integral value from integrator 83 to the comparator's "faster," "proportional," or "positive" value via 85. The fast, immediate value from 85 is added to the value from integrator 83 after an integral delay. The path through 85 can be understood as a stable proportional positive path, similar to a stable zero in a feedback system such as a PID controller or Bode plot. Without path 85, undesirable oscillations may occur in some applications.

[0087] In this way, a thermometer-encoded digital signal is generated, representing the input voltage Vin at the voltage / current converter 80. This signal can be converted into a binary output signal by the thermometer / binary encoder 86. The thermometer-encoded signal can be, for example, a 64-bit thermometer-encoded signal.

[0088] Furthermore, the thermometer-encoded signal is fed back as a feedback signal to the voltage / current converter 80 via a digital-to-analog converter 87. The digital-to-analog converter 87 in the illustrated embodiment is a multi-bit digital-to-analog converter that feeds back the 64-bit signal encoded by the thermometer. In some embodiments, using such a multi-bit digital-to-analog converter can increase the dynamic range of the Σ-Δ analog-to-digital converter.

[0089] The implementation of the Σ-Δ analog-to-digital converter is understood as an example only, and other converters such as SAR converters (successive approximation registers, tracking converters (tracking ADCs), or other continuous-time converters can also be used.

[0090] Although Figure 8 Only a single voltage / current converter 80 is shown in the illustration, but multiple voltage / current converters 80 may be provided in other embodiments, which may optionally be connected in parallel. This can increase transconductance, thereby reducing noise, especially for small input signals. In some embodiments, the parallel connection may only occur with small input signals, such as when the voltage or current level is below a predetermined threshold, while only one voltage / current converter is used with larger input signals. In this way, combined with the described chopping, in some embodiments, a corresponding gain can be achieved even with small input signals without causing significant offset and linearity errors.

[0091] In some applications, such as Figure 2 Inductive sensors in this context require analog-to-digital conversion of multiple input signals. Figure 2 In this case, there are three input signals: Inu, Inv, and Inw.

[0092] In some embodiments, for this purpose, each input signal may be provided with, such as Figure 3 As shown or as Figure 8 The apparatus shown is illustrated. In other embodiments, a single analog-to-digital converter device may be provided, which alternately processes various input signals via a multiplexer 90. One example of such a device is shown... Figure 9 As shown in the image.

[0093] exist Figure 9 In embodiments, inductive sensors (e.g.) Figure 2 The signal from an inductive sensor (with three acquisition coils 30A, 30B, and 30C) is processed. Acquisition coil 30A is connected to input pads 31A and 31B of the illustrated analog-to-digital converter device; acquisition coil 30B is connected to input pads 31C and 31D; and acquisition coil 30C is connected to input pads 31E and 31F. Input pads 31A to 31F are connected to a multiplexer 90, which is configured to select the signal from one of the acquisition coils 30A to 30C for further processing.

[0094] The multiplexer 90 operates at a frequency fADC, which determines the time interval between signals from the respective acquisition coils 30A to 30C.

[0095] The selected signal is sent to demodulator 92, whose function corresponds to Figure 3 The demodulator 33 contains a corresponding demodulated signal with frequency fdemod, which is fed from oscillator component 91. A low-pass filter 93 is shown connected downstream of demodulator 92; as in the previously discussed embodiments, it may also be composed of an input resistor (e.g., Figure 3 32A, 32B) and capacitors (e.g. Figure 3 Formed as 34). The output of the low-pass filter 93 is connected to the input of the incremental analog-to-digital converter 95. The incremental analog-to-digital converter is essentially a time-continuous converter; however, it only operates continuously over time in some sections, i.e., in sections where it processes the input signals from the acquisition coils 30A to 30C respectively. The incremental analog-to-digital converter 95 has a chopper modulator 96 and a chopper demodulator 97 at its input, the chopper demodulator being shown at the output, but it can also be configured as follows. Figure 8 The arrangement shown is inside the converter.

[0096] The converter types described above can be used as incremental analog-to-digital converters 95. For example, a SAR converter can be used in conjunction with a tracking converter.

[0097] Combinations of different converters are also possible. Low-pass filter 93 can also be the inherent low-pass filter of analog-to-digital converter 95.

[0098] The low-pass filter and incremental analog-to-digital converter (ADC) are reset according to the frequency fADC used for operation of multiplexer 90, thereby "restarting" each segment of the signal processed by one of the receiving coils 30A to 30C. A previous value can be supplied to incremental ADC 95 as a starting value, corresponding to the end value of a previous time period used for the corresponding receiving coil. Alternatively, prev can also be a predicted value derived from previous history. (Refer to...) Figure 13 To explain.

[0099] exist Figure 13In the diagram, curves 1300A-C and 1301A-C illustrate the trajectory of the input signal to be digitized. In segments 1300A, 1300B, and 1300C, the corresponding input signal is fed to an analog-to-digital converter (e.g., the input signal is generated by receiving coil 30A and selected by multiplexer 90), while no digitization occurs in segments 1301A, 1301B, and 1301C (e.g., because multiplexer 90 selects the signal from another receiving coil). At the beginning of segment 1300A, as indicated by reference numeral 1303A, a transient process is required until the digital output signal stabilizes to the correct value. A similar transient process is required if, as shown for segment 1300B, the value at the end of segment 1300A is used as the starting value, as indicated by reference numeral 1303B. Therefore, predictive techniques are used in some embodiments, as indicated by arrows 1302A and 1302B. This approach uses not only the ending value of the previous segment but also the trend from one or more preceding segments. For example, in a simple case, the trend can be adjusted using the average slope of the preceding segments, thereby adjusting the starting value. In other embodiments, predictive techniques can be used. For instance, linear, quadratic, or sine curves can be applied to the preceding segments, and the starting value can be determined thereby.

[0100] As a further alternative, analog-to-digital converters (ADCs) can be switched between different operating principles or types. For example, at the beginning of each segment 1300A, 1300B, 1300C, SAR ADCs can be performed first to quickly reach the corresponding initial value, and then a Σ-Δ converter can be used to track that value, for example, to reflect changes in the input value.

[0101] Refer again Figure 9 Furthermore, a range selection component 94 can be provided, which allows selection of the input range for the incremental converter 95 via a signal RF, for example, by setting a reference value. This expands the range in which the input signal can be converted. This selection of the input range is achieved through additional inputs to the incremental converter 95, as shown, rather than through error-prone additional circuitry preceding the input stage of the incremental converter 95, such as an amplifier with variable gain, as is done in some conventional solutions. For example, in some embodiments, offset errors can be reduced and the unavoidable offsets, noise, and transient processes of upstream chopper or non-chopper amplifiers can be avoided.

[0102] This range switching can be achieved simply by switching the transconductance of the input stage of the decrement converter 95. Therefore, the voltage-to-current conversion of the input stage can be switched by a factor. Alternatively, the full-scale range of the digital-to-analog converter can be switched in the feedback path of the decrement converter 95 (see the previous embodiments) or in the reference of the decrement converter. This also causes a scaling change in LSB / V (least significant bit per volt of input voltage) at the output of the decrement converter 95. Even the reference... Figure 9 The incremental converter 95 shown discusses this range selection, which may also be provided in continuous-time converters of other exemplary embodiments described herein.

[0103] By providing a chopper modulator and a chopper demodulator, chopper ripple can be generated in the output signal. This ripple can be compensated for by a feedback path. Corresponding embodiments are described in... Figure 10 As shown in the figures. Again, the parts already described with reference to the preceding figures are identified by the same reference numerals and will not be explained in detail again.

[0104] The first input signal is provided via input pads 31A and 31B, and from there is fed to demodulator 33A via input resistors 32A and 32B, which operates at frequency fdemod and corresponds to Figure 3 The demodulator 33. Downstream of the demodulator 33A is a capacitor array of 1000A, whose function corresponds to... Figure 3 Capacitors 34 and 35A and 35B.

[0105] In a corresponding manner, the second input signal can be delivered to the demodulator 33B via pads 31C, 31D and input resistors 32C, 32B, with capacitor arrangement 1000B connected downstream of it.

[0106] The signal processed in this manner is fed to a combined multiplexer and a chopper modulator, wherein the function of the multiplexer is indicated by reference numeral 1001, and the function of the chopper modulator is... Figure 3 The corresponding chopper modulator function is indicated by reference numeral 36. The function of the chopper modulator is essentially multiplication by +1 or -1, corresponding to the optional exchange of the inputs. To additionally integrate multiplexer functionality, this exchange can be extended to all inputs (in...). Figure 10 In the case of... That is, when processing signals provided via pads 31A, 31B, the signals are then ultimately delivered to the voltage / current converter 80 with the same or interchanged polarity (interchangeable lines), which corresponds to... Figure 8 The voltage / current converter 80, and when the signals delivered to the pads 31C, 31D are processed, these corresponding signals are delivered directly or interchangeably to the voltage / current converter 80.

[0107] Multiplexer to according to Figure 7The ADC operates at frequency fADC, and the modulator (i.e., the line switch) operates at frequency fchop.

[0108] The signal is then converted using a time-continuous Σ-Δ analog-to-digital converter, the structure of which initially corresponds to... Figure 8 The structure is the same, and the corresponding components have the same reference numerals. The integrator 1002, which operates at frequency Fclk1, basically corresponds to... Figure 8 The integrator 83 can be implemented, for example, as an increment / decrement counter. It can also be provided here. Figure 8 Components 84 and 85. In Figure 10 In one embodiment, a notch filter 1003 is also provided at the output.

[0109] and Figure 8 Compared to the embodiments in, Figure 10 The embodiment has two feedback paths 1011 and 1012, which ultimately generate feedback signals that are sent to the digital-to-analog converter 87.

[0110] The function of the first feedback path 1011 basically corresponds to Figure 8 The feedback is such that adder 1005 corresponds to adder 85, and adder 1006 corresponds to adder 84, so that a thermometer-encoded signal exists at the output of adder 1006. This signal is chopped at the chopping frequency fchop in chopper modulator 1007 and sent to adder 1008.

[0111] The second feedback path 1012 includes a demodulation element 1009 together with a digital Σ-Δ modulator 1010. The demodulation element 1009 performs biphase demodulation based on the chopping frequency and, together with the digital Σ-Δ modulator 1010, generates an offset signal, such as a four-bit offset signal that at least partially compensates for the ripple caused by chopping. This technique is known in itself. Therefore, the signal supplied to the digital-to-analog converter 87 also includes a component compensating for the ripple caused by chopping.

[0112] Optional bit rotation 1013 can further reduce offset through dynamic allocation techniques (dynamic element matching). Bit rotation is one of many possibilities known in itself for equalizing the average nonlinearity of a converter over time. Other conventional methods can also be used.

[0113] This technology can also be used elsewhere. Now, let's refer to... Figure 11 Describe an embodiment using this variable element allocation.

[0114] For example, the reference current, the resistance of the amplifier, or the sense resistor 81 can be limited for range selection.

[0115] exist Figure 11In this embodiment, the previously discussed receiving coils 22A, 22B, and 22C, as well as the excitation coil 20, are provided. The inductor 21 is not shown and is only provided by… Figure 11 The transformer coupling symbol is used to represent this.

[0116] The excitation coil 20 is provided with an excitation signal by the oscillator 1101, wherein the capacitors 24A and 24B, which have already been discussed, are provided on the line from the oscillator 1101 to the excitation coil 20. For example, the excitation coil 20, the receiving coils 22A to 22C, and the capacitors 24A and 24B can be provided on the printed circuit board 1100.

[0117] As shown, output signals Inu, Inv, and Inw are fed to filter / demodulation unit 1102. Component 1102 includes an arrangement of input resistors 1103, wherein each channel (LN0, LN1, LN2) is assigned two input resistors, whose functions correspond to... Figure 8 The input resistors 32A and 32B in the diagram represent the functions of the input resistor arrangement 1103. Downstream of the input resistor arrangement 1103 is the multiplexer and demodulation arrangement 1104, which is controlled by the frequency fdemod and initially performs the operation. Figure 3 The demodulator 33 performs the function of the demodulator. Furthermore, the multiplexer and demodulator arrangement 1104 switches the corresponding input channels (LNu, LNv, LNw) to the corresponding output signals UP, UN; VP, VN; WP, WN. This can be accomplished using a fixed allocation. However, the allocation can also be changed to achieve dynamic component allocation (dynamic element matching).

[0118] The capacitor arrangement 1105 at the output of the multiplexer and demodulator arrangement 1104 is a downstream capacitor arrangement 1105, whose function corresponds to Figure 3 Capacitors 34, 35A, 35B or Figure 10 The capacitors are arranged in arrays 1000A and 1000B. Then, a separate path is set for digitization of each pair of output signals (UP, UN; VP, VN; WP, WN) in array 1102. Figure 9 and 10 In contrast to multiplexers, which handle multiplexing, parallel processing is performed here. This typically requires more chip area, but is faster with the same implementation and clock speed of an analog-to-digital converter because all signals are converted in parallel.

[0119] Each path includes chopper modulators 36A, 36B, and 36C; time-continuous Σ-Δ analog-to-digital converters 37A, 37B, and 37C; and digital chopper demodulators 38A, 38B, and 38C, whose functions correspond to... Figure 3 The corresponding components are 36, 37, and 38. Each continuous-time Σ-Δ analog-to-digital converter 37A, 37B, and 37C can be similar to... Figure 3The continuous-time Σ-Δ analog-to-digital converter 37 has integrator capacitors, and these capacitors are connected to the remainder of the converter via a chopper, such as... Figure 3 Components 39, 310A, and 310B. These are in... Figure 11 It is not displayed separately. As mentioned above, the chopper frequency fchop can be synchronized with the demodulator frequency fdemod.

[0120] Furthermore, the demodulator frequency fdemod is synchronized with the excitation frequency supplied to the excitation coil 20. In some embodiments, dynamic element matching may also occur between the respective elements 36A to 36C, 37A to 37C, and 38A to 38C, such that the channel signal can be processed using various combinations of chopper modulators, time-continuous Σ-Δ analog-to-digital converters, and chopper demodulators. The digital output signals u, v, and w can then be further processed. As explained for the incremental analog-to-digital converter 95 and the range selection 94 therein, a range selection can also be provided for each of the continuous-time analog-to-digital converters 37A, 37B, and 37C, indicated here by reference numeral 1109.

[0121] To generate the signal fdemod, the signal from oscillator 1101 is fed to phase matching member 1106 via phase comparator 1108. Phase matching member then generates a signal fdemod synchronized with the output signal of oscillator 1101. Furthermore, the oscillator signal itself can be demodulated by demodulator 1107. The amplitude of the oscillator signal can then be determined using the output signal of demodulator 1107. By measuring the amplitude, as described above, the frequency fdemod can be determined based on the zero-crossing of the oscillation at frequency fLC caused by excitation coil 20 and parasitic capacitance.

[0122] The resistor arrangement 1103 and the capacitor arrangement 1105 can together form a low-pass filter. In addition, the resistor arrangement 1103 can be used to prevent electrostatic discharge (ESD protection).

[0123] This dynamic component allocation can occur during operation, during initial calibration, or during device startup.

[0124] In addition to providing such Figure 10 In addition to feedback paths like 1012 to reduce ripple, this can also be additionally or alternatively incorporated with multiplexers (e.g., Figure 9 and 10 In the embodiment, this is achieved by synchronizing the frequency fADC with the chopping frequency fchop in the device that works together. Figure 12 The explanation is as follows. If the frequency fADC is an integer multiple of the chopping frequency, this means that the integral of the signal including the chopping ripple is over an integer number of cycles of the chopping ripple (in...). Figure 12(This is explained through the integration time period T1), and the signal is generated by... Figure 12 The curve 1200 in the figure represents this. Therefore, the positive and negative contributions of the ripple can essentially be averaged out. If this were not the case, such as... Figure 12 As shown in the time period T2, the ripple will not be uniform.

[0125] Figure 14 A flowchart for illustration is shown. This method can be performed using the aforementioned apparatus and system, and is described with reference to the above embodiments for simplicity. However, it is not implemented in the above embodiments. Figure 14 The application of the method.

[0126] In 1401, the method includes directly demodulating the input signal to be converted without variable gain, particularly using passive demodulation with a mixer operating at the demodulation frequency fdemod.

[0127] One example is using Figure 2 Demodulator 33 Figure 1 Demodulator 12 or Figure 9 The demodulator 92 performs demodulation. Demodulation may include low-pass filtering, which can be done using an input resistor and a capacitor connected downstream of the demodulator, as described above. The input resistor may also be used to prevent electrostatic discharge.

[0128] In 1402, as described above, the signal demodulated in this manner is continuously subjected to analog-to-digital conversion, at least for a time period, using a chopper modulator and a chopper demodulator. As already explained, "at least for a time period" specifically refers to situations that may involve... Figure 3 Single-time continuous analog-to-digital converters, such as Figure 11 A separate time-continuous analog-to-digital converter for each channel or also Figure 9 and 10 The multiplexed incremental analog-to-digital converter in [the context]. The changes and modifications described above for the device also apply accordingly. Figure 14 Therefore, various frequencies, such as demodulation frequency, excitation frequency, chopper frequency, or the switching frequency of the multiplexer fADC, can be synchronized as described above, using methods such as... Figure 10 Feedback used to reduce ripple can be achieved using multiplexing or dynamic element allocation. This list should not be considered exhaustive, and all the variations and additions described above can be applied to the method accordingly.

[0129] In the above description, demodulation is performed at the demodulation frequency fdemod using a demodulator, and chopping is performed at the chopping frequency fchop. In the embodiments discussed below, a time-continuous analog-to-digital converter with inherent chopper and demodulation functions is used, particularly a Σ-Δ analog-to-digital converter.

[0130] The corresponding embodiments will now be discussed with reference to Figures 15 to 23. Components and elements used in the above embodiments have the same reference numerals and will not be explained in detail thereafter.

[0131] Figure 15A A system having means for analog-to-digital conversion according to an embodiment is shown. (As already referenced...) Figure 3 As described, Figure 15A The device for analog-to-digital conversion receives signals from the receiving coil 30 at input pads 31A and 31B. Figure 15A In this case, no input resistor is provided, and the input voltage Vin applied to pads 31A, 31B is supplied to voltage / current converter 80, which substantially corresponds to the voltage / current converter already referenced. Figure 8 The voltage / current converter 80 is described. However, with... Figure 8 Instead, there is no demodulator or chopper, so the input voltage Vin applied to pads 31A, 31B is directly fed to the current / voltage converter 80 that has already been discussed.

[0132] The integrator capacitors 310A and 310B, which have already been discussed, are connected downstream of the current / voltage converter 80 via chopper 39. The capacitance values ​​of integrator capacitors 310A and 310B can be in the range of 5 to 30 pF. Figure 15A In the embodiments, capacitors 310A and 310 may have a ratio Figure 3 Smaller capacitance values, for example, capacitance values ​​that are 10 times smaller.

[0133] Chopper 39 operates at a chopper frequency fchop, which, in contrast to the previous embodiment, corresponds to the desired demodulation frequency fdemod. As described above, this demodulation frequency fdemod is generated from the average frequency of the signal received by receiver coil 30. Thus, integration, RC filtering, chopping, and demodulation are achieved along with the resistors of current / voltage converter 80.

[0134] Current / voltage converter 80 in Figure 15B The diagram schematically shows that the input voltage Vin is applied to the gate junctions of transistors 1504 and 1505 and the output signal is generated through current sources 1502, 1503, 1507, and 1508. Figure 15A The resistor of the current / voltage converter 80 shown corresponds to Figure 15B The resistor 1506 can have a value on the order of 400Ω, while the drain current of transistors 1504 and 1505 can exceed 200μA.

[0135] The analog integration, demodulation, and chopping signals are converted into digital signals by a digitizer 1500. As explained later, this digitizer 1500 may include a comparator. The digitized signal is then multiplied alternately by +1 and -1 according to the chopping frequency fchop (which in turn corresponds to the demodulation frequency fdemod) by a multiplier 1501 to generate the digital output signal digout. Furthermore, the digital output signal digout is fed back via a digital-to-analog converter 87, as already referenced... Figure 8 The explanation is as follows. For illustrative purposes, it is still... Figure 15A The signal waveform is schematically illustrated. As shown at the output (dig out), the amplitude of the digital output signal depends on... Figure 15A The system, and especially the frequency used by the digitizer 1500, and the capacitance values ​​Cinteg of capacitors 310A and 310B.

[0136] Figure 15C The differential voltage between integrator capacitors 310A and 310B at various frequencies is shown, along with various frequency values: the frequency used for converter operation, the chopping frequency equal to the demodulation frequency, and the frequency Gm / 2πCinteg, derived from the transconductance Gm and capacitance value Cinteg of the voltage / current converter 80. The transconductance corresponds to the reciprocal of the resistance value of resistor 1506 in the voltage / current converter 80.

[0137] use Figure 15A In the embodiments described, the inherent chopper and demodulation functions can be implemented using a time-continuous analog-to-digital converter, eliminating the need to provide a demodulator and chopper at the input of the voltage / current converter 80. This reduces layout noise, saves power and chip area, and improves accuracy. Furthermore, signal convolution effects and offset errors can be reduced. RC filtering caused by resistor 1506 and capacitors 310A, 310B improves electromagnetic compatibility.

[0138] As an alternative to the voltage / current converter 80, a corresponding system can also be built using an operational amplifier, i.e., it is best to consider the signal integration over the voltage range rather than the integration of the current across the capacitor. Figure 16A The corresponding embodiments are shown in the figure. Figure 16A In the embodiments, with Figure 15ACompared to the previous embodiment, the voltage / current converter 80, chopper 39, and capacitors 310A and 310B are replaced by an arrangement with an operational amplifier 1600, whose inputs are connected to pads 31A and 31B via input resistors 32A and 32B. The resistance values ​​of resistors 32A and 32B can be around 400Ω. Instead of capacitors 310A and 310B, switched capacitors 1602A and 1602B are provided in the feedback path of the operational amplifier 1600, as shown in the embodiment in Figure 16. Switches 1601A to 1601D operate at a chopping frequency fchop, as shown in Figure 16. Figure 15A In one embodiment, it is equal to the demodulation frequency fdemod.

[0139] Figure 16B An equivalent circuit diagram of operational amplifier 1600 is shown, which has current sources 1603, 1604 and 1607 and input transistors 1605 and 1606. The input voltage from pads 31A and 31B is applied to the gate junction of the input transistors via resistors 32A and 32B.

[0140] also, Figure 16A The embodiments in the example correspond to Figure 15A In one embodiment, the output of the digital-to-analog converter is fed back to the input of the operational amplifier 1600.

[0141] The RC filter here is formed by resistors 32A and 32B and capacitors 1602A and 1602B. The integrator function is also implemented here by capacitors 1602A and 1602B. Furthermore, chopping and demodulation are performed in a manner similar to those already designed for… Figure 15A The explanation method is as follows.

[0142] Even in Figure 15A and 16A The device provides a built-in RC filter, and additional RC filters can also be provided, for example, to improve electromagnetic compatibility. Its size can be smaller than that of a device that does not have an integrated RC filter with an integrated capacitor.

[0143] At higher temperatures, Figure 16A The embodiments in the text may have advantages over Figure 15A Advantages of the embodiments described.

[0144] The following table shows various examples of input voltage, input resistances 32A and 32B, capacitance Cint of capacitors 1602A and 1602D, ADC frequency f, and voltage at the integrator for further illustration. It can be seen that for higher input voltages with smaller input resistances, a correspondingly larger integrator capacitance is required to keep the voltage to be integrated sufficiently small.

[0145]

[0146] The above is for Figure 3 Reference Figure 4 The explained behavior also applies to the inherent RC filter (including the corresponding integrator capacitor) that is being explained. Figure 15A and 16A Examples of implementations.

[0147] As already explained, in Figure 15A and 16A In some embodiments, the demodulation frequency, which is the same as the chopping frequency, is synchronized with the following: the average frequency of the signal received by the receiving coil 30, and the frequency fADC used by the analog-to-digital converter (ADC) to operate and output the digital signal. In the above embodiments and the embodiments described below, for example, the digitizer 1500, comparator 82, digital integrator 83, thermometer / binary encoder 86, and digital-to-analog converter 87 are controlled by the frequency fADC. Examples of this synchronization are... Figures 17A to 17C As shown in the image.

[0148] exist Figure 17A In this embodiment, an LC oscillator 1701 generates a signal that is sent via pads 1700A and 1700B to the excitation coil 20, as described with reference to FIG24B. The signal generated by the LC oscillator 1701 is also output to a phase-locked loop (PLL) 1702, which uses an oscillator and a frequency divider 1703 (here referred to as the ADC oscillator / divider) to generate a chopping frequency fchop equal to fdemod, a frequency fADC, and a frequency fdig. fADC can also be fchop. For example, fADC can be generated from fdig by frequency division. For example, fdig can be 40MHz, and fADC can be 10MHz. fdig thus serves as the basis for the generation of fADC. Figure 17A In this process, fchop, fADC, and fdig are synchronized according to the excitation frequency generated by the LC oscillator 1701 for the excitation coil 20. This is achieved by sending the output signal of the LC oscillator 1701 to the phase-locked loop 1702 as a reference, which then controls the ADC oscillator 1703 in sequence.

[0149] exist Figure 17B Instead of LC oscillator 1701, a controllable LC oscillator 1704 is provided, which may, for example, include a variable capacitor as shown in the figure. This capacitor is adjusted by a digital PLL 1705, such that the frequency generated by LC oscillator 1704 is adjusted to the frequency generated by ADC oscillator 1703 and fed to digital PLL 1705 as a reference frequency. Figure 17A The frequency of the ADC oscillator 1703 is adjusted by the PLL 1702 depending on the frequency of the LC oscillator 1701, while... Figure 17BThe reverse approach is taken: the frequency of the LC oscillator 1704 is adjusted to the frequency of the ADC oscillator 1703 via a digital PLL 1705. In both cases, the frequencies fchop, fADC, and fdig can then be generated using a frequency divider interconnected with the ADC oscillator 1703. The reference frequency mentioned above can also be a divided version, such as a divided version of fdig.

[0150] Figure 17B variants in Figure 17C As shown in [the image]. Figure 17C In this embodiment, an LC oscillator 1706 is provided to generate an excitation signal for an excitation coil 20, which has two switchable capacitors as shown. These are controlled by a digital PLL 1707 using a Σ-Δ data stream. Furthermore, Figure 17C The working principle corresponds to the working principle in Figure 17D.

[0151] Now refer to Figures 18 to 22 explain Figure 15A and 16A Variations of the embodiments.

[0152] Figure 18 It shows Figure 15A Variations of the embodiments. In Figure 18 In, with Figure 15A In contrast, resistors 1901A and 1901B are connected upstream of capacitors 310A and 310B. Resistors 1901A and 1902B introduce zeros in the transfer function of the device, which in some embodiments leads to an analog-to-digital converter loop (in... Figure 18 In this case, it is basically an uncontrolled oscillation of the ∑-Δ loop, and the analog-to-digital converter loop is in Figure 18 In this case, it is essentially a Σ-Δ loop, consisting of an analog integrator (implemented via integrator capacitors 310A and 310B), a digital integrator 83, and a digital-to-analog converter 87. The phase after the two integrators in the loop can be -180°, which in some cases may mean uncontrolled oscillations in the feedback. This phase can be reduced, or in other words, the phase reserve can be increased, by introducing resistors 1901A and 1901B at their zeros.

[0153] In addition, Figure 18 In, similar to Figure 8 , Figure 15A The digitizer 1500 is implemented by a comparator 82, a digital integrator 83, and a thermometer / binary encoder 86. Figure 15A The multiplier 1501 is implemented here by a first multiplier 38 between comparator 82 and digital integrator 83 and a second multiplier 1901 in the feedback path to the digital-to-analog converter 87 already discussed.

[0154] in addition, Figure 18 The working principle of the Chinese embodiment corresponds to Figure 15A The working principle of [the process / mechanism]. Just like in [the context of something else]. Figure 8 In this context, counter 85 and adder 84 can be additionally provided in parallel with digital integrator 83, as shown in the reference. Figure 8 As described.

[0155] Figure 19 Another embodiment is shown, which is supplemented by feedback 2000 for eliminating offset ripple. Figure 18 The embodiment in the text. Here, the signal is filtered before or after multiplier 38 and added to the input of digital-to-analog converter 87 by means of adder 2001 in order to eliminate ripple caused by chopping, etc. This can be basically as described in the reference. Figure 10 As explained, it is carried out as described. Further implementations and information regarding such feedback for eliminating chopper-induced ripples can also be found in the applicant's German patent application DE 10 2020 111 914.3.

[0156] Essentially, chopping eliminates the offset, i.e., the DC voltage offset, but this introduces AC voltage ripple in the output signal. This is compensated for by additional digital offset ripple feedback 2000.

[0157] Figure 20 It shows Figure 16A Modifications to the embodiments. Besides Figure 16A In this digitizer 1500 and multiplier 1501, as... Figure 19 As shown in the figure, it is implemented by comparator 82, multiplier 38, digital integrator 83, thermometer / binary encoder 86, and multiplier 1901, such as Figure 19 As shown. Furthermore, as... Figure 19 As shown, the digital offset ripple feedback 2000 is implemented using adder 2001. Finally, Figure 20 The embodiment includes switchable input resistors 2101A, 2101B and 2102A, 2102B, wherein resistors 2101A and 2101B can be activated and deactivated by switches 2100A and 2100B. The resistance values ​​of resistors 2101A and 2102B can be a factor of 10 smaller than those of resistors 2102A and 2102B, so that when switches 2100A and 2100B are closed, resistors 2101A and 2101B determine the total input resistance. For example, resistors 2101A and 2101B can have a resistance value of approximately 400 ohms, while resistors 2102A and 2102B can have a resistance value of, for example, 4kΩ. In this way, switching between different input signal ranges is possible. Figure 16A compared to, Figure 20Various modifications (implementation of digitizers, digital offset ripple feedback, and switchable input resistors) can be implemented independently of each other, even if they are in... Figure 20 They are displayed together.

[0158] Figure 21 It shows Figure 20 Variations of the embodiments described herein. Instead of digital offset ripple feedback 2000, analog offset ripple feedback 2201 is provided here, which additionally loads the input of operational amplifier 1600 based on the signal obtained at the input of comparator 82. Furthermore, instead of digital-to-analog converter 87, digital-to-analog converter 2200 is provided, which has a switchable resistor that can be applied an input voltage or a reference voltage. Such digital-to-analog converters are also used in conjunction with operational amplifiers in conventional structures, rather than current-controlled digital-to-analog converters such as digital-to-analog converter 87. These variations (analog feedback 2201 and digital-to-analog converter 2200) can also be implemented independently of each other.

[0159] Figure 22 It shows Figure 19 The modification is as follows: Here, instead of the digital offset ripple feedback 2000 used to load the input of the digital-to-analog converter 87 via adder 2001, the output of the digital offset ripple feedback 2000 is supplied to the voltage / current converter 80 via a separate analog-to-digital converter 2300. Instead of multiplier 1901, chopper 2301 is then provided at the output of digital-to-analog converter 87. From Figures 19 to 22 It can be seen that there are various methods to eliminate offset ripple.

[0160] In addition, regarding Figures 1 to 14 The variations and modifications discussed in the embodiments can also be applied to the embodiments in Figures 15 to 22.

[0161] Some implementations are defined by the following examples: Example 1. An apparatus for analog-to-digital conversion, comprising: A demodulator is used to demodulate an input signal with a demodulation frequency without requiring a variable preamplifier. A chopper modulator, connected downstream of the demodulator, is used to chop the signal. An analog-to-digital converter, connected downstream of a chopper modulator and operating continuously over time, at least for a given time period, and A chopper demodulator is used to chop signals. Example 2. The apparatus according to Example 1, wherein the demodulator includes a mixer for mixing the input signal with the demodulated signal. Example 3. The apparatus according to Example 1 or 2, wherein the demodulator has at least one input resistor connected upstream and a capacitor assembly connected downstream, wherein the at least one input resistor and the capacitor assembly form a low-pass filter. Example 4. The apparatus according to any one of Examples 1 to 3, wherein the demodulation frequency of the demodulated signal is an integer multiple of the chopping frequency of the chopping signal. Example 5. An apparatus according to any one of the preceding examples, wherein the analog-to-digital converter has an integrator capacitor connected to the remaining analog-to-digital converter via a chopper device operating based on a chopper signal. Example 6. The apparatus according to any one of the preceding examples, wherein the input signal is directly fed to the demodulator. Example 7. An apparatus for analog-to-digital conversion, comprising: An analog-to-digital converter, operating continuously over time at least during a time period, the analog-to-digital converter having: At least one integrator capacitor, said at least one integrator capacitor depending on the chopper signal connected to the remaining analog-to-digital converter, wherein the chopper signal has a frequency equal to the demodulation frequency used to demodulate the input signal of the device, and A chopper demodulator is used to chop signals. Example 8. The apparatus according to Example 7, wherein the analog-to-digital converter includes a voltage-to-current converter, wherein the input of the voltage-to-current converter is configured to receive the input signal, and wherein at least one integrator capacitor is connected to the output of the voltage-to-current converter via a chopper device operating based on a chopper signal. Example 9. The apparatus according to Example 8, wherein the at least one integrator capacitor is connected to the chopper apparatus via at least one resistor. Example 10. An apparatus according to any one of Examples 1 to 9, wherein the analog-to-digital converter comprises a plurality of voltage / current converters connected in parallel, wherein the inputs of the plurality of voltage / current converters are configured to selectively receive input signals. Example 11. The apparatus according to Example 7, wherein the analog-to-digital converter includes an operational amplifier, wherein the input of the operational amplifier is configured to receive the input signal, and wherein the at least one integrator capacitor is connected between the input and output of the operational amplifier by a switching switch that is switched based on a chopping signal. Example 12. An apparatus according to any one of Examples 1 to 11, wherein the analog-to-digital converter has at least one analog-to-digital converter from the group consisting of: a time-continuous Σ-Δ analog-to-digital converter, and an analog-to-digital converter having an incremental converter that operates continuously over time. Example 13. An apparatus according to any one of Examples 1 to 12, wherein the analog-to-digital converter includes a feedback path for reducing ripple caused by chopping. Example 14. An apparatus according to any one of Examples 1 to 13, wherein the apparatus is designed to process a plurality of input channels via an analog-to-digital converter, and the apparatus includes a multiplexer for selecting one input channel to be processed. Example 15. An apparatus according to any one of Examples 14 and 1 to 6, wherein the multiplexer is combined with the demodulator. Example 16. The apparatus according to Example 14 or 15, wherein the chopping frequency of the chopping signal is an integer multiple of or equal to the alternating frequency used by the multiplexer to switch between input channels. Example 17. An apparatus according to any one of Examples 1 to 16, wherein the apparatus is configured for parallel processing of a plurality of input channels, wherein a plurality of analog-to-digital converters including analog-to-digital converters are provided, wherein the apparatus includes a component for dynamic element selection for processing signals from the input channels. Example 18. The apparatus according to any one of Examples 1 to 17 further includes a component for selecting the input range of the analog-to-digital converter via a control input to the analog-to-digital converter. Example 19. An apparatus according to any one of Examples 1 to 18, wherein the apparatus further comprises a switchable input resistor for selecting the input range of the analog-to-digital converter. Example 20. A system comprising: Sensors, and An apparatus for analog-to-digital conversion according to any one of Examples 1 to 19, for processing signals from the sensor. Example 21. The system according to Example 20, wherein the sensor includes an inductive sensor having an excitation coil and at least one receiving coil, wherein an input signal can be acquired from the receiving coil, and wherein the demodulation frequency is equal to the excitation frequency of the excitation signal delivered by the excitation coil. Example 22. A system according to Example 20 or 21, wherein the clock frequency of the analog-to-digital converter is an integer multiple of or equal to the frequency of the demodulated signal. Example 23. The system according to any one of Examples 20 to 22 further includes a phase-locked loop for synchronizing the demodulation frequency with the excitation frequency and / or the clock frequency of the analog-to-digital converter. Example 24. A method for analog-to-digital conversion, comprising: Direct demodulation of the input signal without the need for a variable preamplifier, and At least during the time period, the demodulated input signal is subjected to time-continuous analog-to-digital conversion using chopper modulation and chopper demodulation with a chopper frequency. Example 25. The method described in Example 24, wherein direct demodulation includes mixing the input signal with the demodulated signal. Example 26. The method according to Example 24 or 25, wherein the demodulation frequency is an integer multiple of the chopper frequency of the chopper modulation and the chopper demodulation. Example 27. The method according to any one of Examples 24 to 26, wherein the analog-to-digital converter has an integrator capacitor, the method further comprising: The connection between the integrator capacitor and the rest of the analog-to-digital converter is chopped. Example 28. A method for analog-to-digital conversion, comprising performing a time-continuous analog-to-digital conversion on an input signal for at least a time period, wherein the time-continuous analog-to-digital conversion for at least a time period includes the operation of an integrator capacitor based on a chopping signal, wherein the chopping signal has a chopping frequency equal to the demodulation frequency used to demodulate the input signal to be converted.

[0162] Example 29. The method according to any one of Examples 24 to 28, wherein the method for processing multiple input channels includes multiplexing to select the input channel to be processed, wherein the chopping frequency is an integer multiple of the alternating frequency used for switching between the input channels.

[0163] Example 30. The method according to any one of Examples 24 to 29, wherein the method includes a multiplexer for selecting input signals to be processed in order to process multiple input channels.

[0164] Although specific embodiments have been illustrated and described in this specification, those skilled in the art will recognize that various alternative and / or equivalent implementations can be used without departing from the specific embodiments shown and described herein. The scope of the invention may vary and may be chosen accordingly. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the invention is intended to be limited only by the claims and their equivalents.

Claims

1. An apparatus for analog-to-digital conversion, comprising: Demodulator (12; 33； 33A, 33B; 92), used to demodulate the input signal with a demodulated signal (fdemod) having a demodulation frequency, without requiring a variable preamplifier. The chopper modulator (13; 36; 36A-36C), connected downstream of the demodulator (12; 33; 33A, 33B; 92), is used for chopping based on the chopper signal. An analog-to-digital converter (14; 37; 37A-37C) is connected downstream of the chopper modulator (13; 36; 36A-36C) and operates continuously over time, at least for a period of time. A chopper demodulator (15; 38; 38A-38C), connected downstream of the analog-to-digital converter, is used to chop the signal based on the chopper signal.

2. The apparatus of claim 1, wherein the demodulator (12; 33; 33A, 33B; 92) includes a mixer for mixing the input signal with the demodulated signal (fdemod).

3. The apparatus according to claim 1 or 2, wherein the demodulator (12; 33; 33A, 33B; 92) has at least one input resistor (32A, 32B, 32C, 32D) connected upstream of the demodulator and a capacitor assembly (34, 35A, 35B; 1000A, 1000B) connected downstream of the demodulator, wherein the at least one input resistor (32A, 32B, 32C, 32D) and the capacitor assembly form a low-pass filter.

4. The apparatus according to claim 1 or 2, wherein the demodulation frequency of the demodulated signal (fdemod) is an integer multiple of the chopping frequency of the chopping signal.

5. The apparatus according to claim 1 or 2, wherein the analog-to-digital converter (14; 37; 37A-37C) has an integrator capacitor (310A, 310B) connected to the remaining components of the analog-to-digital converter (14; 37; 37A-37C) via a chopper device (39) operating based on the chopper signal.

6. The apparatus according to claim 1 or 2, wherein the analog-to-digital converter comprises a plurality of voltage / current converters (80) connected in parallel, wherein the inputs of the plurality of voltage / current converters (80) are configured to selectively receive the input signal.

7. The apparatus of claim 1 or 2, wherein the analog-to-digital converter has at least one analog-to-digital converter (14; 37; 37A-37C) from the group consisting of: a time-continuous Σ-Δ analog-to-digital converter, and an analog-to-digital converter having an incremental converter that operates continuously over time.

8. The apparatus of claim 1 or 2, wherein the analog-to-digital converter (14; 37; 37A-37C) includes a feedback path (1012; 2000; 2201) for reducing ripple caused by chopping.

9. The apparatus of claim 1 or 2, wherein the apparatus is designed to process multiple input channels via the analog-to-digital converter (14; 37; 37A-37C), and the apparatus includes a multiplexer (90; 1001) for selecting the input channels to be processed.

10. The apparatus of claim 9, wherein the multiplexer (90; 1001) is combined with the demodulator (12; 33; 33A, 33B; 92).

11. The apparatus of claim 10, wherein the chopping frequency of the chopping signal is an integer multiple of or equal to the alternating frequency (fADC) used by the multiplexer (90; 1001) to switch between the input channels.

12. The apparatus of claim 1 or 2, wherein the apparatus is configured for parallel processing of a plurality of input channels, wherein a plurality of analog-to-digital converters (14; 37; 37A-37C) including the analog-to-digital converters (14; 37; 37A-37C) are provided, wherein the apparatus includes a component for dynamic element selection for processing signals from the input channels.

13. The apparatus of claim 1 or 2, further comprising means for selecting the input range of the analog-to-digital converter (14; 37; 37A-37C) via a control input to the analog-to-digital converter (14; 37; 37A-37C).

14. The apparatus of claim 1 or 2, wherein the apparatus further comprises a switchable input resistor (2101A, 2101B, 2102A, 2102B) for selecting the input range of the analog-to-digital converter (14; 37; 37A-37C).

15. An apparatus for analog-to-digital conversion, comprising: An analog-to-digital converter, operating continuously over time at least during a time period, the analog-to-digital converter having: At least one integrator capacitor (310A, 310B; 1602A, 1602B), said at least one integrator capacitor depending on the connection of the chopping signal to the remaining components of the analog-to-digital converter (14; 37; 37A-37C), wherein said chopping signal has a frequency equal to the demodulation frequency used to demodulate the input signal of the device, and A chopper demodulator, connected downstream of the analog-to-digital converter, is used to chop the signal based on the chopped signal.

16. The apparatus of claim 15, wherein the analog-to-digital converter includes a voltage / current converter (80), wherein the input of the voltage / current converter (80) is configured to receive the input signal, and wherein the at least one integrator capacitor (310A, 310B; 1602A, 1602B) is connected to the output of the voltage / current converter (80) via a chopper device (39) operating based on the chopper signal.

17. The apparatus of claim 16, wherein the at least one integrator capacitor (310A, 310B; 1602A, 1602B) is connected to the chopper apparatus (39) via at least one resistor (1901A, 1901B).

18. The apparatus according to any one of claims 15 to 17, wherein the analog-to-digital converter comprises a plurality of voltage / current converters (80) connected in parallel, wherein the inputs of the plurality of voltage / current converters (80) are configured to selectively receive the input signal.

19. The apparatus of claim 15, wherein the analog-to-digital converter includes an operational amplifier (1600), wherein the input of the operational amplifier (1600) is configured to receive the input signal, and wherein the at least one integrator capacitor (310A, 310B; 1602A, 1602B) is connected between the input and output of the operational amplifier (1600) by a switching switch (1601A-1601D) that is switched based on the chopping signal.

20. The apparatus according to any one of claims 15 to 17, wherein the analog-to-digital converter has at least one analog-to-digital converter (14; 37; 37A-37C) from the group consisting of: a time-continuous Σ-Δ analog-to-digital converter, and an analog-to-digital converter having an incremental converter that operates continuously over time.

21. The apparatus according to any one of claims 15 to 17, wherein the analog-to-digital converter (14; 37; 37A-37C) includes a feedback path (1012; 2000; 2201) for reducing ripple caused by chopping.

22. The apparatus according to any one of claims 15 to 17, wherein the apparatus is designed to process multiple input channels via the analog-to-digital converter (14; 37; 37A-37C), and the apparatus includes a multiplexer (90; 1001) for selecting the input channels to be processed.

23. The apparatus of claim 22, wherein the multiplexer (90; 1001) is combined with the demodulator (12; 33; 33A, 33B; 92).

24. The apparatus of claim 22, wherein the chopping frequency of the chopping signal is an integer multiple of or equal to the alternating frequency (fADC) used by the multiplexer (90; 1001) to switch between the input channels.

25. The apparatus according to any one of claims 15 to 17, wherein the apparatus is configured for parallel processing of a plurality of input channels, wherein a plurality of analog-to-digital converters (14; 37; 37A-37C) including the analog-to-digital converters (14; 37; 37A-37C) are provided, wherein the apparatus includes a component for dynamic element selection for processing signals from the input channels.

26. The apparatus according to any one of claims 15 to 17, further comprising means for selecting the input range of the analog-to-digital converter (14; 37; 37A-37C) via a control input to the analog-to-digital converter (14; 37; 37A-37C).

27. The apparatus according to any one of claims 15 to 17, wherein the apparatus further comprises a switchable input resistor (2101A, 2101B, 2102A, 2102B) for selecting the input range of the analog-to-digital converter (14; 37; 37A-37C).

28. A sensor system, comprising: Sensors, and The apparatus for analog-to-digital conversion according to any one of claims 1 to 27, for processing signals from said sensor.

29. The sensor system of claim 28, wherein the sensor comprises an inductive sensor having an excitation coil (20) and at least one receiving coil (22A-22C), wherein the input signal can be acquired from the receiving coil, and wherein the demodulation frequency is equal to the excitation frequency of the excitation signal delivered by the excitation coil (20).

30. The sensor system of claim 29, wherein the clock frequency of the analog-to-digital converter (14; 37; 37A-37C) is an integer multiple of or equal to the frequency of the demodulated signal (fdemod).

31. The sensor system of claim 29 further includes a phase-locked loop (1702, 1705, 1707) for synchronizing the demodulation frequency with the excitation frequency and / or the clock frequency of the analog-to-digital converter (14; 37; 37A-37C).

32. A method for analog-to-digital conversion, comprising: Direct demodulation of the input signal without the need for a variable preamplifier, and At least within a time period, the demodulated input signal is subjected to time-continuous analog-to-digital conversion using chopper modulation and chopper demodulation at a chopper frequency. The chopping modulation is performed before the analog-to-digital conversion, and the chopping demodulation is performed after the analog-to-digital conversion.

33. The method of claim 32, wherein the direct demodulation comprises mixing the input signal with the demodulated signal.

34. The method according to claim 32 or 33, wherein the demodulation frequency is an integer multiple of the chopper frequency of the chopper modulation and the chopper demodulation.

35. The method of claim 32 or 33, wherein the analog-to-digital converter (14; 37; 37A-37C) has an integrator capacitor (310A, 310B), wherein the method further comprises: The integrator capacitors (310A, 310B) and the analog-to-digital converter (14; Switch the connection of the remaining components of 37 (37A-37C).

36. The method of claim 32 or 33, wherein the method for processing multiple input channels includes multiplexing to select the input channel to be processed, wherein the chopping frequency is an integer multiple of the alternating frequency (fADC) used for switching between the multiplexing input channels.

37. A method for analog-to-digital conversion, comprising performing a time-continuous analog-to-digital conversion on an input signal for at least a time period, wherein the time-continuous analog-to-digital conversion for at least the time period includes the operation of an integrator capacitor based on a chopping signal, wherein the chopping signal has a chopping frequency equal to the demodulation frequency used to demodulate the input signal to be converted. The analog-to-digital conversion is followed by chopping at the demodulation frequency.

38. The method of claim 37, wherein the method for processing multiple input channels includes multiplexing to select the input channel to be processed, wherein the chopping frequency is an integer multiple of the alternating frequency (fADC) used for switching between the multiplexing input channels.

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