Integrated circuit structure and memory structure

Abstract

This disclosure provides an integrated circuit structure and a memory structure. The integrated circuit structure includes a first memory storage group and a second memory storage group, which share a set of data read / write driving circuitry. The data read / write driving circuitry includes: a read control module connected to a read data bus, the first read / write data bus, and the second read / write data bus, used to read data from the first memory storage group onto the read data bus via the first read / write data bus, or to read data from the second memory storage group onto the read data bus via the second read / write data bus; and a write control module connected to a write data bus, the first read / write data bus, and the second read / write data bus, used to write data from the write data bus into the first memory storage group via the first read / write data bus, or to write data from the write data bus into the second memory storage group via the second read / write data bus. Embodiments of this disclosure can save integrated circuit layout area in the memory.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to an integrated circuit structure and a memory structure using the integrated circuit structure. Background Technology

[0002] In the current DDR4 (fourth generation DRAM) design, due to the existence of Bank Groups [1:0], the internal memory array of the DRAM is divided into four Bank Groups (BGs). Cross-reading and writing between different BGs can increase the DRAM access efficiency. In this design, the data connections to different BGs are merged in the central area of ​​the four BGs, sharing a data bus to transmit data to the Data Queue (DQ). Since the data connections need to reach each BG through long metal traces, the drive circuit for the read / write data lines in the central area needs to be large. This size, multiplied by the 72-bit data line width, results in the data read / write drive circuits of the four BGs occupying a large layout area, leading to longer data lines from the DQ and a larger data line loading.

[0003] For example, the layout area of ​​the central region is large in both the X direction (the extension direction of the data lines connecting the DQ section) and the Y direction (perpendicular to the X direction, the extension direction of the data lines connecting the various BG sections). A large area in the X direction increases the load on the data lines coming from the DQ end, and a large area in the Y direction increases the load on the data lines at the BG end. In terms of layout routing, the routing in the X direction will run through the top metal layer, and the routing in the Y direction will run through the first metal layer, so the load problem in the Y direction will be more severe.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide an integrated circuit structure and a memory structure using the integrated circuit structure, so as to overcome, at least to some extent, the problem of large area occupied by the integrated circuit layout of the memory due to the limitations and defects of related technologies.

[0006] According to a first aspect of this disclosure, an integrated circuit structure is provided, including a first storage group and a second storage group, wherein the first storage group and the second storage group share a set of data read / write driving circuits. The data read / write driving circuits include: a read control module connected to a read data bus, a first read / write data bus, and a second read / write data bus, configured to read data from the first storage group onto the read data bus via the first read / write data bus, or to read data from the second storage group onto the read data bus via the second read / write data bus; and a write control module connected to a write data bus, the first read / write data bus, and the second read / write data bus, configured to write data from the write data bus into the first storage group via the first read / write data bus, or to write data from the write data bus into the second storage group via the second read / write data bus; wherein the read data bus includes multiple read data lines, the write data bus includes multiple write data lines, and the multiple read data lines and the multiple write data lines are interleaved.

[0007] In one exemplary embodiment of this disclosure, the write control module includes: a write control unit connected to the write data bus; a first write driver unit, with a first end connected to the write control unit and a second end connected to the first storage group via the first read / write data bus; and a second write driver unit, with a first end connected to the write control unit and a second end connected to the second storage group via the second read / write data bus.

[0008] In an exemplary embodiment of this disclosure, the first write driving unit and the second write driving unit are located in a first region, the first write driving unit and the second write driving unit are arranged side by side in a first direction, and the write control unit is arranged side by side with the first region in a second direction, the second direction being perpendicular to the first direction.

[0009] In an exemplary embodiment of this disclosure, the first write driving unit is located in the first column, the second write driving unit is located in the second column, and the write control unit occupies the first column and the second column in the first direction.

[0010] In an exemplary embodiment of this disclosure, a gap extending along the second direction is provided between the first write driving unit and the second write driving unit, and the projections of a segment of the first read / write data bus and a segment of the second read / write data bus are located within the gap.

[0011] In an exemplary embodiment of this disclosure, the first repository group and the second repository group are located in a second region, and the second region, the first region, and the write control unit are sequentially arranged in the second direction.

[0012] In an exemplary embodiment of this disclosure, the read control module includes: a first read control unit, the first end of which is connected to the first storage group via a first read / write data bus; a second read control unit, the first end of which is connected to the second storage group via a second read / write data bus; and a read drive unit, which is connected to the second end of the first read control unit, the second end of the second read control unit, and the read data bus.

[0013] In an exemplary embodiment of this disclosure, the first read control unit and the second read control unit are located in a third region, the first read control unit and the second read control unit are arranged side by side in a first direction, the third region is arranged side by side with the read drive unit in a second direction, and the second direction is perpendicular to the first direction.

[0014] In an exemplary embodiment of this disclosure, the first read control unit is located in the first column, the second read control unit is located in the second column, and the read drive unit occupies the first column and the second column in the first direction.

[0015] In an exemplary embodiment of this disclosure, the first repository group and the second repository group are located in a second region, and the second region, the third region, and the read drive unit are sequentially arranged in the second direction.

[0016] In one exemplary embodiment of this disclosure, the first read / write data bus and the second read / write data bus are interleaved.

[0017] In one exemplary embodiment of this disclosure, the first repository group and the second repository group are arranged side by side in a first direction.

[0018] In an exemplary embodiment of this disclosure, the plurality of read data lines and the plurality of write data lines are alternately arranged in a first wiring area and a second wiring area. The first wiring area, the read control module, and the second wiring area are arranged side by side in a first direction. The read data lines and the write data lines extend along a second direction in both the first wiring area and the second wiring area. The second direction is perpendicular to the first direction.

[0019] In an exemplary embodiment of this disclosure, a first power line is provided on the side of the first wiring area adjacent to the read control module, and the first power line extends along the second direction; a second power line is provided on the side of the second wiring area adjacent to the read control module, and the second power line extends along the second direction.

[0020] In an exemplary embodiment of this disclosure, a first shielding line is provided on the side of the first wiring area away from the read control module, and the first shielding line extends along the second direction; a second shielding line is provided on the side of the second wiring area away from the read control module, and the second shielding line extends along the second direction.

[0021] In an exemplary embodiment of this disclosure, the first read / write data bus and the second read / write data bus extend along the second direction within a third wiring region. The third wiring region is disposed between the first wiring region and the second wiring region. A third power line is disposed on the side of the third wiring region adjacent to the first wiring region, and a fourth power line is disposed on the side of the third wiring region adjacent to the second wiring region. Both the third power line and the fourth power line extend along the second direction.

[0022] According to a second aspect of this disclosure, a memory structure is provided, comprising: a first memory bank group and a second memory bank group, which are combined and disposed in a first layout region, the first memory bank group and the second memory bank group sharing a set of integrated circuit structures as described in any of the preceding claims; a third memory bank group and a fourth memory bank group, which are combined and disposed in a second layout region, the third memory bank group and the fourth memory bank group sharing another set of integrated circuit structures as described in any of the preceding claims; wherein the first memory bank group and the second memory bank group are arranged side by side in a first direction, the third memory bank group and the fourth memory bank group are arranged side by side in the first direction, the first layout region and the second layout region are arranged side by side in a second direction, and the second direction is perpendicular to the first direction.

[0023] In an exemplary embodiment of this disclosure, the first repository group, the second repository group, the third repository group, and the fourth repository group are jointly connected to a read data bus and a write data bus. The read data bus includes multiple read data lines, and the write data bus includes multiple write data lines. Both the multiple read data lines and the multiple write data lines extend along the second direction.

[0024] The embodiments of this disclosure save the layout area of ​​the data read / write driver circuit between different storage groups and the data bus by setting the first storage group and the second storage group to share a set of data read / write driver circuits, thereby reducing the integrated circuit layout area of ​​the memory and the size of the memory.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a schematic diagram of the integrated circuit structure in an exemplary embodiment of this disclosure.

[0028] Figure 2 This is a schematic diagram of the structure of the write control module and the read control module in one embodiment of this disclosure.

[0029] Figure 3 This is a schematic diagram of the layout of the write control module and the read control module in one embodiment of this disclosure.

[0030] Figure 4 This is a schematic diagram of the layout and wiring of the read control module and the write control module in one embodiment of this disclosure.

[0031] Figure 5 This is a layout and wiring diagram of the read control module and the write control module in another embodiment of this disclosure.

[0032] Figure 6 This is a schematic diagram of a memory structure in one embodiment of the present disclosure.

[0033] Figure 7 This is a schematic diagram of the memory structure in another embodiment of this disclosure. Detailed Implementation

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0035] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0036] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic diagram of the integrated circuit structure in an exemplary embodiment of this disclosure.

[0038] refer to Figure 1 The integrated circuit structure 100 may include:

[0039] The first repository group BG0 and the second repository group BG1 share a set of data read / write driver circuit 1, which includes:

[0040] The write control module 11 is connected to the write data bus WR, the first read / write data bus RW1, and the second read / write data bus RW2. It is used to write the data of the write data bus WR to the first storage group BG0 through the first read / write data bus RW1, or to write the data of the write data bus WR to the second storage group BG1 through the second read / write data bus RW2.

[0041] The read control module 12 is connected to the read data bus RD, the first read / write data bus RW1, and the second read / write data bus RW2. It is used to read the data of the first repository group BG0 onto the read data bus RD through the first read / write data bus RW1, or to read the data of the second repository group BG1 onto the read data bus RD through the second read / write data bus RW2.

[0042] The read data bus RD includes multiple read data lines, and the write data bus WR includes multiple write data lines. The read data lines and write data lines are interleaved.

[0043] To reduce the layout area occupied by the data read / write drive circuit, embodiments of this disclosure combine identical control circuits in different BGs as much as possible. Since BG0 and BG1 share a set of read / write data buses (RD+WR), receivers with write functions in different BGs can be combined, and drivers with read functions in different BGs can be combined, thereby reducing the overall area of ​​the data read / write drive circuit and reducing the memory size.

[0044] The write control module 11 and the read control module 12 are described below.

[0045] Figure 2 This is a schematic diagram of the structure of the write control module and the read control module in one embodiment of this disclosure.

[0046] refer to Figure 2 In one embodiment, the write control module 11 includes:

[0047] Write control unit 111 is connected to write data bus WR;

[0048] The first write drive unit 112 has a first end connected to the write control unit 111 and a second end connected to the first storage group BG0 through the first read / write data bus RW1.

[0049] The second write drive unit 113 has its first end connected to the write control unit 111, and its second end connected to the second storage group BG1 via the second read / write data bus RW2.

[0050] The read control module 12 includes:

[0051] The first read control unit 121 has its first end connected to the first storage group BG0 via the first read / write data bus RW1.

[0052] The second read control unit 122 has its first end connected to the second storage group BG1 via the second read / write data bus RW2.

[0053] The read drive unit 123 is connected to the second end of the first read control unit 121, the second end of the second read control unit 122, and the read data bus RD.

[0054] The data read and write times of the first storage group BG0 and the second storage group BG1 are different. That is, when writing data, the data transmitted on the write data bus WR is used to alternately write to the first storage group BG0 and the second storage group BG1; when reading data, data is alternately read from the first storage group BG0 and the second storage group BG1 onto the read data bus RD.

[0055] As can be seen from the above analysis, the data writing logic of the first storage group BG0 and the second storage group BG1 is the same and the writing timing is complementary. Therefore, in this embodiment of the present disclosure, a write control unit 111 is used to complete the write logic control of the two storage groups, so as to write the data to be written on the write data bus WR to the two write drive units (first write drive unit 112 and second write drive unit 113) connected to the first storage group BG0 and the second storage group BG1 respectively in a time-sharing manner, so that the data is written to the first storage group BG0 and the second storage group BG1 respectively through the two write drive units.

[0056] Understandably, the write control unit 111 can have a write buffer function to buffer data received from the write data bus WR, thereby enabling alternating time-division writing to the first write drive unit 112 and the second write drive unit 113. Alternating time-division writing means that data to be written is written to the first write drive unit 112 in a first time period, and to the second write drive unit 113 in a second time period. Both the first and second time periods include multiple time periods, with the end of one first time period close to the start of one second time period, and the end of one second time period close to the start of the next first time period.

[0057] Similarly, as can be seen from the above analysis, when reading data, the data reading logic for the first storage group BG0 and the second storage group BG1 is the same, and the reading timing is complementary. Therefore, in this embodiment of the present disclosure, two read control units (first read control unit 121 and second read control unit 122) connected to the first storage group BG0 and the second storage group BG1 respectively are used to read data from the first storage group BG0 and the second storage group BG1 respectively, and then output them to a read drive unit 123 in a time-division manner, and send them to the read data bus RD through the read drive unit 123.

[0058] The first read control unit 121 and the second read control unit 122 can both have read buffering functions to buffer data read from the first storage group BG0 and the second storage group BG1, respectively, so as to alternately output the data to the read drive unit 123 in a time-sharing manner. Alternating time-sharing output means that the read drive unit 123 reads data from the first read control unit 121 in a third time period and reads data from the second read control unit 122 in a fourth time period. Both the third and fourth time periods include multiple time periods. The end time of a third time period is close to the start time of a fourth time period, and the end time of a fourth time period is close to the start time of the next third time period.

[0059] Therefore, in this embodiment of the disclosure, for two storage groups, a write control unit and a read drive unit are used for read and write control, which greatly saves the circuit setup and layout area of ​​the data read and write drive circuit. In addition, since read and write operations cannot be performed simultaneously, multiple read data lines and multiple write data lines are set up in an interleaved manner, which is beneficial to realize that the read data lines and write data lines are mutually shielded, thereby suppressing signal interference between adjacent read data lines or adjacent write data lines.

[0060] Figure 3 This is a schematic diagram of the layout of the write control module and the read control module in one embodiment of this disclosure.

[0061] refer to Figure 3When laying out the circuit, the write control module 11 and the read control module 12 can be arranged side by side to minimize the layout area of ​​the data read and write drive circuit.

[0062] exist Figure 3 In the embodiment shown, the first write driving unit 112 and the second write driving unit 113 are located in the first region A1, such that the first write driving unit 112 and the second write driving unit 113 are arranged side by side in the first direction, and the write control unit 111 is arranged side by side with the first region A1 in the second direction, the second direction being perpendicular to the first direction.

[0063] The first repository group BG0 and the second repository group BG1 are located in the second region A2, and the second region A2, the first region A1, and the write control unit 111 are arranged sequentially in the second direction. In one embodiment, the first repository group BG0 and the second repository group BG1 are arranged side by side in the first direction.

[0064] The first read control unit 121 and the second read control unit 122 are located in the third region A3. The first read control unit 121 and the second read control unit 122 are arranged side by side in the first direction, and the third region A3 and the read drive unit 123 are arranged side by side in the second direction. In one embodiment, the second region A2, the third region A3, and the read drive unit 123 are arranged sequentially in the second direction.

[0065] In this configuration, the first write drive unit 112 is located in the first column, the second write drive unit 113 is located in the second column, and the write control unit 111 occupies both the first and second columns in the first direction. The first read control unit 121 is located in the first column, the second read control unit 122 is located in the second column, and the read drive unit 123 occupies both the first and second columns in the first direction. Figure 3 The two-column, two-row layout method shown can minimize the layout of the data read / write driver circuit.

[0066] exist Figure 3 In the illustrated embodiment, the second region A2, the first region A1, and the third region A3 are arranged sequentially in the second direction. In other embodiments of this disclosure, the order of the first region A1 and the third region A3 may be adjusted, or the arrangement order of the second region A2, the first region A1, and the third region A3 may be adjusted. This disclosure does not impose any special restrictions on this.

[0067] Figure 4 This is a schematic diagram of the layout and wiring of the read control module and the write control module in one embodiment of this disclosure.

[0068] refer to Figure 4In one embodiment, there is a gap extending along a second direction between the first write drive unit 112 and the second write drive unit 113, and the projection of a segment of the first read / write data bus RW1 and the projection of a segment of the second read / write data bus RW2 are located within the gap.

[0069] In one embodiment, the first read / write data bus RW1 and the second read / write data bus RW2 are interleaved. Since the first read / write data bus and the second read / write data bus do not operate simultaneously, their interleaved arrangement serves as a shield for each other.

[0070] In addition, Figure 4 In the embodiment shown, multiple read data lines and multiple write data lines are arranged alternately in the first wiring area B1 and the second wiring area B2. The first wiring area B1, the read control module 12, and the second wiring area B2 are arranged side by side in the first direction. The read data lines and write data lines extend along the second direction in both the first wiring area and the second wiring area. The second direction is perpendicular to the first direction.

[0071] In one embodiment, a first power line P1 is provided on the side of the first wiring area B1 adjacent to the read control module 12, and the first power line P1 extends along the second direction; a second power line P2 is provided on the side of the second wiring area B2 adjacent to the read control module 12, and the second power line P2 extends along the second direction.

[0072] In one embodiment, a first shielding line S1 is provided on the side of the first wiring area B1 away from the read control module 12, and the first shielding line S1 extends along the second direction; a second shielding line S2 is provided on the side of the second wiring area B2 away from the read control module 12, and the second shielding line S2 extends along the second direction.

[0073] In the data lines coming from DQ, write and read data lines are routed separately and can shield each other. However, after passing through the center area, the data lines are no longer separated into write and read data lines, requiring an additional set of lines for shielding, which increases the layout area. In this embodiment, after merging BG0 and BG1, since BG0 and BG1 do not operate simultaneously, the data lines of these two repository groups can also shield each other, thereby improving the utilization rate of lines in the layout and reducing the layout area.

[0074] Therefore, when merging BG0 and BG1, in order to make the read data line and write data line mutually shielded, the same group of read drive units and write drive units can be placed along the second direction. For the convenience of wiring, the individual drive units can be divided into one column or two columns.

[0075] When BG0 and BG1 are merged, the write driver units cannot be merged and can be drawn in a single column. However, the read driver units of the two repository groups can be merged. In order to make the read data lines and write data lines mutually shielded, the read driver units need to be drawn in two columns. Then, the read data lines and write data lines in the read data bus and write data bus are routed to the two sides. Shielding lines are added to the outermost edge of the data lines to prevent other lines from affecting the data lines. The data lines close to the driver unit will use the power line as the shielding line and do not need to be shielded by adding any additional shielding lines.

[0076] Figure 5 This is a layout and wiring diagram of the read control module and the write control module in another embodiment of this disclosure.

[0077] refer to Figure 5 In one embodiment, the first read / write data bus RW1 and the second read / write data bus RW2 extend along a second direction within a third wiring region B3. The third wiring region B3 is located between the first wiring region B1 and the second wiring region B2. A third power line P3 is provided on the side of the third wiring region B3 adjacent to the first wiring region B1, and a fourth power line P4 is provided on the side of the third wiring region B3 adjacent to the second wiring region B2. Both the third power line P3 and the fourth power line P4 extend along the second direction.

[0078] After drawing the write driver unit and read driver unit in a double row or a single row, increase the distance between the two rows and arrange the read and write data buses from the central area to the storage group. When arranging, the data buses of BG0 and BG1 (i.e., the first read and write data bus RW1 and the second read and write data bus RW2) are arranged alternately. This group of data buses uses power lines as shielding layers on both sides near the write driver unit, so no other shielding layers need to be added. The utilization rate of the traces is very high and the wiring area is reduced.

[0079] In addition, in actual layout, the circuit parts of the write control module 11 and the read control module 12 can be set on the same layer, and the data lines can be set on other layers. The data lines can be set on the same layer or on different layers.

[0080] like Figure 5 As shown, in one embodiment, the first wiring area B1 and the second wiring area B2 can be respectively set in the area where the projected area overlaps with the first write driving unit 112 and the second write driving unit 113, thereby reducing the layout area occupied by the central area and reducing the wiring length through multi-layer wiring, thereby reducing the load on the data line.

[0081] Figure 6 This is a schematic diagram of a memory structure in one embodiment of the present disclosure.

[0082] refer to Figure 6In one embodiment, the memory structure 600 may include:

[0083] The first repository group BG0 and the second repository group BG1 are combined and set in the first layout area C1. The first repository group BG0 and the second repository group BG1 share a set of... Figures 1-5 The integrated circuit structure 61 shown in the embodiment is disposed in the first layout region C1;

[0084] The third repository group BG2 and the fourth repository group BG3 are combined and located in the second layout area C2. The third repository group BG2 and the fourth repository group BG3 share another set of... Figures 1-5 The integrated circuit structure 62 shown in the embodiment is disposed in the second layout region C2;

[0085] In this configuration, the first repository group BG0 and the second repository group BG1 are arranged side-by-side in the first direction, the third repository group BG2 and the fourth repository group BG3 are arranged side-by-side in the first direction, and the first layout area C1 and the second layout area C2 are arranged side-by-side in the second direction, which is perpendicular to the first direction. The first direction is the extension direction of the read data bus RD and the write data bus WR connecting the DQ terminal.

[0086] In one embodiment, the first repository group BG0, the second repository group BG1, the third repository group, and the fourth repository group are jointly connected to the read data bus RD and the write data bus WR. The read data bus RD includes multiple read data lines, and the write data bus WR includes multiple write data lines. Both the multiple read data lines and the multiple write data lines extend along a second direction.

[0087] After the merger, the central region will change from four layout blocks to two layout blocks. Before the change, each layout block corresponded to one repository group, responsible for reading and writing to that repository group. After the change, each layout block corresponds to two repository groups, enabling alternating reading and writing. Furthermore, a smaller central region layout area is achieved through integrated circuit structures 61 and 62, which have smaller layout areas.

[0088] Figure 7 This is a schematic diagram of the memory structure in another embodiment of this disclosure.

[0089] refer to Figure 7 In another embodiment, the first layout area C1 and the second layout area C2 can also be arranged side by side in the first direction. However, from the perspective of cabling floorplan, in order to reduce the load on the data lines at the BG end, the floorplan of the central area can be given priority. Figure 6 The illustrated embodiment.

[0090] This disclosure improves the drive circuit structure and layout design of the read / write data bus and data lines between different BGs, extends the shared data bus section, and optimizes the BG control logic by merging the read driver and write control unit. This simplifies the read / write bus drive circuit structure and saves layout area. The design of this disclosure can be applied to circuits driving the DDR4 central data bus and BG data lines, but is not limited to this scope; any circuit system that includes data bus control and data distribution can adopt this design.

[0091] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0092] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. An integrated circuit structure, comprising a first repository group and a second repository group, characterized in that, The first repository group and the second repository group share a set of data read / write driver circuits, which include: A read control module is connected to a read data bus, a first read / write data bus, and a second read / write data bus. It is used to read data from the first repository group onto the read data bus via the first read / write data bus, and to read data from the second repository group onto the read data bus via the second read / write data bus. A write control module is connected to a write data bus, a first read / write data bus, and a second read / write data bus. It is used to write data from the write data bus to the first repository group via the first read / write data bus, and to write data from the write data bus to the second repository group via the second read / write data bus. The read data bus includes multiple read data lines, and the write data bus includes multiple write data lines, which are interleaved.

2. The integrated circuit structure as described in claim 1, characterized in that, The write control module includes: A write control unit is connected to the write data bus; The first write driver unit has a first end connected to the write control unit and a second end connected to the first storage group via the first read / write data bus. The second write drive unit has its first end connected to the write control unit and its second end connected to the second storage group via the second read / write data bus.

3. The integrated circuit structure as described in claim 2, characterized in that, The first write driver unit and the second write driver unit are located in the first region, and the first write driver unit and the second write driver unit are arranged side by side in the first direction. The write control unit is arranged side by side with the first region in the second direction, and the second direction is perpendicular to the first direction.

4. The integrated circuit structure as described in claim 3, characterized in that, The first write drive unit is located in the first column, the second write drive unit is located in the second column, and the write control unit occupies the first column and the second column in the first direction.

5. The integrated circuit structure as described in claim 3, characterized in that, There is a gap extending along the second direction between the first write driver unit and the second write driver unit, and the projection of a segment of the first read / write data bus and the projection of a segment of the second read / write data bus are located within the gap.

6. The integrated circuit structure as described in claim 3, characterized in that, The first repository group and the second repository group are located in the second region, and the second region, the first region, and the write control unit are sequentially arranged in the second direction.

7. The integrated circuit structure as described in claim 1, characterized in that, The read control module includes: The first read control unit is connected to the first storage group via a first read / write data bus. The second read control unit has its first end connected to the second storage group via a second read / write data bus. The read drive unit is connected to the second end of the first read control unit, the second end of the second read control unit, and the read data bus.

8. The integrated circuit structure as described in claim 7, characterized in that, The first read control unit and the second read control unit are located in the third region. The first read control unit and the second read control unit are arranged side by side in the first direction. The third region is arranged side by side with the read drive unit in the second direction, which is perpendicular to the first direction.

9. The integrated circuit structure as described in claim 7, characterized in that, The first read control unit is located in the first column, the second read control unit is located in the second column, and the read drive unit occupies the first column and the second column in a first direction.

10. The integrated circuit structure as described in claim 8, characterized in that, The first repository group and the second repository group are located in the second region, and the second region, the third region, and the read drive unit are arranged sequentially in the second direction.

11. The integrated circuit structure as described in claim 5, characterized in that, The first read / write data bus and the second read / write data bus are interleaved.

12. The integrated circuit structure according to any one of claims 1 to 11, characterized in that, The first repository group and the second repository group are arranged side by side in a first direction.

13. The integrated circuit structure as described in claim 1, characterized in that, The multiple read data lines and the multiple write data lines are arranged alternately in the first wiring area and the second wiring area. The first wiring area, the read control module, and the second wiring area are arranged side by side in the first direction. The read data lines and the write data lines extend along the second direction in both the first wiring area and the second wiring area. The second direction is perpendicular to the first direction.

14. The integrated circuit structure as described in claim 13, characterized in that, A first power line is provided on the side of the first wiring area adjacent to the read control module, and the first power line extends along the second direction; a second power line is provided on the side of the second wiring area adjacent to the read control module, and the second power line extends along the second direction.

15. The integrated circuit structure as described in claim 14, characterized in that, A first shielding line is provided on the side of the first wiring area away from the read control module, and the first shielding line extends along the second direction; a second shielding line is provided on the side of the second wiring area away from the read control module, and the second shielding line extends along the second direction.

16. The integrated circuit structure as described in claim 13, characterized in that, The first read / write data bus and the second read / write data bus extend along the second direction within the third wiring area. The third wiring area is located between the first wiring area and the second wiring area. A third power line is provided on the side of the third wiring area adjacent to the first wiring area, and a fourth power line is provided on the side of the third wiring area adjacent to the second wiring area. Both the third power line and the fourth power line extend along the second direction.

17. A memory structure, characterized in that, include: The first repository group and the second repository group are combined and arranged in the first layout area, and the first repository group and the second repository group share a set of integrated circuit structures as described in any one of claims 1-16; The third and fourth repository groups are combined and arranged in the second layout area, and the third and fourth repository groups share another integrated circuit structure as described in any one of claims 1-16; The first repository group and the second repository group are arranged side by side in a first direction, the third repository group and the fourth repository group are arranged side by side in the first direction, the first layout area and the second layout area are arranged side by side in a second direction, and the second direction is perpendicular to the first direction.

18. The memory structure as described in claim 17, characterized in that, The first repository group, the second repository group, the third repository group, and the fourth repository group are jointly connected to a read data bus and a write data bus. The read data bus includes multiple read data lines, and the write data bus includes multiple write data lines. Both the multiple read data lines and the multiple write data lines extend along the second direction.

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