Method of writing data in a non-volatile memory device, non-volatile memory device and method of operating a memory system

Abstract

A method of writing data in a nonvolatile storage device, a nonvolatile storage device performing the method of writing data, and a method of operating a storage system using the method of writing data are provided. In the method of writing data in a nonvolatile storage device, a write command, a write address, and write data to be programmed are received. When offset information representing a verify level is provided, the offset information is received. The offset information is provided when it is determined that the write data corresponds to a distributed degradation pattern by checking an input / output (I / O) pattern of the write data. When the offset information is received, the write data is programmed based on the offset information such that at least one state among a plurality of states included in a threshold voltage distribution of a storage cell in which the write data is stored is changed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0163790, filed with the Korean Intellectual Property Office (KIPO) on November 30, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The example embodiments generally relate to semiconductor integrated circuits, and more specifically to a method of writing data in a non-volatile memory device, a non-volatile memory device for performing the method of writing data, and a method of operating a memory system using the method of writing data. Background Technology

[0004] Semiconductor memory devices can generally be divided into two categories based on whether they retain the stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when power is off, and non-volatile memory devices, which retain stored data when power is off. Volatile memory devices can perform read and write operations at relatively high speeds, but the contents stored in them may be lost when power is off. Non-volatile memory devices retain their stored contents even when power is off, meaning they can be used to store data that must be retained regardless of whether power is supplied.

[0005] Recently, with the increasing integration of non-volatile memory devices, the reliability associated with the degradation and / or deterioration of data stored in these devices has gradually decreased. Therefore, various solutions to address the degradation problem have been investigated. Summary of the Invention

[0006] At least one example embodiment of this disclosure provides a method for writing data to a non-volatile storage device, which improves and / or enhances the reliability of the data to be stored.

[0007] At least one example embodiment of this disclosure provides a non-volatile storage device for performing a method of writing data.

[0008] At least one example embodiment of this disclosure provides a method for operating a storage system using a method of writing data.

[0009] According to an example embodiment, in a method of writing data to a non-volatile storage device, a write command, a write address, and write data to be programmed are received. Offset information is received when offset information representing a verification level is provided. Offset information is provided when it is determined, by examining the input / output (I / O) pattern of the write data, that the write data corresponds to a predetermined or expected distribution degradation pattern. Upon receiving the offset information, the write data is programmed based on the offset information, causing at least one of a plurality of states included in the threshold voltage distribution of the storage cell storing the write data to change.

[0010] According to an example embodiment, a non-volatile storage device includes a memory cell array and processing circuitry. The memory cell array includes a plurality of memory cells. The processing circuitry receives a write command, a write address, and write data to be programmed, receives offset information representing a verification level, and, upon receiving the offset information, programs the write data based on the offset information such that at least one of a plurality of states included in the threshold voltage distribution of the memory cell storing the write data changes. The offset information is provided when it is determined, by examining the input / output (I / O) pattern of the write data, that the write data corresponds to a predetermined or expected distribution degradation pattern.

[0011] According to an example embodiment, in a method of operating a memory system including a memory controller and a non-volatile memory device, a write command, a write address, and write data to be programmed are sent to the non-volatile memory device via the memory controller. The memory controller detects the input / output (I / O) pattern of the write data. When it is determined that the write data is either writing cold data or reading hot data, the memory controller selects an optimal or improved verification level. Writing cold data is data that has been written less than a predetermined or expected first number of times. Reading hot data is data that has been read more than a predetermined or expected second number of times. Offset information including the optimal or improved verification level is generated by the memory controller. The offset information is sent by the memory controller to the non-volatile memory device. The non-volatile memory device changes at least one verification level from a first verification level to an Nth verification level based on the offset information. The first verification level to the Nth verification level respectively correspond to a first state to an Nth state included in a threshold voltage distribution. The non-volatile memory device performs one or more programming cycles on the write data based on the first to Nth verification levels, where at least one verification level has been changed, such that at least one of the first to Nth states is changed. The first state corresponds to the lowest voltage level, and the Nth state corresponds to the highest voltage level. When writing cold data, at least one state is changed to increase the interval between the (N-1)th and Nth states. When writing hot data, at least one state is changed to increase the interval between the first and second states.

[0012] In the method for writing data, the method for operating a non-volatile storage device, and the method for operating a storage system according to the example embodiments, the I / O pattern of the data to be written can be checked in real time or at runtime. When a specific, predetermined, or anticipated pattern is detected, a specific verification level can be adjusted or controlled to increase the margin of a specific state corresponding to degradation susceptible to the specific pattern (e.g., to increase the interval between adjacent states). Along with the written data, information associated with or related to the adjusted verification level can be provided as offset information. Therefore, degradation of the written data can be effectively reduced or prevented, and reliability can be improved or enhanced. Attached Figure Description

[0013] Illustrative and non-limiting exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figure 1 This is a flowchart illustrating a method for writing data to a non-volatile storage device according to an example embodiment.

[0015] Figure 2 This is a block diagram illustrating a storage system according to an example embodiment.

[0016] Figure 3 This is a block diagram illustrating a non-volatile storage device according to an example embodiment.

[0017] Figure 4 yes Figure 3 A perspective view of an example of a memory block included in a memory cell array included in a non-volatile storage device.

[0018] Figure 5 It shows a reference. Figure 4 The circuit diagram of the equivalent circuit of the described memory block.

[0019] Figure 6 This is a block diagram illustrating an example of a memory controller included in a storage system according to an example embodiment.

[0020] Figure 7 This is a block diagram illustrating a storage system according to an example embodiment.

[0021] Figure 8 It is shown Figure 1 A flowchart illustrating an example of receiving offset information.

[0022] Figure 9 It is shown Figure 1 A flowchart illustrating an example of programming the written data based on offset information.

[0023] Figure 10 It is shown Figure 9 A flowchart illustrating an example of programming operations.

[0024] Figure 11 and Figure 12 It is used to describe Figure 10 The diagram shows the operation.

[0025] Figure 13 It is shown Figure 9 A flowchart of another example of programming operations.

[0026] Figure 14 and Figure 15 It is used to describe Figure 13 The diagram shows the operation.

[0027] Figure 16 It is shown Figure 9 A flowchart of another example of programming operations.

[0028] Figure 17 It is used to describe Figure 16 The diagram shows the operation.

[0029] Figure 18 It is shown Figure 9 A flowchart of another example of programming operations.

[0030] Figure 19 and Figure 20 It is used to describe Figure 18 The diagram shows the operation.

[0031] Figure 21 and Figure 22 This is a flowchart illustrating a method for writing data to a non-volatile storage device according to an example embodiment.

[0032] Figure 23 This is a block diagram illustrating a storage device and a storage system including the storage device according to an example embodiment. Detailed Implementation

[0033] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which exemplary embodiments are illustrated. However, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0034] Figure 1 This is a flowchart illustrating a method for writing data to a non-volatile storage device according to an example embodiment.

[0035] Reference Figure 1 The method for writing data according to the example embodiment is performed by a non-volatile storage device comprising multiple storage cells. Detailed configuration of the non-volatile storage device and the storage system including the non-volatile storage device will be provided in reference to... Figures 2 to 7 Describe it.

[0036] In the method for writing data to a non-volatile storage device according to an example embodiment, a write command, a write address, and write data to be programmed are received (operation S100). For example, the write command, write address, and write data can be sent from a memory controller included in a storage system to the non-volatile storage device.

[0037] Receive offset information representing the verification level (operation S200). Offset information is provided when it is determined, by checking the input / output (I / O) mode of the written data, that the written data corresponds to a predetermined or expected distribution deterioration pattern. For example, the memory controller can determine the I / O mode of the written data, and the offset information generated as a result of this determination can be sent from the memory controller to the non-volatile storage device.

[0038] In some example embodiments, the distributed degradation mode may include a first degradation mode associated with data retention characteristics and a second degradation mode associated with read interference characteristics. For example, when the written data is cold data that has been written or programmed fewer than a predetermined or expected first number of times, the written data may be determined to correspond to the first degradation mode. For example, when the written data is hot data that has been read or retrieved more than a predetermined or expected second number of times, the written data may be determined to correspond to the second degradation mode. (Refer to...) Figure 8 Describe operation S200 in detail.

[0039] although Figure 1 The example shows the execution of operation S100 followed by operation S200, but the example embodiment is not limited thereto, and operation S100 and operation S200 may be executed substantially simultaneously or concurrently.

[0040] When offset information is received, the write data is programmed based on the offset information, causing at least one of the multiple states included in the threshold voltage distribution of the storage cell storing the write data to change (operation S300). For example, the multiple states may include multiple programming states, and the write data can be programmed to change only some or a portion of the multiple programming states.

[0041] In some example embodiments, the multiple states may include a first state through an Nth state, where N is a natural number greater than or equal to 2. For example, the first state may correspond to the lowest voltage level, and the Nth state may correspond to the highest voltage level. For example, when writing data corresponds to a first degradation mode, the writing data may be programmed to increase the interval between the (N-1)th state and the Nth state. For example, when writing data corresponds to a second degradation mode, the writing data may be programmed to increase the interval between the first state and the second state. (See also...) Figures 9 to 20 Describe the operation of S300 in detail.

[0042] In non-volatile memory devices such as NAND flash memory, when data is programmed, the data is maintained in a distributed form (e.g., a distribution of cells or a distribution of cell threshold voltages). This distribution changes or shifts due to degradation and / or deterioration, and programming parameters are set or controlled to overcome these distribution changes. Among the various programming parameters, verification levels can be used to specify or set the starting position for each state in the distribution. If the interval (or gap) between the verification levels of two adjacent states is relatively wide, it indicates that the distribution margin between the two adjacent states is relatively wide, and therefore, it can be said that the two adjacent states are relatively strong or robust to degradation that leads to changes in the distribution. However, if all verification levels are fixed, it may be difficult to effectively overcome all types of degradation that may occur on the written data.

[0043] In the method for writing data to a non-volatile storage device according to the example embodiment, the I / O pattern of the data to be written can be checked in real time or at runtime. When a specific, predetermined, or anticipated pattern is detected, a specific verification level can be adjusted or controlled to increase the margin of a specific state corresponding to degradation susceptible to the specific pattern (e.g., to increase the interval between adjacent states). Along with the written data, information associated with or related to the adjusted verification level can be provided as offset information. Therefore, degradation of the written data can be effectively reduced or prevented, and reliability can be improved or enhanced.

[0044] Figure 2 This is a block diagram illustrating a storage system according to an example embodiment.

[0045] Reference Figure 2 The storage system 10 includes a memory controller 20 and a non-volatile storage device 40. The storage system 10 may also include multiple signal lines 30 that electrically connect the memory controller 20 to the non-volatile storage device 40.

[0046] The non-volatile storage device 40 is controlled by the memory controller 20. For example, based on the data from the host device (e.g., Figure 23Upon request from the host device 1100, the memory controller 20 may store data (e.g., write or program) to the non-volatile storage device 40, or may retrieve (e.g., read or sense) data from the non-volatile storage device 40.

[0047] Multiple signal lines 30 may include control lines, command lines, address lines, data input / output (I / O) lines, and power lines. The memory controller 20 can send commands (CMD), addresses (ADDR), and control signals (CTRL) to the non-volatile memory device 40 via the command lines, address lines, and control lines; it can exchange data signals (DAT) with the non-volatile memory device 40 via the data I / O lines; and it can send power supply voltages (PWR) to the non-volatile memory device 40 via the power lines. Although not explicitly stated... Figure 2 As shown, but the plurality of signal lines 30 may also include DQS lines for transmitting a data strobe signal (DQS). In some example embodiments, at least some or all of the signal lines 30 may be referred to as channels.

[0048] Figure 3 This is a block diagram illustrating a non-volatile storage device according to an example embodiment.

[0049] Reference Figure 3 The non-volatile storage device 100 includes a memory cell array 110, an address decoder 120, a page buffer circuit 130, a data input / output (I / O) circuit 140, a voltage generator 150, and / or a control circuit 160.

[0050] The memory cell array 110 is connected to the address decoder 120 via multiple string select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The memory cell array 110 is also connected to the page buffer circuitry 130 via multiple bit lines (BL). The memory cell array 110 may include multiple memory cells (e.g., multiple non-volatile memory cells) connected to the multiple word lines (WL) and multiple bit lines (BL). The memory cell array 110 may be divided into multiple memory blocks BLK1, BLK2, ..., BLKz, each memory block comprising memory cells. Furthermore, each of the multiple memory blocks BLK1, BLK2, ..., BLKz may be divided into multiple pages.

[0051] In some example embodiments, such as referring to Figure 4 and Figure 5 As described, the memory cell array 110 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional (3D) structure (or vertical structure). In some example embodiments, the memory cell array 110 may include a plurality of vertically oriented cell strings (e.g., a plurality of vertical NAND strings) such that at least one memory cell is situated on top of another memory cell.

[0052] The control circuit 160 receives commands CMD and addresses ADDR from an external source (e.g., a memory controller) and controls erase, program, and read operations of the non-volatile memory device 100 based on the commands CMD and ADDR. Erasing operations may include executing a series of erase cycles, and programming operations may include executing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0053] For example, control circuit 160 can generate control signal CON for controlling voltage generator 150, control signal PBC for controlling page buffer circuit 130 based on command CMD, and row address R_ADDR and column address C_ADDR based on address ADDR. Control circuit 160 can provide row address R_ADDR to address decoder 120 and column address C_ADDR to data I / O circuit 140.

[0054] Control circuit 160 can execute according to reference Figure 1 The described example embodiment describes a method for writing data. For example, control circuit 160 may receive offset information OFS, which represents a verification level and is provided when the written data corresponds to a predetermined or expected distribution degradation pattern, and may control the programming cycle of non-volatile storage device 100 based on the offset information OFS. Additionally, control circuit 160 may, based on reference to… Figure 21 and Figure 22 The described example embodiments demonstrate how to perform a method for writing data.

[0055] Address decoder 120 can be connected to memory cell array 110 via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL.

[0056] For example, in a data erase / write / read operation, the address decoder 120 can determine at least one word line among multiple word lines WL as the selected word line based on the row address R_ADDR, and can determine the remaining word lines or unselected word lines of the multiple word lines WL other than the selected word line as unselected word lines.

[0057] In addition, during data erase / write / read operations, the address decoder 120 can determine at least one of the multiple string select lines SSL as the selected string select line based on the row address R_ADDR, and can determine the remaining string select lines or unselected string select lines of the multiple string select lines SSL excluding the selected string select line.

[0058] Furthermore, during data erase / write / read operations, the address decoder 120 can determine at least one of the multiple ground selection lines GSL as the selected ground selection line based on the row address R_ADDR, and can determine the remaining ground selection lines or unselected ground selection lines of the multiple ground selection lines GSL other than the selected ground selection line as unselected ground selection lines.

[0059] Voltage generator 150 can generate the voltage VS required for the operation of non-volatile memory device 100 based on voltage PWR and control signal CON. Voltage VS can be applied to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL via address decoder 120. Additionally, voltage generator 150 can generate the erase voltage VERS required for data erase operations based on power supply PWR and control signal CON. Eraser voltage VERS can be applied directly or via bit line BL to memory cell array 110.

[0060] For example, during an erase operation, voltage generator 150 may apply an erase voltage VERS to the common source line and / or bit line BL of the memory block (e.g., a selected memory block), and may apply an erase permission voltage (e.g., a ground voltage) to all or some word lines of the memory block via address decoder 120. Additionally, during an erase verification operation, voltage generator 150 may apply an erase verification voltage VEVFY to all word lines of the memory block simultaneously or sequentially, one word line at a time.

[0061] For example, during programming operations, voltage generator 150 can apply a programming voltage to selected word lines and a programming pass voltage to unselected word lines via address decoder 120. Additionally, during programming verification operations, voltage generator 150 can apply a programming verification voltage to selected word lines and a verification pass voltage to unselected word lines via address decoder 120.

[0062] Additionally, during normal read operations, voltage generator 150 can apply a read voltage to the selected word line and a read pass voltage to the unselected word line via address decoder 120. During data recovery read operations, voltage generator 150 can apply a read voltage to the word line adjacent to the selected word line and a recovery read voltage to the selected word line via address decoder 120.

[0063] Page buffer circuitry 130 can be connected to memory cell array 110 via multiple bit lines BL. Page buffer circuitry 130 may include multiple page buffers. In some example embodiments, each page buffer may be connected to one bit line. In other example embodiments, each page buffer may be connected to two or more bit lines.

[0064] Page buffer circuit 130 can store data DAT to be programmed into memory cell array 110 or can read data DAT sensed from memory cell array 110. In other words, page buffer circuit 130 can operate as a write driver or a sense amplifier depending on the operating mode of non-volatile memory device 100.

[0065] Data I / O circuit 140 can be connected to page buffer circuit 130 via data line DL. Data I / O circuit 140 can provide data DAT from outside non-volatile memory device 100 to memory cell array 110 via page buffer circuit 130, or it can provide data DAT from memory cell array 110 to outside non-volatile memory device 100 based on column address C_ADDR.

[0066] Figure 4 yes Figure 3 A perspective view of an example of a memory block included in a memory cell array included in a non-volatile storage device.

[0067] Reference Figure 4 The memory block BLKi includes multiple cell strings (e.g., multiple vertical NAND strings) formed on a substrate in a three-dimensional structure (or vertical structure). The memory block BLKi includes a structure extending along a first direction D1, a second direction D2, and a third direction D3.

[0068] A substrate 111 is provided. For example, the substrate 111 may have a well containing a first type of charge carrier impurity (e.g., a first conductivity type). For example, the substrate 111 may have a p-well formed by implanting a Group 3 element such as boron (B). In particular, the substrate 111 may have a pouch-shaped p-well disposed within an n-well. In some example embodiments, the substrate 111 has a p-type well (or a p-type pouch-shaped well). However, the conductivity type of the substrate 111 is not limited to p-type.

[0069] A plurality of doped regions 311, 312, 313, and 314, arranged along a second direction D2, are disposed in / on a substrate 111. These plurality of doped regions 311 to 314 may have a second type of charge carrier impurity (e.g., a second conductivity type) different from the first type of substrate 111. In some exemplary embodiments according to the invention, the first to fourth doped regions 311 may have an n-type conductivity. However, the conductivity type of the first to fourth doped regions 311 is not limited to n-type.

[0070] A plurality of insulating materials 112 extending along a first direction D1 are sequentially disposed on a region of substrate 111 between the first doped region 311 and the second doped region 312 along a third direction D3. For example, the plurality of insulating materials 112 are disposed at a specific distance spaced along the third direction D3. For example, the insulating materials 112 may include insulating materials such as oxide layers.

[0071] On the region of substrate 111 between the first doped region 311 and the second doped region 312, a plurality of pillars 113 are sequentially disposed along a first direction D1 and passing through an insulating material along a third direction D3. For example, the plurality of pillars 113 contact the substrate 111 through the insulating material 112.

[0072] In some exemplary embodiments, each pillar 113 may comprise a variety of materials. For example, the channel layer 114 of each pillar 113 may comprise a silicon material having a first conductivity type. For example, the channel layer 114 of each pillar 113 may comprise a silicon material having the same conductivity type as the substrate 111. In some exemplary embodiments conceived according to the present invention, the channel layer 114 of each pillar 113 comprises p-type silicon. However, the channel layer 114 of each pillar 113 is not limited to p-type silicon.

[0073] The internal material 115 of each pillar 113 includes an insulating material. For example, the internal material 115 of each pillar 113 may include an insulating material such as silicon oxide. In some examples, the internal material 115 of each pillar 113 may include an air gap. As discussed herein, the term "air" may refer to atmospheric air or other gases that may be present during the manufacturing process.

[0074] An insulating layer 116 is disposed along the exposed surfaces of the insulating material 112, pillars 113, and substrate 111 in the region between the first doped region 311 and the second doped region 312. For example, as shown, the insulating layer 116 disposed on the surface of the insulating material 112 may be located between the pillars 113 and a plurality of stacked first conductive materials 211, 221, 231, 241, 251, 261, 271, 281, and 291. In some examples, it is not necessary to provide an insulating layer 116 between the first conductive materials 211 to 291 corresponding to the ground select line GSL (e.g., 211) and the string select line SSL (e.g., 291). In some example embodiments, the ground select line GSL is the bottommost first conductive material in the stack of the first conductive materials 211 to 291, and the string select line SSL is the topmost first conductive material in the stack of the first conductive materials 211 to 291.

[0075] In the region between the first doped region 311 and the second doped region 312, a plurality of first conductive materials 211 to 291 are disposed on the surface of the insulating layer 116. For example, a first conductive material 211 extending along a first direction D1 is disposed between the insulating material 112 adjacent to the substrate 111 and the substrate 111. More specifically, the first conductive material 211 extending along the first direction D1 is disposed between the insulating layer 116 and the substrate 111 at the bottom of the insulating material 112 adjacent to the substrate 111.

[0076] A first conductive material extending along a first direction D1 is disposed between an insulating layer 116 at the top of a particular insulating material in the insulating material 112 and an insulating layer 116 at the bottom of a particular insulating material in the insulating material 112. For example, a plurality of first conductive materials 221 to 281 extending along the first direction D1 are disposed between the insulating materials 112, and it is understood that an insulating layer 116 is disposed between the insulating materials 112 and the first conductive materials 221 to 281. The first conductive materials 211 to 291 may be made of conductive metal, but in other exemplary embodiments of the present invention, the first conductive materials 211 to 291 may include conductive materials such as polycrystalline silicon.

[0077] In the region between the second doped region 312 and the third doped region 313, a structure identical to that on the first doped region 311 and the second doped region 312 can be provided. In the region between the second doped region 312 and the third doped region 313, a plurality of insulating materials 112 extending along a first direction D1 are provided. Furthermore, a plurality of pillars 113 are sequentially provided along the first direction D1 and pass through the plurality of insulating materials 112 along a third direction D3. An insulating layer 116 is provided on the exposed surfaces of the plurality of insulating materials 112 and the plurality of pillars 113, and a plurality of first conductive materials 211 to 291 extend along the first direction D1. Similarly, in the region between the third doped region 313 and the fourth doped region 314, a structure identical to that on the first doped region 311 and the second doped region 312 can be provided.

[0078] Multiple drain regions 320 are respectively disposed on multiple pillars 113. The drain regions 320 may comprise silicon material doped with a second type of charge carrier impurity. For example, the drain regions 320 may comprise silicon material doped with an n-type dopant. In some exemplary embodiments of the present invention, the drain regions 320 comprise n-type silicon material. However, the drain regions 320 are not limited to n-type silicon material.

[0079] On the drain region, a plurality of second conductive materials 331, 332, and 333 extending along a second direction D2 are disposed. The second conductive materials 331 to 333 are spaced apart from each other by a specific distance along a first direction D1. The second conductive materials 331 to 333 are respectively connected to the drain region 320 in their respective regions. The drain region 320 and the second conductive materials 331 to 333 extending along the second direction D2 can be connected via each contact plug. For example, each contact plug can be a conductive plug made of a conductive material such as metal. The second conductive materials 331 to 333 may include metallic materials. The second conductive materials 331 to 333 may include conductive materials such as polycrystalline silicon.

[0080] exist Figure 4 In the example, first conductive materials 211 to 291 can be used to form word lines WL, serial select lines SSL, and ground select lines GSL. For example, first conductive materials 221 to 281 can be used to form word lines WL, wherein conductive materials belonging to the same layer can be interconnected. Second conductive materials 331 to 333 can be used to form bit lines BL. The number of layers of first conductive materials 211 to 291 can be varied depending on the process and control technology.

[0081] Figure 5 It shows a reference. Figure 4 The circuit diagram of the equivalent circuit of the described memory block.

[0082] Figure 5 The memory block BLKi can be formed on the substrate in a three-dimensional (or vertical) structure. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0083] Reference Figure 5 The memory block BLKi may include multiple NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each NAND string NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground select transistor GST. For example, bit lines BL1 to BL3 may correspond to... Figure 4 The second conductive materials 331 to 333 in the middle, and the common source line CSL can be interconnected. Figure 4 It is formed by the first doped region 311 to the fourth doped region 314 in the middle.

[0084] Each string select transistor (SST) can be connected to a corresponding string select line (SSL1, SSL2, and SSL3). Multiple memory cells MC1 through MC8 can be connected to corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. Each ground select transistor (GST) can be connected to a corresponding ground select line (GSL1, GSL2, and GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1 through BL3), and each ground select transistor (GST) can be connected to the common source line CSL. Figure 5 In the example, some string select transistors SST are connected to the same bit line (e.g., one of BL1 to BL3) to connect the corresponding NAND strings to the same bit line via the select voltage applied to the appropriate string select lines SSL1 to SSL3 and the ground select lines GSL1 to GSL3, thereby making the appropriate selection.

[0085] Cell strings connected to a single bit line can form a column, and cell strings connected to a single string select line can form a row. For example, cell strings NS11, NS21, and NS31 connected to the first bit line BL1 can correspond to the first column, and cell strings NS11, NS12, and NS13 connected to the first string select line SSL1 can form the first row.

[0086] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separate. Memory cells located on the same semiconductor layer share a single word line. Strings of cells in the same row share a string select line. The common source line CSL is connected to all cell strings.

[0087] exist Figure 5 In the example, memory block BLKi is shown connected to eight word lines WL1 to WL8 and three bit lines BL1 to BL3, and each of the NAND strings NS11 to NS33 is shown to include eight memory cells MC1 to MC8. However, the example embodiment is not limited thereto. In some example embodiments, each memory block may be connected to any number of word lines and bit lines, and each NAND string may include any number of memory cells.

[0088] A three-dimensional vertical array structure may include vertically oriented NAND strings such that at least one memory cell is situated above another memory cell. At least one memory cell may include a charge trapping layer. The following patent documents (entirely incorporated herein by reference) describe suitable configurations of memory cell arrays including a three-dimensional vertical array structure, wherein the three-dimensional memory array is configured as multiple layers and shares word lines and / or bit lines between the multiple layers: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0089] Although the array of memory cells included in the non-volatile memory device according to the example embodiment is described based on a NAND flash memory device, the non-volatile memory device according to the example embodiment can be any non-volatile memory device, such as phase random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc.

[0090] Figure 6 This is a block diagram illustrating an example of a memory controller included in a storage system according to an example embodiment.

[0091] Reference Figure 6 The memory controller 400 may include a processor 410, a memory 420, a parameter manager 430, a host interface (I / F) 440, an error correction code (ECC) engine 450, a memory interface (I / F) 460, and / or an advanced encryption standard (AES) engine 470.

[0092] Processor 410 can respond to a host device (e.g., via host interface 440) Figure 23 The host device 1100 receives commands to control the operation of the memory controller 400. For example, the processor 410 can control the storage system (e.g., Figure 2 The operation of the storage system 10) can be controlled by using firmware for operating the storage system.

[0093] Memory 420 can store instructions and data executed and processed by processor 410. For example, memory 420 can be implemented using volatile storage devices, such as dynamic random access memory (DRAM), static random access memory (SRAM), cache memory, etc.

[0094] Parameter Manager 430 can be used to execute based on reference Figure 1The described example embodiment describes a method for writing data. For example, parameter manager 430 can perform this. Figure 1 The operation S200 is described above. The parameter manager 430 may include an I / O mode detection unit (IPDU) 432 for detecting or sensing I / O modes of written data and a verification level control unit (VLCU) 434 for controlling or adjusting verification levels. The verification level control unit 434 may include a preset (or predetermined or expected) lookup table (LUT) 436 for controlling or adjusting verification levels. For example, the lookup table 436 may include a relationship between the I / O mode of written data and its optimal or improved verification level. In some example embodiments, at least a portion of the parameter manager 430 may be implemented as hardware. For example, at least a portion of the parameter manager 430 may be included in a computer-based electronic system. In other example embodiments, at least a portion of the parameter manager 430 may be implemented as instruction code or program routines (e.g., software programs). For example, the instruction code or program routines may be executed by the computer-based electronic system and may be stored in any storage device located inside or outside the computer-based electronic system.

[0095] The ECC engine 450 used for error correction can perform coding and modulation using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc., or can perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0096] Host interface 440 provides a physical connection between the host device and the storage system. Host interface 440 provides an interface corresponding to the bus format of the host device for communication between the host device and the storage system. In some example embodiments, the bus format of the host device may be a Small Computer System Interface (SCSI) or a Serial Attached SCSI (SAS) interface. In other example embodiments, the bus format of the host device may be USB, Peripheral Component Interconnect (PCI) Rapid (PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Non-Volatile Memory (NVM) Rapid (NVMe), etc.

[0097] Memory interface 460 can be used with non-volatile memory devices (e.g., Figure 2The memory interface 460 exchanges data with the non-volatile storage device 40. The memory interface 460 can transfer data to or receive data read from the non-volatile storage device. In some example embodiments, the memory interface 460 may be connected to the non-volatile storage device via a single channel. In other example embodiments, the memory interface 460 may be connected to the non-volatile storage device via two or more channels. For example, the memory interface 460 may be configured to conform to standard protocols such as Switched or Open NAND Flash Interface (ONFI).

[0098] The AES engine 470 can perform at least one of encryption and decryption operations on data input to the memory controller 400 using a symmetric key algorithm. Although not described in detail, the AES engine 470 may include an encryption module and a decryption module. For example, the encryption and decryption modules may be implemented as separate modules. Alternatively, a module capable of performing encryption and decryption operations may be implemented within the AES engine 470.

[0099] Figure 7 This is a block diagram illustrating a storage system according to an example embodiment.

[0100] Reference Figure 7 The storage system 50 may include a storage device 500 and a memory controller 600. Figure 7 The interface between the storage device 500 and the memory controller 600 is shown in detail.

[0101] The storage device 500 may include first to eighth pins P11, P12, P13, P14, P15, P16, P17 and P18, a memory interface circuit 510, a control logic circuit 520 and a memory cell array 530.

[0102] The memory interface circuit 510 can receive a chip enable signal nCE from the memory controller 600 via its first pin P11. In response to the chip enable signal nCE, the memory interface circuit 510 can send signals to and receive signals from the memory controller 600 via its second pin P12 to its eighth pin P18. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 510 can send signals to and receive signals from the memory controller 600 via its second pin P12 to its eighth pin P18.

[0103] The memory interface circuit 510 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 600 via pins P12 to P14. The memory interface circuit 510 can receive or send the data signal DQ to the memory controller 600 via pin P17. Command CMD, address ADDR, and data DATA can be sent via the data signal DQ. For example, the data signal DQ can be sent via multiple data signal lines. In some example embodiments, pin P17 may include multiple pins corresponding to multiple data signals DQ.

[0104] The memory interface circuit 510 can obtain the command CMD from the data signal DQ, which is received in the enable portion (e.g., a high-level state) of the command latch enable signal CLE based on the switching time point of the write enable signal nWE. The memory interface circuit 510 can also obtain the address ADDR from the data signal DQ, which is received in the enable portion (e.g., a high-level state) of the address latch enable signal ALE based on the switching time point of the write enable signal nWE.

[0105] In some example embodiments, the write enable signal nWE can be held statically (e.g., high or low) and can toggle between high and low. For example, the write enable signal nWE can be toggled during the transmission of command CMD or address ADDR. Therefore, the memory interface circuitry 510 can obtain command CMD or address ADDR based on the switching time of the write enable signal nWE.

[0106] The memory interface circuit 510 can receive the read enable signal nRE from the memory controller 600 via its fifth pin P15. The memory interface circuit 510 can receive the data strobe signal DQS from the memory controller 600 via its sixth pin P16, or it can send the data strobe signal DQS to the memory controller 600.

[0107] In the data output operation of the storage device 500, the memory interface circuit 510 can receive a switched read enable signal nRE via pin 5 P15 before outputting the data DATA. The memory interface circuit 510 can generate a data strobe signal DQS that switches based on the switching of the read enable signal nRE. For example, the memory interface circuit 510 can generate a data strobe signal DQS that starts switching after a predetermined or anticipated delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The memory interface circuit 510 can send a data signal DQ including the data DATA based on the switching time of the data strobe signal DQS. Therefore, the data DATA can coincide with the switching time of the data strobe signal DQS and can be sent to the memory controller 600.

[0108] In the data input operation of the storage device 500, when a data signal DQ including data DATA is received from the memory controller 600, the memory interface circuit 510 can receive a switching data strobe signal DQS from the memory controller 600 along with the data DATA. The memory interface circuit 510 can obtain the data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the memory interface circuit 510 can sample the data signal DQ at the rising and falling edges of the data strobe signal DQS and obtain the data DATA.

[0109] In some example embodiments, the command CMD, address ADDR, and data DATA obtained based on the write enable signal nWE and the data strobe signal DQS can correspond to the command, address, and data used to perform a data write operation according to the example embodiment.

[0110] The memory interface circuit 510 can send a ready / busy output signal nR / B to the memory controller 600 via pin 8 P18. The memory interface circuit 510 can also send status information of the memory device 500 to the memory controller 600 via the ready / busy output signal nR / B. When the memory device 500 is in a busy state (e.g., when an operation is being performed on the memory device 500), the memory interface circuit 510 can send a ready / busy output signal nR / B indicating the busy state to the memory controller 600. When the memory device 500 is in a ready state (e.g., when no operation is being performed on the memory device 500 or an operation has been completed), the memory interface circuit 510 can send a ready / busy output signal nR / B indicating the ready state to the memory controller 600. For example, when the memory device 500 reads data DATA from the memory cell array 530 in response to a page read command, the memory interface circuit 510 can send a ready / busy output signal nR / B indicating a busy state (e.g., a low level) to the memory controller 600. For example, when the storage device 500 programs data DATA into the memory cell array 530 in response to a programming command, the memory interface circuit 510 can send a ready / busy output signal nR / B indicating a busy state to the memory controller 600.

[0111] Control logic circuit 520 can control the overall operation of storage device 500. Control logic circuit 520 can receive commands CMD and addresses ADDR obtained from memory interface circuit 510. Control logic circuit 520 can generate control signals for controlling other components of storage device 500 in response to the received commands CMD and addresses ADDR. For example, control logic circuit 520 can generate various control signals for programming data DATA to or reading data DATA from memory cell array 530.

[0112] The memory cell array 530 can store data obtained from the memory interface circuit 510 under the control of the control logic circuit 520. The memory cell array 530 can also output the stored data to the memory interface circuit 510 under the control of the control logic circuit 520.

[0113] The storage cell array 530 may include multiple storage cells. For example, the multiple storage cells may be flash memory cells. However, the example embodiment is not limited to this, and the storage cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, MRAM cells, etc. In the following description, NAND flash memory cells are used as the primary example of storage cells.

[0114] The memory controller 600 may include first to eighth pins P21, P22, P23, P24, P25, P26, P27, and P28, as well as a controller interface circuit 610. The first pins P21 to P28 may correspond to the first pins P11 to P18 of the memory device 500, respectively.

[0115] The controller interface circuit 610 can send a chip enable signal nCE to the memory device 500 via the first pin P21. The controller interface circuit 610 can send signals to the memory device 500 selected by the chip enable signal nCE and receive signals from the memory device 500 selected by the chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0116] The controller interface circuit 610 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 500 via pins P22 to P24. The controller interface circuit 610 can send the data signal DQ to the memory device 500 or receive the data signal DQ from the memory device 500 via pin P27.

[0117] The controller interface circuit 610 can send a data signal DQ, including a command CMD or an address ADDR, to the memory device 500 along with the switched write enable signal nWE. The controller interface circuit 610 can also send the data signal DQ, including a command CMD, to the memory device 500 by sending a command latch enable signal CLE with an enabled state. Furthermore, the controller interface circuit 610 can send the data signal DQ, including an address ADDR, to the memory device 500 by sending an address latch enable signal ALE with an enabled state.

[0118] The controller interface circuit 610 can send a read enable signal nRE to the memory device 500 via its fifth pin P25. The controller interface circuit 610 can receive a data strobe signal DQS from the memory device 500 or send a data strobe signal DQS to the memory device 500 via its sixth pin P26.

[0119] In the data output operation of the storage device 500, the controller interface circuit 610 can generate and send a switching read enable signal nRE to the storage device 500. For example, before outputting data DATA, the controller interface circuit 610 can generate a read enable signal nRE that changes from a static state (e.g., high or low level) to a switching state. Therefore, the storage device 500 can generate a switching data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 610 can receive a data signal DQ including data DATA from the storage device 500 along with the switching data strobe signal DQS. The controller interface circuit 610 can obtain data DATA from the data signal DQ based on the switching time of the data strobe signal DQS.

[0120] In the data input operation of the storage device 500, the controller interface circuit 610 can generate a switching data strobe signal DQS. For example, before sending data DATA, the controller interface circuit 610 can generate a data strobe signal DQS that changes from a static state (e.g., high or low level) to a switching state. The controller interface circuit 610 can send a data signal DQ including data DATA to the storage device 500 based on the switching time of the data strobe signal DQS.

[0121] The controller interface circuit 610 can receive the ready / busy output signal nR / B from the storage device 500 via pin 8 P28. The controller interface circuit 610 can determine the status information of the storage device 500 based on the ready / busy output signal nR / B.

[0122] Figure 8 It is shown Figure 1 A flowchart illustrating an example of receiving offset information.

[0123] Reference Figure 1 and Figure 8 In operation S200, the I / O mode for writing data can be detected (operation S210). For example, operation S210 can be performed by... Figure 6 The I / O mode detection unit 432 in the middle is executed.

[0124] In some example embodiments, I / O patterns for writing data can be detected based on write addresses. For example, I / O patterns for writing data can be identified or confirmed based on the location (or popularity) of write addresses tracked in real time (or at runtime). For example, a counter can be used to check the location of write addresses. As another example, various machine learning schemes can be used to track and / or predict the location of write addresses. For example, as will be referred to... Figure 23 As described, a neural processing unit (NPU) can be used to perform machine learning.

[0125] In other example embodiments, the I / O pattern of written data can be detected based on the number of times the written data is accessed. For example, the I / O pattern of written data can be identified or confirmed based on access patterns tracked in real time. For instance, when the number of accesses (or access frequency) of specific data is relatively high (e.g., higher than a reference number), the data can be classified as hot data. When the number of accesses of specific data is relatively low (e.g., lower than a reference number), the data can be classified as cold data.

[0126] When the written data corresponds to a distributed degradation mode and the verification level needs to be changed (operation S220: Yes), an optimal or improved verification level can be selected (operation S230), and offset information including the optimal or improved verification level can be generated and provided (operation S240). For example, operations S220, S230, and S240 can be performed by... Figure 6 The verification level control unit 434 or lookup table 436 in the middle is executed.

[0127] In some example embodiments, the I / O mode for writing data may include writing hot data, writing cold data, reading hot data, and reading cold data, categorized based on the data's address, location, and / or the number of times the data is accessed.

[0128] In some example embodiments, distribution degradation can include data retention degradation and read interference degradation. Data retention degradation can affect the upper state of a plurality of states included in the threshold voltage distribution of the memory cell, while read interference degradation can affect the lower state of a plurality of states. In other words, the upper state may change or may be altered due to data retention degradation, while the lower state may change or may be altered due to read interference degradation. Distribution degradation modes can include a first degradation mode that is susceptible to (or weakened by) data retention degradation and a second degradation mode that is susceptible to read interference degradation.

[0129] In some example embodiments, when the written data is cold data, for example when the number of write operations against the write address is relatively small, it can be determined that the written data corresponds to a first degradation mode. Therefore, a specific verification level can be changed (e.g., an optimal or improved verification level can be reselected) to improve and / or enhance the reliability of the written data. Cold data can be data that is to be retained or remain in storage space for a relatively long time, and the probability of suffering data retention degradation can be relatively high. Therefore, the reliability of cold data can be improved when it is more resistant or robust to data retention degradation. As mentioned above, data retention degradation can affect the upper state; therefore, for cold data, the verification level can be controlled or adjusted to increase the margin of the upper state. (See also...) Figures 10 to 15 Describes the detailed steps for adjusting the verification level when writing cold data.

[0130] In some example embodiments, when the written data is read-hot data, for example when the number of read operations against the write address and / or the written data is relatively high, it can be determined that the written data corresponds to a second degradation mode. Therefore, a specific verification level can be changed (e.g., selecting an optimal or improved verification level) to improve and / or enhance the reliability of the written data. Read-hot data may be data with a relatively high read frequency and may be relatively more susceptible to read interference degradation. Therefore, the reliability of read-hot data can be improved when it has stronger resistance or robustness to read interference degradation. As mentioned above, read interference degradation can affect the lower state; therefore, for read-hot data, the verification level can be controlled or adjusted to increase the margin of the lower state. (Refer to...) Figures 16 to 20 This describes the detailed steps for adjusting the verification level when reading thermal data.

[0131] In some example embodiments, when selecting an optimal or improved verification level in operation S230, the conditions affecting the error bits of each page can be considered together. The unit of read operation can be a page, and the degree to which multiple states affect reliability (e.g., the degree of error bits) can differ for each page. For example, a particular state of a specific page may have a greater impact on the number of error bits during a read, and vice versa. Therefore, as the number of error bits for a particular page increases, the verification level can be further adjusted to change the margin of the specific states affecting the error bits of that particular page.

[0132] After performing operations S230 and S240, the optimal or improved verification level and / or offset information representing the optimal or improved verification level can be stored (operation S250). For example, the optimal or improved verification level and / or offset information can be stored in a memory controller (e.g., Figure 6 The memory controller 400 includes a memory 420, which includes a parameter storage unit.

[0133] The process can be terminated when the written data does not correspond to the distributed degradation mode and there is no need to change the verification level (operation S220: No).

[0134] In some example embodiments, when the written data is hot data, for example when the number of write operations to the write address is relatively high, it can be determined that the written data does not correspond to the first degradation mode and the second degradation mode. Hot data can be data that is to be written relatively frequently and has a relatively high probability of becoming invalid data, and the probability of suffering data retention degradation can be relatively low. Therefore, hot data can be programmed to be written without adjusting the verification level.

[0135] In some example embodiments, when the written data is cold data, for example when the number of read operations against the write address and / or the written data is relatively small, it can be determined that the written data does not correspond to the first degradation mode and the second degradation mode. Cold data can be read relatively infrequently, and the likelihood of it suffering from read interference degradation can be relatively low. Therefore, cold data can be programmed to be read without adjusting the verification level.

[0136] Figure 9 It is shown Figure 1 A flowchart illustrating an example of writing data programmatically based on offset information.

[0137] Reference Figure 1 and Figure 9 In operation S300, offset information can be received (operation S310). At least one verification level from the first verification level to the Nth verification level can be changed based on the offset information (operation S320). The first verification level to the Nth verification level can respectively correspond to the first to the Nth states included in the threshold voltage distribution of the memory cell storing the written data. One or more programming cycles can be performed on the written data based on the first to Nth verification levels where at least one verification level has been changed, causing at least one state from the first to the Nth state to change (operation S330). The optimal or improved verification level can vary depending on the I / O mode of the written data, and detailed operation will be described later.

[0138] Figure 10 It is shown Figure 9 A flowchart illustrating an example of programming operations. Figure 11 and Figure 12 It is used to describe Figure 10 The diagram shows the operation.

[0139] Reference Figure 9 , Figure 10 , Figure 11 and Figure 12 In operation S310, first offset information can be received (operation S312). For example, the first offset information may indicate that the written data is cold data and corresponds to a first degradation mode, and may include an optimal or improved verification level for improving the reliability of writing cold data.

[0140] In operation S320, the Nth verification level can be changed from the first verification level to the Nth verification level based on the first offset information, thereby changing the Nth state from the first state to the Nth state (operation S322). Among multiple states and multiple verification levels, the first state and the first verification level can correspond to the lowest voltage level, and the Nth state and the Nth verification level can correspond to the highest voltage level. As described above, for writing cold data, the Nth verification level can be controlled or adjusted to increase the margin of the Nth state as the highest state.

[0141] In some example embodiments, it can be as follows Figure 11 Adjust the verification level as shown. In Figure 11 In the distribution of threshold voltage VTH shown, the first to Nth states E, P1, P2, ..., P(N-3), P(N-2), and P(N-1) shown in the upper part, and the first to Nth verification levels VL1, VL2, VL3, ..., VL(N-2), VL(N-1), and VLN shown in the lower part, can represent an example before performing operation S322, for example, the distribution of the initial threshold voltage. Furthermore, the first to Nth states E, P1, P2, ..., P(N-3), P(N-2), and P(N-1)' shown in the lower part, and the first to Nth verification levels VL1, VL2, VL3, ..., VL(N-2), VL(N-1), and VLN' shown in the lower part, can represent an example after performing operation S322 and adjusting the verification levels. For example, the first state E and the first verification level VL1 can represent the erase state and the erase verification level, and the second state P1 to the Nth state P(N-1) and the second verification level VL2 to the Nth verification level VLN can represent the programming state and the programming verification level. For example, when the memory cell is a triple-level cell (TLC), N can be eight.

[0142] For example, when operation S322 is executed, the Nth verification level, which is the highest level, can be increased from VLN to VLN', and the Nth state, which is the highest state, can be changed from P(N-1) to P(N-1)'. In other words, only one programming state and only one programming verification level can be changed. Therefore, the interval between the (N-1)th state and the Nth state can be increased from VD1 to VD1' (e.g., the interval between the (N-1)th verification level and the Nth verification level can be increased), and as the margin of the Nth state increases, the reliability against data retention degradation can be improved. The remaining states and verification levels other than the Nth state and the Nth verification level can be maintained.

[0143] In operation S330, the written data can be programmed one or more times based on the first verification level to the Nth verification level (i.e., from the first verification level to the changed Nth verification level) (operation S332). For example, the programming cycle can include programming operations and programming verification operations. For example, the programming cycle can be repeatedly executed to form Figure 11 The lower part shows the distribution of the threshold voltage VTH.

[0144] In some example embodiments, operation S332 can be performed based on an incremental step pulse programming (ISPP) scheme.

[0145] For example, such as Figure 12 As shown, multiple programming loops PLOOP1, PLOOP2, PLOOP3, ..., PLOOPK can be executed sequentially, where K is a natural number greater than or equal to 2. For each programming loop, the programming operations in programming operations PO1, PO2, PO3, ..., POK using the programming voltage VPGM and the corresponding programming verification operations in programming verification operations PV1, PV2, PV3, ..., PVK using the programming verification voltage VPV can be executed sequentially. The level of the programming voltage VPGM in the current programming loop can be higher than the level of the programming voltage VPGM in the previous programming loop, and the programming verification voltage VPV can have a constant level (e.g., verification level VPVL). For example, the verification level VPVL can correspond to... Figure 11 The verification level is one of VL2 to VLN.

[0146] For example, in the first programming loop PLOOP1, the programming voltage VPGM can have an initial programming level VPLI. In the second programming loop PLOOP2, the programming voltage VPGM can have a level that increases from the initial programming level VPLI by the operating level ΔVP. In the third programming loop PLOOP3, the programming voltage VPGM can have a level that increases from the programming voltage VPGM in the second programming loop PLOOP2 by the operating level ΔVP. In the Kth programming loop PLOOPK, which is the last programming loop, the programming voltage VPGM can have the final programming level VPLF.

[0147] although Figure 12 It is shown that only the programming voltage VPGM increases with repeated execution of the programming cycle, but the example embodiment is not limited to this, and the programming verification voltage VPV may also increase. In some example embodiments, the programming voltage VPGM may decrease and / or the programming verification voltage VPV may decrease as the programming cycle is repeated. Furthermore, although Figure 12The example shows an increase in the programming voltage VPGM level by a fixed level (e.g., operating level ΔVP), but the example embodiment is not limited to this, and the amount of change in the programming voltage VPGM can be varied for each programming cycle.

[0148] Figure 13 It is shown Figure 9 A flowchart of another example of programming operations. Figure 14 and Figure 15 It is used to describe Figure 13 A diagram illustrating the operation. (And...) Figure 10 , Figure 11 and Figure 12 Duplicate descriptions will be omitted.

[0149] Reference Figure 9 , Figure 13 , Figure 14 and Figure 15 In operation S310, first offset information can be received (operation S314). Except that the optimal or improved verification level included in the first offset information in operation S314 differs from the optimal or improved verification level included in the first offset information in operation S312, the first offset information in operation S314 can be similar to... Figure 10 The first offset information in operation S312.

[0150] In operation S320, operation S322 can be combined with... Figure 10 The operation S322 is the same or substantially the same. Furthermore, in addition to the Nth verification level being changed by operation S322, at least one of the verification levels from the first verification level to the (N-1)th verification level can be further changed based on the first offset information (operation S324). Even if the Nth verification level is adjusted by operation S322 to increase the margin of the Nth state, the entire width of the threshold voltage distribution can be maintained; therefore, operation S324 can be performed separately to maintain the entire width of the threshold voltage distribution.

[0151] In some example embodiments, it can be as follows Figure 14 Adjust the verification level as shown. In Figure 14In the distribution of the threshold voltage VTH shown, the first to Nth states E', P1, P2, ..., P(N-3), P(N-2), and P(N-1)' shown at the bottom, and the first to Nth verification levels VL1', VL2, VL3, ..., VL(N-2), VL(N-1), and VLN', can represent an example after performing operations S322 and S324 and adjusting the verification levels. For example, when performing operation S322, the Nth verification level can be increased from VLN to VLN', and the Nth state can be changed from P(N-1) to P(N-1)'. Furthermore, when performing operation S324, the first verification level can be increased from VL1 to VL1', and the first state can be changed from E to E'.

[0152] In other example embodiments, it can be as follows Figure 15 Adjust the verification level as shown. In Figure 15 In the distribution of threshold voltage VTH shown, the first to Nth states E', P1', P2', ..., P(N-3)', P(N-2) and P(N-1)' shown at the bottom, and the first to Nth verification levels VL1', VL2', VL3', ..., VL(N-2'), VL(N-1) and VLN', can represent an example after performing operations S322 and S324 and adjusting the verification levels. For example, when performing operation S322, the Nth verification level can be increased from VLN to VLN', and the Nth state can be changed from P(N-1) to P(N-1)'. Furthermore, when operation S324 is executed, the first to the (N-2)th verification levels can be increased from VL1, VL2, VL3, ..., VL(N-2) to VL1', VL2', VL3', ..., VL(N-2)' respectively, and the first to the (N-2)th states can be changed from E, P1, P2, ..., P(N-3) to E', P1', P2', ..., P(N-3)' respectively.

[0153] When the verification level is adjusted to such Figure 14 and Figure 15 As shown, while the margin in the Nth state increases, the entire width of the threshold voltage VTH distribution can remain at VDT.

[0154] In some example embodiments, even when operation S324 is performed separately, it is not possible to change all programming verification levels and all programming states, and at least one programming verification level and at least one programming state can be maintained. For example, in Figure 14 In the example, the programming verification levels VL2 to VL(N-1) and programming states P1 to P(N-2) can remain unchanged and can be maintained. Figure 15 In the example, the programming verification level VL(N-1) and the programming state P(N-2) can remain unchanged and can be maintained.

[0155] In operation S330, the written data can be programmed one or more times based on the first to Nth verification levels, including the changed verification levels (operation S334). Operation S334 can be combined with... Figure 10 The operations in S332 are the same or substantially the same. For example, a programmed loop can be repeatedly executed to form... Figure 14 or Figure 15 The lower part shows the distribution of the threshold voltage VTH.

[0156] Figure 16 It is shown Figure 9 A flowchart of another example of programming operations. Figure 17 It is used to describe Figure 16 A diagram illustrating the operation. (And...) Figure 10 , Figure 11 and Figure 12 Identical descriptions will be omitted.

[0157] Reference Figure 9 , Figure 16 and Figure 17 In operation S310, second offset information can be received (operation S316). For example, the second offset information may indicate that the written data is hot data and corresponds to a second degradation mode, and may include an optimal or improved verification level for improving the reliability of hot data reading.

[0158] In operation S320, the first verification level can be changed from the first verification level to the Nth verification level based on the second offset information, thereby changing the first state from the first state to the Nth state (operation S326). As described above, for reading hot data, the first verification level can be controlled or adjusted to increase the margin of the first state as the lowest state.

[0159] In some example embodiments, the verification level can be as follows: Figure 17 Adjust as shown. In Figure 17 In the distribution of threshold voltage VTH shown, the first to Nth states E", P1, P2, ..., P(N-3), P(N-2) and P(N-1) shown in the lower part, as well as the first to Nth verification levels VL1", VL2, VL3, ..., VL(N-2), VL(N-1), VLN, can represent an example after performing operation S326 and adjusting the verification level.

[0160] For example, when operation S326 is executed, the first verification level, which is the lowest level, can be reduced from VL1 to VL1" and the first state, which is the lowest state, can be changed from E to E". Therefore, the interval between the first state and the second state can be increased from VD2 to VD2' (e.g., the interval between the first verification level and the second verification level can be increased), and with the increased margin of the first state, reliability against read interference degradation can be improved. The remaining states and verification levels, other than the first state and the first verification level, can be maintained.

[0161] In operation S330, the written data can be programmed one or more times based on the first verification level to the Nth verification level, including changes to the first verification level (operation S336). Operation S336 can be combined with... Figure 10 The operations in S332 are the same or substantially the same. For example, a programmed loop can be repeatedly executed to form... Figure 17 The lower part shows the distribution of the threshold voltage VTH.

[0162] Figure 18 It is shown Figure 9 A flowchart of another example of programming operations. Figure 19 and Figure 20 It is a description Figure 18 The diagram shows the operation. Figure 10 , Figure 11 , Figure 12 , Figure 16 and Figure 17 Repeated descriptions will be omitted.

[0163] Reference Figure 9 , Figure 18 , Figure 19 and Figure 20 In operation S310, second offset information can be received (operation S318). Except that the optimal or improved verification level included in the second offset information in operation S318 differs from the optimal or improved verification level included in the second offset information in operation S316, the second offset information in operation S318 can be similar to... Figure 16 The second offset information in operation S316.

[0164] In operation S320, operation S326 can be combined with... Figure 16The operation S326 is the same or substantially the same. In addition to the first verification level changed by operation S326, at least one of the verification levels from the first verification level to the Nth verification level can be further changed based on the second offset information (operation S328). Even when the first verification level is adjusted by operation S326 to increase the margin of the first state, the entire width of the threshold voltage distribution can be maintained; therefore, operation S328 can be performed separately to maintain the entire width of the threshold voltage distribution.

[0165] In some example embodiments, the verification level can be as follows: Figure 19 Adjust as shown. In Figure 19 In the distribution of the threshold voltage VTH shown, the first to Nth states E", P1, P2, ..., P(N-3), P(N-2) and P(N-1)" shown at the bottom, and the first to Nth verification levels VL1", VL2, VL3, ..., VL(N-2), VL(N-1) and VLN" can represent examples after performing operations S326 and S328 and adjusting the verification levels. For example, when performing operation S326, the first verification level can be reduced from VL1 to VL1", and the first state can be changed from E to E". Furthermore, when performing operation S328, the Nth verification level can be reduced from VLN to VLN", and the Nth state can be changed from P(N-1) to P(N-1)".

[0166] In other example embodiments, the verification level can be as follows: Figure 20 Adjust as shown. In Figure 20 In the distribution of the threshold voltage VTH shown, the first to Nth states E", P1, P2", ..., P(N-3)", P(N-2)" and P(N-1)" shown at the bottom, and the first to Nth verification levels VL1", VL2, VL3", ..., VL(N-2)", VL(N-1)" and VLN" can represent examples after performing operations S326 and S328 and adjusting the verification levels. For example, when performing operation S326, the first verification level can be reduced from VL1 to VL1" and the first state can be changed from E to E". Furthermore, when operation S328 is executed, the third to Nth verification levels can be increased from VL3, ..., VL(N-2), VL(N-1), VLN to VL3", ..., VL(N-2)", VL(N-1)" and VLN" respectively, and the third to Nth states can be changed from P2, ..., P(N-3), P(N-2), P(N-1) to P2", ..., P(N-3)", P(N-2)" and P(N-1)" respectively.

[0167] like Figure 19 and Figure 20When the verification level is adjusted as shown, the margin in the first state increases while the entire width VTH of the threshold voltage distribution can be maintained at VDT.

[0168] In some example embodiments, even when operation S328 is performed separately, it is not possible to change all programming verification levels and all programming states, and at least one programming verification level and at least one programming state can be maintained. For example, in Figure 19 In the example, the programming verification levels VL2 to VL(N-1) and programming states P1 to P(N-2) can remain unchanged and can be maintained. Figure 20 In the example, the programming verification level VL2 and the programming state P1 can remain unchanged and can be maintained.

[0169] In operation S330, the written data can be programmed one or more times based on the first to Nth verification levels, including the changed verification levels (operation S338). Operation S338 can be combined with... Figure 16 The operations in S336 are the same or substantially the same. For example, a programmed loop can be repeatedly executed to form... Figure 19 or Figure 20 The lower part shows the distribution of the threshold voltage VTH.

[0170] Although reference Figures 10 to 15 An example embodiment is described where only the margin increase of the Nth state is described (e.g., only the interval between the (N-1)th and Nth states increases from VD1 to VD1'), although references are made to... Figures 16 to 20 An example embodiment is described where only the margin of the first state is increased (e.g., only the interval between the first and second states increases from VD2 to VD2'), but the example embodiment is not limited thereto, and the margin of at least one other state may be changed otherwise. For example, as shown in the reference... Figure 8 The margin of at least one other state affecting the error bit of each page can be further modified.

[0171] Although reference Figures 8 to 20 The example embodiments are described based on specific I / O patterns of written data, specific degradation patterns, specific distributions of threshold voltages, and specific verification levels, but the example embodiments are not limited thereto. For example, when the I / O pattern of written data corresponds to any degradation pattern that causes a change in distribution, the example embodiments can be extended, applied, or adopted to examples where any verification level in any distribution of threshold voltages can be adjusted to improve reliability.

[0172] Figure 21 and Figure 22 This is a flowchart illustrating a method for writing data to a non-volatile storage device according to an example embodiment. Figure 1 Repeated descriptions will be omitted.

[0173] Reference Figure 21 In the method for writing data to a non-volatile storage device according to the example embodiment, operation S100 can be combined with... Figure 1 The operation S100 is the same or substantially the same.

[0174] Determine whether the written data corresponds to a distributed degradation mode by checking the I / O mode of the written data (operation S410).

[0175] When the written data corresponds to a distributed degradation mode (operation S410: Yes), offset information is received (operation S420). Operations S410 and S420 can correspond to... Figure 1 Operation S200. Operation S300, performed upon receiving offset information, can be related to... Figure 1 The operation S300 is the same or basically the same.

[0176] When the written data does not correspond to a distribution degradation mode (operation S410: No), offset information is not received (or not received) (operation S430). When no offset information is received, the written data is programmed such that all the multiple states included in the threshold voltage distribution of the memory cell storing the written data remain unchanged (operation S500). For example, a programming loop can be repeatedly executed to form... Figure 11 The upper part shows the distribution of the threshold voltage VTH.

[0177] Reference Figure 22 In the method for writing data to a non-volatile storage device according to the example embodiment, operations S100, S200, and S300 can be respectively connected with... Figure 1 The operations S100, S200 and S300 are the same or basically the same.

[0178] The lookup table used to select the optimal or improved verification level is updated in real time (operation S600). The lookup table can be used to generate offset information in operation S200 and can be used for execution. Figure 8 Operation S230 in the example. Figure 6 The lookup table 436 in the S600 can correspond to the lookup table in operation S600.

[0179] In some example embodiments, the lookup table can be updated in real time based on program / erase (P / E) cycle information. In other example embodiments, the lookup table can be updated in real time based on at least one of other pieces of information associated with the operation and / or characteristics of the non-volatile storage device.

[0180] As those skilled in the art will understand, the inventive concept can be embodied in systems, methods, computer program products, and / or in computer program products contained in one or more computer-readable media containing computer-readable program code. The computer-readable program code can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, the computer-readable medium can be a non-transitory computer-readable medium.

[0181] The elements disclosed above may include or be implemented with one or more of the following processing circuits: for example, hardware including logic circuits; hardware / software combinations, such as a processor executing software; or combinations thereof. More specifically, the processing circuits may include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0182] Figure 23 This is a block diagram illustrating a storage device and a storage system including the storage device according to an example embodiment.

[0183] Reference Figure 23 The storage system 1000 includes a host device 1100 and a storage device 1200.

[0184] The host device 1100 controls the overall operation of the storage system 1000. Although in Figure 23 Although not shown, host device 1100 may include a host processor and host memory. For example, the host processor may execute an operating system (OS). The host memory may store instructions and / or data executed and / or processed by the host processor. For example, the operating system executed by the host processor may include a file system for file management and device drivers for controlling peripheral devices including storage device 1200 at the operating system level.

[0185] Storage device 1200 is accessed by host device 1100. Storage device 1200 includes storage controller 1210, multiple non-volatile memories (NVMs) 1220a, 1220b and 1220c and buffer memory 1230.

[0186] Storage controller 1210 can control the operation of storage device 1200 and / or the operation of multiple non-volatile memories 1220a, 1220b, and 1220c based on commands and data received from host device 1100. The multiple non-volatile memories 1220a, 1220b, and 1220c can store multiple types of data. For example, the multiple non-volatile memories 1220a, 1220b, and 1220c can store metadata, various user data, etc. Buffer memory 1230 can store instructions and / or data executed and / or processed by storage controller 1210, and can temporarily store data that has been stored or will be stored in the multiple non-volatile memories 1220a, 1220b, and 1220c. Figure 2 Storage system 10 and / or Figure 7 The storage system 50 can be implemented in the form of a storage device 1200. For example, the storage controller 1210 can correspond to... Figure 2 The memory controller 20 and / or Figure 7 The memory controller 600, and the non-volatile memories 1220a, 1220b, and 1220c can correspond to Figure 2 The non-volatile storage device 40 and / or Figure 7 The storage device 500 in it.

[0187] The parameter manager (PM) 1212 included in the storage controller 1210 can correspond to Figure 6 The parameter manager 430 is included. In some example embodiments, the storage controller 1210 may also include a neural processing unit (NPU) 1214 for detecting I / O patterns of written data.

[0188] In some example embodiments, storage device 1200 may be a solid-state drive (SSD), universal flash memory (UFS), multimedia card (MMC), or embedded multimedia card (eMMC). In other example embodiments, storage device 1200 may be one of a secure digital card (SD), micro SD card, memory stick, chip card, universal serial bus (USB) card, smart card, compact flash memory (CF) card, etc.

[0189] This invention concept can be applied to a wide range of electronic devices and systems, including non-volatile storage devices and storage equipment. For example, it can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0190] The foregoing is an illustrative description of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims. Accordingly, it should be understood that the foregoing is a description of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A method for writing data to a non-volatile storage device, the method comprising: Receive the write command, the write address, and the write data to be programmed; Check the input / output pattern of the written data and determine whether the written data corresponds to a distributed degradation pattern; When it is determined that the written data corresponds to the distribution degradation mode, offset information representing the verification level is received, and when the offset information is received, the written data is programmed based on the offset information such that at least one of the multiple states included in the threshold voltage distribution of the storage cell storing the written data is changed. as well as When it is determined that the written data does not correspond to the distributed degradation mode, the offset information is not received, and when the offset information is not received, the written data is programmed so that all states in the plurality of states remain unchanged.

2. The method according to claim 1, wherein, The distributed degradation modes include a first degradation mode associated with data retention characteristics and a second degradation mode associated with read interference characteristics.

3. The method according to claim 2, wherein: When the written data is cold data that has been written less than a first number of times, it is determined that the written data corresponds to the first degradation mode, and When the written data is hot data that has been read more than the second number of times, it is determined that the written data corresponds to the second degradation mode.

4. The method according to claim 2, wherein: The plurality of states includes a first state to an Nth state, where N is a natural number greater than or equal to 2. The first state corresponds to the lowest voltage level, and the Nth state corresponds to the highest voltage level. When the written data corresponds to the first degradation mode, the written data is programmed to increase the interval between the (N-1)th state and the Nth state, and When the written data corresponds to the second degradation mode, the written data is programmed to increase the interval between the first state and the second state.

5. The method according to claim 1, wherein, Receiving the offset information includes: When the written data corresponds to the distribution degradation pattern and the verification level needs to be changed, an improved verification level is selected; and Generate and provide the offset information representing the improved verification level.

6. The method according to claim 5, wherein, The input / output mode of the written data is based on the write address detection.

7. The method according to claim 5, wherein, The input / output mode of the written data is detected based on the number of times the written data is accessed.

8. The method according to claim 5, wherein, The improved verification level is selected based on a preset lookup table.

9. The method according to claim 8, further comprising: The preset lookup table used for selecting the improved verification level is updated in real time.

10. The method according to claim 5, wherein, Receiving the offset information also includes: The offset information representing the improved verification level is stored.

11. The method according to claim 1, wherein: The plurality of states includes a first state to an Nth state, where N is a natural number greater than or equal to 2. The first state corresponds to the lowest voltage level, and the Nth state corresponds to the highest voltage level. Programming the written data upon receiving the offset information includes: Based on the offset information, the Nth verification level is changed from the first verification level to the Nth verification level, causing the Nth state to change, wherein the first verification level to the Nth verification level respectively correspond to the first state to the Nth state; and Based on the first verification level to the changed Nth verification level, the written data is processed one or more times in a programming loop.

12. The method according to claim 11, wherein, Changing the Nth verification level includes increasing the Nth verification level, thereby increasing the interval between the (N-1)th state and the Nth state.

13. The method according to claim 11, wherein, Programming the written data upon receiving the offset information further includes: Based on the offset information, the first verification level is further changed to at least one of the verification levels from the (N-1)th verification level.

14. The method according to claim 13, wherein, Even when at least one of the verification levels, from the first verification level to the Nth verification level, changes, the entire width of the threshold voltage distribution remains unchanged.

15. The method according to claim 1, wherein: The plurality of states includes a first state to an Nth state, where N is a natural number greater than or equal to 2. The first state corresponds to the lowest voltage level, and the Nth state corresponds to the highest voltage level. Programming the written data upon receiving the offset information includes: Based on the offset information, the first verification level is changed from the first verification level to the Nth verification level, causing the first state to change, wherein the first verification level to the Nth verification level respectively correspond to the first state to the Nth state; and Based on the changed first verification level to the Nth verification level, the written data is processed one or more times in a programming loop.

16. The method according to claim 15, wherein, Changing the first verification level includes lowering the first verification level, thereby increasing the interval between the first state and the second state.

17. The method according to claim 15, further comprising: Based on the offset information, the second verification level is further changed to at least one of the Nth verification levels.

18. A non-volatile storage device, comprising: A storage cell array, wherein the storage cell array comprises a plurality of storage cells; as well as Processing circuit, the processing circuit being configured to: Receive the write command, the write address, and the write data to be programmed; Check the input / output pattern of the written data and determine whether the written data corresponds to a distributed degradation pattern; When it is determined that the written data corresponds to the distribution degradation mode, offset information representing the verification level is received, and the written data is programmed based on the offset information upon receiving the offset information, such that at least one of the multiple states included in the threshold voltage distribution of the storage cell storing the written data is changed. as well as When it is determined that the written data does not correspond to the distributed degradation mode, the offset information is not received, and when the offset information is not received, the written data is programmed so that all states in the plurality of states remain unchanged.

19. A method of operating a memory system including a memory controller and a non-volatile memory device, the method comprising: The memory controller sends a write command, a write address, and write data to be programmed to the non-volatile memory device; The memory controller detects the input / output pattern of the written data; When it is determined that the written data is either cold data or hot data, the memory controller selects an improved verification level. The cold data is data that has been written less than a first number of times, and the hot data is data that has been read more than a second number of times. The memory controller generates offset information including the improved verification level; The memory controller sends the offset information to the non-volatile memory device; The non-volatile storage device changes at least one of the verification levels from a first verification level to an Nth verification level based on the offset information. The first verification level to the Nth verification level respectively correspond to a first state to an Nth state in the threshold voltage distribution of the storage cell storing the written data, where N is a natural number greater than or equal to 2. The non-volatile storage device performs one or more programming cycles on the written data based on the first verification level to the Nth verification level, where at least one of the verification levels is changed, such that at least one state among the first state to the Nth state changes. Wherein, the first state corresponds to the lowest voltage level, and the Nth state corresponds to the highest voltage level. Wherein, when the written data is the written cold data, the at least one state is changed such that the interval between the (N-1)th state and the Nth state increases, and Wherein, when the written data is the read hot data, the at least one state is changed such that the interval between the first state and the second state is increased.

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