Integrated circuit and method of manufacturing the same

Abstract

Embodiments of the invention provide an integrated circuit including a plurality of first-tier deep lines and a plurality of first-tier shallow lines. The integrated circuit also includes a plurality of second-tier deep lines and a plurality of second-tier shallow lines. Each of the first-tier deep lines and the first-tier shallow lines is located in a first conductive layer. Each of the second-tier deep lines and the second-tier shallow lines is located in a second conductive layer above the first conductive layer. Embodiments of the invention also provide a method of manufacturing an integrated circuit.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to integrated circuits and methods of manufacturing the same. Background Technology

[0002] The latest trend in integrated circuit (IC) miniaturization has resulted in smaller, lower-power devices that deliver more functionality at higher speeds. Miniaturization processes also lead to more stringent design and manufacturing specifications and challenges in reliability. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for ICs, while ensuring compliance with standard cell layout design and manufacturing specifications. Summary of the Invention

[0003] One aspect of the present invention provides an integrated circuit comprising: a plurality of first deep lines and a plurality of first shallow lines, wherein each of the first deep lines and the first shallow lines is located in a first conductive layer above a transistor on a substrate; and a plurality of second deep lines and a plurality of second shallow lines, wherein each of the second deep lines and the second shallow lines is located in a second conductive layer above the first conductive layer.

[0004] Another aspect of the present invention provides an integrated circuit comprising: a plurality of first-layer deep lines and a plurality of first-layer shallow lines, wherein each of the first-layer deep lines and the first-layer shallow lines is located in a first conductive layer; a conductive path having a low-resistivity portion and a low-permeability portion, wherein the low-resistivity portion is connected to an output of a first active device and the low-permeability portion is connected to an input of a second active device; wherein the low-resistivity portion includes at least one first-layer deep line but does not include the first-layer shallow lines; and wherein the low-permeability portion includes at least one first-layer shallow line but does not include the first-layer deep line.

[0005] Another aspect of the present invention provides a method for manufacturing an integrated circuit, comprising: manufacturing a first deep line and a first shallow line extending in a first direction in a first insulating layer; manufacturing a through-hole connector, a second deep line, and a second shallow line in a second insulating layer, wherein the second deep line and the second shallow line extend in a second direction perpendicular to the first direction; and wherein one of the through-hole connectors connects one of the second deep lines to one of the first shallow lines, or connects one of the second shallow lines to one of the first deep lines. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a layout diagram of an integrated circuit according to some embodiments.

[0008] Figures 2A to 2D According to some embodiments Figure 1 A cross-sectional view of an integrated circuit.

[0009] Figure 3A It is a cross-sectional view of deep and shallow lines with marked depth dimensions according to some embodiments.

[0010] Figure 3B These are resistivity and capacitance diagrams depicted according to some embodiments of the variation with respect to the depth of the conductor.

[0011] Figures 4A to 4C According to some embodiments Figure 1 A cross-sectional view of an integrated circuit.

[0012] Figure 5 This is a layout diagram of an integrated circuit having a signal conduction path formed by a combination of dark and light lines, according to some embodiments.

[0013] Figures 6A to 6F It is a layout diagram of an integrated circuit with a signal conduction path according to some embodiments, the signal conduction path being formed by different configurations of low resistivity portions, low permeability portions and abrupt change points.

[0014] Figure 7 This is a layout diagram of an integrated circuit having multiple signal conduction paths formed by a combination of dark and shallow lines, according to some embodiments.

[0015] Figures 8A to 8B This is a schematic diagram of an integrated circuit having multiple signal conduction paths formed by a combination of dark and shallow lines, according to some embodiments.

[0016] Figure 9 This is a layout diagram of an integrated circuit having multiple signal conduction paths formed by deep lines, according to some embodiments.

[0017] Figure 10 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments.

[0018] Figure 11 This is a flowchart of a method for manufacturing deep and shallow lines according to some embodiments.

[0019] Figures 12A to 12E This is a cross-sectional view of an example device structure based on some embodiments.

[0020] Figure 13 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0021] Figure 14 This is a block diagram of an integrated circuit (IC) manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0024] In some embodiments, the integrated circuit includes both deep and shallow lines in both the first and second conductive layers. The selection of deep and shallow lines for constructing various signal conduction paths allows for improved integrated circuit performance. In some embodiments, the resistance-capacitance (RC) constant of the signal conduction path from the first active device to the second active device is reduced. In some embodiments, the time delay of signal propagation from the first active device to the second active device in the signal conduction path is reduced. In some embodiments, the signal conduction path includes abrupt changes between a low resistivity portion and a low permeability portion of the signal conduction path. In some embodiments, the signal conduction path transitions from a deep line to a shallow line at the abrupt change point. In some embodiments, the signal propagation time delay in the signal conduction path from the first active device to the second active device is reduced when abrupt changes from a plurality of abrupt change point candidates is selected on the signal conduction path.

[0025] Figure 1 This is a layout diagram of an integrated circuit 100 according to some embodiments. Figures 2A to 2D According to some embodiments Figure 1 A cross-sectional view of the integrated circuit 100. The integrated circuit 100 includes a first deep line and a first shallow line extending in the X direction. The integrated circuit 100 also includes a second deep line and a second shallow line extending in the Y direction. The first deep lines (111D, 112D, 113D, 115D, 117D, 118D, and 119D) and the first shallow lines (111S, 112S, 117S, and 118S) are located in a first conductive layer. The second deep lines (123D and 128D) and the second shallow lines (122S, 123S, 127S, and 128S) are located in a second conductive layer.

[0026] Integrated circuit 100 includes a first active device D1 and a second active device D2. The output of the first active device D1 is electrically connected to the input of the second active device D2 through a conduction path 101. The conduction path 101 includes segments of a first layer deep line 112D, a second layer deep line 123D, a first layer deep line 115D, a second layer deep line 128D, and a first layer deep line 118D. Through-hole connector 1V1 electrically connects the first layer deep line 112D to the second layer deep line 123D. Through-hole connector 1V2 electrically connects the second layer deep line 123D to the first layer deep line 115D. Through-hole connector 1V3 electrically connects the first layer deep line 115D to the second layer deep line 128D. Through-hole connector 1V4 electrically connects the second layer deep line 128D to the first layer deep line 118D. The output of the first active device D1 is electrically connected to the first layer deep line 112D, and the input of the second active device D2 is electrically connected to the first layer deep line 118D.

[0027] exist Figure 1In the diagram, conduction path 101 includes a first deep line and a second deep line, but does not include a first shallow line and a second shallow line. That is, conduction path 101 does not contain a first shallow line and a second shallow line. The resistance per unit length of the first deep line is less than the resistance per unit length of the first shallow line, while the capacitance per unit length of the first deep line is greater than the capacitance per unit length of the first shallow line. Similarly, the resistance per unit length of the second deep line is less than the resistance per unit length of the second shallow line, while the capacitance per unit length of the second deep line is greater than the capacitance per unit length of the second shallow line. The geometric difference between the first deep line and the first shallow line lies in… Figures 2A to 2D The cross-sectional view is identifiable. The geometric difference between the second deep line and the second shallow line is... Figures 2A to 2D It is also identifiable in the cross-sectional view.

[0028] exist Figure 2A , Figure 2B and Figure 2C The corresponding description is as follows: Figure 1 A cross-sectional view of integrated circuit 100 in the cutting planes specified by lines AA', BB', and CC'. Figures 2A to 2C In the first layer, deep lines 111D and 112D and shallow lines 111S and 112S are deposited on the insulating layer 205. Each of the deep lines 111D and 112D extends along the Z direction into the interlayer dielectric 210 at a depth d1. Each of the shallow lines 111S and 112S extends along the Z direction into the interlayer dielectric 210 at a depth s1. The depth d1 of the deep lines is greater than the depth s1 of the shallow lines.

[0029] exist Figures 2A to 2C In this process, interlayer dielectric 220 is deposited on top of interlayer dielectric 210 and on top of the first deep layer and the first shallow layer. Figure 2A In the middle, the second shallow line 122S extends along the Y direction and is embedded in the interlayer dielectric 220 at a depth s2. Figure 2B In this configuration, the second deep line 123D extends along the Y direction and is embedded in the interlayer dielectric 220 at a depth d2. Furthermore, the second deep line 123D is electrically connected to the first deep line 112D via a through-hole connector 1V1. Figure 2C In the middle, the cross-section of the second deep line and the second shallow line did not appear along the line formed by... Figure 1 The cross-sectional view of the cutting plane specified by line CC'.

[0030] exist Figure 2D The description is as follows: Figure 1 The line PP' in the diagram shows a cross-sectional view of the integrated circuit 100 in the cutting plane specified by the line PP'. Figure 2DIn the middle layer, a second deep layer 123D and second shallow layers 122S and 123S are deposited on the interlayer dielectric 210. The second deep layer 123D extends along the Z-direction into the interlayer dielectric 220 at a depth d2. Each of the second shallow layers 122S and 123S extends along the Z-direction into the interlayer dielectric 220 at a depth s2. The depth d2 of the second deep layer is greater than the depth s2 of the second shallow layer. Figure 2D In the first layer, the deep line 112D extends along the X direction and is embedded in the interlayer dielectric 210. The second layer, the deep line 123D, is electrically connected to the first layer, the deep line 112D, through a through-hole connector 1V1.

[0031] exist Figures 2A to 2D In this design, the depths of the first deep line and the first shallow line are adjusted according to design specifications, and the depths of the second deep line and the second shallow line are also adjusted according to design specifications. The difference between the depth d1 of the first deep line and the depth s1 of the first shallow line is related to the difference in resistance and capacitance between the two lines. The difference between the depth d2 of the second deep line and the depth s2 of the second shallow line is also related to the difference in resistance and capacitance between the two lines. The depth difference between d1 and d2, and the depth difference between s1 and s2, are also related to other design considerations. In some embodiments, depth d1 is different from depth d2. In some embodiments, depth d1 is the same as depth d2. In some embodiments, depth s1 is different from depth s2. In some embodiments, depth s1 is the same as depth s2.

[0032] Figure 3A It is a cross-sectional view of deep and shallow lines with marked depth dimensions according to some embodiments. Figure 3B This is a schematic diagram illustrating the variation of resistivity and permittivity with respect to wire depth according to some embodiments. Figure 3A In one example, the deep line, marked with the letter "A," is modified from the uniform line by extending the deep line further into the interlayer dielectric 210 than the uniform line, and the shallow line, marked with the letter "B," is modified from the uniform line by extending the deep line into the interlayer dielectric 210 less than the uniform line. The uniform line appears in a design where all conductors in the interlayer dielectric 210 have the same depth "h." Figures 3A to 3B In this process, the depth "d" of the deep line and the depth "s" of the shallow line are compared with the depth "h" of the uniform line.

[0033] exist Figure 3BIn the diagram, curve 310D is a graph showing the relative capacitance change ΔCt based on the relative height change LA=(dh) / h of the depth curve, and curve 320D is a graph showing the relative resistance change ΔRs based on the relative height change LA=(dh) / h of the depth curve. As the depth of the depth curve increases, the capacitance value in curve 310D increases, while the resistance value in curve 320D decreases. For example, when the depth of the depth curve increases by 30%, the capacitance value in curve 310D increases by 14%, and the resistance value in curve 320D decreases by 30%. The changes in capacitance and resistance values ​​as the depth of the depth curve increases lead to changes in the RC constant of the depth curve. Figure 3B In one example, when the depth of the deep line increases by 30%, the RC constant per unit length of the deep line decreases by 20%.

[0034] exist Figure 3B In the diagram, curve 310S is a graph showing the relative capacitance change ΔCt based on the relative height change of the shallow line LB=(sh) / h, and curve 320S is a graph showing the relative resistance change ΔRs based on the relative height change of the shallow line LB=(sh) / h. As the depth of the shallow line decreases, the capacitance value in curve 310S decreases, and the resistance value in curve 320S increases. For example, when the depth of the shallow line decreases by 30%, the capacitance value in curve 310S decreases by 16%, and the resistance value in curve 320S increases by 65%. The changes in capacitance and resistance as the depth of the shallow line decreases cause a change in the RC constant of the shallow line. Figure 3B In one example, when the depth of the shallow line is reduced by 30%, the RC constant per unit length of the shallow line increases by 39%.

[0035] exist Figure 3B In some instances, the RC constant of the deeper wire is smaller than that of the shallower wire. In some embodiments, the deeper wire is chosen to form the signal transmission path, which needs to reduce the time delay caused by the RC constant of the wire. Figure 1 In this embodiment, the conduction path 101 between the first active device D1 and the second active device D2 is formed by a first deep line 112D, a second deep line 123D, a first deep line 115D, a second deep line 128D, and a first deep line 118D. The conduction path 101 is expected to have a smaller RC constant compared to an alternative path formed by a combination of first and / or second shallow lines for connecting the first active device D1 and the second active device D2. On the other hand, the alternative conduction path formed by a combination of first and / or second shallow lines is expected to have a smaller stray capacitance.

[0036] Because the characteristics of conduction paths formed by deep lines differ from those formed by shallow lines, the selection of deep and shallow conduction paths in an integrated circuit allows for some performance improvements. In some embodiments, the conduction paths of interest in the integration are sorted based on the delay time of each conduction path, and those conduction paths with delay times longer than the critical delay time are selected to form a list of selected paths for speed improvement. In some embodiments, the critical delay time is the delay time corresponding to a relaxation time of zero. Here, relaxation time refers to the time that may delay a task without causing a delay in another task or affecting the overall task completion of the circuit system. In some embodiments, based on deep lines (e.g., Figure 1 The automatic placement and routing (APR) procedure is configured to find a first deep layer and a second deep layer to form the selected path for speed improvement. In some embodiments, the APR procedure is also configured to find a first shallow layer and a second shallow layer to form one or more conduction paths that serve as a means of reducing stray capacitance.

[0037] exist Figures 2A to 2D In this configuration, the first deep lines 111D to 112D and the first shallow lines 111S to 112S are located in a first conductive layer above the insulating layer 205, and the second deep lines 123D and the second shallow lines 122S and 123S are located in a second conductive layer above the first conductive layer. In some embodiments, the insulating layer 205 is a top insulating layer fabricated in a front-end processing (FEOL) process, and the first conductive layer (having the first deep lines and the first shallow lines) is a first metal layer M0 immediately above a transistor fabricated in the integrated circuit, while the second conductive layer (having the second deep lines and the second shallow lines) is a second metal layer M1 immediately above the first metal layer M0.

[0038] In some optional embodiments, the insulating layer 205 is an interlayer dielectric layer covering the first metal layer M0, and the first conductive layer (having a first deep line and a first shallow line) is a second metal layer M1 immediately above the first metal layer M0, while the second conductive layer (having a second deep line and a second shallow line) is a third metal layer M2 immediately above the second metal layer M1. In other optional embodiments, Figures 2A to 2D The first and second conductive layers are correspondingly the fourth metal layer M3 and the third metal layer M2. In other embodiments, Figures 2A to 2D The first conductive layer is a metal layer above the fourth metal layer M3, and Figures 2A to 2D The second conductive layer is a metal layer above the third metal layer M2. Furthermore, the second conductive layer is located above the first conductive layer. Figures 2A to 2DUnlike some embodiments, in some alternative embodiments, the second conductive layer is below the first conductive layer.

[0039] exist Figures 2A to 2D The image depicts two conductive layers, one with dark lines and the other with light lines. However, in some embodiments, Figure 1 The integrated circuit 100 also includes additional conductive layers. Some additional conductive layers have both deep and shallow lines, while some additional conductive layers of the integrated circuit 100 consist only of uniform lines. For example, in Figures 4A to 4C In the illustrated embodiment, there are three conductive layers, each with both deep and shallow lines.

[0040] Figures 4A to 4C According to some embodiments Figure 1 A cross-sectional view of an integrated circuit. Figures 4A to 4C The cross-sectional view and Figures 2A to 2C The cross-sectional views in the diagrams are located in the same cutting plane. Figures 4A to 4C and Figures 2A to 2C The cross-sectional views in the images have the same first conductive layer and the same second conductive layer. Figures 4A to 4C and Figures 2A to 2C In the first conductive layer, there are first deep lines 111D to 112D and first shallow lines 111S to 112S embedded in the interlayer dielectric 210, and the second conductive layer has second deep lines 123D and second shallow lines 122S embedded in the interlayer dielectric 220. Figures 4A to 4C The third conductive layer is also depicted. The third conductive layer has a third deep line 431D to 432D and a third shallow line 431S to 432S embedded in the interlayer dielectric 430.

[0041] In some optional embodiments, the stacking positions of the first conductive layer, the second conductive layer, and the third conductive layer are... Figures 4A to 4C The stacking positions shown differ. For example, in some alternative embodiments, the third conductive layer is located between the first and second conductive layers. In some alternative embodiments, the third conductive layer is located below both the first and second conductive layers. In contrast, Figures 4A to 4C The third conductive layer is located above both the first and second conductive layers. Furthermore, although... Figures 4A to 4C The third conductive layer is formed with both deep and shallow lines, but in some alternative embodiments, the third conductive layer is formed with only uniform lines. In some alternative embodiments, the third conductive layer with only uniform lines is located below both the first and second conductive layers. In some alternative embodiments, the third conductive layer with only uniform lines is located between the first and second conductive layers.

[0042] In some embodiments, except Figures 4A to 4C In addition to the three conductive layers shown, Figure 1The integrated circuit 100 further includes additional conductive layers, which are either formed with uniform lines or with both deep and shallow lines. In some alternative embodiments, at least two conductive layers are deposited between the first and second conductive layers. Each of the at least two conductive layers is formed with a uniform line or simultaneously with both deep and shallow lines. In some alternative embodiments, at least two conductive layers are deposited on top of the first and second conductive layers. In some alternative embodiments, at least two conductive layers are deposited beneath both the first and second conductive layers.

[0043] In some embodiments, the signal conduction path is formed with a combination of deep lines in the first conductive layer, the second conductive layer, and / or other conductive layers to reduce the RC constant of the signal conduction path. In some embodiments, the signal conduction path is formed with a combination of shallow lines in the first conductive layer, the second conductive layer, and / or other conductive layers to reduce stray capacitance at various segments of the signal conduction path. In some embodiments, the signal conduction path connecting the output of the first active device to the input of the second active device is formed with a combination of deep and shallow lines in each conductive layer to reduce the total time delay of signal propagation from the first active device to the second active device along the signal conduction path.

[0044] Figure 5 This is a layout diagram of an integrated circuit 500 having a signal conduction path formed by a combination of deep and shallow lines according to some embodiments. The integrated circuit 500 includes a first layer of deep lines and a first layer of shallow lines extending in the X direction. The integrated circuit 500 also includes a second layer of deep lines and a second layer of shallow lines extending in the Y direction. The first layer of deep lines (512D, 513D, 514D, 518D, and 519D) and the first layer of shallow lines (512S, 517S, and 518S) are located in a first conductive layer. The second layer of deep lines (523D, 525D, 527D, and 528D) and the second layer of shallow lines (522S, 523S, 526S, and 527S) are located in a second conductive layer.

[0045] Integrated circuit 500 includes a first active device D1 and a second active device D2. The output of the first active device D1 is electrically connected to the input of the second active device D2 through a conductive path including a low-resistivity portion 501 and a low-permeability portion 502. The low-resistivity portion 501 of the conductive path includes first layer deep lines 512D and 514D and second layer deep lines 523D and 525D. The low-permeability portion 502 of the conductive path includes first layer shallow lines 517S and 518S and second layer shallow line 527S. In the low-resistivity portion 501, the first layer deep line 512D is electrically connected to the second layer deep line 523D through a through-hole connector 5V1, the second layer deep line 523D is electrically connected to the first layer deep line 514D through a through-hole connector 5V2, and the first layer deep line 514D is electrically connected to the second layer deep line 525D through a through-hole connector 5V3. In the low permittivity section 502, the first layer shallow line 517S is electrically connected to the second layer shallow line 527S via a through-hole connector 5V5, and the second layer shallow line 527S is electrically connected to the first layer shallow line 518S via a through-hole connector 5V6.

[0046] When the second layer deep line 525D is electrically connected to the first layer shallow line 517S through the through-hole connector 5V4, the low resistivity portion 501 of the conduction path is electrically connected to the low permeability portion 502 of the conduction path. The mutation point 5MP is located at the through-hole connector 5V4 between the low resistivity portion 501 and the low permeability portion 502 of the conduction path. The low resistivity portion 501 is electrically connected between the output of the first active device D1 and the mutation point 5MP, and the low permeability portion 502 is electrically connected between the mutation point 5MP and the input of the second active device D2.

[0047] Compared to some alternative designs where the signal path from the first active device D1 to the second active device D2 is formed by a uniform line (whose depth is less than the depth of the deep line but greater than the depth of the shallow line), the low resistivity portion 501 with the deep line and the low permeability portion 502 with the shallow line are selected to increase the signal speed transmitted from the first active device D1 to the second active device D2.

[0048] In some embodiments, such as in Figures 6A to 6F In the illustrated embodiments, different configurations of the low resistivity portion, the low permeability portion, and the abrupt change point are compared to find an optimal configuration. In some embodiments, the optimal configuration is selected to reduce the total time delay of signal propagation along the signal conduction path from the first active device to the second active device. In addition to the total time delay, in some embodiments, the selection of the optimal configuration also includes balancing other factors, such as electromigration attributable to IR voltage drop and cross-connections attributable to stray capacitance.

[0049] Figures 6A to 6FThis is a layout diagram of an integrated circuit with a signal conduction path according to some embodiments, the signal conduction path being formed by different configurations of low resistivity portions, low permeability portions, and abrupt change points. Figures 6A to 6F In each layout diagram, different locations along the signal transmission path are selected as abrupt change points. Based on Figures 6A to 6F The layout diagram compares different configurations of the signal propagation path to reduce the signal propagation time from the first active device D1 to the second active device D2.

[0050] In such Figure 6A In the first configuration shown, the conduction path from the first active device D1 to the second active device D2 includes a low resistivity portion 601A and a low permeability portion 602A. The low resistivity portion 601A includes a first layer deep line 512D. The low permeability portion 602A includes a second layer shallow line 522S, a first layer shallow line 614S, a second layer shallow line 625S, a first layer shallow line 517S, a second layer shallow line 527S, and a first layer shallow line 518S (which are correspondingly connected together via via connectors 6V2, 6V3, 6V4, 6V5, and 6V6). A transition point 6MP is located at the via connector 6V1 that electrically connects the first layer deep line 512D to the second layer shallow line 522S. The low resistivity portion 601A is located between the output of the first active device D1 and the transition point 6MP. The low permeability portion 602A is located between the transition point 6MP and the input of the second active device D2.

[0051] In such Figure 6B In the second configuration shown, the conduction path from the first active device D1 to the second active device D2 includes a low resistivity portion 601B and a low permeability portion 602B. The low resistivity portion 601B includes a first layer deep line 512D and a second layer deep line 523D connected together via a via connector 6V1. The low permeability portion 602B includes a first layer shallow line 614S, a second layer shallow line 625S, a first layer shallow line 517S, a second layer shallow line 527S, and a first layer shallow line 518S (which are correspondingly connected together via via connectors 6V3, 6V4, 6V5, and 6V6). A transition point 6MP is located at the via connector 6V2 that electrically connects the second layer deep line 523D and the first layer shallow line 614S. The low resistivity portion 601B is located between the output of the first active device D1 and the transition point 6MP. The low permeability portion 602B is located between the transition point 6MP and the input of the second active device D2.

[0052] exist Figure 6CIn the third configuration shown, the conduction path from the first active device D1 to the second active device D2 includes a low resistivity portion 601C and a low permeability portion 602C. The low resistivity portion 601C includes a first-layer deep line 512D, a second-layer deep line 523D, and a first-layer deep line 514D (which are connected together correspondingly via via connectors 6V1 and 6V2). The low permeability portion 602C includes a second-layer shallow line 625S, a first-layer shallow line 517S, a second-layer shallow line 527S, and a first-layer shallow line 518S (which are connected together correspondingly via via connectors 6V4, 6V5, and 6V6). The abrupt change point 6MP is located at the via connector 6V3 that electrically connects the first-layer deep line 514D to the second-layer shallow line 625S. The low resistivity portion 601C is located between the output of the first active device D1 and the abrupt change point 6MP. The low-permeability portion 602C is located between the abrupt change point 6MP and the input of the second active device D2.

[0053] exist Figure 6D In the fourth configuration shown, the conduction path from the first active device D1 to the second active device D2 includes a low resistivity portion 601D and a low permeability portion 602D. The low resistivity portion 601D includes a first deep line 512D, a second deep line 523D, a first deep line 514D, and a second deep line 525D (which are correspondingly connected together via via connectors 6V1, 6V2, and 6V3). The low permeability portion 602D includes a first shallow line 517S, a second shallow line 527S, and a first shallow line 518S (which are correspondingly connected together via via connectors 6V5 and 6V6). The abrupt change point 6MP is located at the via connector 6V4 that electrically connects the second deep line 525D to the first shallow line 517S. The low resistivity portion 601D is located between the output of the first active device D1 and the abrupt change point 6MP. The low-permeability portion 602D is located between the abrupt change point 6MP and the input of the second active device D2.

[0054] exist Figure 6EIn the fifth configuration shown, the conduction path from the first active device D1 to the second active device D2 includes a low resistivity portion 601E and a low permeability portion 602E. The low resistivity portion 601E includes a first deep line 512D, a second deep line 523D, a first deep line 514D, a second deep line 525D, and a first deep line 517D (which are correspondingly connected together via via connectors 6V1, 6V2, 6V3, and 6V4). The low permeability portion 602E includes a second shallow line 527S electrically connected to a first shallow line 518S via a via connector 6V6. The abrupt change point 6MP is located at the via connector 6V5 that electrically connects the first deep line 517D and the second shallow line 527S. The low resistivity portion 601E is located between the output of the first active device D1 and the abrupt change point 6MP. The low-permeability portion 602E is located between the abrupt change point 6MP and the input of the second active device D2.

[0055] exist Figure 6F In the sixth configuration shown, the conduction path from the first active device D1 to the second active device D2 includes a low resistivity portion 601F and a low permeability portion 602F. The low resistivity portion 601F includes a first deep line 512D, a second deep line 523D, a first deep line 514D, a second deep line 525D, a first deep line 517D, and a second deep line 527D (which are correspondingly connected together via via connectors 6V1, 6V2, 6V3, 6V4, and 6V5). The low permeability portion 602F includes a first shallow line 518S. A transition point 6MP is located at the via connector 6V6 that electrically connects the second deep line 527D to the first shallow line 518S. The low resistivity portion 601F is located between the output of the first active device D1 and the transition point 6MP. The low permeability portion 602F is located between the transition point 6MP and the input of the second active device D2.

[0056] In some embodiments, the Automatic Placement and Routing (APR) procedure is compared. Figures 6A to 6F The total time delay of signal propagation from the first active device D1 to the second active device D2 in each configuration, and the APR program selects... Figures 6A to 6F The configuration with the minimum total signal propagation time delay. The mutation point 6MP selected by the APR program is located at one of the through-hole connectors (such as 6V1, 6V2, 6V3, 6V4, 6V5, or 6V6).

[0057] In some embodiments, multiple signal propagation paths share a common portion of the signal propagation path. Selecting the abrupt change point for each signal propagation path involves comparing the total time delay of signal propagation in each signal propagation path across different configurations.

[0058] Figure 7This is a layout diagram of an integrated circuit 700 having multiple signal conduction paths formed by a combination of dark and light lines, according to some embodiments. Figure 7 In the first active device D1, the output of the first active device D1 is electrically connected to the input of the second active device D2 through a first conduction path including a low resistivity portion 701 and a low permeability portion 702, and the output of the first active device D1 is electrically connected to the input of the third active device D3 through a second conduction path including a low resistivity portion 703 and a low permeability portion 704.

[0059] exist Figure 7 middle, Figure 7 The low resistivity portion 701 of the first conduction path in the middle and Figure 5 The low resistivity portion of 501 is the same. Figure 7 The low permittivity portion 702 of the first conduction path and Figure 5 The low permittivity portion of 502 is the same. Figure 7 The first abrupt change point 7MP1 in the first conduction path is located at the through-hole connector 5V4. The low resistivity section 701 is electrically connected between the output of the first active device D1 and the first abrupt change point 7MP1, and the low permeability section 702 is electrically connected between the first abrupt change point 7MP1 and the input of the second active device D2.

[0060] exist Figure 7 In the second conductive path, the low resistivity portion 703 includes a first deep line 512D, a second deep line 523D, a first deep line 514D, and a second deep line 525D (which are correspondingly connected together via through-hole connectors 5V1, 5V2, and 5V3). The low permeability portion 704 of the second conductive path includes a first shallow line 715S, a second shallow line 727S, and a first shallow line 718S (which are correspondingly connected together via through-hole connectors 7V5 and 7V6). Figure 7 The second abrupt change point 7MP2 of the second conduction path is located at the through-hole connector 7V4 that electrically connects the second deep line 525D and the first shallow line 715S. The low resistivity section 703 is electrically connected between the output of the first active device D1 and the second abrupt change point 7MP2, and the low permeability section 704 is electrically connected between the second abrupt change point 7MP2 and the input of the third active device D3.

[0061] exist Figure 7In this configuration, when the first conductive path is from the first active device D1 to the second active device D2 and the second conductive path is from the first active device D1 to the third active device D3, the first and second conductive paths share a common conductive path from the output of the first active device D1 to the second layer deep line 525D. Here, the second layer deep line 525D is a fan-out node that branches the common conductive path into the first and second conductive paths. The low-permittivity portion 702 of the first conductive path forms at least a portion of the first branch conductive path between the fan-out node and the input of the second active device D2. The low-permittivity portion 704 of the second conductive path forms at least a portion of the second branch conductive path between the fan-out node and the input of the third active device D3. Each of the first and second branch conductive paths is a conductive path that does not include the first and second layer deep lines. In some embodiments, each branch conductive path does not include deep lines not only in the first and second conductive layers, but also in other conductive layers. In some embodiments, although each branch conduction path does not include deep lines in the first and second conduction layers, each branch conduction path still includes deep lines in one or more other conduction layers.

[0062] exist Figure 1 , Figure 5 and Figures 6A to 6F In each conduction path from the first active device D1 to the second active device D2, the abrupt change point is located between the low resistivity portion and the low permittivity portion of the conduction path. In some embodiments, the abrupt change point is located at a via connector. In some embodiments, such as in Figures 8A to 8B In each conduction path, the mutation point is a fan-out node that connects at least two branch conduction paths, and each of the at least two branch conduction paths includes a portion of a low-capacitance conduction path.

[0063] Figures 8A to 8B This is a schematic diagram of an integrated circuit having multiple signal conduction paths formed by a combination of dark and light lines, according to some embodiments. Figure 8AIn this embodiment, a first conductive path from the first active device D1 to the second active device D2 includes a low resistivity portion and a low permeability portion. The low resistivity portion of the first conductive path includes a first deep line 862D and a second deep line 872D electrically connected together via a via connector 8V67. The low permeability portion of the first conductive path includes a first shallow line 868S and a second shallow line 878S electrically connected together via a via connector 8V76. The first deep line 862D and the first shallow line 868S are located in a first conductive layer. The second deep line 872D and the second shallow line 878S are located in a second conductive layer. In some embodiments, the integrated circuit includes at least eight metal layers (M0 to M7) above a top insulating layer fabricated in a front-end process (FEOL). The first conductive layer is a seventh metal layer M6 (above the other six metal layers M0 to M5), and the second conductive layer is an eighth metal layer M7 (above the other seven metal layers M0 to M6).

[0064] exist Figure 8A In this configuration, the low-resistivity portion of the first conductive path is electrically connected to the low-permeability portion of the first conductive path via a second layer of wire 874. In some embodiments, the second layer of wire 874 is a second deep wire. In some embodiments, the second layer of wire 874 is a second shallow wire. In some embodiments, the second layer of wire 874 is a second uniform wire (its depth is greater than the depth of the second shallow wire but less than the depth of the second deep wire). Figure 8A In this configuration, the second layer conductor 874 is a fan-out node. The first conductive path includes a first abrupt change point 8MP1 at the fan-out node located between the resistivity portion and the low-permeability portion. A second conductive path from the first active device D1 to the third active device D3 branches off from the first conductive path at the fan-out node (i.e., from the first active device D1 to the second active device D2). The second conductive path includes a low-resistivity portion and a low-permeability portion. The low-resistivity portion is located between the first active device D1 and the second abrupt change point 8MP2 at the fan-out node. The low-permeability portion is located between the second abrupt change point 8MP2 and the input of the third active device D3. The low-resistivity portion of the second conductive path includes a first layer deep line 862D and a second layer deep line 872D. The low-permeability portion of the second conductive path includes a first layer shallow line 866S and a second layer shallow line 876S electrically connected together via corresponding through-hole connectors.

[0065] In some embodiments, in addition to the first deep line 862D in the seventh metal layer M6 and the second deep line 872D in the eighth metal layer M7, the low resistivity portion of the first conductive path also includes wires 822D, 832D, 842D, and 852D electrically connected together via corresponding via connectors 8V23, 8V34, and 8V45. Wire 852D is electrically connected to the first deep line 862D via via connector 8V56. Wire 822D is electrically connected to the output of the first active device D1. In some embodiments, wire 822D is electrically connected to the output of the first active device D1 via some via connectors and wires (not shown) in the first metal layer M0 and the second metal layer M1. In some embodiments, wire 822D is a deep line in the third metal layer M2, wire 832D is a deep line in the fourth metal layer M3, wire 842D is a deep line in the fifth metal layer M4, and wire 852D is a deep line in the sixth metal layer M5. In some embodiments, one or more of conductors 822D, 832D, 842D, and 852D are not dark conductors. In some embodiments, one or more of conductors 822D, 832D, 842D, and 852D are light conductors or uniform conductors.

[0066] In some embodiments, in addition to the first shallow line 868S in the seventh metal layer M6 and the second shallow line 878S in the eighth metal layer M7, the low-permittivity portion of the first conductive path connected to the second active device D2 also includes wires 828S, 838S, 848S, and 858S electrically connected together via corresponding via connectors 8V32, 8V43, and 8V54. Wire 858S is electrically connected to the first shallow line 868S via via connector 8V65. Wire 828S is electrically connected to the input of the second active device D2. In some embodiments, wire 828S is electrically connected to the input of the second active device D2 via some via connectors and some wires (not shown) in the first metal layer M0 and the second metal layer M1. In some embodiments, wire 828S is a shallow line in the third metal layer M2, wire 838S is a shallow line in the fourth metal layer M3, wire 848S is a shallow line in the fifth metal layer M4, and wire 858S is a shallow line in the sixth metal layer M5. In some embodiments, one or more of conductors 828S, 838S, 848S, and 858S are not shallow lines. In some embodiments, one or more of conductors 828S, 838S, 848S, and 858S are deep lines or uniform lines.

[0067] In some embodiments, in addition to the first shallow line 866S in the seventh metal layer M6 and the second shallow line 876S in the eighth metal layer M7, the low-permeability portion of the second conductive path connected to the third active device D3 includes wires 826S, 836S, 846S, and 856S electrically connected together via various via connectors. Wire 856S is electrically connected to the first shallow line 866S via a corresponding via connector. Wire 826S is electrically connected to the input of the third active device D3. In some embodiments, wire 826S is electrically connected to the input of the third active device D3 via some via connectors and some wires in the first metal layer M0 and the second metal layer M1. In some embodiments, wire 826S is a shallow line in the third metal layer M2, wire 836S is a shallow line in the fourth metal layer M3, wire 846S is a shallow line in the fifth metal layer M4, and wire 856S is a shallow line in the sixth metal layer M5. In some embodiments, one or more of conductors 826S, 836S, 846S, and 856S are not shallow wires. In some embodiments, one or more of conductors 826S, 836S, 846S, and 856S are deep wires or uniform wires.

[0068] When the first conduction path from the first active device D1 to the second active device D2 is implemented with low resistivity and low permittivity portions, the time delay of signal propagation along the first conduction path is reduced. Figure 8A In one specific example shown, the signal propagation time delay in the first conduction path, which has low resistivity and low permeability portions, is reduced by 5.4% compared to an alternative design where all conductors in the first conduction path are implemented as uniform lines. This 5.4% reduction is the sum of the individual reductions of 1.5%, 1.8%, 0.2%, 0.4%, 0.4%, and 1.1% in the metal layers M7, M6, M5, M4, M3, and M2, respectively.

[0069] exist Figure 8A In the specific example shown, the second deep line 872D of the low resistivity portion and the second shallow line 878S of the low permeability portion are located in the eighth metal layer M7. Compared to the optional design of uniform conductors, the time delay attributed to the second deep line 872D and the second shallow line 878S is reduced by 1.5%. Figure 8A In the specific example shown, the first deep line 862D of the low resistivity portion and the first shallow line 868S of the low permeability portion are located in the seventh metal layer M6. Compared to the alternative design of uniform conductors, the time delay attributed to the first deep line 862D and the first shallow line 868S is reduced by 1.8%.

[0070] exist Figure 8AIn the specific example shown, the deep line 852D and the shallow line 858S are located in the sixth metal layer M5. Compared to the optional design with uniform conductors, the time delay attributed to the deep line 852D and the shallow line 858S is reduced by 0.2%. Figure 8A In the specific example shown, the deep line 842D and the shallow line 848S are located in the fifth metal layer M4. Compared to the optional design with uniform conductors, the time delay attributed to the deep line 842D and the shallow line 848S is reduced by 0.4%. Figure 8A In the specific example shown, the deep line 832D and the shallow line 838S are located in the fourth metal layer M3. Compared to the optional design with uniform conductors, the time delay attributed to the deep line 832D and the shallow line 838S is reduced by 0.4%. Figure 8A In the specific example shown, the deep line 822D and the shallow line 828S are located in the third metal layer M2. Compared to the alternative design of uniform conductors, the time delay attributed to the deep line 822D and the shallow line 828S is reduced by 1.1%.

[0071] exist Figure 8A In the illustrated embodiment, the reduction in signal propagation time delay in the first conduction path includes contributions from time delay reductions in metal layers M7, M6, M5, M4, M3, and M2. In some embodiments, such as in Figure 8B In a specific instance, when the total length of the low resistivity and low permeability portions of the first conductive path implemented in the first and second conductive layers is much greater than the total length of the wires in the same path in all other conductive layers, the reduction in the time delay of signal propagation in the first conductive path is primarily determined by the reduction in time delay in the first and second conductive layers. Figure 8B In this structure, the first conductive layer is located in the ninth metal layer M8, and the second conductive layer is located in the tenth metal layer M9.

[0072] exist Figure 8BIn the first conductive path from the first active device D1 to the second active device D2, there are low resistivity and low permeability portions. The low resistivity portion of the first conductive path includes a first deep line 882D in the ninth metal layer M8 and a second deep line 892D in the tenth metal layer M9. The first deep line 882D and the second deep line 892D are electrically connected together via a via connector 8V89. The first deep line 882D in the low resistivity portion is electrically connected to the output of the first active device D1 via a via connector 8V78 and other via connectors / wires in the various metal layers (from M0 to M7). The low permeability portion of the first conductive path includes a first shallow line 888S in the ninth metal layer M8 and a second shallow line 898S in the tenth metal layer M9. The first shallow line 888S and the second shallow line 898S are electrically connected together via a via connector 8V98. The first shallow line 888S in the low-permeability section is electrically connected to the input of the second active device D2 via the through-hole connector 8V78 and other through-hole connectors / wires in the various metal layers (from M0 to M7).

[0073] exist Figure 8B In this configuration, the low-resistivity portion of the first conductive path is electrically connected to the low-permeability portion of the first conductive path via a second layer of wire 894. In some embodiments, the second layer of wire 894 is a second deep wire. In some embodiments, the second layer of wire 894 is a second shallow wire. In some embodiments, the second layer of wire 894 is a second uniform wire. The second layer of wire 894 is a fan-out node. The first conductive path (from the first active device D1 to the second active device D2) and the second conductive path (from the first active device D1 to the third active device D3) branch off at the fan-out node (i.e., the second layer of wire 894).

[0074] exist Figure 8B In this second conduction path, a low resistivity portion and a low permeability portion are also included. The low resistivity portion is located between the first active device D1 and the second layer conductor 894. The low permeability portion is located between the second layer conductor 894 and the third active device D3. The low resistivity portion of the second conduction path includes a first layer deep conductor 882D and a second layer deep conductor 892D. The low permeability portion of the second conduction path includes a first layer shallow conductor 886S and a second layer shallow conductor 896S electrically connected together via corresponding through-hole connectors.

[0075] exist Figure 8B In this context, when the first conduction path from the first active device D1 to the second active device D2 is implemented with low resistivity and low permittivity portions, the time delay of signal propagation along the first conduction path is reduced. Figure 8B In the specific example shown, the reduction in signal propagation time delay in the first conduction path is mainly determined by the reduction in time delay in the ninth metal layer M8 and the tenth metal layer M9. Figure 8B In the specific example shown, the time delay caused by the first deep line 882D and the first shallow line 888S in the ninth metal layer M8 is reduced by 2.8% compared to an alternative design of uniform conductive lines. Figure 8B In the specific example shown, the time delay caused by the second deep line 892D and the second shallow line 898S in the tenth metal layer M9 is reduced by 2.0% compared to an alternative design with uniform conductive lines. Figure 8B In the specific example shown, compared to an alternative design where all wires in the first conduction path are implemented as uniform lines, the total time delay of signal propagation in the first conduction path is reduced by 4.7%.

[0076] In some embodiments, when the total length of the first conductive path from the first active device D1 to the second active device D2 is less than a predetermined distance, each wire in the first conductive path is implemented as a deep wire. In some embodiments, the value of the predetermined distance used by the APR program is set by the user. In some embodiments, the value of the predetermined distance used by the APR program is read from a database or technical document.

[0077] In some embodiments, such as Figure 9 As shown, the output of the first active device D1 is electrically connected to multiple receiving devices (such as D2A, D2B, D2C, and D2D). In some embodiments, when the total length of the conductive path from the first active device D1 to each receiving device (such as D2A, D2B, D2C, or D2D) is less than a predetermined distance, the wires in all conductive paths from the output of the first active device D1 to the multiple receiving devices D2A to D2D are implemented with deep lines in at least two conductive layers. Figure 9 In this configuration, the conduction path from the first active device D1 to the plurality of receiving devices D2A to D2D is broken at the fan-out node (i.e., wire 934D). The common part of the conduction path from the first active device D1 to the plurality of receiving devices D2A to D2D is from the output of the first active device D1 to wire 934D.

[0078] exist Figure 9 In this configuration, the common portion of the conduction path includes a first-layer deep wire 922D in the third metal layer M2 and a second-layer deep wire 932D in the fourth metal layer M3. The first-layer deep wire 922D and the second-layer deep wire 932D are electrically connected together via a through-hole connector 9V23. The first-layer deep wire 922D is electrically connected to the output of the first active device D1 via various through-hole connectors and various wires (including deep wire 912D in the second metal layer M1). The common portion of the conduction path is electrically connected via wire 934D to branch paths leading to each receiving device (such as D2A, D2B, D2C, or D2D). Figure 9 In this process, conductor 934D is implemented as a deep line in the fourth metal layer M3.

[0079] exist Figure 9 In this configuration, the branch path of each receiving device (such as D2A, D2B, D2C, or D2D) includes a deep line (correspondingly 929D, 928D, 927D, or 926D) in the third metal layer M2 and a deep line (correspondingly 939D, 938D, 937D, or 936D) in the fourth metal layer M3. Each of the deep lines 939D, 938D, 937D, and 936D is electrically connected between a fan-out node (i.e., wire 934D) and one of the corresponding deep lines 929D, 928D, 927D, or 926D. Each of the deep lines 929D, 928D, 927D and 926D is electrically connected to the input of one of the corresponding receiving devices D2A, D2B, D2C or D2D via various through-hole connectors and various wires (such as through one of the corresponding deep lines 919D, 918D, 917D or 916D in the second metal layer M1).

[0080] exist Figure 9 In the case where the total length of the deep wires in metal layers M2 and M3 of the conduction path from the first active device D1 to the receiving element (such as D2A, D2B, D2C or D2D) is greater than the total length of the wires for the same conduction path in all other conductive layers, the reduction in the time delay of signal propagation in the conduction path to each receiving device is mainly determined by the reduction in time delay in the third metal layer M2 and the fourth metal layer M3.

[0081] exist Figure 9 In the specific example shown, compared to the alternative design of a uniform conductor, the time delay reduction attributed to the deep line 922D in the third metal layer M2 is 2.7%, and the time delay reduction attributed to the deep line 932D in the fourth metal layer M3 is 1.1%. Figure 9 In the specific example shown, the time delay reduction attributed to the deep lines (929D, 928D, 927D, or 926D) in the third metal layer M2 on the branch path is 0.2%, and the time delay reduction attributed to the deep lines (939D, 938D, 937D, or 936D) in the fourth metal layer M3 on the branch path is -0.3% compared to an alternative design with uniform conductors. Figure 9 In the specific example shown, the total time delay of signal propagation in the conduction path from the first active device D1 to one of the receiving devices (such as D2A, D2B, D2C, or D2D) is reduced by 3.7% compared to an alternative design in which all wires in the conduction path are implemented as uniform lines.

[0082] Figure 10 This is a flowchart of a method 1000 for manufacturing an integrated circuit according to some embodiments. Figure 10 The operational sequence of method 1000 described herein is for illustrative purposes only; the operation of method 1000 can be performed in conjunction with... Figure 10 The order shown differs from the order in which they are executed. It should be understood that... Figure 10 Additional operations are performed before, during, and / or after the method described in this document 1000, and some other processes may be described only briefly in this document.

[0083] In operation 1010 of method 1000, a conduction path is selected to connect the first active device and the second active device. In some embodiments, the selected conduction path is selected to improve speed because if the selected conduction path is implemented as a uniform line, the selected conduction path has a delay time longer than the critical delay time.

[0084] In operation 1015 of method 1000, the length of the transmission path is compared with a predetermined value in the APR procedure. If the length of the transmission path is less than the predetermined value, the process flow of method 1000 proceeds to operation 1018. On the other hand, if the length of the transmission path is not less than the predetermined value, the process flow of method 1000 proceeds to operation 1020.

[0085] In operation 1018 of method 1000, following the "yes" decision from operation 1015, a deep line is selected for the conduction path in at least two conductive layers. Figure 9 In an example embodiment, when the total length of the conduction path from the first active device D1 to each receiving device (such as D2A, D2B, D2C or D2D) is less than a predetermined distance, the metal layers M2 and M3 of all conduction paths from the output of the first active device D1 to the multiple receiving devices D2A to D2D are implemented with deep lines.

[0086] In operation 1020 of method 1000, following the decision "no" from operation 1015, a candidate group of mutation points is generated. Figures 6A to 6F In some example embodiments, the candidate mutation point group includes via connectors 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6. In some example embodiments, one or more candidate mutation points are located at fan-out nodes. Examples of fan-out nodes include... Figure 7 The second deep line 525D in the middle Figure 8A The second layer of conductor 874 or Figure 8B The second layer of conductors is 894.

[0087] In operation 1030 of method 1000, the time delay of signal propagation in the conduction paths of at least two mutation point candidates is evaluated. Figures 6A to 6FIn an example embodiment, when one of the via connectors 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6 is selected as the abrupt change point 6MP, the time delay of signal propagation in the conduction path is evaluated for each case. In some embodiments, only some of the via connectors 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6 are evaluated to achieve the abrupt change point 6MP.

[0088] In operation 1040 of method 1000, based on the time delay obtained in operation 1030, the candidate mutation point with the smallest time delay is selected as the mutation point. Figures 6A to 6F In an example embodiment, after evaluating each of the via connectors 6V1, 6V2, 6V3, 6V4, 6V5, and 6V6 as a mutation point 6MP, a mutation point candidate with the minimum time delay is selected. In one example, when the via connector 6V4 is selected as the mutation point 6MP, the conduction path from the first active device D1 to the second active device D2 has the minimum time delay. Figures 8A to 8B In the example embodiment, the selected mutation point is located at the fan-out node (i.e., Figure 8A The second layer of conductor 874 or Figure 8B The second layer of conductor (894) is located at this point.

[0089] In some embodiments, after selecting the abrupt change point, a layout pattern for the low resistivity portion of the conduction path and a layout pattern for the low permeability portion of the conduction path are generated using an APR program. The process then proceeds to operation 1050.

[0090] In operation 1050 of method 1000, a low-resistivity portion and a low-permeability portion of the conduction path are fabricated. The low-resistivity portion of the conduction path includes one or more deep lines between the output of the first active device and the abrupt change point. The low-permeability portion of the conduction path includes one or more shallow lines between the abrupt change point and the input of the second active device. Figure 6D In an example embodiment, the low resistivity portion 601D manufactured in operation 1050 includes a first deep line 512D, a second deep line 523D, a first deep line 514D, and a second deep line 525D. Figure 6D In an example embodiment, the low-permeability portion 602D manufactured in operation 1050 includes a first layer of shallow lines 517S, a second layer of shallow lines 527S, and a first layer of shallow lines 518S. Figure 6D In an example embodiment, the low resistivity portion 601D is located between the output of the first active device D1 and the abrupt change point 6MP, while the low permeability portion 602D is located between the abrupt change point 6MP and the input of the second active device D2.

[0091] Figure 11This is a flowchart of a method 1100 for manufacturing at least one deep line and at least one shallow line according to some embodiments. Figure 11 The operational sequence of method 1100 described herein is for illustrative purposes only; the operation of method 1100 can be performed in conjunction with... Figure 11 The order shown differs from the order in which they are executed. It should be understood that... Figure 11 Additional operations are performed before, during, and / or after the method 1100 described herein, and some other processes may be described only briefly.

[0092] Figures 12A to 12E This is a cross-sectional view of an example device structure manufactured during operation of method 1100 according to some embodiments. Figure 12E Chinese description Figure 6F The integrated circuits in the cut planes MM' and NN' (correspondingly made by...) Figure 6F The cross-sectional view within the lines MM' and NN' (specified in the diagram). Figure 12E In the cross-sectional view of the cut plane NN', the first shallow line 518S and the first deep lines 517D to 519D embedded in the interlayer dielectric 210 are fabricated on the insulating layer 205. The depth of each first deep line (e.g., 517D, 518D, 519D) is greater than the depth of the first shallow line 518S. The interlayer dielectric 220 is deposited on the interlayer dielectric 210 and on the first deep lines and the first shallow lines. A second deep line 527D extending along the Y direction is embedded in the interlayer dielectric 220. Furthermore, the second deep line 527D is electrically connected to the first shallow line 518S through a through-hole connector 6V6 and to the first deep line 517D through a through-hole connector 6V5.

[0093] exist Figure 12E In the cross-sectional view of the cut plane MM', the first shallow line 518S embedded in the interlayer dielectric 210 is fabricated on the insulating layer 205. The interlayer dielectric 220 is deposited on the interlayer dielectric 210 and the first shallow line 518S. Second shallow lines 526S to 527S and second deep lines 527D to 528D are fabricated in the interlayer dielectric 220 on top of the interlayer dielectric 210. Furthermore, the second deep line 527D is electrically connected to the first shallow line 518S via a through-hole connector 6V6.

[0094] Figure 11Method 1100 includes operations 1110, 1120, 1130, 1140, 1150, 1160, and 1170. In operation 1110 of method 1100, a first insulating layer is deposited on another base insulating layer. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or other suitable deposition processes. In some embodiments, the base insulating layer is a top insulating layer fabricated in a front-end process (FEOL) process. In some embodiments, the base insulating layer is one of an interlayer dielectric (ILD) layer fabricated after the FEOL process. In one example embodiment, as Figure 12A As shown, an interlayer dielectric 210 is deposited on top of the insulating layer 205.

[0095] In operation 1120 of method 1100, deep trenches and shallow trenches are formed in the first insulating layer. In some embodiments, the pattern of the deep trenches and shallow trenches is defined by a mask layer fabricated on the first insulating layer using photolithography. In some embodiments, the etching process for forming the deep trenches and shallow trenches includes deep reactive ion etching or other suitable etching processes. In one example embodiment, as... Figure 12A As shown, shallow trenches 1218S and deep trenches 1217D to 1219D are formed in the interlayer dielectric 210.

[0096] In operation 1130 of method 1100, a first deep line is formed in the deep trench and a first shallow line is formed in the shallow trench. In some embodiments, metallic material is deposited into the deep and shallow trenches, followed by a polishing process, such as chemical mechanical polishing (CMP), for planarization and removal of excess metallic material. In some embodiments, the deposition process of the metallic material includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or other suitable deposition processes. In one example embodiment, as... Figure 12B As shown, metallic materials are deposited into shallow trenches 1218S and deep trenches 1217D to 1219D (e.g. Figure 12A (As shown) After that, a first shallow line 518S and a first deep line 517D to 519D are formed in the interlayer dielectric 210.

[0097] In operation 1140 of method 1100, a second insulating layer is deposited over the first insulating layer. In some embodiments, the deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or other suitable deposition processes. In one example embodiment, such as Figure 12C As shown, interlayer dielectric 210 is deposited on top of interlayer dielectric 210.

[0098] In operation 1150 of method 1100, a via opening is formed in the second insulating layer. In operation 1160 of method 1100, a deep trench and a shallow trench are formed in the second insulating layer. In some embodiments, the via opening, the deep trench, and the shallow trench are formed in multiple steps of the patterning process and the etching process. In some embodiments, the patterning process includes forming a mask layer on the second insulating layer using photolithography. In some embodiments, the etching process for forming the via opening, the deep trench, and the shallow trench includes deep reactive ion etching or other suitable etching processes. In one example embodiment, such as Figure 12D As shown, through-hole openings 12V5 to 12V6, shallow trenches 1226S to 1227S, and deep trenches 1227D to 1228D are formed in the interlayer dielectric 220.

[0099] In operation 1170 of method 1100, metallic material is deposited into the via opening, deep trench, and shallow trench, thereby correspondingly forming a second deep line and a second shallow line in the deep trench and shallow trench of the second insulating layer. In one example embodiment, as Figure 12E As shown, when depositing metallic material to the via openings 12V5 to 12V6 ( Figure 12D (Middle) and deposited to shallow trenches 1226S to 1227S and deep trenches 1227D to 1228D ( Figure 12D After that, a second layer of shallow lines 526S to 527S and a second layer of deep lines 527D to 528D are formed in the interlayer dielectric 220. In addition, a through-hole connector 6V5 is formed to connect the second layer of deep lines 527D to the first layer of deep lines 517D, and a through-hole connector 6V5 is formed to connect the second layer of deep lines 527D to the first layer of shallow lines 518S.

[0100] Figure 13 This is a block diagram of an electronic design automation (EDA) system 1300 according to some embodiments.

[0101] In some embodiments, EDA system 1300 includes an APR system. According to one or more embodiments, the design layout method described herein represents wire routing, which, according to some embodiments, can be implemented, for example, using EDA system 1300.

[0102] In some embodiments, the EDA system 1300 is a general-purpose computing device including a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. Among other things, the storage medium 1304 is encoded with computer program code 1306 (i.e., an executable instruction set), that is, the computer program code is stored thereon. Execution of the instructions 1306 by the hardware processor 1302 represents at least partially an EDA tool that implements part or all of the methods described herein according to one or more embodiments (hereinafter, the processes and / or methods mentioned).

[0103] Processor 1302 is electrically connected to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically connected to input / output (I / O) interface 1310 via bus 1308. Network interface 1312 is also electrically connected to processor 1302 via bus 1308. Network interface 1312 is connected to network 1314 so that processor 1302 and computer-readable storage medium 1304 can be connected to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304 to make system 1300 available to perform some or all of the aforementioned processes and / or methods. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0104] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, fiber optic, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, mobile electronic disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes optical disc read-only memory (CD-ROM), optical disc read / write memory (CD-R / W), and / or digital video optical disc (DVD).

[0105] In one or more embodiments, storage medium 1304 stores computer program code 1306 configured to enable system 1300 (where such execution (at least partially) represents an EDA tool) to perform some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1304 also stores information that facilitates the execution of some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1304 stores a standard cell library 1307, including standard cells such as those disclosed herein. In one or more embodiments, storage medium 1304 stores one or more layout diagrams 1309 corresponding to one or more layouts disclosed herein.

[0106] EDA system 1300 includes I / O interface 1310. I / O interface 1310 is connected to external circuitry. In one or more embodiments, I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0107] EDA system 1300 also includes a network interface 1312 connected to processor 1302. Network interface 1312 allows system 1300 to communicate with a network 1314 connected to one or more other computer systems. Network interface 1312 includes a wireless network interface such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA, or a wired network interface such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more systems 1300.

[0108] System 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1302. The information is transferred to processor 1302 via bus 1308. EDA system 1300 is configured to receive UI-related information via I / O interface 1310. This information is stored as a user interface (UI) 1342 on computer-readable medium 1304.

[0109] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, part or all of the described processes and / or methods are executed as part of a software application for an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application used by the EDA system 1300. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0110] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or storage units, such as one or more of optical discs such as DVDs, magnetic disks such as hard disks, and semiconductor memories such as ROM, RAM, and memory cards.

[0111] Figure 14This is a block diagram of an integrated circuit (IC) manufacturing system 1400 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, the manufacturing system 1400 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one element in a layer of a semiconductor integrated circuit.

[0112] exist Figure 14 In this IC manufacturing system 1400, entities interact with each other throughout the design, development, and manufacturing cycles, such as design studio 1420, mask room 1430, and IC manufacturer / producer (“fab”) 1450 and / or services related to the manufacture of IC devices 1460. The entities in system 1400 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design studio 1420, mask room 1430, and IC fab 1450 are owned by a single, larger company. In some embodiments, two or more of design studio 1420, mask room 1430, and IC fab 1450 coexist in a shared facility and use shared resources.

[0113] Design studio (or design team) 1420 generates IC design layout 1422. IC design layout 1422 includes various geometric patterns designed for IC device 1460. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1460 to be manufactured. The various layers combine to form various IC components. For example, a portion of IC design layout 1422 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on a semiconductor substrate. Design studio 1420 implements appropriate design procedures to form IC design layout 1422. The design process includes one or more of logic design, physical design, or placement and routing. IC design layout 1422 is presented in one or more data files containing information about the geometric patterns. For example, IC design layout 1422 may be represented in GDSII or DFII file format.

[0114] Mask chamber 1430 includes data preparation 1432 and mask fabrication 1444. Mask chamber 1430 uses an IC design layout 1422 to fabricate one or more masks 1445 to fabricate various layers of an IC device 1460 according to the IC design layout 1422. Mask chamber 1430 performs mask data preparation 1432, in which the IC design layout 1422 is converted into a representative data file (RDF). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1445 or a semiconductor wafer 1453. The design layout 1422 is manipulated by mask data preparation 1432 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1450. Figure 14 In this diagram, mask data preparation 1432 and mask manufacturing 1444 are shown as separate elements. In some embodiments, mask data preparation 1432 and mask manufacturing 1444 can be collectively referred to as mask data preparation.

[0115] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. OPC adjusts the IC design layout diagram 1422. In some embodiments, mask data preparation 1432 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0116] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that checks the IC design layout 1422, which has already been processed in the OPC, against a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to address issues such as variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for constraints during mask fabrication 1444, which can reverse some modifications performed by the OPC to satisfy the mask creation rules.

[0117] In some embodiments, mask data preparation 1432 includes lithography process inspection (LPC), an LPC simulation performed by ICfab 1450 to fabricate IC device 1460. The LPC simulates this process based on IC design layout 1422 to create a simulated fabricated device, such as IC device 1460. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to fabricate the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after a simulated fabricated device has been created by the LPC, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1422.

[0118] It should be understood that, for clarity, the above description of mask data preparation 1432 has been simplified. In some embodiments, data preparation 1432 includes additional features such as logic operations (LOPs) to modify the IC design layout 1422 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1422 during data preparation 1432 can be performed in various different sequences.

[0119] Following mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 is fabricated based on a modified IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures based on the IC design layout 1422. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to pattern the mask (photomask or intermediate mask) 1445 according to the modified IC design layout 1422. The mask 1445 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1445. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary intermediate mask of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1445 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1445, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask may be a decaying PSM or an alternating PSM. One or more masks generated by mask fabrication 1444 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0120] IC fab 1450 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 1450 is a semiconductor foundry. For example, there may be a manufacturing plant for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing plant can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing plant may provide additional services for foundry operations.

[0121] IC fab 1450 includes manufacturing tools 1452 configured to perform various manufacturing operations on a semiconductor wafer 1453, such that IC device 1460 is manufactured according to one or more masks (e.g., mask 1445). In various embodiments, manufacturing tools 1452 include one or more of the following: a wafer stepper, an ion implanter, a coater, a process chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment as discussed herein capable of performing one or more suitable manufacturing processes.

[0122] IC fab 1450 uses mask 1445, fabricated through mask chamber 1430, to fabricate IC device 1460. Therefore, IC fab 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, using mask 1445, semiconductor wafer 1453 is fabricated through IC fab 1450 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate having multiple material layers formed thereon. Semiconductor wafer 1453 also includes one or more of various doped regions, dielectric components, and multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0123] This invention relates to an integrated circuit. The integrated circuit includes a plurality of first deep lines and a plurality of first shallow lines. Each of the first deep lines and the first shallow lines is located in a first conductive layer above a transistor on a substrate. The integrated circuit also includes a plurality of second deep lines and a plurality of second shallow lines. Each of the second deep lines and the second shallow lines is located in a second conductive layer above the first conductive layer.

[0124] In some embodiments, the integrated circuit further includes: a conductive path having at least one first deep line and at least one second deep line, but not including the first shallow line and the second shallow line.

[0125] In some embodiments, the integrated circuit further includes: a conduction path having a low resistivity portion and a low permeability portion, wherein the low resistivity portion is connected to the output of a first active device, and wherein the low permeability portion is connected to the input of a second active device; wherein the low resistivity portion includes at least one first deep line or at least one second deep line, but does not include the first shallow line or the second shallow line; and wherein the low permeability portion includes at least one first shallow line or at least one second shallow line, but does not include the first deep line or the second deep line.

[0126] In some embodiments, the low resistivity portion includes at least one first deep line and at least one second deep line; and the low permeability portion includes at least one first shallow line and at least one second shallow line.

[0127] In some embodiments, the low resistivity portion is connected to the low permeability portion via a through-hole connector between the first conductive layer and the second conductive layer.

[0128] In some embodiments, the low resistivity portion is connected to the low permeability portion via a fan-out node.

[0129] In some embodiments, the integrated circuit further includes: a third active device located on the substrate; a branch conduction path located between the fan-out node and the input of the third active device; and wherein the branch conduction path includes at least another first layer shallow line or another second layer shallow line, but does not include a first layer deep line or a second layer deep line.

[0130] In some embodiments, the integrated circuit further includes: a plurality of third-layer deep lines and a plurality of third-layer shallow lines, wherein each of the third-layer deep lines and the third-layer shallow lines is located in a third conductive layer.

[0131] In some embodiments, the third conductive layer is located on top of the second conductive layer.

[0132] In some embodiments, the third conductive layer is located between the first conductive layer and the second conductive layer.

[0133] In some embodiments, the third conductive layer is located above the transistor but below the first conductive layer.

[0134] In some embodiments, the integrated circuit further includes: a plurality of wires located in a third conductive layer between the first conductive layer and the second conductive layer.

[0135] Another aspect of the invention also relates to an integrated circuit. The integrated circuit includes a plurality of first-layer deep lines and a plurality of first-layer shallow lines. Each of the first-layer deep lines and the first-layer shallow lines is located in a first conductive layer. The integrated circuit further includes a conductive path having a low-resistivity portion and a low-permeability portion. The low-resistivity portion is connected to the output of a first active device. The low-permeability portion is connected to the input of a second active device. The low-resistivity portion includes at least one first-layer deep line but does not include any of the first-layer shallow lines. The low-permeability portion includes at least one first-layer shallow line but does not include any of the first-layer deep lines.

[0136] In some embodiments, the integrated circuit further includes: a plurality of second deep lines and a plurality of second shallow lines, wherein each of the second deep lines and the second shallow lines is located in a second conductive layer above the first conductive layer; wherein the low resistivity portion includes at least one second deep line but does not include the second shallow lines; and wherein the low permeability portion includes at least one second shallow line but does not include the second deep lines.

[0137] In some embodiments, the low resistivity portion and the low permeability portion are connected at a through-hole connector between the first conductive layer and the second conductive layer.

[0138] In some embodiments, the low resistivity portion and the low permeability portion are connected at the fan-out node.

[0139] Another aspect of the invention relates to a method. The method includes: fabricating a first deep wire and a first shallow wire extending in a first insulating layer in a first direction; the method further includes: fabricating a through-hole connector, a second deep wire, and a second shallow wire in a second insulating layer. The second deep wire and the second shallow wire extend in a second direction perpendicular to the first direction. One of the through-hole connectors connects one of the second deep wires to one of the first shallow wires, or connects one of the second shallow wires to one of the first deep wires.

[0140] In some embodiments, the method further includes forming deep trenches for deep lines of the first layer and shallow trenches for shallow lines of the first layer in the first insulating layer.

[0141] In some embodiments, the method further includes: forming a through-hole opening for the through-hole connector in the second insulating layer; and forming a deep trench for the deep wires of the second layer and a shallow trench for the shallow wires of the second layer in the second insulating layer.

[0142] In some embodiments, the method further includes depositing metallic material into the through-hole opening, the deep trench, and the shallow trench.

[0143] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit, comprising: A plurality of first-layer deep lines and a plurality of first-layer shallow lines, wherein each of the first-layer deep lines and the first-layer shallow lines is located in a first conductive layer above a transistor on a substrate; and Multiple second-layer deep lines and multiple second-layer shallow lines, wherein each of the second-layer deep lines and the second-layer shallow lines is located in a second conductive layer above the first conductive layer; The conductive path has a low resistivity portion and a low permeability portion, wherein the low resistivity portion is connected to the low permeability portion through a through-hole connector between the first conductive layer and the second conductive layer. The low resistivity portion includes at least one first deep line or at least one second deep line, but does not include the first shallow line or the second shallow line; and The low permittivity portion includes at least one first shallow line or at least one second shallow line, but does not include the first deep line or the second deep line.

2. The integrated circuit according to claim 1, wherein, Each of the first deep line and the first shallow line extends along a first direction.

3. The integrated circuit according to claim 1, in, The low resistivity portion is connected to the output of the first active device, and the low permeability portion is connected to the input of the second active device.

4. The integrated circuit according to claim 3, wherein: The low resistivity portion includes at least one first deep line and at least one second deep line; and The low permittivity portion includes at least one first layer of shallow lines and at least one second layer of shallow lines.

5. The integrated circuit according to claim 2, wherein, The second deep line and the second shallow line extend in a second direction perpendicular to the first direction.

6. The integrated circuit according to claim 1, wherein, The depth of the second depth line is different from the depth of the first depth line.

7. The integrated circuit according to claim 1, further comprising: A third active device is located on the substrate; The branch conduction path is located between the fan-out node and the input of the third active device; as well as The branch conduction path includes at least one other first-layer shallow line or another second-layer shallow line, but does not include a first-layer deep line or a second-layer deep line.

8. The integrated circuit according to claim 1, further comprising: Multiple third-layer deep lines and multiple third-layer shallow lines, wherein each of the third-layer deep lines and the third-layer shallow lines is located in a third conductive layer.

9. The integrated circuit according to claim 8, wherein, The third conductive layer is located on top of the second conductive layer.

10. The integrated circuit according to claim 8, wherein, The third conductive layer is located between the first conductive layer and the second conductive layer.

11. The integrated circuit according to claim 8, wherein, The third conductive layer is located above the transistor but below the first conductive layer.

12. The integrated circuit according to claim 1, further comprising: Multiple wires are located in a third conductive layer between the first conductive layer and the second conductive layer.

13. An integrated circuit, comprising: Multiple first-layer deep lines and multiple first-layer shallow lines, wherein each of the first-layer deep lines and the first-layer shallow lines is located in a first conductive layer; Multiple second-layer deep lines and multiple second-layer shallow lines, wherein each of the second-layer deep lines and the second-layer shallow lines is located in a second conductive layer above the first conductive layer; The conduction path has a low resistivity portion and a low permittivity portion, wherein the low resistivity portion is connected to the output of a first active device and the low permittivity portion is connected to the input of a second active device. Wherein, the low resistivity portion includes at least one first deep line but does not include the first shallow line; and The low permittivity portion includes at least one first shallow line but does not include the first deep line. The low resistivity portion further includes at least one second deep line but does not include a second shallow line; and The low permittivity portion includes at least one second shallow line but does not include a second deep line. The low resistivity portion is connected to the low permeability portion at the through-hole connector between the first conductive layer and the second conductive layer.

14. The integrated circuit according to claim 13, further comprising: Multiple third-layer deep lines and multiple third-layer shallow lines, wherein each of the third-layer deep lines and the third-layer shallow lines is located in a third conductive layer.

15. The integrated circuit according to claim 14, wherein, The third conductive layer is located on top of the second conductive layer.

16. The integrated circuit according to claim 14, wherein, The third conductive layer is located between the first conductive layer and the second conductive layer.

17. A method for manufacturing an integrated circuit, comprising: A first deep line and a first shallow line extending in a first direction are formed in the first insulating layer; A through-hole connector, a second deep wire, and a second shallow wire are fabricated in a second insulating layer, wherein the second deep wire and the second shallow wire extend in a second direction perpendicular to the first direction; and A conduction path is formed, the conduction path having a low resistivity portion and a low permittivity portion. The low resistivity portion includes at least one first deep line or at least one second deep line, but does not include the first shallow line or the second shallow line; and The low permittivity portion includes at least one first shallow line or at least one second shallow line, but does not include the first deep line or the second deep line. One of the through-hole connectors connects the low resistivity portion to the low permeability portion.

18. The method of claim 17, further comprising: Deep trenches for the deep lines of the first layer and shallow trenches for the shallow lines of the first layer are formed in the first insulating layer.

19. The method of claim 17, further comprising: A through-hole opening for the through-hole connector is formed in the second insulating layer; as well as Deep trenches for the deep lines of the second layer and shallow trenches for the shallow lines of the second layer are formed in the second insulating layer.

20. The method of claim 19, further comprising: Metallic material is deposited into the through-hole opening, the deep trench, and the shallow trench.

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