Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method comprises: providing a substrate; removing part of the substrate to form a plurality of active pillars, any two adjacent active pillars in a first direction are separated; forming a plurality of bit lines extending along the first direction, each bit line wraps part of the sidewall of the bottom region of each active pillar in the extension direction. In the semiconductor structure manufacturing method of the present disclosure, the process of forming the bit line is simplified, the formed bit line surrounds part of the sidewall of the circumference of the active pillar, the contact area between the bit line and the active pillar is improved, the contact resistance between the bit line and the active pillar is reduced, and the electrical performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the development of Dynamic Random Access Memory (DRAM), higher integration density and smaller feature size are required in semiconductor devices to improve memory storage capacity. To increase storage density, semiconductor devices have evolved from planar gates to Gate-All-Around (GAA). GAA achieves gate-all-around coverage of the channel on all four sides, thus increasing memory density.

[0003] However, in memory with a fully encircling gate, the bit line is located at the bottom of the gate. The bit line manufacturing process is complex, and the contact area between the bit line and the active region is small, resulting in weak conductivity of the bit line, which affects the electrical performance of the memory. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself.

[0006] A first aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0007] Provide substrate;

[0008] A portion of the substrate is removed to form a plurality of active pillars, wherein any two adjacent active pillars in a first direction are separated.

[0009] Multiple bit lines are formed extending along the first direction, each bit line covering a portion of the sidewall of the bottom region of each active post located in its extending direction.

[0010] According to some embodiments of this disclosure, the removal of a portion of the substrate to form a plurality of active pillars includes:

[0011] A portion of the substrate is removed to form a second pillar and a first pillar located above and connected to the second pillar, wherein a peripheral region of the bottom surface of the first pillar is exposed outside the second pillar.

[0012] According to some embodiments of this disclosure, the provided substrate includes:

[0013] An initial substrate is provided, the initial substrate having a first conductivity type;

[0014] Conductive ions are doped into a first region of the initial substrate to form a first doped region, the first doped region having a second conductivity type that is opposite to the first conductivity type.

[0015] According to some embodiments of this disclosure, removing a portion of the substrate includes:

[0016] The first doped region having a second conductivity type is removed to form the first pillar;

[0017] Continue removing a portion of the first doped region and a portion of the initial substrate having the first conductivity type to form the second pillar.

[0018] According to some embodiments of this disclosure, the first region is etched to form a plurality of first pillars, any two adjacent first pillars in the first direction are separated by a first trench, any two adjacent first pillars in the second direction are separated by a second trench, and the bottom surface of the first pillar is higher than the bottom surface of the first doped region.

[0019] A second etching is performed on the first region and the initial substrate based on the first trench and the second trench to form a second pillar below the first pillar. The second pillar includes a first portion having the first conductivity type and a second portion having the second conductivity type.

[0020] According to some embodiments of this disclosure, forming a plurality of bit lines extending along the first direction includes:

[0021] A first barrier layer is formed, which covers part of the sidewall of the second column and the exposed bottom surface of the first column;

[0022] A metallic material is deposited, which covers the first barrier layer and fills the trenches between the first barrier layers;

[0023] The metal material exposed by the second trench is removed, and the retained metal material forms a bit line metal layer, which, together with the first barrier layer, forms the bit line.

[0024] According to some embodiments of this disclosure, the bit line covers the sidewall of the second portion and a portion of the sidewall of the first portion near the second portion;

[0025] The height of the bit line covering the first portion is less than half the height of the bit line.

[0026] According to some embodiments of this disclosure, the manufacturing method further includes:

[0027] A first isolation layer is formed between the top surface of the retained substrate and the bit line, and the first isolation layer covers a portion of the sidewall of the first portion near the substrate.

[0028] According to some embodiments of this disclosure, any two adjacent active pillars in the second direction are separated, and the manufacturing method further includes:

[0029] A second isolation layer is formed, which fills the gap between adjacent bit lines, and the top surface of the second isolation layer is higher than the top surface of the bit line;

[0030] Multiple word lines extending along the second direction are formed, and the multiple word lines are disposed on the second isolation layer. Each word line covers a portion of the sidewall of each active post located in its extension direction, and the top surface of the word line is lower than the top surface of the active post.

[0031] A third isolation layer is formed, which fills the gap between adjacent word lines and covers the word lines, with the top surface of the third isolation layer flush with the top surface of the active post.

[0032] A second aspect of this disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0033] Base;

[0034] Multiple active columns are disposed on the substrate, and any two adjacent active columns in a first direction are separated.

[0035] Multiple bit lines extending along a first direction, each bit line covering a portion of the sidewall of the bottom region of each of the active pillars located in its extending direction.

[0036] According to some embodiments of this disclosure, the active column includes:

[0037] The second column is disposed on the base;

[0038] A first column is located above and connected to the second column, and the peripheral area of ​​the bottom surface of the first column is outside the second column.

[0039] According to some embodiments of this disclosure, the bit line includes:

[0040] A first barrier layer covers part of the sidewall of the second column and the peripheral area of ​​the bottom surface of the first column;

[0041] Bit line metal layer, the bit line metal layer covering the first barrier layer.

[0042] According to some embodiments of this disclosure, the substrate has a first conductivity type, the first pillar has a second conductivity type, the first conductivity type and the second conductivity type are opposite, and the second pillar includes:

[0043] A first portion, the first portion being connected to the substrate and the first portion having the first conductivity type;

[0044] The second part is connected to the first column and has the second conductivity type.

[0045] According to some embodiments of this disclosure, the bit line covers the sidewall of the second portion and a portion of the sidewall of the first portion near the second portion;

[0046] The height of the bit line covering the first portion is less than half the height of the bit line.

[0047] According to some embodiments of this disclosure, any two adjacent active pillars in the second direction are separated, and the semiconductor structure further includes:

[0048] Multiple word lines extending along the second direction are disposed above the multiple bit lines. Each word line covers a portion of the sidewall of each active post located in its extension direction, and the top surface of the word line is lower than the top surface of the active post.

[0049] According to some embodiments of this disclosure, the semiconductor structure further includes:

[0050] An isolation structure that fills the gaps between adjacent bit lines, between adjacent word lines, between adjacent active pillars, and between word lines and bit lines.

[0051] The semiconductor structure fabrication method and semiconductor structure provided in this disclosure simplify the process of forming bit lines. The formed bit lines surround and cover a portion of the circumferential sidewall of the active pillar, thereby increasing the contact area between the bit lines and the active pillar, reducing the contact resistance between the bit lines and the active pillar, and improving the electrical performance of the semiconductor structure.

[0052] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0054] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0055] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0056] Figure 3 This is a schematic diagram of the AA cross-section of a substrate according to an exemplary embodiment.

[0057] Figure 4 This is a schematic diagram of an AA cross-section of an active column according to an exemplary embodiment.

[0058] Figure 5 This is a top view illustrating the formation of an active column according to an exemplary embodiment.

[0059] Figure 6 This is a schematic diagram of an AA cross-section of a bit line according to an exemplary embodiment.

[0060] Figure 7 This is a schematic diagram of the AA cross-section of the initial substrate according to an exemplary embodiment.

[0061] Figure 8 This is a schematic diagram of the AA cross-section of a substrate according to an exemplary embodiment.

[0062] Figure 9 This is a schematic diagram of the AA section forming the first column according to an exemplary embodiment.

[0063] Figure 10 yes Figure 9 Top view.

[0064] Figure 11 This is a schematic diagram of the AA section forming the second column according to an exemplary embodiment.

[0065] Figure 12 yes Figure 11 Top view.

[0066] Figure 13 This is a schematic diagram of a cross-section AA forming the first isolation layer, according to an exemplary embodiment.

[0067] Figure 14 This is a schematic diagram of an AA cross-section illustrating the formation of an initial barrier layer according to an exemplary embodiment.

[0068] Figure 15 This is a schematic diagram of a cross-section AA showing the formation of a first barrier layer according to an exemplary embodiment.

[0069] Figure 16 This is a schematic diagram of a cross-section AA of a filler metal material according to an exemplary embodiment.

[0070] Figure 17 This is a top view illustrating the formation of an initial bitline layer according to an exemplary embodiment.

[0071] Figure 18 This is a top view illustrating the formation of a bitline metal layer according to an exemplary embodiment.

[0072] Figure 19 This is a schematic diagram of a cross-section AA of a bitline metal layer according to an exemplary embodiment.

[0073] Figure 20 This is a schematic diagram of a cross-section AA showing the formation of a second barrier layer according to an exemplary embodiment.

[0074] Figure 21 This is a schematic diagram of a cross-section AA showing the formation of a second isolation layer according to an exemplary embodiment.

[0075] Figure 22 This is a schematic diagram of an AA cross-section illustrating the formation of a gate oxide layer according to an exemplary embodiment.

[0076] Figure 23 This is a schematic diagram of an AA cross-section illustrating the formation of an initial word line layer according to an exemplary embodiment.

[0077] Figure 24 This is a schematic diagram of an AA cross-section of a character line according to an exemplary embodiment.

[0078] Figure 25 yes Figure 24 Top view.

[0079] Figure 26 This is a schematic diagram of cross-section AA showing the area where the deposited isolation material fills the fifth trench and the unfilled areas of the first and second trenches, according to an exemplary embodiment.

[0080] Figure 27 This is a schematic diagram of a cross-section AA showing the formation of a third isolation layer according to an exemplary embodiment.

[0081] Figure label:

[0082] 100, Substrate; 100a, Initial Substrate; 110, Base Layer; 120, First Doped Region; 120a, First Region; 140, Substrate; 150, Mask Layer; 101, First Trench; 102, Second Trench; 103, Third Trench; 104, Fourth Trench; 105, Fifth Trench; 200, Active Pillar; 210, First Pillar; 211, Peripheral Region; 220, Second Pillar; 221, First Part; 222, The... Two parts; 300, bit line; 310, first barrier layer; 310a, initial barrier layer; 320, bit line metal layer; 320a, initial bit line layer; 330, second barrier layer; 400, word line; 410, gate oxide layer; 420, word line metal layer; 420a, initial word line layer; 500, isolation structure; 510, first isolation layer; 520, second isolation layer; 530, third isolation layer; D1, first direction; D2, second direction. Detailed Implementation

[0083] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0084] The exemplary embodiments of this disclosure provide a method for fabricating a semiconductor structure, which applies the process of forming a gate all around to the bit line fabrication process. The formed bit line fully surrounds and covers part of the circumferential sidewall of the active pillar, which simplifies the bit line formation process, increases the contact area between the bit line and the active pillar, reduces the contact resistance between the bit line and the active pillar, and improves the electrical performance of the semiconductor structure.

[0085] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 1 As shown, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown below, in conjunction with... Figures 3 to 6 The method for fabricating the semiconductor structure in this embodiment will be described.

[0086] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, including the following steps:

[0087] Step S110: Provide a substrate.

[0088] like Figure 3 As shown, the substrate 100 can be a semiconductor substrate, and the material of the semiconductor substrate can include one or more of silicon (Si), germanium (Ge), silicon-germanium (GeSi), and silicon carbide (SiC); it can also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or it can include other materials, such as gallium arsenide or other III-V group compounds. Depending on the need, the semiconductor substrate can be doped with some impurity ions, which can be n-type or p-type impurity ions.

[0089] Step S120: Remove part of the substrate to form multiple active pillars, with any two adjacent active pillars in the first direction being separated.

[0090] like Figure 4 As shown, refer to Figure 3 Multiple active columns 200 are arranged in a matrix array or a parallelogram array, with adjacent active columns 200 spaced apart, and the multiple active columns 200 are arranged along the first direction D1 (see...). Figure 5 ,Right now Figure 4 The active pillars 200 are arranged in multiple columns (in the lateral direction of the substrate 100). In one example, multiple active pillars 200 have the same or different pillar structures. For example, along the thickness direction of the substrate 100 (i.e., along the lateral direction of the substrate 100) Figure 3 Along the thickness direction of the substrate 100, the active pillars 200 can be columnar structures that are wider at the top and narrower at the bottom, or narrower at the top and wider at the bottom, or columnar structures with equal width at both ends. In another example, the active pillars 200 may include multiple connected parts, each part may have the same or different dimensions. For example, along the thickness direction of the substrate 100, the active pillars 200 may include two or more pillars of different dimensions.

[0091] Step S130: Form a plurality of bit lines extending along a first direction, each bit line covering a portion of the sidewall of the bottom region of each active post located in its extension direction.

[0092] like Figure 6 As shown, refer to Figure 4 Bit line 300 extends along the first direction D1, in a direction perpendicular to the first direction D1 (i.e. Figure 5 In the second direction D2), adjacent bit lines 300 are spaced apart. The number of bit lines 300 corresponds one-to-one with the number of columns of active pillars 200 arranged along the first direction D1. Multiple bit lines 300 respectively cover a portion of the sidewall of multiple columns of active pillars 200 arranged along the first direction D1, and each bit line 300 covers a portion of the circumferential sidewall of each active pillar 200 located in its extending direction. That is, active pillars 200 located in the same column are connected in series by a bit line 300 covering the sidewall of the active pillar 200.

[0093] In the manufacturing method of the semiconductor structure in this embodiment, a bit line surrounding the circumferential sidewall of the active pillar is formed, the bit line covers part of the circumferential sidewall of the active pillar, which increases the contact area between the bit line and the active pillar, reduces the contact resistance between the bit line and the active pillar, and improves the electrical performance of the semiconductor structure.

[0094] According to an exemplary embodiment, this embodiment is a description of step S120 in the above embodiment, removing part of the substrate to form a plurality of active pillars, comprising:

[0095] Part of the substrate is removed to form a second pillar and a first pillar located above the second pillar and connected to the second pillar, wherein the peripheral area of the bottom surface of the first pillar is exposed outside the second pillar.

[0096] As shown in Figure 4 , Figure 5 , with reference to Figure 3 , in one example, the first pillar 210 may be formed before the second pillar 220 is formed. First, part of the substrate 100 is removed to form the first pillar 210, and then part of the substrate 100 under the first pillar 210 is etched to form the second pillar 220. In another example, the first pillar 210 and the second pillar 220 may be formed simultaneously. First, part of the substrate 100 is removed to form an initial pillar (not shown in the figure), the initial pillar is a cylindrical structure with equal width from top to bottom, then part of the circumferential structure at the bottom of the initial pillar is removed, the retained bottom of the initial pillar forms the second pillar 220, and the part of the initial pillar above the second pillar 220 forms the first pillar 210.

[0097] As shown in Figure 4 , the active pillar 200 comprises a coaxially arranged first pillar 210 and a second pillar 220, along the height direction of the active pillar 200, the second pillar 220 is located at the bottom of the first pillar 210. The bottom surface of the first pillar 210 covers the top surface of the second pillar 220, and the peripheral area 211 of the bottom surface of the first pillar 210 is exposed outside the second pillar 220. The active pillar 200 is an inverted "convex" shaped structure, that is, in any direction of the top surface of the second pillar 220, a predetermined distance is spaced between the edge of the top surface of the second pillar 220 and the edge of the bottom surface of the first pillar 210. In other words, for two adjacent active pillars 200, the spacing between the second pillars 220 is greater than the spacing between the first pillars 210.

[0098] In this embodiment, the active pillar is formed into an inverted "convex" shaped structure, the second pillar is located at the bottom of the first pillar and is inwardly contracted relative to the first pillar, and the outer periphery of the second pillar at the bottom of the first pillar serves as a space for forming the bit line, so that positioning can be performed by the edge of the first pillar during the bit line manufacturing process.

[0099] A manufacturing method of a semiconductor structure is provided in exemplary embodiments of the present disclosure, as Figure 2 As shown, Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown below, in conjunction with... Figures 7 to 27 The method for fabricating the semiconductor structure in this embodiment will be described.

[0100] like Figure 2 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, including the following steps:

[0101] Step S210: Provide a substrate, the substrate including a base layer and a first doped region formed on the base layer.

[0102] like Figure 8 As shown, the substrate 100 includes a base layer 110 and a first doped region 120 formed on the base layer 110. The first doped region 120 can be a p-type conductive doped region or an n-type conductive doped region.

[0103] In this embodiment, providing the substrate includes the following steps:

[0104] Step S211: Provide an initial substrate having a first conductivity type.

[0105] like Figure 7 As shown, the initial substrate 100a is a semiconductor substrate, and the material of the semiconductor substrate is the same as that in the above embodiment. The initial substrate 100a is doped with dopant ions of a first conductivity type, and the initial substrate 100a has a first conductivity type, which can be p-type or n-type.

[0106] Step S212: Doping conductive ions into a first region of the initial substrate to form a first doped region. The first doped region has a second conductivity type, which is the opposite of the first conductivity type.

[0107] like Figure 7 , Figure 8 As shown, dopant ions of a second conductivity type can be doped into the first region 120a by ion implantation or diffusion to form a first doped region 120 of the second conductivity type in the first region 120a, while the remaining portion of the initial substrate 100a forms a substrate layer 110. The second conductivity type is opposite in polarity to the first conductivity type; that is, if the initial substrate 100a has a p-type conductivity type, then the first doped region 120 has an n-type conductivity type; or, if the initial substrate 100a has an n-type conductivity type, then the first doped region 120 has a p-type conductivity type.

[0108] In this embodiment, the conductivity type of the substrate layer 110 is p-type and the conductivity type of the first doped region 120 is n-type.

[0109] Step S220: Remove a portion of the first doped region having the second conductivity type to form a first pillar.

[0110] like Figure 9 As shown, refer to Figure 7 , Figure 8 The step of forming the first pillar includes: forming a mask layer 150 on the top surface of the substrate 100, performing a first etching on the first region 120a according to the mask layer 150, the first etching can be dry etching, the depth of the first etching is less than the depth of the first doped region 120, and the retained part of the structure of the first doped region 120 forms a plurality of first pillars 210, the bottom surface of the first pillar 210 is higher than the bottom surface of the first doped region 120.

[0111] like Figure 9 , Figure 10 As shown, multiple first pillars 210 are arranged in multiple columns along a first direction D1, and multiple first pillars 210 are arranged in multiple rows along a second direction D2. The first direction D1 and the second direction D2 may intersect at acute, right, or obtuse angles. Any two adjacent first pillars 210 in the first direction D1 are separated by a first groove 101, and any two adjacent first pillars 210 in the second direction D2 are separated by a second groove 102.

[0112] In this embodiment, after the first pillar 210 is formed, the mask layer 150 is still retained to cover the first pillar 210 to prevent the first pillar 210 from being damaged by the process in subsequent processes.

[0113] Step S230: Continue to remove part of the first doped region and part of the initial substrate with the first conductivity type to form the second pillar.

[0114] In this embodiment, the step of forming the second pillar 220 includes: performing a second etching on the first region 120a and the initial substrate 110a based on the first trench 101 and the second trench 102 to form the second pillar 220 below the first pillar 210. The second pillar 220 includes a first portion 221 having a first conductivity type and a second portion 222 having a second conductivity type. The etching depth of the second etching is lower than the bottom surface of the first doped region 120.

[0115] like Figure 11 , Figure 12 As shown, refer to Figure 9 , Figure 10A second pillar 220 is formed below the first pillar 210 by a second etching. Any two adjacent second pillars 220 in the first direction D1 are separated by a third trench 103, the width of which is greater than the width of the first trench 101. Any two adjacent second pillars 220 in the second direction D2 are separated by a fourth trench 104, the width of which is greater than the width of the second trench 102.

[0116] In some embodiments, the second etching can be wet etching, for example, referring to... Figure 9 Etching solution can be injected into the first trench 101 and the second trench 102, dissolving the first doped region 120 and part of the substrate layer 110 beneath the first trench 101 and the second trench 102. The residence time of the etching solution in the first trench 101 and the second trench 102 can be controlled, referring to… Figure 11 A second column 220 is formed below the first column 210, and the distance between two adjacent second columns 220 is greater than the distance between two adjacent first columns 210.

[0117] In other embodiments, the second etching can be dry etching, see reference. Figure 9 Plasma etching is used to etch the first doped region 120 and a portion of the substrate layer 110 beneath the first trench 101 and the second trench 102. Simultaneously, a bias voltage is applied to the substrate 100 to ensure that the etching rate in the horizontal direction of the second etching is greater than that of the first etching in the horizontal direction. During the second etching process, plasma etching removes a portion of the first doped region 120 and a portion of the substrate layer 110 located beneath the first pillar 210. (Refer to...) Figure 11 The peripheral area 211 of the bottom surface of the first column 210 is exposed. A second column 220 is formed below the first column 210 and is coaxially arranged with the first column 210. In a top view, the first column 210 obscures the second column 220.

[0118] Reference Figure 11 , Figure 12 The portion of the base layer 110 that is preserved is etched to form a base layer 140. The second pillar 220 and the first pillar 210 located thereon together form an active pillar 200. Multiple active pillars 200 are independently disposed on the base layer 140. Multiple active pillars 200 are arranged in multiple columns along the first direction D1 and multiple active pillars 200 are arranged in multiple rows along the second direction D2.

[0119] Step S240: Form a first isolation layer that covers the top surface of the retained substrate and a portion of the sidewalls at the bottom of the second pillar.

[0120] like Figure 13 As shown, refer to Figure 11The first isolation layer 510 can be deposited using any of the following deposition processes: atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The first isolation layer 510 covers a portion of the sidewalls of the first portion 221 near the substrate and fills a portion of the third trench 103 and a portion of the fourth trench 104. The first isolation layer 510 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0121] In this embodiment, the first isolation layer 510 is located between the substrate 140 and the bit line 300. The substrate 140 is formed by etching the retained substrate 100 in a previous step, and the bit line 300 is formed in a subsequent step (described in detail later). The bit line 300 and the retained substrate 100 are electrically isolated by the first isolation layer 510 to prevent leakage between the bit line 300 and the retained substrate 100.

[0122] Step S250: Form a plurality of bit lines extending along a first direction, each bit line covering a portion of the sidewall of the bottom region of each active post located in its extension direction.

[0123] like Figure 19 As shown, refer to Figure 13 In this embodiment, bit line 300 covers the sidewall of the second portion 222 and the sidewall of the first portion 221 near the second portion 222, and the height of bit line 300 covering the first portion 221 is less than half the height of bit line 300.

[0124] In this embodiment, multiple bit lines extending along a first direction are formed, including:

[0125] Step S251: Form a first barrier layer that covers part of the sidewall of the second column and the exposed bottom surface of the first column.

[0126] When forming the first barrier layer 310, an atomic layer deposition process can be used to deposit a barrier material. The barrier material covers the top surface of the first isolation layer 510, the exposed sidewalls of the second pillar 220, the sidewalls of the first pillar 210, the exposed bottom surface of the first pillar 210, and the outer wall of the mask layer 150, forming an initial barrier layer 310a. The material of the initial barrier layer 310a may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0127] Then, a portion of the initial barrier layer 310a is removed. In this step, the etching rate of the barrier layer 310a in the vertical direction is greater than the etching rate in the horizontal direction. The initial barrier layer 310a covering the top surface of the first isolation layer 510 is removed, and the retained initial barrier layer 310a forms the first barrier layer 310. The first barrier layer 310 covers the exposed sidewalls of the second pillar 220, the sidewalls of the first pillar 210, and the exposed bottom surface of the first pillar 210.

[0128] In this embodiment, when forming the first barrier layer 310, the first pillar 210 is used to shield the second pillar 220, and an etching blind area is formed below the first pillar 210. By depositing an initial barrier layer 310a that covers the entire active pillar 200, and then etching the initial barrier layer 310a, it can be ensured that the initial barrier layer 310a located in the etching blind area will not be damaged by etching. This ensures that the initial barrier layer 310a located in the etching blind area can be completely preserved to form the first barrier layer 310, reducing the process difficulty of forming the first barrier layer 310.

[0129] Step S252: Deposit metallic material, which covers the first barrier layer and fills the trenches between the first barrier layers.

[0130] like Figure 16 As shown, refer to Figure 15 The metallic material can be deposited using any of the following deposition processes: atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The metallic material covers the first barrier layer 310 and at least fills the third trench 103 (see reference). Figure 12 ) and fourth trench 104 (refer to Figure 12 The unfilled portion. The metallic material includes one of titanium (Ti), tungsten (W), ruthenium (Ru), or a compound thereof.

[0131] Step S253: Remove the first barrier layer and metal material covering the sidewall of the first column.

[0132] like Figure 17 As shown, refer to Figure 12 , Figure 16 The metal material located in the first trench 101 and the second trench 102 can be removed by dry or wet etching. The retained metal material forms an initial bit line layer 320a. The top surface of the initial bit line layer 320a is lower than the top surface of the second pillar 220 and higher than the top surface of the first part 221, ensuring that the bit line 300 formed in this embodiment can be electrically connected to the second part 222.

[0133] Then, refer to Figure 19The first barrier layer 310 covering the sidewall of the first pillar 210 is removed by dry or wet etching. The retained first barrier layer 310 is disposed between the initial bit line layer 320a and the sidewall of the second pillar 220 to prevent metal material from diffusing into the second pillar 220 and contaminating the active pillar 200.

[0134] Step S254: Remove the metal material exposed by the second trench, and the retained metal material forms a bit line metal layer. The bit line metal layer and the first barrier layer form a bit line.

[0135] like Figure 18 , Figure 19 As shown, refer to Figure 12 , Figure 17 Removing the metal material exposed by the second trench 102 includes: forming a bit line mask that extends along a first direction D1. The projection of the bit line mask onto the substrate 140 falls between the projections of adjacent second trenches 102 onto the substrate 140, and the projection of the bit line mask onto the substrate 140 covers the projections of a plurality of first pillars 210 located in its extending direction onto the substrate 140. In this embodiment, when forming the bit line mask, alignment can be performed based on the edges of the first pillars 210 located in its extending direction, improving the process accuracy of forming the bit line 300.

[0136] Then, the initial bit line layer 320a exposed by the second trench 102 is removed by bit line mask etching to form a plurality of bit line metal layers 320 extending along the first direction D1, with the edge of each bit line metal layer 320 being flush with the edge of the first pillar 210 located in its extension direction.

[0137] like Figure 19 As shown, each bit line metal layer 320 forms a bit line 300 with a first barrier layer 310 covering its sidewalls and top surface. In this embodiment, the bit lines 300 form around the second pillar 220 (see reference). Figure 11 The peripheral area 211 of the part of the circumferential sidewall and the bottom surface of the first column 210 is covered, which increases the contact area between the bit line 300 and the active column 200.

[0138] In some embodiments, forming a plurality of bit lines extending along a first direction further includes:

[0139] Step S255: Form a second barrier layer, covering the exposed top surface and sidewalls of the second cover bit line.

[0140] like Figure 20 As shown, refer to Figure 19 The second barrier layer 330 can be deposited using an atomic layer deposition process. The second barrier layer 330 covers the exposed sidewalls and top surface of the bit line 300. The material of the second barrier layer 330 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0141] In this embodiment, the second barrier layer 330 and the first barrier layer 310 retained in the above steps are connected as a single unit. The second barrier layer 330 and the retained first barrier layer 310 separate the bit line 300 and the active pillar 200, achieving a better isolation effect to prevent the material of the bit line from diffusing into the material of the active pillar 200 and causing contamination during the application of the formed semiconductor structure.

[0142] Compared to the structure of active pillars with equal width at the top and bottom, the fabrication method in this embodiment eliminates the need to form a new photomask during the etching of the initial bit line layer. Multiple independent bit lines can be etched by aligning and positioning the bit lines along the edge of the first pillar. Furthermore, the spacing between adjacent bit lines is equal to the width of the second trench, preventing short circuits caused by insufficient spacing between adjacent bit lines after multiple electrical conductions in the semiconductor structure. Simultaneously, the bit lines formed in this embodiment surround and cover part of the circumferential sidewall of the second pillar, increasing the contact area between the bit lines and the active pillar, reducing the contact resistance between the bit lines and the active pillar, and improving the conductivity of the semiconductor structure.

[0143] According to an exemplary embodiment, this embodiment is a description of the above embodiments. The method for fabricating the semiconductor structure in this embodiment further includes the following steps:

[0144] Step S260: Form a second isolation layer, the second isolation layer fills the gap between adjacent bit lines, and the top surface of the second isolation layer is higher than the top surface of the bit line.

[0145] like Figure 21 As shown, refer to Figure 20 A second isolation layer 520 can be deposited using any of the following deposition processes: atomic layer deposition, chemical vapor deposition, or physical vapor deposition. The second isolation layer 520 then fills the third trench 103 (see reference). Figure 12 ) and fourth trench 104 (refer to Figure 12 For the unfilled portion, the top surface of the second insulating layer 520 is higher than the bottom surface of the first pillar 210. The second insulating layer 520 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0146] Step S270: Form multiple word lines extending along the second direction. The multiple word lines are disposed on the second isolation layer. Each word line covers a portion of the sidewall of each active post located in its extension direction. The top surface of the word line is lower than the top surface of the active post.

[0147] In this embodiment, forming multiple word lines 400 extending along the second direction includes the following steps:

[0148] like Figure 22 As shown, refer to Figure 21A gate oxide layer 410 is formed using an atomic layer deposition process. The gate oxide layer 410 covers the exposed sidewalls of the first pillar 210 and the outer surface of the mask layer 150. The material of the gate oxide layer 410 may include at least one of silicon oxide or silicon oxynitride.

[0149] Then, conductive metal is deposited by chemical vapor deposition, physical vapor deposition, or sputtering. The conductive metal covers the gate oxide layer 410 and fills the first trench 101 (see reference). Figure 12 ) and second trench 102 (refer to Figure 12 ).

[0150] Next, as Figure 23 As shown, refer to Figure 22 The top surface of the conductive metal is etched back to a point below the top surface of the first pillar 210 to form the initial word line layer 420a. In this embodiment, the etching selection ratio of the conductive metal and the gate oxide layer 410 is 1:1, that is, the gate oxide layer 410 and the conductive metal are etched at the same rate, and the gate oxide layer 410 is also etched to a point where its top surface is below the top surface of the first pillar 210.

[0151] Next, as Figure 24 , Figure 25 As shown, refer to Figure 23 A portion of the initial word line layer 420a is etched away, and a fifth trench 105 extending along the second direction D2 is formed in each first trench 101. The fifth trench 105 exposes the top surface of the second isolation layer 520. The fifth trench 105 divides the retained initial word line layer 420a into multiple word line metal layers 420 extending along the second direction D2. The word line metal layers 420 and the gate oxide layer 410 located between them and the first pillar 210 form word lines 400. That is, each word line 400 covers a portion of the sidewall of each first pillar 210 located in its extending direction.

[0152] Step S280: Form a third isolation layer. The third isolation layer fills the gaps between adjacent word lines and covers the word lines. The top surface of the third isolation layer is flush with the top surface of the active pillar.

[0153] In this embodiment, forming the third isolation layer 530 includes: as follows Figure 26 As shown, refer to Figure 24 The deposited isolation material fills the unfilled portions of the fifth trench 105, the first trench 101, and the second trench 102, and also covers the mask layer 150. Then, as... Figure 27 As shown, refer to Figure 26 The isolation material is etched and the mask layer 150 is removed to expose the top surface of the first pillar 210. The remaining isolation material forms the third isolation layer 530.

[0154] like Figure 27As shown, the first isolation layer 510, the second isolation layer 520 and the third isolation layer 530 together form an isolation structure 500. The adjacent word lines 400, adjacent bit lines 300, bit lines 300 and word lines 400 and adjacent active pillars 200 in the semiconductor structure are electrically isolated by the isolation structure 500.

[0155] The fabrication method of this embodiment applies the process of forming a fully encircling gate to the bit line process. The semiconductor structure formed in this embodiment not only has word lines surrounding the first pillar of the active pillar, increasing the contact area between word lines and active pillars, but also bit lines surrounding the second pillar of the active pillar, increasing the contact area between bit lines and active pillars, further reducing the contact resistance of the semiconductor structure and optimizing the electrical performance of the semiconductor structure.

[0156] According to an exemplary embodiment, a semiconductor structure, such as Figure 27 As shown, refer to Figure 25 The semiconductor structure includes: a substrate 140, a plurality of active pillars 200 disposed on the substrate 140, and a plurality of bit lines 300 extending along a first direction D1. Any two adjacent active pillars 200 in the first direction D1 are separated, and each bit line 300 covers a portion of the sidewall of the bottom region of each active pillar 200 located in its extension direction.

[0157] In some embodiments, such as Figure 27 As shown, refer to Figure 11 , Figure 12 The active column 200 includes a second column 220 disposed on the base 140 and a first column 210 located above the second column 220. The first column 210 is connected to the second column 220, and the peripheral area 211 of the bottom surface of the first column 210 is exposed outside the second column 220.

[0158] In some embodiments, such as Figure 27 As shown, refer to Figure 25 The bit line 300 includes a first barrier layer 310 and a bit line metal layer 320. The first barrier layer 310 covers part of the sidewall of the second pillar 220 and the peripheral area 211 of the bottom surface of the first pillar 210. The bit line metal layer 320 covers the first barrier layer 310 and extends along the first direction D1.

[0159] In some embodiments, such as Figure 27 As shown, refer to Figure 11 The substrate 140 has a first conductivity type, the first pillar 210 has a second conductivity type, the first conductivity type and the second conductivity type are opposite, the second pillar 220 includes a first portion 221 connected to the substrate 140 and a second portion 222 connected to the first pillar 210, the first portion 221 has the first conductivity type, and the second portion 222 has the second conductivity type.

[0160] like Figure 27 As shown, refer to Figure 11 Bit line 300 covers the sidewall of the second part 222 and the sidewall of the first part 221 near the second part 220. The height of the bit line 300 covering the first part 222 is less than half the height of the bit line 300.

[0161] In some embodiments, such as Figure 27 As shown, refer to Figure 25 In the second direction D2, any two adjacent active pillars 200 are separated. The semiconductor structure also includes multiple word lines 400 extending along the second direction D2. The multiple word lines 400 are disposed above the multiple bit lines 300. Each word line 400 covers a portion of the sidewall of each active pillar 200 located in its extending direction, and the top surface of the word line is lower than the top surface of the active pillar 200. In this embodiment, each word line 400 covers a portion of the sidewall of each first pillar 210 located in its extending direction.

[0162] In some embodiments, such as Figure 27 As shown, the semiconductor structure also includes an isolation structure 500, which fills the gaps between adjacent bit lines 300, adjacent word lines 400, adjacent active pillars 200, and between word lines 400 and bit lines 300.

[0163] In this embodiment, the circumferential sidewalls of the bit lines and active pillars of the semiconductor structure are in contact, which increases the contact area between the bit lines and the active pillars, reduces the internal resistance of the semiconductor structure, and improves the electrical performance of the semiconductor structure.

[0164] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0165] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0166] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. It is understood that the terms "first," "second," etc., used in this disclosure can be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0167] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0168] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: Providing a substrate includes: providing an initial substrate having a first conductivity type; doping a first region of the initial substrate with conductive ions to form a first doped region having a second conductivity type, the second conductivity type being opposite to the first conductivity type; The process involves removing a portion of the substrate to form a plurality of active pillars, wherein any two adjacent active pillars in a first direction are separated; the process includes: performing a first etching on the first region to remove a portion of the first doped region having a second conductivity type, forming a plurality of first pillars, wherein any two adjacent first pillars in the first direction are separated by a first trench, and any two adjacent first pillars in a second direction are separated by a second trench, wherein the bottom surface of the first pillar is higher than the bottom surface of the first doped region; performing a second etching on the first region and the initial substrate based on the first trench and the second trench to further remove a portion of the first doped region and a portion of the initial substrate having a first conductivity type, forming a second pillar below the first pillars, wherein the second pillar includes a first portion having the first conductivity type and a second portion having the second conductivity type; the first pillar is connected to the second pillar, and the peripheral region of the bottom surface of the first pillar is exposed outside the second pillar; Multiple bit lines are formed extending along the first direction, each bit line covering a portion of the sidewall of the bottom region of each active post located in its extending direction.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The formation of multiple bit lines extending along the first direction includes: A first barrier layer is formed, which covers part of the sidewall of the second column and the exposed bottom surface of the first column; A metallic material is deposited, which covers the first barrier layer and fills the trenches between the first barrier layers; The metal material exposed by the second trench is removed, and the retained metal material forms a bit line metal layer, which, together with the first barrier layer, forms the bit line.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The bit line covers the sidewall of the second portion and the sidewall of the first portion near the second portion; The height of the bit line covering the first portion is less than half the height of the bit line.

4. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The manufacturing method further includes: A first isolation layer is formed between the top surface of the retained substrate and the bit line, and the first isolation layer covers a portion of the sidewall of the first portion near the substrate.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, In the second direction, any two adjacent active pillars are separated, and the manufacturing method further includes: A second isolation layer is formed, which fills the gap between adjacent bit lines, and the top surface of the second isolation layer is higher than the top surface of the bit line; Multiple word lines extending along the second direction are formed, and the multiple word lines are disposed on the second isolation layer. Each word line covers a portion of the sidewall of each active post located in its extension direction, and the top surface of the word line is lower than the top surface of the active post. A third isolation layer is formed, which fills the gap between adjacent word lines and covers the word lines, and the top surface of the third isolation layer is flush with the top surface of the active post.

6. A semiconductor structure, characterized in that, The semiconductor structure includes: Base; Multiple active columns are disposed on the base, and any two adjacent active columns in a first direction are separated; each active column includes: a second column disposed on the base; and a first column located above and connected to the second column, wherein the peripheral area of ​​the bottom surface of the first column is located outside the second column. Multiple bit lines extending along a first direction, each bit line covering a portion of the sidewall of the bottom region of each of the active pillars located in its extending direction; The substrate has a first conductivity type, the first column has a second conductivity type, the first conductivity type and the second conductivity type are opposite, and the second column includes: a first part, the first part being connected to the substrate and having the first conductivity type; and a second part, the second part being connected to the first column and having the second conductivity type.

7. The semiconductor structure according to claim 6, characterized in that, The bit line includes: A first barrier layer covers part of the sidewall of the second column and the peripheral area of ​​the bottom surface of the first column; Bit line metal layer, the bit line metal layer covering the first barrier layer.

8. The semiconductor structure according to claim 6, characterized in that, The bit line covers the sidewall of the second part and a portion of the sidewall of the first part near the second part; The height of the bit line covering the first portion is less than half the height of the bit line.

9. The semiconductor structure according to claim 6, characterized in that, In the second direction, any two adjacent active pillars are separated, and the semiconductor structure further includes: Multiple word lines extending along the second direction are disposed above the multiple bit lines. Each word line covers a portion of the sidewall of each active post located in its extension direction, and the top surface of the word line is lower than the top surface of the active post.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure also includes: An isolation structure that fills the gaps between adjacent bit lines, between adjacent word lines, between adjacent active pillars, and between word lines and bit lines.

Images