Semiconductor chip and semiconductor package comprising the same

Abstract

A semiconductor chip and a semiconductor package including the same are provided. The semiconductor chip includes a chip body including a signal input / output circuit unit, a chip pad unit arranged on one surface of the chip body and including a first chip pad and a second chip pad having different surface areas from each other, and a chip pad selection circuit unit arranged in the chip body and electrically connected with the signal input / output circuit unit and the chip pad unit. The chip pad selection circuit unit is configured to select one chip pad of the first chip pad and the second chip pad and electrically connect the selected one chip pad with the signal input / output circuit unit.

Description

Technical Field

[0001] This disclosure relates generally to packaging technology, and more specifically to semiconductor chips with chip pads having different surface areas and semiconductor packages including the semiconductor chips. Background Technology

[0002] Today, the semiconductor industry is moving towards manufacturing lightweight, compact, high-speed, multifunctional, high-performance, and high-reliability semiconductor products at low cost, and semiconductor packaging technology is a crucial part of achieving this goal. Semiconductor packaging technology refers to the techniques used to mount semiconductor chips, which have circuitry formed through wafer fabrication processes, onto a packaging substrate. The packaging substrate secures the electrical connection between the semiconductor chip and external electronic devices and protects the semiconductor chip from external environmental influences. Techniques for mounting semiconductor chips on packaging substrates include wiring and bonding methods between the semiconductor chip and the packaging substrate, and flip-chip bonding methods. Summary of the Invention

[0003] A semiconductor chip according to embodiments of the present disclosure may include: a chip body including a signal input / output circuit unit; a chip pad unit disposed on one surface of the chip body and including a first chip pad and a second chip pad having different surface areas; and a chip pad selection circuit unit disposed in the chip body and electrically connected to the signal input / output circuit unit and the chip pad unit. The chip pad selection circuit unit may be configured to select one of the first chip pad and the second chip pad and electrically connect the selected chip pad to the signal input / output circuit unit.

[0004] A semiconductor package according to another embodiment of the present disclosure may include a package substrate and a semiconductor chip disposed on the package substrate. The package substrate may include a substrate body and a plurality of chip connection pads disposed on a surface of the substrate body. The semiconductor chip may include a chip body and a plurality of chip pad units disposed on a surface of the chip body, the surface of the chip body facing the surface of the substrate body, and the plurality of chip pad units corresponding to the plurality of chip connection pads. Each of the plurality of chip pad units may include a first chip pad and a second chip pad arranged spaced apart from each other and having different surface areas. One of the first chip pads and the second chip pads may be electrically connected to a corresponding chip connection pad among the plurality of chip connection pads.

[0005] A semiconductor package according to another embodiment of this disclosure may include: a package substrate including a substrate body having an upper surface and a lower surface; and a semiconductor chip mounted above the upper surface of the substrate body. The package substrate may include a plurality of chip connection pads disposed on the upper surface of the substrate body and arranged in one direction. The semiconductor chip may include: a chip body including a signal input / output circuit unit; a plurality of chip pad units disposed on a surface of the chip body, the surface of the chip body facing the surface of the substrate body, and the plurality of chip pad units corresponding to the plurality of chip connection pads; and a chip pad selection circuit unit connected to the signal input / output circuit unit and the plurality of chip pad units. Each of the plurality of chip pad units may include a first chip pad and a second chip pad arranged spaced apart from each other and having different surface areas. One of the first chip pads and the second chip pads may be electrically connected to a corresponding chip connection pad among the plurality of chip connection pads. Attached Figure Description

[0006] Figure 1 This is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0007] Figure 2 This is a schematic plan view of a packaging substrate according to an embodiment of the present disclosure.

[0008] Figure 3 This is a schematic plan view of a semiconductor chip according to an embodiment of the present disclosure.

[0009] Figure 4 This is a schematic view illustrating the parasitic capacitance generated by the chip pads of a semiconductor chip according to an embodiment of the present disclosure.

[0010] Figure 5 This is a circuit diagram of a chip pad selection circuit unit of a semiconductor chip according to an embodiment of the present disclosure.

[0011] Figure 6 This is a schematic plan view of a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of elements (e.g., the width and thickness of elements) are enlarged to clearly illustrate the components of each device. The terms used herein may correspond to words chosen with consideration for their function in the embodiments, and the meaning of these terms may be interpreted differently by one of ordinary skill in the art to which the embodiments pertain. Where there are explicit and detailed definitions, these terms may be interpreted according to those definitions. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain.

[0013] Furthermore, unless explicitly used in a different form in the context, the singular form of a word should be understood to include the plural form of that word. It is understood that the terms “comprising,” “including,” or “having” are intended to specify the presence of a feature, quantity, step, operation, component, element, part, or combination thereof, but do not preclude the presence or possibility of adding one or more other features, quantities, steps, operations, components, elements, parts, or combinations thereof.

[0014] In this specification, the phrase "predetermined direction" can refer to a direction that includes a direction defined in a coordinate system and a direction opposite to that direction. As an example, in the xyz coordinate system, the x-direction can include directions parallel to the x-direction. That is, the x-direction can refer to all directions in which the absolute value of the x-axis increases positively along the x-axis from the origin 0 and in which the absolute value of the x-axis increases negatively along the x-axis from the origin 0. Each of the y-direction and z-direction can be interpreted in substantially the same way in the xyz coordinate system.

[0015] In this specification, in addition to the direct bonding of one component to another, bonding between one component and another can include indirect bonding by inserting an intermediate material between the two components. As an example, bonding between the chip connection pads of the package substrate and the chip pads of the semiconductor chip can refer not only to the direct bonding of the chip connection pads and the chip pads, but also to the insertion of bonding materials such as bumps or solder between the chip connection pads and the chip pads so that the chip connection pads and the chip pads can bond to each other.

[0016] Figure 1 This is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present disclosure. (See also...) Figure 1 The semiconductor package 1 may include: a package substrate 10; and a semiconductor chip 20 disposed on the package substrate 10. The package substrate 10 and the semiconductor chip 20 may be joined together by means of a conductive connector 230. For example, the conductive connector 230 may include bumps.

[0017] The packaging substrate 10 may include a substrate body 110 having an upper surface 110S1 and a lower surface 110S2. The packaging substrate 10 may include chip connection pads 120 disposed on the upper surface 110S1. The packaging substrate 10 may include a plurality of connection pads 130 disposed spaced apart from the chip connection pads 120. In one embodiment, the plurality of connection pads 130 may be disposed on the lower surface 110S2 of the substrate body 110. The packaging substrate 10 may include a plurality of connection structures 140 respectively disposed on the plurality of connection pads 130. The plurality of connection structures 140 may include, for example, bumps or solder beads. For example, the plurality of connection structures 140 may be configured to electrically connect to other semiconductor packages or other electronic systems.

[0018] although Figure 1 Not shown in the diagram, but in an embodiment, the chip bonding pads 120 may be arranged along a direction (e.g., the y-direction) on the upper surface 110S1 of the substrate body 110. This will be discussed later. Figure 2 The arrangement of multiple chip connection pads 120 is described. Furthermore, the connection pads 130 may be arranged along one direction (e.g., the y-direction) on the lower surface 110S2 of the substrate body 110. This will be discussed later. Figure 2 The arrangement of multiple connection pads 130 is described below. For ease of description, when two distinct connection pads are selected from the multiple connection pads 130, the two selected connection pads are referred to as the first connection pad 130a and the second connection pad 130b, respectively. In this case, among the multiple connection structures 140, the connection structure contacting the first connection pad 130a can be referred to as the first connection structure 140a, and the connection structure contacting the second connection pad 130b can be referred to as the second connection structure 140b.

[0019] Reference Figure 1 Multiple wirings 150 can be arranged on / in the substrate body 110. A first wiring 150a of the multiple wirings 150 can electrically connect a first connection structure 140a to a corresponding chip connection pad 120. A second wiring 150b of the multiple wirings 150 can electrically connect a second connection structure 140b to... Figure 1 Other chip connection pads 120 are not shown in the diagram.

[0020] In this embodiment, the first wiring 150a and the second wiring 150b may have different lengths. Therefore, when an electrical signal is transmitted along the first wiring 150a and the second wiring 150b, different parasitic capacitances may be generated in the first wiring 150a and the second wiring 150b due to the different wiring lengths. (Refer to...) Figure 1The first wiring 150a and the second wiring 150b may include a first outer layer circuit a1 and a second outer layer circuit b1 respectively disposed on the upper surface 110S1 of the substrate body 110. Each of the first outer layer circuit a1 and the second outer layer circuit b1 may have various shapes and lengths. Figure 1 As shown, the first outer layer circuit a1 and the second outer layer circuit b1 can have different path lengths. Therefore, when an electrical signal is transmitted along the first outer layer circuit a1 and the second outer layer circuit b1, different parasitic capacitances can be generated along the first outer layer circuit a1 and the second outer layer circuit b1 based on their different lengths. Furthermore, the first wiring 150a and the second wiring 150b can each include a first via a2 and a second via b2, which connect the first outer layer circuit a1 and the second outer layer circuit b1 to the first connection pad 130a and the second connection pad 130b, respectively. Figure 1 As shown, the first through hole a2 and the second through hole b2 can have the same path length.

[0021] exist Figure 1 In some embodiments not shown, the configuration of the plurality of wirings 150 can vary. As an example, each of the plurality of wirings 150 may further include at least one inner layer circuit within the substrate body 110. The at least one inner layer circuit may be electrically connected to the outer layer circuit and connection pads via at least one via. In this case, the magnitude of the parasitic capacitance generated in each of the plurality of wirings 150 may vary depending on the sum of the lengths of the outer and inner layer circuits.

[0022] Reference Figure 1 The semiconductor chip 20 may include: a chip body 210 having a first surface 210S1 and a second surface 210S2; and chip pad units 220 disposed on the first surface 210S1. The chip body 210 may include an internal integrated circuit. In an embodiment, the internal integrated circuit may be disposed in an internal region of the chip body 210 adjacent to the first surface 210S1. Although in Figure 1 Although not shown, the chip body 210 may include signal input / output circuitry units electrically connected to an internal integrated circuit. The internal integrated circuit can process electrical signals using various methods. The electrical signals processed in the internal integrated circuit can be transmitted to the signal input / output circuitry and can reach the chip pad units 220 on the first surface 210S1. Furthermore, electrical signals input from the package substrate 10 through the chip pad units 220 can pass through the signal input / output circuitry units and can be transmitted to the internal integrated circuitry in the chip body 210. (Referring later...) Figure 5 Describes the electrical signal transmission between the signal input / output circuit unit and the chip pad unit 220.

[0023] Chip pad units 220 on the first surface 210S1 can be arranged to correspond to chip connection pads 120 on the upper surface 110S1 of the substrate body 110. Each of the chip pad units 220 may include a first chip pad 220a and a second chip pad 220b, which are arranged spaced apart from each other on the first surface 210S1. The first chip pad 220a and the second chip pad 220b may have different surface areas on the first surface 210S1. One of the chip pads 220a and 220b can be bonded to the corresponding chip connection pad 120 by means of a conductive connector 230. (Referring later...) Figure 6 The method describes a method for determining one of the first chip pads 220a and the second chip pad 220b to be coupled to the chip connection pad 120.

[0024] The chip pad to be bonded to chip connection pad 120 can act as a bonding pad. Signal input / output circuit units can be electrically connected to the chip connection pad 120 of the package substrate 10 via the bonding pad. (Refer to...) Figure 1 The second chip pad 220b can serve as a bonding pad. The other chip pad, which is not bonded to the chip connection pad 120, between the first chip pad 220a and the second chip pad 220b, can serve as a test pad for testing the internal integrated circuits of the semiconductor chip 20. This test pad can also serve as a connection pad for connecting electrical test instruments to the internal integrated circuits of the semiconductor chip 20. In this embodiment, electrical testing using the test pads can be performed before the semiconductor chip 20 is mounted on the package substrate 10.

[0025] although Figure 1 Not shown, but a chip pad selection circuit unit may be arranged in the chip body 210. The chip pad selection circuit unit is electrically connected to the first chip pad 220a, the second chip pad 220b, and the signal input / output circuit unit, respectively. The chip pad selection circuit unit can be configured to select one of a bonding pad and a test pad (i.e., one of the first chip pad 220a and the second chip pad 220b) and electrically connect the selected pad to the signal input / output circuit unit. This will be discussed later. Figure 5 Describe the detailed structure of the chip pad selection circuit unit.

[0026] Despite Figure 1 Not shown, but chip pad units 220 can be arranged along a direction (e.g., the y-direction) on the first surface 210S1 of the chip body 210. Each of the first chip pad 220a and the second chip pad 220b can be arranged along a direction. (See below for further details.) Figure 3Describes the arrangement of multiple chip pad units 220.

[0027] Figure 2 This is a schematic plan view of a packaging substrate according to an embodiment of the present disclosure. Figure 2 It can be Figure 1 The diagram shows a plan view of the packaging substrate 10 of the semiconductor package 1.

[0028] Reference Figure 2 Multiple chip connection pads 120 can be arranged along a first direction (e.g., the y-direction) on the upper surface 110S1 of the substrate body 110. In one embodiment, the multiple chip connection pads 120 can be arranged to form a row L1 along the first direction. Multiple connection pads 130 can be arranged on the lower surface 110S2 of the substrate body 110. Although in Figure 2 Not shown in the diagram, but the connection structure ( Figure 1 The 140s can be respectively arranged on the corresponding connection pads 130. As an example, such as Figure 1 As shown, the first connection structure 140a can be arranged on the first connection pad 130a, and the second connection structure 140b can be arranged on the second connection pad 130b.

[0029] Refer to together Figure 1 and Figure 2 In an embodiment, each first connection structure 140a on the first connection pad 130a can be electrically connected to a corresponding chip connection pad among the plurality of chip connection pads 120 via a first wiring 150a. Each second connection structure 140b on the second connection pad 130b can be electrically connected to a corresponding chip connection pad among the plurality of chip connection pads 120 via a second wiring 150b. The first wiring 150a and the second wiring 150b can have corresponding first outer layer circuits a1 and second outer layer circuits b1. Figure 1 and Figure 2 As shown, the first outer layer circuit a1 and the second outer layer circuit b1 can have different path lengths. In an embodiment, each first connection pad 130a and each second connection pad 130b can be arranged adjacent to each other. Therefore, each first connection structure 140a and each second connection structure 140b can be arranged adjacent to each other. However, this teaching is not limited to this, and the arrangement of the first connection pads 130a and the second connection pads 130b can be determined by the design of the package substrate 10. This design can include various arrangements according to the function and purpose of the semiconductor package 1, such as connection pads 130, connection structures 140, and wiring 150. Although Figure 2 Not shown, but all the connection pads 130 can be connected to the corresponding chip connection pads 120 in the same way via the outer layer circuitry on the upper surface 110S1.

[0030] Refer to together Figure 1 and Figure 2 Multiple wirings 150 can be arranged to connect each of the multiple connection structures 140 to a corresponding chip connection pad 120. Figure 2 For ease of description, a first wiring 150a and a second wiring 150b are shown as embodiments of a plurality of wirings 150. The first wiring 150a may have a first outer layer circuit a1 located on the upper surface 110S1, and the second wiring 150b may have a second outer layer circuit b1 located on the upper surface 110S1. In embodiments, the length of each of the plurality of wirings 150 may be different. As the length of the wirings 150 decreases, the parasitic capacitance of the semiconductor package 1 generated by the wirings 150 on the substrate body 110 can be reduced.

[0031] In an implementation, the length of the first outer circuit a1 may be shorter than the length of the second outer circuit b1. For example... Figure 1 As shown, when the first via a2 and the second via b2 have the same path length, the length of the first wiring 150a with the first outer layer circuit a1 may be shorter than the length of the second wiring 150b with the second outer layer circuit b1. In this case, the parasitic capacitance generated by the first wiring 150a may be smaller than the parasitic capacitance generated by the second wiring 150b. Hereinafter, the parasitic capacitance generated by the aforementioned wiring is referred to as "package parasitic capacitance".

[0032] In embodiments of this disclosure, a configuration is provided to compensate for differences in package parasitic capacitance caused by variations in the length of multiple wirings 150. These differences in package parasitic capacitance arise from the multiple wirings 150 connected to multiple chip connection pads 120. See below. Figure 3 Each chip connection pad 120, which is respectively connected to the first wiring 150a and the second wiring 150b, is connected to one of the first chip pad 220a and the second chip pad 220b, which have different surface areas, to compensate for the difference in parasitic capacitance of the package.

[0033] Figure 3 This is a schematic plan view of a semiconductor chip according to an embodiment of the present disclosure. Figure 3 It can be Figure 1 The semiconductor chip 20 of the semiconductor package 1 is shown in the figure.

[0034] Reference Figure 3 Multiple chip pad units 220 can be arranged on the first surface 210S1 of the chip body 210. The multiple chip pad units 220 can be arranged along a first direction (e.g., the y-direction). As an embodiment, the multiple chip pad units 220 can be arranged to form a column L0 along the first direction.

[0035] Each of the plurality of chip pad units 220 can be arranged spaced apart from each other and includes a first chip pad 220a and a second chip pad 220b having different surface areas from each other. In the embodiment, and as... Figure 3 As shown, the first chip pad 220a may have a smaller surface area than the second chip pad 220b.

[0036] Reference Figure 3 Multiple first chip pads 220a can be arranged in a column along a first direction. Multiple second chip pads 220b can be arranged spaced apart from the multiple first chip pads 220a and in a column along the first direction.

[0037] Figure 4 This is a schematic view illustrating the parasitic capacitance generated by the chip pads of a semiconductor chip according to an embodiment of the present disclosure. Figure 4 The chip pads 320, internal circuit layer 340 and interlayer dielectric layer 330 arranged on one surface of a semiconductor chip are schematically shown.

[0038] Chip pads 320 and internal circuit layers 340 are conductive layers, and an interlayer dielectric layer 330 can be interposed between chip pads 320 and internal circuit layers 340. The parasitic capacitance generated between chip pads 320 and internal circuit layers 340 is proportional to the product w*l of the dielectric constant of the interlayer dielectric layer 330 and the surface area representing chip pads 320, and inversely proportional to the thickness d of the interlayer dielectric layer 330. Therefore, as the surface area of ​​chip pads 320 decreases, the parasitic capacitance generated between chip pads 320 and internal circuit layers 340 can be reduced. In the following text, the parasitic capacitance generated between chip pads on a semiconductor chip and internal circuit layers in a semiconductor chip is referred to as "pad parasitic capacitance".

[0039] Refer to together Figure 3 and Figure 4 When the chip pad with the smaller surface area among the first chip pad 220a and the second chip pad 220b is electrically connected to the corresponding chip connection pad 120, the parasitic capacitance of the pad in the semiconductor package 1 may be relatively small. On the other hand, when the chip pad with the larger surface area among the first chip pad 220a and the second chip pad 220b is connected to the corresponding chip connection pad 120, the parasitic capacitance of the pad in the semiconductor package 1 may be relatively large. That is, each of the first chip pad 220a and the second chip pad 220b may exhibit or have a parasitic capacitance proportional to the surface area of ​​the first chip pad 220a and the second chip pad 220b.

[0040] Figure 5This is a circuit diagram of a chip pad selection circuit unit for a semiconductor chip according to an embodiment of the present disclosure. (Refer to...) Figure 5 The chip pad selection circuit unit 240 can be arranged in Figure 1 and Figure 3 In the semiconductor chip 20 of the semiconductor package 1.

[0041] Reference Figure 5 The chip pad selection circuit unit 240 can be connected with... Figure 3 The signal input / output circuit unit 201 and the chip pad unit 220 in the chip body 210 are connected. The signal input / output circuit unit 201 can be connected to the internal integrated circuit of the semiconductor chip 20. In an embodiment, a chip pad selection circuit unit 240 can be arranged between the signal input / output circuit unit 201 and the chip pad unit 220 in the chip body 210. The chip pad selection circuit unit 240 can be arranged inside the chip body 210. The chip pad selection circuit unit 240 can select one of two chip pads 220a and 220b and connect the selected chip pad to the signal input / output circuit unit 201. The chip pad selection circuit unit 240 can select one of two chip pads 220a and 220b and connect the selected chip pad to the signal input / output circuit unit 201. Figure 3 Each of the multiple chip pad units 220 in the process plays a role.

[0042] The chip pad selection circuit unit 240 can be configured to select a chip pad between the first chip pad 220a and the second chip pad 220b and electrically connect the selected chip pad to the signal input / output circuit 201. As an embodiment, the chip pad selection circuit unit 240 can be configured to electrically connect the selected chip pad to the signal input / output circuit unit 201 and electrically disconnect the other unselected chip pad between the first chip pad 220a and the second chip pad 220b from the signal input / output circuit unit 201. In an implementation, when performing electrical testing on the internal integrated circuit, the chip pad selection circuit unit 240 can electrically connect one of the first chip pads 220a and the second chip pad 220b to set it as a test pad. When the internal integrated circuit is electrically connected to the package substrate, the chip pad selection circuit unit 240 can electrically connect the other chip pad between the first chip pad 220a and the second chip pad 220b to set it as a bonding pad.

[0043] In the following text, reference will be made to Figure 5The method of operating the chip pad selection circuit unit 240 is schematically described. First, signal information S is transmitted from the signal input / output circuit unit 201 to the input buffer 410 of the chip pad selection circuit unit 240. The input buffer 410 transmits the signal information S to the first transfer transistor 430 and the second transfer transistor 440. In this case, a separate control signal OPT can be input to the input terminal of the inverter 420 connected to each of the first transfer transistor 430 and the second transfer transistor 440. The control signal OPT is either a "high" signal or a "low" signal. The "high" signal and the "low" signal are distinguishable. For example, the "high" signal has a higher voltage than the "low" signal. The "high" signal can turn on the NMOS transistor in the chip pad selection circuit unit 240, and the "low" signal can turn on the PMOS transistor in the chip pad selection circuit unit 240.

[0044] When the control signal OPT is "high", the inverted control signal OPTB output from inverter 420 can turn on the first transmission transistor 430, and the signal information S can be output to the first chip pad 220a via the first buffer 450 and the second buffer 460. The transmission of the signal information S is shown as a first signal path R1. In this case, a first transistor 492 for preventing signal transmission failure can be arranged on the first signal path R1. The first transistor 492 can be controlled by the inverted control signal OPTB.

[0045] Simultaneously, when the control signal OPT is "low," the inverted control signal OPTB output from inverter 420 can turn on the second transmission transistor 440, and the signal information S can be output to the second chip pad 220b via the third buffer 470 and the fourth buffer 480. The transmission of the signal information S is shown as the second signal path R2. In this case, a second transistor 494 for preventing signal transmission failure can be arranged on the second signal path R2. The second transistor 494 can be controlled by the control signal OPT.

[0046] Refer again Figure 5 One of the first chip pad 220a and the second chip pad 220b can act as a bonding pad. That is, one of the first chip pad 220a and the second chip pad 220b can be bonded to... Figure 1 and Figure 2 The corresponding chip connection pads 120 of the substrate body 110 are bonded. The other of the first chip pad 220a and the second chip pad 220b can serve as a test pad. The test pad can serve as a pad for testing the semiconductor chip 20 to electrically connect with the internal integrated circuit of the semiconductor chip 20.

[0047] In this implementation, the chip pad selection circuit unit 240 can electrically connect the signal input / output circuit unit 201 to the test pads during testing of the semiconductor chip 20 using a test apparatus. In this case, the signal input / output circuit unit 201 and the bonding pads can maintain an open-circuit state. After testing the semiconductor chip 20 using the test pads, the semiconductor chip 20 can be bonded to the package substrate (…). Figure 1 (10). After the semiconductor chip 20 is bonded to the package substrate 10, the chip pad selection circuit unit 240 can electrically connect the signal input / output circuit unit 201 to the bonding pad and electrically disconnect the signal input / output circuit unit 201 from the test pad. Therefore, after the semiconductor package 1 is tested, the internal integrated circuit can maintain an electrical connection with the bonding pad and an electrical open-circuit state with the test pad.

[0048] In embodiments of this disclosure, as described below Figure 6 The selection of bonding pads and test pads from the first chip pad 220a and the second chip pad 220b can refer to the wiring length from the chip connection pad 120 of the package substrate 10 that overlaps with the first chip pad 220a and the second chip pad 220b to the corresponding connection structure 140 (or connection pad 130).

[0049] Figure 6 This is a schematic plan view of a semiconductor package according to an embodiment of the present disclosure. Figure 6 It can be Figure 3 The semiconductor chip 20 is installed Figure 2 A view on the upper surface 110S1 of the packaging substrate 10. Furthermore, Figure 6 It can be Figure 1 The diagram shows a plan view of semiconductor package 1.

[0050] Reference Figure 1 , Figure 2 and Figure 6 A plurality of chip pad units 220 on the first surface 210S1 of the semiconductor chip 20 can be arranged to face and overlap with a plurality of chip connection pads 120 on the upper surface 110S1 of the packaging substrate 10. Each of the plurality of chip pad units 220 may include a first chip pad 220a and a second chip pad 220b arranged spaced apart from each other and having different surface areas relative to each other. (Refer to...) Figure 6 In one embodiment, the first chip pad 220a may have a smaller surface area than the second chip pad 220b. (See also...) Figure 1 , Figure 2 and Figure 6In each of the plurality of chip pad units 220, the first chip pad 220a and the second chip pad 220b can be arranged to overlap with the corresponding chip connection pad 120.

[0051] In one implementation, for each of the plurality of chip pad units 220, a chip connection pad 120 overlapping with a chip pad unit 220 can be electrically connected to a connection structure 140 using wiring 150. In this case, depending on the length of the wiring 150 connecting the connection structure 140 and the chip connection pad 120, a bonding pad to be bonded to the chip connection pad 120 can be determined from among the first chip pad 220a and the second chip pad 220b of the chip pad unit 220.

[0052] In the implementation method, refer together Figure 1 , Figure 2 and Figure 6 Two connection structures 140a and 140b can be selected from a plurality of connection structures 140. In an embodiment, the two connection structures 140a and 140b can be determined by the design configuration of the package substrate 10. For example, the design configuration may include various arrangements of the connection pads 130, connection structures 140, and wiring 150 according to the function and purpose of the semiconductor package. The first connection structure 140a of the two connection structures 140a and 140b can be connected to the corresponding chip connection pad 120 via the first connection pad 130a through the first wiring 150a. The second connection structure 140b of the two connection structures 140a and 140b can be connected to the corresponding chip connection pad 120 via the second connection pad 130b through the second wiring 150b. Figure 1 , Figure 2 and Figure 6 As shown, the length of the first wiring 150a, including the first outer layer circuit a1, can be shorter than the length of the second wiring 150b, including the second outer layer circuit b1. In this case, the chip connection pad 120 connected to the first wiring 150a can be bonded to the second chip pad 220b, which has a larger surface area than the first chip pad 220a and the second chip pad 220b. The chip connection pad 120 connected to the second wiring 150b can be bonded to the first chip pad 220a, which has a smaller surface area than the first chip pad 220a and the second chip pad 220b.

[0053] In the first wiring 150a and the second wiring 150b respectively connected to the first connection structure 140a and the second connection structure 140b, the shorter first wiring 150a can exhibit or have a relatively smaller package parasitic capacitance on the signal path compared to the second wiring 150b. In this case, the chip connection pad 120 connected to the first wiring 150a can bond to the second chip pad 220b, which has a relatively larger surface area. Therefore, the signal path from the chip connection pad 120 via the second chip pad 220b to the internal integrated circuit can have a relatively large pad parasitic capacitance. Therefore, the signal path from the first connection structure 140a via the first connection pad 130a, the first wiring 150a, the chip connection pad 120, and the second chip pad 220b to the internal integrated circuit can have a relatively small package parasitic capacitance and a relatively large pad parasitic capacitance.

[0054] Meanwhile, among the first wiring 150a and the second wiring 150b, the longer second wiring 150b, compared to the first wiring 150a, can exhibit or have a relatively large package parasitic capacitance on the signal path. In this case, the chip connection pad 120 connected to the second wiring 150b can bond to the first chip pad 220a, which has a relatively small surface area. Therefore, the signal path from the chip connection pad 120 via the first chip pad 220a to the internal integrated circuit can have a relatively small pad parasitic capacitance. Therefore, the signal path from the second connection structure 140b via the second connection pad 130b, the second wiring 150b, the chip connection pad 120, and the first chip pad 220a to the internal integrated circuit can have a relatively large package parasitic capacitance and a relatively small pad parasitic capacitance.

[0055] Using the method described above, the chip pads bonded to the chip connection pads respectively connected to the plurality of connection structures 140 can be determined. In embodiments of this disclosure, differences in package parasitic capacitance generated in the package substrate 10 due to length differences of the plurality of wirings 150 between each of the plurality of connection structures 140 and each of the corresponding plurality of chip connection pads 120 can be offset by using different pad parasitic capacitances. In other words, the deviation between the sum of the package parasitic capacitance and the pad parasitic capacitance generated in each of the plurality of signal paths through the plurality of chip connection pads 120 of the semiconductor package can be reduced.

[0056] Therefore, the deviation in the sum of parasitic capacitances generated in the signal transmission path from each of the multiple connection structures on the package substrate through the corresponding chip connection pads and chip pads to the internal integrated circuit of the semiconductor chip can be reduced. Thus, by reducing the variation in the transmission characteristics of the electrical signals generated with respect to each of the multiple connection structures, the electrical reliability of the semiconductor package can be improved.

[0057] This teaching has been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should be considered illustratively, not restrictively. The scope of this teaching is not limited to the foregoing description but is defined by the appended claims, and all distinguishing features within the equivalent scope should be understood to be included in the inventive concept.

[0058] Cross-references to related applications

[0059] This application claims priority to Korean Patent Application No. 10-2020-0165149, filed on November 30, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor chip, the semiconductor chip comprising: The chip body includes a signal input / output circuit unit; A plurality of chip pad units are disposed on the surface of the chip body, and each of the plurality of chip pad units includes a first chip pad and a second chip pad that have different surface areas and are adjacent to each other; and A chip pad selection circuit unit is disposed in the chip body and electrically connected to the signal input / output circuit unit and the chip pad unit. Specifically, the chip pad selection circuit unit selects one of the first chip pads and the second chip pads, and electrically connects the selected chip pad to the signal input / output circuit unit. The first chip pad and the second chip pad are selectively selected as bonding pads to be bonded to the chip connection pads of the package substrate to provide different parasitic capacitances.

2. The semiconductor chip according to claim 1, wherein, The chip pad selection circuit unit further disconnects the other unselected chip pad from the signal input / output circuit unit.

3. The semiconductor chip according to claim 1, wherein, Each of the first chip pad and the second chip pad has a surface area and a parasitic capacitance proportional to the surface area.

4. The semiconductor chip according to claim 1, wherein, The chip pad selection circuit unit electrically connects the signal input / output circuit unit to a selected chip pad based on the control signal provided to the chip pad selection circuit unit.

5. A semiconductor package, the semiconductor package comprising: Packaging substrate; as well as Semiconductor chips arranged on the packaging substrate, The packaging substrate includes: Substrate body; and Multiple chip connection pads are arranged on the surface of the substrate body. The semiconductor chip includes: The chip body; and A plurality of chip pad units are disposed on the surface of the chip body, the surface of the chip body facing the surface of the substrate body, and the plurality of chip pad units correspond to a plurality of chip connection pads. Each of the plurality of chip pad units includes a first chip pad and a second chip pad arranged spaced apart from each other and having different surface areas. Specifically, one of the first chip pads and the second chip pads is electrically connected to a corresponding chip connection pad among the plurality of chip connection pads. The semiconductor package further includes: Multiple connection pads are arranged on the substrate body and spaced apart from the multiple chip connection pads; The substrate body has multiple wirings that electrically connect the multiple chip connection pads to the multiple connection pads respectively; and The first connection structure and the second connection structure are arranged on the plurality of connection pads. The first connection structure is electrically connected to the first chip connection pad among the plurality of chip connection pads via the first wiring among the plurality of wirings. The second connection structure is electrically connected to the second chip connection pad among the plurality of chip connection pads via the second wiring among the plurality of wirings. The length of the first wiring is shorter than the length of the second wiring. Wherein, the first chip connection pad is electrically connected to the chip pad with the larger surface area among the first chip pads and second chip pads of the corresponding chip pad units in the plurality of chip pad units, and The second chip connection pad is electrically connected to the chip pad with the smaller surface area among the first chip pad and the second chip pad of the corresponding chip pad unit in the plurality of chip pad units.

6. The semiconductor package according to claim 5, in, The semiconductor chip further includes: Signal input / output circuit unit, the signal input / output circuit unit being arranged in the chip body; and A chip pad selection circuit unit is electrically connected to the signal input / output circuit unit and the plurality of chip pad units, and... The chip pad selection circuit unit selects one of the first chip pads and the second chip pads, and electrically connects the selected chip pad to the signal input / output circuit unit.

7. The semiconductor package according to claim 6, wherein, The chip pad selection circuit unit further disconnects the other unselected chip pad from the signal input / output circuit unit.

8. The semiconductor package according to claim 5, in, The signal path from the first connection structure via the first chip connection pad to the internal integrated circuit of the semiconductor chip has a larger pad parasitic capacitance compared to the signal path from the second connection structure via the second chip connection pad to the internal integrated circuit of the semiconductor chip.

9. A semiconductor package, the semiconductor package comprising: A packaging substrate, the packaging substrate comprising a substrate body having an upper surface and a lower surface; as well as A semiconductor chip, the semiconductor chip being mounted above the upper surface of the substrate body. The packaging substrate includes multiple chip connection pads, which are arranged on the upper surface of the substrate body and distributed in one direction. The semiconductor chip includes: The chip body includes a signal input / output circuit unit; A plurality of chip pad units are disposed on the surface of the chip body, the surface of the chip body facing the upper surface of the substrate body, and the plurality of chip pad units correspond to a plurality of chip connection pads; and A chip pad selection circuit unit is provided, which is connected to the signal input / output circuit unit and the plurality of chip pad units. Each of the plurality of chip pad units includes a first chip pad and a second chip pad arranged spaced apart from each other and having different surface areas. Wherein, one of the first chip pads and the second chip pads is electrically connected to a corresponding chip connection pad among the plurality of chip connection pads. The semiconductor package further includes: A plurality of connection pads are disposed on the lower surface of the substrate body; and Multiple wirings electrically connect the multiple chip connection pads to their respective connection pads; and The first connection structure and the second connection structure are respectively arranged on the first connection pad and the second connection pad in the plurality of connection pads. The first connection structure is electrically connected to the first chip connection pad among the plurality of chip connection pads via the first wiring among the plurality of wirings. The second connection structure is electrically connected to the second chip connection pad among the plurality of chip connection pads via the second wiring among the plurality of wirings. The length of the first wiring is shorter than the length of the second wiring. Wherein, the first chip connection pad is electrically connected to the chip pad with the larger surface area among the first chip pads and second chip pads of the corresponding chip pad units in the plurality of chip pad units, and The second chip connection pad is electrically connected to the chip pad with the smaller surface area among the first chip pad and the second chip pad of the corresponding chip pad unit in the plurality of chip pad units.

10. The semiconductor package according to claim 9, wherein, The chip pad selection circuit unit further disconnects the other unselected chip pad from the signal input / output circuit unit.

11. The semiconductor package according to claim 9, wherein, In each of the plurality of chip pad units, One of the first chip pads and the second chip pads is a bonding pad that is electrically connected to a corresponding chip connection pad among the plurality of chip connection pads, and The first chip pad and the second chip pad are both test pads configured to be connected to a test device.

12. The semiconductor package of claim 11, wherein, The signal input / output circuit unit is electrically connected to the corresponding chip connection pad via the bonding pad.

13. The semiconductor package according to claim 9, wherein, In each of the plurality of chip pad units, the first chip pad and the second chip pad are arranged to overlap with the corresponding chip connection pad.

14. The semiconductor package according to claim 9, in, The signal path from the first connection structure via the first chip connection pad to the internal integrated circuit of the semiconductor chip has a larger pad parasitic capacitance compared to the signal path from the second connection structure via the second chip connection pad to the internal integrated circuit of the semiconductor chip.

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