Non-volatile memory device and memory system including the same

Abstract

A non-volatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure over the common source line layer, a plurality of channel structures through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0166969, filed on December 2, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a non-volatile memory device and a memory system including the non-volatile memory device. More specifically, the present invention relates to a three-dimensional (3D) non-volatile memory device comprising two structures bonded to each other and a memory system including the 3D non-volatile memory device. Background Technology

[0004] Consumers require non-volatile memory devices with high performance, small size, and low cost. Therefore, 3D non-volatile memory devices in which multiple memory cells are arranged vertically have been proposed to achieve highly integrated non-volatile memory devices. Additionally, a non-volatile memory device has been proposed that has a reduced planar area formed by bonding a first structure to a second structure, wherein the first structure is formed by forming a portion of the non-volatile memory device on a first substrate, and the second structure is formed by forming another portion of the non-volatile memory device on a second substrate. Summary of the Invention

[0005] The present invention relates to a nonvolatile memory device having reduced common source line noise and / or reduced planar area and / or a memory system including the nonvolatile memory device.

[0006] According to embodiments of the present invention, a non-volatile memory device may include a first structure and a second structure bonded to the first structure. The first structure may include a first substrate, peripheral circuitry on the first substrate, a first insulating structure on the first substrate and the peripheral circuitry, a plurality of first bonding pads on the first insulating structure, and a first interconnect structure located in the first insulating structure and connected to the peripheral circuitry and the plurality of first bonding pads. The second structure may include a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked above the common source line layer, a plurality of channel structures passing through a cell region of the stacked structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stacked structure and contacting the common source line layer, a second insulating structure on the stacked structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure. The second interconnect structure may be connected to the plurality of gate layers, the plurality of channel structures, the dummy channel structures, and the plurality of second bonding pads. The plurality of second bonding pads may each contact a plurality of first bonding pads. The step region of the stacked structure may be located on one side of a cell region of the stacked structure and have a step shape.

[0007] According to another embodiment of the present invention, a non-volatile memory device may include a first structure and a second structure bonded to the first structure. The first structure may include a first substrate, peripheral circuitry on the first substrate, a first insulating structure on the first substrate and the peripheral circuitry, a plurality of first bonding pads on the first insulating structure, and a first interconnect structure located in the first insulating structure and connected to the peripheral circuitry and the plurality of first bonding pads. The second structure may include a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked above the common source line layer, a plurality of channel structures passing through cell regions of the stacked structure and contacting the common source line layer, a word line dicing structure passing through the stacked structure and elongated in a first direction, a dummy word line dicing structure passing through the stacked structure, a second insulating structure on the stacked structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure. The second interconnect structure may be connected to the plurality of gate layers, the plurality of channel structures, the dummy word line dicing structure, and the plurality of second bonding pads. The dummy word line dicing structure may electrically contact the common source line layer and may be elongated in the first direction. Multiple first bonding pads can contact multiple second bonding pads respectively. The stepped region of the stacked structure can be located on one side of the cell region of the stacked structure and can have a stepped shape.

[0008] According to another embodiment of the present invention, a memory system may include a non-volatile memory device having a first structure and a second structure bonded to the first structure, and a memory controller electrically connected to the non-volatile memory device and configured to control the non-volatile memory device. The first structure may include a first substrate, peripheral circuitry on the first substrate, a first insulating structure on the first substrate and the peripheral circuitry, a plurality of first bonding pads on the first insulating structure, and a first interconnect structure located in the first insulating structure and connected to the peripheral circuitry and the plurality of first bonding pads. The second structure may include a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers alternately stacked above the common source line layer, a plurality of channel structures passing through cell regions of the stacked structure and contacting the common source line layer, a word line dicing structure passing through the stacked structure and elongated in a first direction, a common source line contact passing through the stacked structure and electrically contacting the common source line layer, a second insulating structure on the stacked structure, a plurality of second bonding pads on the second insulating structure, input / output pads connected to the memory controller, and a second interconnect structure in the second insulating structure. The second interconnect structure can connect to multiple gate layers, multiple channel structures, common source line contacts, input / output pads, and multiple second bonding pads. Multiple first bonding pads can contact multiple second bonding pads respectively. The stepped region of the stacked structure can be located on one side of the cell region of the stacked structure and can have a stepped shape. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1A This is a cross-sectional view of a non-volatile memory device according to an embodiment of the present invention.

[0011] Figure 1B yes Figure 1A A magnified view of region A;

[0012] Figure 2A This is a bottom view of a non-volatile memory device according to an embodiment of the present invention.

[0013] Figure 2B It is along Figure 2A A cross-sectional view of a non-volatile memory device taken by line B-B';

[0014] Figures 3A to 3M This is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to an embodiment of the present invention.

[0015] Figures 4A to 4JThis is a cross-sectional view illustrating a method for manufacturing a non-volatile memory device according to an embodiment of the present invention.

[0016] Figure 5 This is a schematic diagram of a memory system including a non-volatile memory device according to an embodiment of the present invention.

[0017] Figure 6 This is a schematic perspective view of a memory system including a non-volatile memory device according to an embodiment of the present invention; and

[0018] Figure 7 This is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present invention. Detailed Implementation

[0019] Figure 1A This is a cross-sectional view of a non-volatile memory device 100 according to an embodiment of the present invention. Figure 1B yes Figure 1A A magnified view of region A.

[0020] Reference Figure 1A and Figure 1B The non-volatile memory device 100 includes a first structure S1 and a second structure S2 bonded to the first structure S1. The first structure S1 is contactable with the second structure S2, such that a plurality of first bonding pads BP1 of the first structure S1 and a plurality of second bonding pads BP2 of the second structure S2 are in contact with each other. In some embodiments, when the first bonding pads BP1 and the second bonding pads BP2 are both copper (Cu), the first structure S1 can be bonded to the second structure S2 via Cu-Cu bonding.

[0021] The first structure S1 may include a first substrate 110, a peripheral circuit PC on the first substrate 110, a first insulating structure IL1 on the first substrate 110 and the peripheral circuit PC, a plurality of first bonding pads BP1 on the first insulating structure IL1, and a first interconnect structure IC1 in the first insulating structure IL1.

[0022] The first substrate 110 may include semiconductor materials such as group IV, group III-V, or group II-VI semiconductor materials. Group IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Group III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). Group II-VI semiconductor materials may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). The first substrate 110 may be a bulk wafer or an epitaxial layer.

[0023] The peripheral circuit PC can be disposed on the first substrate 110. The peripheral circuit PC may include a plurality of transistors 120. For example, the transistors 120 may include a gate electrode 122 above the first substrate 110, a gate insulating layer 121 between the gate electrode 122 and the first substrate 110, a gate separator 123 on the side surface of the gate electrode 122, and a source electrode 124 and a drain electrode 125 on both sides of the gate electrode 122.

[0024] The first insulating structure IL1 can cover the first substrate 110 and the peripheral circuit PC. Although Figure 1A Not shown, but the first insulating structure IL1 may include multiple insulating layers stacked on top of each other. The first insulating structure IL1 may include, for example, an insulating material, which may include silicon oxide, silicon nitride, a low dielectric constant (low k) material, or a combination thereof. A low dielectric constant material is a material with a dielectric constant lower than that of silicon oxide, and may include, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicon glass (OSG), spin-coated glass (SOG), spin-coated polymers, or a combination thereof.

[0025] The first bonding pad BP1 may be disposed on the first insulating structure IL1. In some embodiments, the upper surface of the first bonding pad BP1 may be coplanar with the upper surface of the first insulating structure IL1. That is, the first bonding pad BP1 may not protrude from the upper surface of the first insulating structure IL1. The first bonding pad BP1 may include a conductive material, which may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or combinations thereof.

[0026] The first interconnect structure IC1 can be disposed in the first insulating structure IL1. The first interconnect structure IC1 can be connected to the peripheral circuit PC and a plurality of first bonding pads BP1. The first interconnect structure IC1 can connect the peripheral circuit PC to the plurality of first bonding pads BP1. The first interconnect structure IC1 can also connect a plurality of transistors 120 in the peripheral circuit PC. The first interconnect structure IC1 may include multiple lines, vias connecting the multiple lines to each other, and plugs connecting the multiple lines and the plurality of transistors 120 to each other. The first interconnect structure IC1 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or combinations thereof.

[0027] The second structure S2 may include a low-resistance conductive layer 270, a common source line layer 210 on the low-resistance conductive layer 270, a stacked structure SS above the common source line layer 210, a plurality of channel structures 240 passing through the cell region CELL of the stacked structure SS, a plurality of dummy channel structures 280 passing through the step region EXT of the stacked structure SS, a second insulating structure IL2 on the stacked structure SS, a plurality of second bonding pads BP2 on the second insulating structure IL2, and a second interconnect structure IC2 in the second insulating structure IL2.

[0028] In some embodiments, the second structure S2 may further include a lower conductive layer 250 between the common source line layer 210 and the stacked structure SS. In some embodiments, the second structure S2 may further include a lower support layer 260 between the lower conductive layer 250 and the stacked structure SS. In some embodiments, the second structure S2 may further include a third insulating structure IL3 on the second insulating structure IL2, and a low-resistance conductive layer 270 and input / output pads 290 passing through the third insulating structure IL3.

[0029] The common source line layer 210 may include, for example, a semiconductor material (such as a group IV, III-V, or II-VI semiconductor material). The common source line layer 210 may include, for example, polysilicon. A low-resistance conductive layer 270 may contact the common source line layer 210 and serve as part of the common source line. The resistivity of the material constituting the low-resistance conductive layer 270 may be lower than the resistivity of the material constituting the common source line layer 210. For example, when the common source line layer 210 comprises polysilicon, the low-resistance conductive layer 270 may include a metal. This metal may include, for example, copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or combinations thereof. The low-resistance conductive layer 270 can reduce common source line noise by reducing the pure reactance of the common source line.

[0030] A stacked structure SS may be disposed above a common source line layer 210. The stacked structure SS may include multiple gate layers (e.g., multiple first gate layers 230a and multiple second gate layers 230b) and multiple interlayer insulating layers (e.g., multiple first interlayer insulating layers 220a and multiple second interlayer insulating layers 220b) alternately stacked above the common source line layer 210. The stacked structure SS may include a first portion SSa above the common source line layer 210 and a second portion SSb on the first portion SSa. The first portion SSa of the stacked structure SS may include multiple first gate layers 230a and multiple first interlayer insulating layers 220a alternately stacked above the common source line layer 210. The second portion SSb of the stacked structure SS may include multiple second gate layers 230b and multiple second interlayer insulating layers 220b alternately stacked on the first portion SSa of the stacked structure SS.

[0031] A stacked structure SS may include a cell region (CELL) and a step region (EXT). The step region EXT of the stacked structure SS may be located on one side of the cell region (CELL) of the stacked structure SS and may have a step shape. For example, the step region EXT of the stacked structure SS may have a step shape that descends in the +Z direction.

[0032] The plurality of gate layers (e.g., a plurality of first gate layers 230a and a plurality of second gate layers 230b) may include, but are not limited to, tungsten (W), copper (Cu), silver (Ag), gold (Au), aluminum (Al), or combinations thereof. The plurality of interlayer insulating layers (e.g., a plurality of first interlayer insulating layers 220a and a plurality of second interlayer insulating layers 220b) may include insulating materials, which may include silicon oxide, silicon nitride, low dielectric constant materials, or combinations thereof.

[0033] Each of the plurality of channel structures 240 may pass through the cell region of the stacked structure SS and contact the common source line layer 210. In some embodiments, the channel structure 240 may also pass through the lower conductive layer 250 and the lower support layer 260.

[0034] Reference Figure 1B The channel structure 240 may be located in the first channel via 240Ha and the second channel via 240Hb. The channel structure 240 may include a gate insulating layer 241 on the first channel via 240Ha and the second channel via 240Hb, and a channel layer 242 on the gate insulating layer 241. In some embodiments, the channel structure 240 may include a buried insulating layer 243 on the channel layer 242 and a channel pad 244 in the end portion of the second channel via 240Hb.

[0035] The gate insulating layer 241 may extend between the common source line layer 210 and the channel layer 242, and between the stacked structure SS and the channel layer 242. The gate insulating layer 241 may include a barrier insulating layer 241a, a charge storage layer 241b, and a tunneling insulating layer 241c sequentially stacked on the first channel via 240Ha and the second channel via 240Hb. The barrier insulating layer 241a may include, for example, silicon oxide, silicon nitride, a metal oxide with a dielectric constant higher than that of silicon oxide, or combinations thereof. The metal oxide may include, for example, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof. The charge storage layer 241b may include, for example, silicon nitride, boron nitride, polysilicon, or combinations thereof. The tunneling insulating layer 241c may include, for example, a metal oxide or silicon oxide. In some embodiments, the barrier insulating layer 241a, the charge storage layer 241b, and the tunneling insulating layer 241c may respectively comprise oxides, nitrides, and oxides.

[0036] The channel layer 242 may surround the side surface and one end of the buried insulating layer 243. The channel layer 242 may include a semiconductor material such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material. In some embodiments, the channel layer 242 may include polysilicon.

[0037] The buried insulating layer 243 may fill the space surrounded by the channel layer 242 and the channel pads 244. The buried insulating layer 243 may include, for example, an insulating material, which may include silicon nitride, silicon oxide, a low dielectric constant material, or a combination thereof. In some embodiments, the buried insulating layer 243 may include silicon oxide.

[0038] The channel pad 244 may contact the channel layer 242 and the buried insulating layer 243. In some embodiments, the channel pad 244 may also contact the gate insulating layer 241. The channel pad 244 may include a conductive material such as a semiconductor material (such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe)), a metallic material (such as tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), or silver (Ag)), a metal nitride (such as titanium nitride (TiN) or tantalum nitride (TaN)) or a combination thereof. In some embodiments, the channel pad 244 may include polysilicon.

[0039] Refer again Figure 1A Multiple dummy channel structures 280 can pass through the stepped region EXT of the stacked structure SS and contact the common source line layer 210. The dummy channel structures 280 can also pass through the lower conductive layer 250 and the lower support layer 260. The dummy channel structures 280 can also pass through the second portion IL2b and the third portion IL2c of the second insulating structure IL2. The dummy channel structures 280 can be located in a first dummy channel via 280Ha passing through the stepped region EXT of the stacked structure SS and the third portion IL2c of the second insulating structure IL2, and a second dummy channel via 280Hb passing through the second portion IL2b of the second insulating structure IL2.

[0040] The dummy channel structure 280 may include an insulating layer 282 on the first dummy channel via 280Ha and the second dummy channel via 280Hb, and a conductive layer 281 on the insulating layer 282. The conductive layer 281 may extend over the first dummy channel via 280Ha and the second dummy channel via 280Hb, and contact the common source line layer 210. The insulating layer 282 may extend between the conductive layer 281 and the step region EXT of the stacked structure SS. The insulating layer 282 may also extend between the conductive layer 281 and a second portion IL2b of the second insulating structure IL2. The insulating layer 282 may also extend between the conductive layer 281 and a third portion IL2c of the second insulating structure IL2. In some embodiments, the insulating layer 282 may also extend between the conductive layer 281 and the lower support layer 260. In some embodiments, the insulating layer 282 may also extend between the conductive layer 281 and the lower conductive layer 250.

[0041] The conductive layer 281 may include a conductive material such as a semiconductor material or a metallic material. The conductive layer 281 may include, for example, polysilicon, copper (Cu), tungsten (W), aluminum (Al), gold (Au), silver (Ag), or combinations thereof. The insulating layer 282 may include, for example, silicon oxide, silicon nitride, a low dielectric constant material, or combinations thereof.

[0042] The dummy channel structure 280 passing through the step region EXT of the stacked structure SS can be used as a common source line contact for contacting the common source line layer 210. Because the planar area occupied by the common source line contact for contacting the common source line layer 210 from outside the stacked structure SS is not required, the planar area of ​​the non-volatile memory device 100 can be reduced.

[0043] The second insulating structure IL2 may cover the stacked structure SS, the multiple channel structures 240, and the multiple dummy channel structures 280. The second insulating structure IL2 may include multiple insulating layers. For example, the second insulating structure IL2 may include a first portion IL2a, a second portion IL2b on the first portion IL2a, and a third portion IL2c on the second portion IL2b. The second insulating structure IL2 may include, for example, an insulating material, which may include silicon oxide, silicon nitride, a low-dielectric material, or a combination thereof.

[0044] Multiple second bonding pads BP2 may be arranged on the second insulating structure IL2. In some embodiments, the upper surface of the second bonding pads BP2 may be coplanar with the lower surface of the second insulating structure IL2. That is, the second bonding pads BP2 may not protrude from the lower surface of the second insulating structure IL2. The second bonding pads BP2 may include a conductive material, which may include copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or combinations thereof.

[0045] The second interconnect structure IC2 can be disposed in the second insulating structure IL2 and can be connected to multiple gate layers (e.g., multiple first gate layers 230a and multiple second gate layers 230b), multiple channel structures 240, dummy channel structures 280, and multiple second bonding pads BP2. For example, the second interconnect structure IC2 can connect multiple gate layers (e.g., multiple first gate layers 230a and multiple second gate layers 230b), multiple channel structures 240, and dummy channel structures 280 to multiple second bonding pads BP2. In some embodiments, the second interconnect structure IC2 can also be connected to input / output pads 290. For example, the second interconnect structure IC2 can connect input / output pads 290 to second bonding pads BP2.

[0046] Multiple gate layers (e.g., multiple first gate layers 230a and multiple second gate layers 230b) can be connected to the peripheral circuit PC via the second interconnect structure IC2, multiple second bonding pads BP2, multiple first bonding pads BP1, and the first interconnect structure IC1. Additionally, multiple channel structures 240 can be connected to the peripheral circuit PC via the second interconnect structure IC2, multiple second bonding pads BP2, multiple first bonding pads BP1, and the first interconnect structure IC1. Furthermore, a dummy channel structure 280 can be connected to the peripheral circuit PC via the second interconnect structure IC2, second bonding pads BP2, first bonding pads BP1, and the first interconnect structure IC1. Finally, input / output pads 290 can be connected to the peripheral circuit PC via the second interconnect structure IC2, second bonding pads BP2, first bonding pads BP1, and the first interconnect structure IC1.

[0047] The second interconnect structure IC2 may include multiple lines, vias connecting the multiple lines to each other, and multiple plugs contacting multiple gate layers (e.g., multiple first gate layers 230a and multiple second gate layers 230b), multiple channel structures 240, dummy channel structures 280, and input / output pads 290. The second interconnect structure IC2 may include conductive materials such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), or combinations thereof.

[0048] The lower conductive layer 250 may extend between the lower support layer 260 and the common source line layer 210. The lower conductive layer 250 may comprise a conductive material such as a semiconductor material or a metallic material. The lower conductive layer 250 may comprise polysilicon, aluminum (Al), tungsten (W), silver (Ag), gold (Au), or combinations thereof. In some embodiments, such as Figure 1B As shown, the lower conductive layer 250 can penetrate the gate insulating layer 241 and contact the channel layer 242.

[0049] The lower support layer 260 may extend between the stacked structure SS and the lower conductive layer 250. The lower support layer 260 may include a conductive material such as a semiconductor material or a metallic material. The lower support layer 260 may include polysilicon, aluminum (Al), tungsten (W), silver (Ag), gold (Au), or combinations thereof. In some embodiments, the common source line layer 210, the lower conductive layer 250, and the lower support layer 260 may include polysilicon, therefore, the boundaries between the common source line layer 210 and the lower conductive layer 250, and between the lower conductive layer 250 and the lower support layer 260, may be unclear or unidentifiable.

[0050] The third insulating structure IL3 can be arranged on the second insulating structure IL2 and the low-resistance conductive layer 270. Although Figure 1A Not shown, but the third insulating structure IL3 may include multiple insulating layers stacked on top of each other. The third insulating structure IL3 may include insulating materials such as silicon oxide, silicon nitride, low dielectric constant materials, or combinations thereof.

[0051] The input / output pads 290 can pass through the third insulating structure IL3. The input / output pads 290 can be exposed to the outside of the non-volatile memory device 100. (See reference...) Figure 5 and Figure 6 As described, the input / output pads 290 can be connected to a memory controller (not shown) external to the non-volatile memory device 100. The input / output pads 290 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or gold (Au).

[0052] Figure 2A This is a bottom view of a non-volatile memory device 100A according to an embodiment of the present invention. Figure 2B It is along Figure 2A A cross-sectional view of the non-volatile memory device 100A taken along line B-B'. The following description will refer to... Figure 1A and Figure 1B The described non-volatile memory device 100 and the reference Figure 2A and Figure 2B Differences between the described non-volatile memory devices 100A.

[0053] Reference Figure 2A and Figure 2B , and reference Figure 1A and Figure 1B Similar to the described non-volatile memory device 100A, the non-volatile memory device 100A may include a first structure S1 and a second structure S2A bonded to the first structure S1. The first structure S1 is similar to the referenced... Figure 1A The description is the same. The second structure S2A may also include a word line cutting structure WS and a dummy word line cutting structure DWS. Although Figure 2A and Figure 2B Not shown, but the second structure S2A may include Figure 1A The dummy channel structure 280 shown may not include the dummy channel structure 280, or may include the dummy channel structure 280 having the same configuration as the channel structure 240.

[0054] The word line cut structure WS can pass through the stacked structure SS and can be elongated in the first horizontal direction (direction X). The word line cut structure WS can pass through the stepped region EXT and the cell region CELL of the stacked structure SS in the first horizontal direction (direction X). The word line cut structure WS can also pass through the second portion IL2b of the second insulating structure IL2 and the lower support layer 260. The word line cut structure WS can be located in the word line cut portion WSH passing through the stacked structure SS. The word line cut portion WSH can also pass through the second portion IL2b of the second insulating structure IL2 and the lower support layer 260. The word line cut structure WS can include, for example, an insulating material, including silicon oxide, silicon nitride, a low dielectric constant material, or a combination thereof.

[0055] The dummy word line cut structure DWS can pass through the stepped region EXT of the stacked structure SS in the vertical direction (direction Z) and is elongated in the first horizontal direction (direction X). The dummy word line cut structure DWS can be located within the stepped region EXT of the stacked structure SS and may not pass through the cell region CELL of the stacked structure SS. The dummy word line cut structure DWS can also pass through the second portion IL2b of the second insulating structure IL2 and the lower support layer 260. The dummy word line cut structure DWS can be located within the dummy word line cut portion DWSH that passes through the stepped region EXT of the stacked structure SS. The dummy word line cut portion DWSH can also pass through the second portion IL2b of the second insulating structure IL2 and the lower support layer 260.

[0056] In some embodiments, the dummy word line cut structure (DWS) may not directly contact the common source line layer 210, but it can make electrical contact with the common source line layer 210 through the lower conductive layer 250. In another embodiment, the dummy word line cut structure (DWS) can pass through the lower conductive layer 250 and make direct contact with the common source line layer 210.

[0057] The dummy word line cut structure DWS may include a conductive layer DWSa that contacts the common source line layer 210 and an insulating layer DWSb between the conductive layer DWSa and the stacked structure SS. In some embodiments, the conductive layer DWSa may not directly contact the common source line layer 210, but may make electrical contact with the common source line layer 210 through the lower conductive layer 250. The insulating layer DWSb may also extend between the conductive layer DWSa and the second portion IL2b of the second insulating structure IL2. In addition, the insulating layer DWSb may also extend between the conductive layer DWSa and the lower support layer 260. In other words, the insulating layer DWSb may be disposed on the dummy word line cut portion DWSH.

[0058] The conductive layer DWSa may include, for example, polycrystalline silicon, copper (Cu), tungsten (W), aluminum (Al), gold (Au), silver (Ag), or combinations thereof. The insulating layer DWSb may include, for example, silicon oxide, silicon nitride, a low dielectric constant material, or combinations thereof.

[0059] The second interconnect structure IC2 can also be connected to the dummy word line cut structure DWS. For example, the dummy word line cut structure DWS can be connected to the peripheral circuit PC through the second interconnect structure IC2, the second bonding pad BP2, the first bonding pad BP1, and the first interconnect structure IC1. However, the second interconnect structure IC2 may not be connected to the word line cut structure WS.

[0060] According to an embodiment of the present invention, the dummy word line cut structure DWS passing through the step region EXT of the stacked structure SS can be used as a contact for the common source line layer 210. Because the planar area occupied by the common source line contact of the common source line layer 210 that contacts the outside of the stacked structure SS is not required, the planar area of ​​the non-volatile memory device 100A can be reduced.

[0061] Figures 3A to 3M This is for describing the manufacture of a non-volatile memory device 100 according to an embodiment of the present invention (see [link]). Figure 1A A cross-sectional view of the method.

[0062] Reference Figure 3AA second substrate 215 may be provided. The second substrate 215 may include, for example, a semiconductor material (such as a group IV semiconductor material, a group III-V semiconductor material, or a group II-VI semiconductor material). A common source line layer 210 may be formed on the second substrate 215. A first portion of the initial stacked structure PSa may be formed over the common source line layer 210. The first portion of the initial stacked structure PSa may be formed by alternately forming a plurality of first interlayer insulating layers 220a and a plurality of first sacrificial layers 235a over the common source line layer 210. Each of the plurality of first sacrificial layers 235a may include a material having etch selectivity relative to each of the plurality of first interlayer insulating layers 220a. For example, when the first interlayer insulating layer 220a includes silicon oxide, the first sacrificial layer 235a may include silicon nitride.

[0063] In some embodiments, a lower sacrificial layer 255 may also be formed between the common source line layer 210 and the first portion PSa of the initial stacked structure. In some embodiments, a lower support layer 260 may also be formed between the lower sacrificial layer 255 and the first portion PSa of the initial stacked structure. The lower sacrificial layer 255 may include a material having etch selectivity relative to the common source line layer 210 and the lower support layer 260. For example, when the common source line layer 210 and the lower support layer 260 comprise polysilicon, the lower sacrificial layer 255 may comprise silicon nitride.

[0064] The first portion PSa of the initial stacked structure can be patterned so that the step region EXT of the first portion PSa of the initial stacked structure has a step shape. Next, the third portion IL2c of the second insulating structure can be formed on the second substrate 215 and the first portion PSa of the initial stacked structure. Next, a first channel via 240Ha through the cell region CELL of the first portion PSa of the initial stacked structure and a first dummy channel via 280Ha through the step region EXT of the first portion PSa of the initial stacked structure can be formed. The first dummy channel via 280Ha can also pass through the third portion IL2c of the second insulating structure. The first channel via 240Ha and the first dummy channel via 280Ha can also pass through the lower support layer 260 and the lower sacrificial layer 255.

[0065] Next, the first channel via 240Ha and the first dummy channel via 280Ha are filled with the first filling layer 240Fa and the first dummy filling layer 280Fa, respectively. In some embodiments, the first filling layer 240Fa and the first dummy filling layer 280Fa may comprise polysilicon.

[0066] Reference Figure 3BThe second portion PSb of the initial stacked structure can be formed on the first portion PSa of the initial stacked structure. The second portion PSb of the initial stacked structure can be formed by alternately forming a plurality of second interlayer insulating layers 220b and a plurality of second sacrificial layers 235b on the first portion PSa of the initial stacked structure. Each of the plurality of second sacrificial layers 235b may include a material having etch selectivity relative to each of the plurality of second interlayer insulating layers 220b. For example, when the second interlayer insulating layer 220b comprises silicon oxide, the second sacrificial layer 235b may comprise silicon nitride.

[0067] Next, the second portion PSb of the initial stacked structure can be patterned so that the stepped region EXT of the second portion PSb of the initial stacked structure has a stepped shape. Next, the second portion IL2b of the second insulating structure can be formed on the third portion IL2c of the second insulating structure and on the first portion PSa and the second portion PSb of the initial stacked structure. Next, a second channel hole 240Hb can be formed through the second portion PSb of the initial stacked structure and exposing the first filler layer 240Fa, and a second dummy channel hole 280Hb can be formed through the second portion IL2b of the second insulating structure and exposing the first dummy filler layer 280Fa.

[0068] Reference Figure 3C The second channel via 240Hb and the second dummy channel via 280Hb can be filled with the second fill layer 240Fb and the second dummy fill layer 280Fb, respectively. In some embodiments, the second fill layer 240Fb and the second dummy fill layer 280Fb may comprise polysilicon.

[0069] Reference Figure 3C and Figure 3D The first dummy filler layer 240Fa and the second dummy filler layer 240Fb can be removed from the first channel hole 240Ha and the second channel hole 240Hb, respectively. To limit and / or prevent the removal of the first dummy filler layer 280Fa and the second dummy filler layer 280Fb, a mask can be formed to cover and expose the second dummy filler layer 280Fb before removing the first filler layer 240Fa and the second filler layer 240Fb. This mask can be removed after removing the first filler layer 240Fa and the second filler layer 240Fb.

[0070] Next, a channel structure 240 can be formed in the first channel hole 240Ha and the second channel hole 240Hb. (Refer to...) Figure 3D and Figure 1BA gate insulating layer 241 can be formed on the first channel via 240Ha and the second channel via 240Hb. For example, the gate insulating layer 241 can be formed by sequentially forming a barrier insulating layer 241a, a charge storage layer 241b, and a tunneling insulating layer 241c on the first channel via 240Ha and the second channel via 240Hb. A channel layer 242 can be formed on the gate insulating layer 241. A buried insulating layer 243 can be formed on the channel layer 242. The buried insulating layer 243 can fill the first channel via 240Ha, the second channel via 240Hb, the gate insulating layer 241, and the channel layer 242. Next, portions of the gate insulating layer 241, the channel layer 242, and the buried insulating layer 243 located in the end portion of the second channel via 240Hb can be removed, and a channel pad 244 can be formed in the end portion of the second channel via 240Hb.

[0071] Reference Figure 3D and Figure 3E The first dummy fill layer 280Fa and the second dummy fill layer 280Fb can be removed from the first dummy channel aperture 280Ha and the second dummy channel aperture 280Hb, respectively. In some embodiments, to limit and / or prevent the removal of the channel structure 240, a mask for covering the channel structure 240 and exposing the second dummy fill layer 280Fb can be formed before the removal of the first dummy fill layer 280Fa and the second dummy fill layer 280Fb. The mask can be removed after the removal of the first dummy fill layer 280Fa and the second dummy fill layer 280Fb.

[0072] Next, a dummy channel structure 280 can be formed in the first dummy channel hole 280Ha and the second dummy channel hole 280Hb. First, an insulating layer 282 can be formed on the sidewalls of the first dummy channel hole 280Ha and the second dummy channel hole 280Hb. For example, the insulating layer 282 can be formed on the upper surface of the second portion IL2b of the second insulating structure, the sidewalls of the second dummy channel hole 280Hb, and the sidewalls and bottom of the first dummy channel hole 280Ha. The insulating layer 282 on the upper surface of the second portion IL2b of the second insulating structure and the bottom of the first dummy channel hole 280Ha can be removed by anisotropic etching of the insulating layer 282. Next, a conductive layer 281 can be formed on the insulating layer 282. The conductive layer 281 can fill the first dummy channel hole 280Ha, the second dummy channel hole 280Hb, and the insulating layer 282.

[0073] Reference Figure 3E and Figure 3FA space 255H can be formed between the common source line layer 210 and the lower support layer 260 by removing the lower sacrificial layer 255. The gate insulating layer 241 of the channel structure 240 and the insulating layer 282 of the dummy channel structure 280 can be exposed in the space 255H. To remove the lower sacrificial layer 255, although... Figure 3E and Figure 3F Not shown, but word line cutouts can be formed through the initial stack structure (e.g., the first portion PSa and the second portion PSb) and the lower support layer 260 and expose the lower sacrificial layer 255 before the lower sacrificial layer 255 is removed. Etching agent can reach the lower sacrificial layer 255 through the word line cutouts and etch the lower sacrificial layer 255.

[0074] Reference Figure 3F and Figure 3G An opening 240P through the gate insulating layer 241 of the channel structure 240 can be formed by removing a portion of the gate insulating layer 241 exposed in the space 255H. The channel layer 242 can be exposed in the space 255H through the opening 240P. In some embodiments, the insulating layer 282 of the dummy channel structure 280 is thick enough that the conductive layer 281 may not be exposed in the space 255H even when the insulating layer 282 of the dummy channel structure 280 is exposed to the etchant used to remove a portion of the gate insulating layer 241 of the channel structure 240. In another embodiment, the insulating layer 282 of the dummy channel structure 280 may be exposed to the etchant used to remove a portion of the gate insulating layer 241 of the channel structure 240, so that the exposed portion of the insulating layer 282 can be etched to expose the conductive layer 281 in the space 255H.

[0075] Reference Figure 3G and Figure 3H A lower conductive layer 250 can be formed in space 255H. The lower conductive layer 250 can contact the channel layer 242 through opening 240P. In some embodiments, the lower conductive layer 250 may not contact the conductive layer 281. Figure 3H As shown in the examples, in some embodiments, the lower conductive layer 250 may penetrate the insulating layer 282 and contact the conductive layer 281.

[0076] Reference Figure 3H and Figure 3I Multiple spaces 235Ha and 235Hb can be formed between multiple interlayer insulating layers (e.g., multiple first interlayer insulating layers 220a and multiple second interlayer insulating layers 220b) by removing multiple sacrificial layers (e.g., multiple first sacrificial layers 235a and multiple second sacrificial layers 235b).

[0077] Reference Figure 3I and Figure 3JMultiple gate layers (e.g., multiple first gate layers 230a and multiple second gate layers 230b) can be formed in multiple spaces 235Ha and 235Hb between multiple interlayer insulating layers (e.g., multiple first interlayer insulating layers 220a and multiple second interlayer insulating layers 220b). Therefore, a stacked structure SS comprising a first portion SSa and a second portion SSb can be formed, wherein the first portion SSa comprises first interlayer insulating layers 220a and first gate layers 230a alternately stacked above a common source line layer 210, and the second portion SSb comprises second interlayer insulating layers 220b and second gate layers 230b alternately stacked above the first portion SSa.

[0078] Reference Figure 3K This allows the formation of a first portion IL2a of the second insulating structure IL2, a second interconnect structure IC2, and multiple second bonding pads BP2. Therefore, a second insulating structure IL2 comprising a first portion IL2a, a second portion IL2b, and a third portion IL2c can be completed.

[0079] Reference Figure 3K and Figure 3L The second substrate 215 can be removed from the common source line layer 210 and the second insulating structure IL2. A low-resistance conductive layer 270 on the common source line layer 210, the second insulating structure IL2 and the third insulating structure IL3 on the low-resistance conductive layer 270, and input / output pads 290 passing through the third insulating structure IL3 can be formed. Therefore, the second structure S2 can be completed.

[0080] Reference Figure 3M A peripheral circuit PC including multiple transistors 120 can be formed on the first substrate 110. Next, a first insulating structure IL1, a first interconnect structure IC1 in the first insulating structure IL1, and multiple first bonding pads BP1 on the first insulating structure IL1 can be formed on the first substrate 110 and the peripheral circuit PC. Thus, the first structure S1 can be completed.

[0081] Reference Figure 1A The first structure S1 can be bonded to the second structure S2, so that multiple first bonding pads BP1 respectively contact multiple second bonding pads BP2. Therefore, a non-volatile memory device 100 can be completed.

[0082] Figures 4A to 4J This is for describing the manufacture of a non-volatile memory device 100A according to an embodiment of the present invention (see [link]). Figure 2B A cross-sectional view of the method.

[0083] Reference Figure 4A According to reference Figures 3A to 3DThe described operations can form a common source line layer 210 on the second substrate 215, a lower sacrificial layer 255 on the common source line layer 210, a lower support layer 260 on the lower sacrificial layer 255, an initial stacked structure PS on the lower support layer 260, and a channel structure 240 through the initial stacked structure PS (see [link]). Figure 3D The third portion IL2c of the second insulating structure on the second substrate 215, and the second portion IL2b of the second insulating structure on the initial stacked structure PS. A dummy channel structure 280 may not be formed (see...). Figure 3E The virtual channel structure 280 can be formed by a structure identical to that of the channel structure 240, or it can be as follows: Figure 3E The diagram shows a dummy channel structure 280. The initial stacked structure PS may include multiple interlayer insulating layers 220 and multiple sacrificial layers 235 alternately stacked on the lower support layer 260. Although... Figure 4A Not shown, but according to reference Figures 3A to 3D The described operation can pattern the step region EXT of the initial stacked structure PS to have a step shape.

[0084] Reference Figure 4B It can form a second part IL2b that passes through the lower support layer 260, the initial stacked structure PS, and the second insulating structure and exposes the word line cut-out portion WSH and the dummy word line cut-out portion DWSH of the lower sacrificial layer 255.

[0085] Reference Figure 4C A separator layer SP can be formed on the sidewalls of the word line cut portion WSH and the dummy word line cut portion DWSH. For example, the separator layer SP can be formed on the sidewalls and bottom of the word line cut portion WSH and the dummy word line cut portion DWSH, as well as on the upper surface of the second portion IL2b of the second insulating structure. The portion of the separator layer SP located at the bottom of the word line cut portion WSH and the dummy word line cut portion DWSH, as well as on the upper surface of the second portion IL2b of the second insulating structure, can be removed by anisotropic etching.

[0086] Reference Figure 4C and Figure 4D This can remove the lower sacrificial layer 255. For example... Figure 3G As shown, the gate insulating layer 241 can be etched to expose the channel layer 242. Next, the lower conductive layer 250 can be filled in the space where the lower sacrificial layer 255 has been removed. Next, the separator layer SP can be removed from the sidewalls of the word line cutout (WSH) and the dummy word line cutout (DWSH). Next, multiple spaces 235H can be formed between the multiple interlayer insulating layers 220 by removing the multiple sacrificial layers 235.

[0087] Reference Figure 4Dand Figure 4E Multiple gate layers 230 can be filled in multiple spaces 235H between multiple interlayer insulating layers 220. Therefore, a stacked structure SS comprising multiple gate layers 230 and multiple interlayer insulating layers 220 alternately stacked on a lower support layer 260 can be completed.

[0088] Reference Figure 4F The filler layer WSF and the dummy filler layer DWSF can be filled in the word line cut-out portion WSH and the dummy word line cut-out portion DWSH, respectively. In some embodiments, the filler layer WSF and the dummy filler layer DWSF may include polysilicon.

[0089] Reference Figure 4F and Figure 4G The fill layer WSF is removed from the word line cut section WSH. To limit and / or prevent the removal of the dummy fill layer DWSF, a mask can be formed to cover the dummy fill layer DWSF and expose the fill layer WSF before the fill layer WSF is removed. This mask can be removed after the fill layer WSF is removed. After the fill layer WSF is removed, the word line cut structure WS can be formed in the word line cut section WSH.

[0090] Reference Figure 4G and Figure 4H The dummy filler layer DWSF is removed from the dummy word line cutout portion DWSH. Next, an insulating layer DWSb can be formed on the sidewall of the dummy word line cutout portion DWSH. For example, the insulating layer DWSb can be formed on the sidewall and bottom of the dummy word line cutout portion DWSH and on the upper surface of the second portion IL2b of the second insulating structure, and the portion of the insulating layer DWSb located at the bottom of the dummy word line cutout portion DWSH and on the upper surface of the second portion IL2b of the second insulating structure can be removed by anisotropic etching. Next, a conductive layer DWSa can be formed on the insulating layer DWSb. The conductive layer DWSa can fill the dummy word line cutout portion DWSH and the insulating layer DWSb.

[0091] Reference Figure 4I This allows the formation of a first portion IL2a of the second insulating structure, a second interconnect structure IC2, and multiple second bonding pads BP2. Therefore, a second insulating structure IL2 comprising the first portion IL2a, the second portion IL2b, and the third portion IL2c can be completed.

[0092] Reference Figure 4I and Figure 4JThe second substrate 215 can be removed from the common source line layer 210 and the second insulating structure IL2. A low-resistance conductive layer 270 on the common source line layer 210, the second insulating structure IL2 and the third insulating structure IL3 on the low-resistance conductive layer 270, and input / output pads 290 passing through the third insulating structure IL3 can be formed. Therefore, the second structure S2A can be completed.

[0093] For reference Figure 3M As described, the first structure S1 can be prepared. Next, refer to... Figure 2B The first structure S1 can be bonded to the second structure S2A, so that multiple first bonding pads BP1 respectively contact multiple second bonding pads BP2. Therefore, a non-volatile memory device 100A can be completed.

[0094] Figure 5 This is a schematic diagram of a memory system 1000 including a non-volatile memory device according to an embodiment of the present invention.

[0095] Reference Figure 5 The memory system 1000 may include one or more memory devices 1100 and a memory controller 1200 electrically connected to the memory devices 1100. The memory system 1000 may be, for example, a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device that includes at least one memory device 1100.

[0096] Memory device 1100 may be a non-volatile memory device. For example, memory device 1100 may be a reference. Figures 1A to 2B The described non-volatile memory devices 1100 and 100A are NAND flash memory devices, or combinations thereof. Memory device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. The first structure 1100F may correspond to... Figure 1A and Figure 2B The first structure S1 shown is shown. Figure 1A and Figure 2B The peripheral circuit PC shown may include a line decoder 1110, a page buffer 1120, and logic circuit 1130.

[0097] The second structure 1100S can correspond to Figure 1A and Figure 2B The second structures S2 and S2A are shown. The second structure 1100S may include a bit line BL, a common source line CSL, multiple word lines WL, string select lines UL1 and UL2, ground select lines LL1 and LL2, and multiple memory cell strings CSTR between the bit line BL and the common source line CSL. Figure 1A and Figure 2B The second interconnect structure IC2 shown may include bit lines BL, word lines WL, serial select lines UL1 and UL2, and ground select lines LL1 and LL2. Channel structure 240 and multiple gate layers (e.g., Figure 1A The plurality of first gate layers 230a and the plurality of second gate layers 230b shown herein Figure 2B The multiple gate layers 230 shown can form a memory cell string CSTR. Figure 1A and Figure 2B The common source line layer 210 and the low-resistance conductive layer 270 shown can correspond to the common source line CSL.

[0098] In the second structure 1100S, each of the plurality of memory cell strings CSTRs may include ground select transistors LT1 and LT2 adjacent to the common source line CSL, string select transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the ground select transistors LT1 and LT2 and the string select transistors UT1 and UT2. The number of ground select transistors LT1 and LT2 and the number of string select transistors UT1 and UT2 may be modified differently depending on the embodiment. Channel structure 240 and a plurality of gate layers (e.g., Figure 1A The plurality of first gate layers 230a and the plurality of second gate layers 230b shown herein Figure 2B One of the multiple gate layers 230 shown can form one of multiple transistors (e.g., ground select transistor, string select transistor, and memory cell transistors LT1, LT2, UT1, UT2 and MCT).

[0099] In this embodiment, multiple ground select lines LL1 and LL2 can be connected to the gate electrodes of ground select transistors LT1 and LT2, respectively. A word line WL can be connected to the gate electrode of the memory cell transistor MCT. Multiple string select lines UL1 and UL2 can be connected to the gate electrodes of string select transistors UT1 and UT2, respectively.

[0100] The common source line CSL, multiple ground select lines LL1 and LL2, multiple word lines WL, and multiple serial select lines UL1 and UL2 can be connected to the line decoder 1110. Multiple bit lines BL can be electrically connected to the page buffer 1120.

[0101] The memory device 1100 can communicate with the memory controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130. The input / output pads 1101 can be... Figure 1A and Figure 2B The input / output pad 290 is shown.

[0102] The memory controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (host I / F) 1230. In some embodiments, the memory system 1000 may include a plurality of memory devices 1100, and in this case, the memory controller 1200 may control the plurality of memory devices 1100.

[0103] Processor 1210 can control the overall operation of memory system 1000, including memory controller 1200. Processor 1210 can operate according to certain firmware and can access memory device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface (NANDI / F) 1221 for handling communication with memory device 1100. Control commands for controlling memory device 1100, data to be written to multiple memory cell transistors (MCTs) of memory device 1100, and data to be read from multiple memory cell transistors (MCTs) of memory device 1100 can be transmitted through NAND interface 1221. Host interface 1230 provides communication functionality between memory system 1000 and external host. When a control command is received from an external host through host interface 1230, processor 1210 can control memory device 1100 in response to the control command.

[0104] Figure 6 This is a schematic perspective view of a memory system 2000 including a non-volatile memory device according to an embodiment of the present invention.

[0105] Reference Figure 6 A memory system 2000 according to an embodiment of the present invention may include a main substrate 2001, a memory controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and dynamic random access memory (DRAM) 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the memory controller 2002 via a plurality of wiring patterns 2005 formed on the main substrate 2001.

[0106] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the memory system 2000 and the external host. In an embodiment, the memory system 2000 may communicate with the external host via one of an interface such as USB, Peripheral Component Interconnect High Speed ​​(PCI-Express), Serial Advanced Technology Attachment (SATA), and M-PHY equivalent to Universal Flash Memory (UFS). In an embodiment, the memory system 2000 may operate using power received from the external host via the connector 2006. The memory system 2000 may also include a power management integrated circuit (PMIC) for distributing the power received from the external host to the memory controller 2002 and the semiconductor package 2003.

[0107] The memory controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the memory system 2000.

[0108] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 included in memory system 2000 can also operate as a type of cache memory and can provide space for temporary data storage during control operations on semiconductor package 2003. When memory system 2000 includes DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003, memory controller 2002 may also include a DRAM controller for controlling DRAM 2004.

[0109] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a plurality of semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the plurality of semiconductor chips 2200, a connection structure 2400 electrically connecting the plurality of semiconductor chips 2200 and the package substrate 2100 to each other, and a molding layer 2500 above the package substrate 2100 and covering the plurality of semiconductor chips 2200 and the connection structure 2400.

[0110] The package substrate 2100 can be a printed circuit board including multiple package-on-package pads 2130. Each of the multiple semiconductor chips 2200 can include an input / output pad 2210. The input / output pad 2210 can correspond to... Figure 1A and Figure 2B Input / output pads 290. Each of the plurality of semiconductor chips 2200 may include references. Figures 1A to 2B At least one of the described non-volatile memory devices 100 and 100A.

[0111] In one embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 and the on-package pads 2130 to each other. Therefore, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via a bonding wire method and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In another embodiment, in the first semiconductor package 2003a and the second semiconductor package 2003b, a plurality of semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a connection structure 2400 using a bonding wire method.

[0112] In one embodiment, the memory controller 2002 and the plurality of semiconductor chips 2200 may be included in a single package. In another embodiment, the memory controller 2002 and the plurality of semiconductor chips 2200 may be mounted on a separate insertion substrate, different from the main substrate 2001, and the memory controller 2002 and the plurality of semiconductor chips 2200 may be interconnected by wiring formed on the insertion substrate.

[0113] Figure 7 This is a schematic cross-sectional view of a semiconductor package 2003 according to an embodiment of the present invention.

[0114] Reference Figure 7 In the semiconductor package 2003, the package substrate 2100 can be a printed circuit board. The package substrate 2100 may include a package substrate body portion 2120 and a plurality of package pads 2130 disposed on the upper surface of the package substrate body portion 2120 (see [reference]). Figure 6 ), a plurality of lower pads 2125 disposed on or exposed through the lower surface of the package substrate body portion 2120, and a plurality of upper pads 2130 disposed in the package substrate body portion 2120 (see Figure 6 Multiple internal wirings 2135 electrically connected to each other, including multiple lower pads 2125. (e.g.) Figure 6 As shown, multiple package pads 2130 can be electrically connected to multiple connection structures 2400. For example... Figure 7As shown, multiple lower pads 2125 can be connected to multiple conductive bumps 2800. Figure 6 The memory system 2000 shown has multiple wiring patterns 2005 on its main substrate 2001. Each of the multiple semiconductor chips 2200 may include reference... Figures 1A to 2B The non-volatile memory devices 100 and 100A are described.

[0115] One or more of the elements disclosed above may include or be implemented in processing circuitry (such as hardware including logic circuitry; hardware / software combination such as a processor executing software; or a combination thereof). For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0116] Although embodiments of the inventive concept have been specifically shown and described with reference to the given examples, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A non-volatile memory device, comprising: A first structure includes a first substrate, peripheral circuitry on the first substrate, a first insulating structure on the first substrate and the peripheral circuitry, a plurality of first bonding pads on the first insulating structure, and a first interconnect structure located in the first insulating structure and connected to the peripheral circuitry and the plurality of first bonding pads. as well as A second structure, bonded to the first structure, includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stacked structure including multiple gate layers and multiple interlayer insulating layers alternately stacked above the common source line layer, multiple channel structures passing through cell regions of the stacked structure and contacting the common source line layer, a dummy channel structure passing through step regions of the stacked structure and contacting the common source line layer, a second insulating structure on the stacked structure, multiple second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure. The second interconnect structure is connected to the plurality of gate layers, the plurality of channel structures, the dummy channel structure, and the plurality of second bonding pads. The plurality of second bonding pads respectively contact the plurality of first bonding pads, and The stepped area of ​​the stacked structure is located on one side of the unit area of ​​the stacked structure and has a stepped shape.

2. The non-volatile memory device according to claim 1, wherein, The dummy channel structure connects the common source line layer to the peripheral circuit through the second interconnect structure, the plurality of second bonding pads, the plurality of first bonding pads, and the first interconnect structure.

3. The non-volatile memory device according to claim 1, wherein, The material of the low-resistivity conductive layer has a lower resistivity than the material of the common source electrode layer.

4. The non-volatile memory device according to claim 1, wherein, The low-resistance conductive layer comprises a metal, and The common source line layer comprises polycrystalline silicon.

5. The non-volatile memory device according to claim 1, wherein, The virtual channel structure includes a conductive layer and an insulating layer. The conductive layer contacts the common source line layer, and The insulating layer is located between the conductive layer and the stepped region of the stacked structure.

6. The non-volatile memory device according to claim 5, wherein, The conductive layer comprises polycrystalline silicon.

7. The non-volatile memory device according to claim 1, further comprising: The lower conductive layer is located between the common source line layer and the stacked structure.

8. The non-volatile memory device according to claim 7, wherein, Each of the plurality of channel structures includes a channel layer and a gate insulating layer. The gate insulating layer is located between the channel layer and the cell region of the stacked structure, and The lower conductive layer passes through the gate insulating layer and contacts the channel layer.

9. The non-volatile memory device according to claim 8, wherein, The gate insulating layer also extends between the common source line layer and the channel layer.

10. A non-volatile memory device, comprising: A first structure includes a first substrate, peripheral circuitry on the first substrate, a first insulating structure on the first substrate and the peripheral circuitry, a plurality of first bonding pads on the first insulating structure, and a first interconnect structure located in the first insulating structure and connected to the peripheral circuitry and the plurality of first bonding pads. as well as A second structure, bonded to the first structure, includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stacked structure including multiple gate layers and multiple interlayer insulating layers alternately stacked above the common source line layer, multiple channel structures passing through cell regions of the stacked structure and contacting the common source line layer, a word line cut structure passing through the stacked structure and elongated in a first direction, a dummy word line cut structure passing through the stacked structure, a second insulating structure on the stacked structure, multiple second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure. The second interconnect structure is connected to the plurality of gate layers, the plurality of channel structures, the dummy word wire cut structure, and the plurality of second bonding pads. The dummy word line cut structure makes an electrical contact with the common source line layer and is elongated in the first direction. The plurality of first bonding pads respectively contact the plurality of second bonding pads, and The stepped area of ​​the stacked structure is located on one side of the unit area of ​​the stacked structure and has a stepped shape.

11. The non-volatile memory device according to claim 10, wherein, The word line cutting structure passes through the unit area and step area of ​​the stacked structure in the first direction.

12. The non-volatile memory device according to claim 10, wherein, The dummy word line cutting structure is located in the stepped region of the stacked structure and does not pass through the unit region of the stacked structure.

13. The non-volatile memory device according to claim 10, wherein, The word line cutting structure includes insulating material.

14. The non-volatile memory device according to claim 10, wherein, The virtual character wire-cutting structure includes a conductive layer and an insulating layer. The conductive layer is in electrical contact with the common source line layer, and The insulating layer is located between the conductive layer and the stacked structure.

15. The non-volatile memory device according to claim 14, wherein, The conductive layer comprises polycrystalline silicon.

16. The non-volatile memory device of claim 10, further comprising: A lower conductive layer is located between the common source line layer and the stacked structure; as well as A lower support layer is located between the stacked structure and the lower conductive layer. The character line cutting structure and the dummy character line cutting structure also pass through the lower support layer.

17. A memory system comprising: A non-volatile memory device comprising a first structure and a second structure bonded to the first structure; as well as A memory controller, electrically connected to the non-volatile memory device and configured to control the non-volatile memory device, wherein... The first structure includes a first substrate, peripheral circuitry on the first substrate, a first insulating structure on the first substrate and the peripheral circuitry, a plurality of first bonding pads on the first insulating structure, and a first interconnect structure in the first insulating structure. The first interconnect structure is connected to the peripheral circuit and the plurality of first bonding pads. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stacked structure including multiple gate layers and multiple interlayer insulating layers alternately stacked above the common source line layer, multiple channel structures passing through cell regions of the stacked structure and contacting the common source line layer, a word line dicing structure passing through the stacked structure and elongated in a first direction, a common source line contact passing through the stacked structure and electrically contacting the common source line layer, a second insulating structure on the stacked structure, multiple second bonding pads on the second insulating structure, input / output pads connected to the memory controller, and a second interconnect structure in the second insulating structure. The second interconnect structure is connected to the plurality of gate layers, the plurality of channel structures, the common source line contact, the input / output pads, and the plurality of second bonding pads. The plurality of first bonding pads respectively contact the plurality of second bonding pads, and The stepped area of ​​the stacked structure is located on one side of the unit area of ​​the stacked structure and has a stepped shape.

18. The memory system according to claim 17, wherein, The common source line contact includes a dummy channel structure, and The dummy channel structure passes through the stepped region of the stacked structure and makes electrical contact with the common source line layer.

19. The memory system according to claim 17, wherein, The common source line contact includes a dummy word line cutting structure. The dummy word line cut structure passes through the stepped region of the stacked structure and makes electrical contact with the common source line layer. The virtual character line-cutting structure is elongated in the first direction.

20. The memory system according to claim 17, wherein, The common source line contact includes a conductive layer and an insulating layer. The conductive layer is in electrical contact with the common source line layer, and The insulating layer is located between the conductive layer and the stepped region of the stacked structure.

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