Array substrate, method for manufacturing array substrate, and display device

Abstract

This application discloses an array substrate, a method for fabricating the array substrate, and a display device. The array substrate includes a substrate, a gate, and an oxide semiconductor layer. The gate and the oxide semiconductor layer are disposed on the same side of the substrate, and the projections of the gate and the oxide semiconductor layer onto the substrate at least partially overlap, and the gate and the oxide semiconductor layer are spaced apart. The material of the oxide semiconductor layer includes modified metal elements, and the proportion of modified metal elements in all metal elements gradually decreases from the gate towards the oxide semiconductor layer, which can solve the technical problems of poor stability and low mobility of metal oxide thin film transistors.

Description

Technical Field

[0001] This application relates to the field of display, specifically to an array substrate, a method for manufacturing the array substrate, and a display device. Background Technology

[0002] As display panels evolve towards larger sizes, higher resolutions, higher frequencies, and self-emissive display modes (OLED, MiniLED, MicroLED), increasingly higher demands are being placed on the mobility and stability of thin-film transistors (TFTs) that control the switching and driving of the display. Currently, the amorphous silicon TFTs commonly used in the display industry have low mobility and low on-state current (Ion), which cannot meet the needs of high-end display products (manifested as insufficient charging of LCDs, or insufficient brightness of OLEDs, MiniLEDs, and MicroLEDs). In contrast, metal oxide TFTs have a mobility 10-100 times higher than amorphous silicon TFTs, which can meet the needs of new high-end display products. Therefore, metal oxide TFTs and their display panels are receiving increasing attention from the industry.

[0003] However, compared to low-temperature polycrystalline silicon thin-film transistors, metal oxide thin-film transistors have poorer stability and lower mobility. Summary of the Invention

[0004] This application provides an array substrate, a method for fabricating the array substrate, and a display device, which can solve the technical problems of poor stability and low mobility of metal oxide thin film transistors.

[0005] This application provides an array substrate, including:

[0006] substrate;

[0007] Oxide semiconductor layer;

[0008] A gate, wherein the gate and the oxide semiconductor layer are disposed on the same side of the substrate, the projections of the gate and the oxide semiconductor layer on the substrate at least partially overlap, and the gate and the oxide semiconductor layer are spaced apart;

[0009] The oxide semiconductor layer is made of modified metal elements, and the proportion of the modified metal elements in all metal elements gradually decreases from the gate towards the oxide semiconductor layer.

[0010] Optionally, in some embodiments of this application, the material of the oxide semiconductor layer is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide;

[0011] The modified metal element is aluminum, and the proportion of aluminum in all metal elements gradually decreases from the gate towards the oxide semiconductor layer.

[0012] Optionally, in some embodiments of this application, the material of the oxide semiconductor layer is selected from at least one of indium zinc oxide, indium tin zinc oxide, and indium gallium zinc oxide;

[0013] The modified metal element is indium, and the proportion of indium in all metal elements gradually decreases from the gate towards the oxide semiconductor layer.

[0014] Optionally, in some embodiments of this application, the gate is disposed on the substrate, and the array substrate further includes:

[0015] A gate insulating layer is disposed on the substrate and covers the gate; an oxide semiconductor layer is disposed on the gate insulating layer and is correspondingly disposed to the gate; and

[0016] The source and drain are disposed at a distance between the gate insulating layer and the oxide semiconductor layer, with the source connected to one end of the oxide semiconductor layer and the drain connected to the other end of the oxide semiconductor layer.

[0017] Optionally, in some embodiments of this application, the oxide semiconductor layer is disposed on the substrate, and the array substrate further includes:

[0018] A gate insulating layer is disposed on the oxide semiconductor layer, and the gate is disposed on the gate insulating layer;

[0019] An interlayer insulating layer covers the gate, the gate insulating layer, and the oxide semiconductor layer; and

[0020] The source and drain are disposed on the interlayer insulating layer, with the source connected to one end of the oxide semiconductor layer and the drain connected to the other end of the oxide semiconductor layer.

[0021] This application also provides a method for fabricating an array substrate, comprising the following steps:

[0022] A diffusion layer is formed on a substrate, wherein the material of the diffusion layer includes modified metal elements;

[0023] A metal oxide layer is formed on the substrate, the metal oxide layer covering the diffusion layer, and the material of the metal oxide layer includes at least two metal elements;

[0024] The diffusion layer and the metal oxide layer are heat-treated, and the modified metal element diffuses into the metal oxide layer, so that the proportion of the modified metal element in the metal oxide layer among all metal elements gradually decreases from the substrate toward the metal oxide layer, thereby obtaining an oxide semiconductor layer.

[0025] Optionally, in some embodiments of this application, the step of forming a diffusion layer on the substrate includes:

[0026] A metal layer is formed on a substrate, wherein the material of the metal layer includes the modified metal element;

[0027] The metal layer is heat-treated to transform it into multiple metal particles, forming the diffusion layer.

[0028] Optionally, in some embodiments of this application, the thickness of the metal layer is less than or equal to 10 nanometers.

[0029] Optionally, in some embodiments of this application, the metal layer is an aluminum layer, the modified metal element is aluminum, and the material of the metal oxide layer is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide.

[0030] Optionally, in some embodiments of this application, the metal layer is an indium layer, the modified metal element is indium, and the material of the metal oxide layer is selected from at least one of indium zinc oxide, indium tin zinc oxide, and indium gallium zinc oxide.

[0031] This application also provides a method for fabricating an array substrate, comprising the following steps:

[0032] A metal oxide layer is formed on the substrate, wherein the material of the metal oxide layer comprises at least two metal elements;

[0033] A diffusion layer is formed on a metal oxide layer, wherein the material of the diffusion layer includes modified metal elements;

[0034] The diffusion layer and the metal oxide layer are heat-treated, and the modified metal element diffuses into the metal oxide layer, so that the proportion of the modified metal element in the metal oxide layer among all metal elements gradually decreases from the metal oxide layer toward the substrate, thereby obtaining an oxide semiconductor layer.

[0035] Optionally, in some embodiments of this application, the step of forming a diffusion layer on the metal oxide layer includes:

[0036] A metal layer is formed on a metal oxide layer, wherein the material of the metal layer includes the modified metal element;

[0037] The metal layer is heat-treated to transform it into multiple metal particles, forming the diffusion layer.

[0038] Optionally, in some embodiments of this application, the thickness of the metal layer is less than or equal to 10 nanometers.

[0039] Optionally, in some embodiments of this application, the metal layer is an aluminum layer, the modified metal element is aluminum, and the material of the metal oxide layer is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide.

[0040] Optionally, in some embodiments of this application, the metal layer is an indium layer, the modified metal element is indium, and the material of the metal oxide layer is selected from at least one of indium zinc oxide, indium tin zinc oxide, and indium gallium zinc oxide.

[0041] This application also provides a display device, which includes a counter substrate, a liquid crystal layer and an array substrate as described above, wherein the counter substrate and the array substrate are disposed opposite to each other and the liquid crystal layer is disposed between the counter substrate and the array substrate.

[0042] This application embodiment employs an array substrate, an array substrate fabrication method, and a display device. By gradually decreasing the proportion of modified metal elements in the oxide semiconductor layer from the gate towards the oxide semiconductor layer, a concentration gradient of modified metal elements is formed in the oxide semiconductor layer. The modified metal element content is higher on the side of the oxide semiconductor layer closer to the gate, which is beneficial to improving mobility; the modified metal element content is lower on the side of the oxide semiconductor layer away from the gate, which is beneficial to improving stability, thus achieving the effect of a multilayer metal oxide semiconductor. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a cross-sectional view of the first type of array substrate provided in the embodiments of this application;

[0045] Figure 2 This is a cross-sectional view of the second type of array substrate provided in the embodiments of this application;

[0046] Figure 3 This is a schematic flowchart of the first method for fabricating an array substrate provided in the embodiments of this application;

[0047] Figure 4 This is a schematic diagram of a gate, a gate insulating layer and a metal layer sequentially formed on a substrate according to an embodiment of this application;

[0048] Figure 5 This is a schematic diagram illustrating the conversion of a metal layer into a diffusion layer, provided in an embodiment of this application.

[0049] Figure 6 This is a schematic diagram of forming a metal oxide layer on a diffusion layer provided in an embodiment of this application;

[0050] Figure 7 This is a schematic diagram of heat treatment of the diffusion layer and the metal oxide layer thereon to form an oxide semiconductor layer, provided in an embodiment of this application.

[0051] Figure 8 This is a schematic flowchart of a second method for fabricating an array substrate provided in an embodiment of this application;

[0052] Figure 9 This is a schematic diagram of a metal oxide layer and a metal layer sequentially formed on a substrate, provided in an embodiment of this application;

[0053] Figure 10 This is a schematic diagram illustrating the conversion of a metal layer on a metal oxide layer into a diffusion layer, provided in an embodiment of this application.

[0054] Figure 11 This is a schematic diagram of heat treatment of a metal oxide layer and a diffusion layer thereon to form an oxide semiconductor layer, provided in an embodiment of this application.

[0055] Figure 12 This is a schematic diagram showing the sequential formation of a gate insulating layer and a gate on an oxide semiconductor layer, as provided in an embodiment of this application.

[0056] Figure 13 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0058] This application provides an array substrate, a method for manufacturing the array substrate, and a display device. These will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0059] Please see Figure 1 and Figure 2 This application provides an array substrate, including a substrate 10, a gate 30, and an oxide semiconductor layer 20. The gate 30 and the oxide semiconductor layer 20 are disposed on the same side of the substrate 10, and their projections on the substrate 10 at least partially overlap. The gate 30 and the oxide semiconductor layer 20 are spaced apart, meaning they are disposed in different layer structures, and an insulating layer is provided between them. The oxide semiconductor layer 20 is made of a modified metal element, and the proportion of the modified metal element in all metal elements gradually decreases from the gate 30 towards the oxide semiconductor layer 20. In this embodiment, the oxide semiconductor layer 20 is made of at least two metal elements, one of which is a modified metal element.

[0060] In the array substrate of this application embodiment, by making the proportion of modified metal elements in all metal elements in the oxide semiconductor layer 20 gradually decrease from the gate 30 toward the oxide semiconductor layer 20, that is, the modified metal elements in the oxide semiconductor layer 20 form a concentration gradient. Specifically, the content of modified metal elements on the side of the oxide semiconductor layer 20 closer to the gate 30 is higher, which is beneficial to improving mobility; the content of modified metal elements on the side of the oxide semiconductor layer 20 away from the gate 30 is lower, which is beneficial to improving stability, thus achieving the effect of a multilayer metal oxide semiconductor.

[0061] Specifically, the material of the oxide semiconductor layer 20 is selected from metal oxides. The metal oxide can be a metal oxide containing aluminum, where aluminum is the modified metal element. For example, the material of the oxide semiconductor layer 20 is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide. Of course, depending on the actual situation and specific requirements, the material of the oxide semiconductor layer 20 can also be a metal oxide containing other metal elements. This is not a unique limitation.

[0062] Specifically, when the material of the oxide semiconductor layer 20 is selected from metal oxides containing aluminum, for example, the material of the oxide semiconductor layer 20 is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide, the proportion of aluminum in all metal elements gradually decreases from the gate 30 toward the oxide semiconductor layer 20.

[0063] Specifically, the metal oxide can be a metal oxide containing indium, where indium is a modified metal element. For example, the material of the oxide semiconductor layer 20 is selected from at least one of indium zinc oxide, indium tin zinc oxide, and indium gallium zinc oxide. Of course, depending on the actual situation and specific requirements, the material of the oxide semiconductor layer 20 can also be a metal oxide containing other metal elements, and this is not a unique limitation.

[0064] Specifically, when the material of the oxide semiconductor layer 20 is selected from metal oxides containing indium, for example, the material of the oxide semiconductor layer 20 is selected from at least one of indium zinc oxide, indium tin zinc oxide and indium gallium zinc oxide, the proportion of indium in all metal elements gradually decreases from the gate 30 toward the oxide semiconductor layer 20.

[0065] Specifically, such as Figure 1 As shown, the array substrate in this embodiment can be a bottom gate structure. The array substrate further includes a gate insulating layer 40, a source 51, and a drain 52. The gate 30 is disposed on the substrate 10, the gate insulating layer 40 is disposed on the substrate 10 and covers the gate 30, the oxide semiconductor layer 20 is disposed on the gate insulating layer 40, and the oxide semiconductor layer 20 is disposed corresponding to the gate 30. The source 51 and the drain 52 are disposed at intervals on the gate insulating layer 40 and the oxide semiconductor layer 20. The source 51 is connected to one end of the oxide semiconductor layer 20 through a via, and the drain 52 is connected to the other end of the oxide semiconductor layer 20 through a via.

[0066] It is understood that the specific structure of the array substrate in this application embodiment can be appropriately modified according to the actual situation and specific requirements, and is not limited here. For example, as Figure 2 As shown, the array substrate can be a top-gate structure. The array substrate also includes a gate insulating layer 40, an interlayer insulating layer 60, a source 51, and a drain 52. An oxide semiconductor layer 20 is disposed on the substrate 10. The gate insulating layer 40 is disposed on the oxide semiconductor layer 20. The gate 30 is disposed on the gate insulating layer 40. The interlayer insulating layer 60 covers the gate 30, the gate insulating layer 40, and the oxide semiconductor layer 20. The source 51 and the drain 52 are disposed on the interlayer insulating layer 60. The source 51 is connected to one end of the oxide semiconductor layer 20 through a via, and the drain 52 is connected to the other end of the oxide semiconductor layer 20 through a via.

[0067] Specifically, the oxide semiconductor layer 20 includes a channel region 21, which includes a front channel 211 and a back channel 212 stacked together. The front channel 211 is located on the side of the back channel 212 close to the gate 30. In the channel region 21, the proportion of the modified metal element in all metal elements gradually decreases from the front channel 211 toward the back channel 212.

[0068] In the channel region 21, the proportion of the modified metal element in all metal elements gradually decreases from the front channel 211 to the back channel 212; that is, the ratio of the mass of the modified metal element to the total mass of all metal elements gradually decreases from the front channel 211 to the back channel 212. For example, when the material of the oxide semiconductor layer 20 includes a modified metal element and a first metal element, the ratio of the mass of the modified metal element to the total mass of all metal elements (the sum of the mass of the modified metal element and the mass of the first metal element) is the proportion of the modified metal element in all metal elements. In this embodiment, the material of the oxide semiconductor layer 20 includes at least two metal elements; that is, the material of the oxide semiconductor layer 20 may include two, three, or more metal elements, and is not limited to a single type.

[0069] Please see Figure 3 This application also provides a method for manufacturing an array substrate, which includes the following steps:

[0070] Step B1, as follows Figure 4 and Figure 5 As shown, a diffusion layer 223 is formed on the substrate 10, and the material of the diffusion layer 223 includes modified metal elements;

[0071] Step B2, as follows Figure 6 As shown, a metal oxide layer 221 is formed on the substrate 10, and the metal oxide layer 221 covers the diffusion layer 223. The material of the metal oxide layer 221 includes at least two metal elements, and the metal oxide layer 221 can be obtained by deposition and patterning processes, but is not limited to.

[0072] Step B3, as follows Figure 7 As shown, the diffusion layer 223 and the metal oxide layer 221 are heat-treated to allow the modified metal element to diffuse into the metal oxide layer 221, so that the proportion of the modified metal element in the metal oxide layer 221 in all metal elements gradually decreases from the substrate 10 toward the metal oxide layer 221, thereby obtaining the oxide semiconductor layer 20.

[0073] In the method for fabricating the array substrate according to the embodiments of this application, the modified metal element diffuses into the metal oxide layer 221 by heat treatment of the diffusion layer 223 and the metal oxide layer 221. During the diffusion process, the content of the modified metal element is high on the side of the metal oxide layer 221 closer to the diffusion layer 223 and low on the side of the metal oxide layer 221 farther from the diffusion layer 223, thereby forming a concentration gradient of the modified metal element in the metal oxide layer 221, thereby obtaining the oxide semiconductor layer 20.

[0074] The oxide semiconductor layer 20 obtained includes a channel region 21, which includes a front channel 211 and a back channel 212. The front channel 211 is located on the side of the back channel 212 near the gate 30. In the channel region 21, the proportion of modified metal elements in all metal elements gradually decreases from the front channel 211 to the back channel 212, that is, the modified metal elements in the channel region 21 form a concentration gradient. Specifically, the content of modified metal elements in the front channel 211 is higher, which is beneficial to improving mobility; the content of modified metal elements in the back channel 212 is lower, which is beneficial to improving stability, thus achieving the effect of a multilayer metal oxide semiconductor.

[0075] Specifically, step B1 above includes:

[0076] Step B11: Form a metal layer 222 on the substrate 10. Specifically, the metal layer 222 can be formed by physical vapor deposition, but is not limited to physical vapor deposition. The metal layer 222 is patterned. The material of the metal layer 222 includes modified metal elements.

[0077] Step B12: The metal layer 222 is heat-treated, transforming it into multiple metal particles 224 to form a diffusion layer 223. During the heat treatment of the metal layer 222, the grains in the metal layer 222 grow and accumulate, becoming spaced-apart metal particles 224. Each metal particle 224 includes an inner layer 225 and an outer layer 226, with the outer layer 226 enclosing the inner layer 225. The outer layer 226 is made of metal oxide, while the inner layer 225 is made of metal. Subsequently, in step B3, during the high-temperature baking process, the lattice of the metal particles 224 induces the crystallization behavior of the metal oxide layer 221, resulting in a slight crystallization phenomenon in the obtained oxide semiconductor layer 20. This reduces defect states and improves the stability of the device.

[0078] Optionally, in step B11 above, the metal layer 222 is an aluminum layer, and the modified metal element is aluminum; in step B2, the material of the metal oxide layer 221 is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide. In this embodiment, the material of the outer layer 226 of the metal particles 224 obtained in step B12 can be aluminum oxide, and the material of the inner layer 225 can be aluminum.

[0079] Optionally, in step B11 above, the metal layer 222 is an indium layer, and the modified metal element is indium; in step B2, the material of the metal oxide layer 221 is selected from at least one of indium zinc oxide, indium tin zinc oxide, and indium gallium zinc oxide. In this embodiment, the material of the outer layer 226 of the metal particles 224 obtained in step B12 can be indium oxide, and the material of the inner layer 225 can be indium.

[0080] It is understandable that the materials of the metal layer 222 and the metal oxide layer 221 can be appropriately modified according to the actual situation and specific requirements, and no single limitation is made here.

[0081] Specifically, in step B12 above, the temperature for heat treatment of metal layer 222 is 150 degrees Celsius to 350 degrees Celsius, and the time is 10 minutes to 2 hours. The specific operation of step B12 can be as follows: heat metal layer 222 in an air environment of 150 degrees Celsius to 350 degrees Celsius for 10 minutes to 2 hours.

[0082] Specifically, if the metal layer 222 is too thick, it will lead to the formation of an excessive diffusion layer 223. During the heat treatment of the diffusion layer 223 and the metal oxide layer 221 in step B3, the diffusion layer 223 cannot completely diffuse into the metal oxide layer 221, resulting in a metal diffusion layer 223 still being present on one side of the formed oxide semiconductor layer 20. This will cause the subsequent thin-film transistor to be unable to turn on and thus cause an abnormality. To avoid the above problem, in step B11, the thickness of the metal layer 222 is less than or equal to 10 nanometers. Within this thickness range, the technical problems of poor stability and low mobility of metal oxide thin-film transistors can be solved, and the metal diffusion layer 223 is avoided from still being present under the oxide semiconductor layer 20 after step B3.

[0083] Specifically, in step B3 above, the heat treatment temperature for the diffusion layer 223 and the metal oxide layer 221 is 250°C-450°C, and the time is 10 minutes-2 hours. The specific operation of step B3 can be as follows: heating the diffusion layer 223 and the metal oxide layer 221 in an air environment at 250°C-450°C for 10 minutes-2 hours.

[0084] Specifically, such as Figure 4 As shown, before the step of forming the metal layer 222 on the substrate 10, step B11 further includes:

[0085] A gate 30 and a gate insulating layer 40 are sequentially formed on the substrate 10. The gate insulating layer 40 is disposed on the substrate 10 and covers the gate 30. A metal layer 222 is subsequently formed on the gate insulating layer 40, and the metal layer 222 and the gate 30 are correspondingly disposed, that is, the metal layer 222 and the gate 30 at least partially overlap.

[0086] Specifically, such as Figure 1 and Figure 7 As shown, after step B3 above, the method for fabricating the array substrate further includes:

[0087] A source 51 and a drain 52 are formed on the gate insulating layer 40 and the oxide semiconductor layer 20, with the source 51 and drain 52 spaced apart. The source 51 is connected to one end of the oxide semiconductor layer 20 through a via, and the drain 52 is connected to the other end of the oxide semiconductor layer 20 through a via.

[0088] Please see Figure 8 This application also provides a method for manufacturing an array substrate, which includes the following steps:

[0089] Step B1', as follows Figure 9 As shown, a metal oxide layer 221 is formed on the substrate 10. The material of the metal oxide layer 221 includes at least two metal elements. Specifically, the metal oxide layer 221 can be formed by deposition and patterning.

[0090] Step B2', as follows Figure 9 and Figure 10 As shown, a diffusion layer 223 is formed on the metal oxide layer 221, and the material of the diffusion layer 223 includes modified metal elements;

[0091] Step B3', as follows Figure 11 As shown, the diffusion layer 223 and the metal oxide layer 221 are heat-treated to allow the modified metal element to diffuse into the metal oxide layer 221, so that the proportion of the modified metal element in the metal oxide layer 221 in all metal elements gradually decreases from the metal oxide layer 221 toward the substrate 10, thereby obtaining the oxide semiconductor layer 20.

[0092] In the method for fabricating the array substrate according to the embodiments of this application, the modified metal element diffuses into the metal oxide layer 221 by heat treatment of the diffusion layer 223 and the metal oxide layer 221. During the diffusion process, the content of the modified metal element is high on the side of the metal oxide layer 221 closer to the diffusion layer 223 and low on the side of the metal oxide layer 221 farther from the diffusion layer 223, thereby forming a concentration gradient of the modified metal element in the metal oxide layer 221, thereby obtaining the oxide semiconductor layer 20.

[0093] The oxide semiconductor layer 20 obtained includes a channel region 21, which includes a front channel 211 and a back channel 212. The front channel 211 is located on the side of the back channel 212 near the gate 30. In the channel region 21, the proportion of modified metal elements in all metal elements gradually decreases from the front channel 211 to the back channel 212, that is, the modified metal elements in the channel region 21 form a concentration gradient. Specifically, the content of modified metal elements in the front channel 211 is higher, which is beneficial to improving mobility; the content of modified metal elements in the back channel 212 is lower, which is beneficial to improving stability, thus achieving the effect of a multilayer metal oxide semiconductor.

[0094] Specifically, step B2' above includes:

[0095] Step B21': Form a metal layer 222 on the metal oxide layer 221. Specifically, the metal layer 222 can be formed by physical vapor deposition, but is not limited to physical vapor deposition. The metal layer 222 is patterned. The material of the metal layer 222 includes modified metal elements.

[0096] In step B22', the metal layer 222 is heat-treated, transforming it into multiple metal particles 224 to form a diffusion layer 223. During the heat treatment of the metal layer 222, the grains in the metal layer 222 grow and accumulate, becoming spaced-apart metal particles 224. Each metal particle 224 includes an inner layer 225 and an outer layer 226, with the outer layer 226 enclosing the inner layer 225. The outer layer 226 is made of metal oxide, while the inner layer 225 is made of metal. Subsequently, in step B3, during the high-temperature baking process, the lattice of the metal particles 224 induces the crystallization behavior of the metal oxide layer 221, resulting in a slight crystallization phenomenon in the obtained oxide semiconductor layer 20. This reduces defect states and improves the stability of the device.

[0097] Optionally, in step B21' above, the metal layer 222 is an aluminum layer, and the modified metal element is aluminum; in step B1', the material of the metal oxide layer 221 is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide. In this embodiment, the material of the outer layer 226 of the metal particles 224 obtained in step B22' can be aluminum oxide, and the material of the inner layer 225 can be aluminum.

[0098] Optionally, in step B21' above, the metal layer 222 is an indium layer, and the modified metal element is indium; in step B1', the material of the metal oxide layer 221 is selected from at least one of indium zinc oxide, indium tin zinc oxide, and indium gallium zinc oxide. In this embodiment, the material of the outer layer 226 of the metal particles 224 obtained in step B22' can be indium oxide, and the material of the inner layer 225 can be indium.

[0099] It is understandable that the materials of the metal layer 222 and the metal oxide layer 221 can be appropriately modified according to the actual situation and specific requirements, and no single limitation is made here.

[0100] Specifically, in step B22' above, the temperature for heat treatment of metal layer 222 is 150 degrees Celsius to 350 degrees Celsius, and the time is 10 minutes to 2 hours. The specific operation of step B22' can be as follows: heat metal layer 222 in an air environment of 150 degrees Celsius to 350 degrees Celsius for 10 minutes to 2 hours.

[0101] Specifically, if the metal layer 222 is too thick, it will lead to the formation of an excessive diffusion layer 223. During the heat treatment of the diffusion layer 223 and the metal oxide layer 221 in step B3, the diffusion layer 223 cannot completely diffuse into the metal oxide layer 221, resulting in a metal diffusion layer 223 still being present on one side of the oxide semiconductor layer 20. This will cause the subsequent thin-film transistor to be unable to turn on and thus cause an abnormality. To avoid the above problem, in step B21', the thickness of the metal layer 222 is less than or equal to 10 nanometers. Within this thickness range, the technical problems of poor stability and low mobility of metal oxide thin-film transistors can be solved, and the metal diffusion layer 223 is avoided from still being present under the oxide semiconductor layer 20 after step B3.

[0102] Specifically, in step B3 above, the heat treatment temperature for the diffusion layer 223 and the metal oxide layer 221 is 250°C-450°C, and the time is 10 minutes-2 hours. The specific operation of step B3 can be as follows: heating the diffusion layer 223 and the metal oxide layer 221 in an air environment at 250°C-450°C for 10 minutes-2 hours.

[0103] Specifically, such as Figure 9 As shown, before forming the metal oxide layer 221 on the substrate 10, step B1' further includes:

[0104] A buffer layer 70 is formed on the substrate 10, and a metal oxide layer 221 is subsequently formed on the buffer layer 70. This configuration can improve the adhesion of the metal oxide layer 221, so that the metal oxide layer 221 is stably disposed on the buffer layer 70.

[0105] Specifically, such as Figure 2 and Figure 12 As shown, after step B3' above, the method for fabricating the array substrate further includes:

[0106] A gate insulating layer 40 and a gate 30 are sequentially formed on the oxide semiconductor layer 20, and the projections of the gate 30 and the oxide semiconductor layer 20 onto the substrate 10 at least partially overlap.

[0107] An interlayer insulating layer 60 is formed on the gate 30 and the oxide semiconductor layer 20, and the interlayer insulating layer 60 covers the gate 30, the gate insulating layer 40 and the oxide semiconductor layer 20.

[0108] A source electrode 51 and a drain electrode 52 are formed on the interlayer insulating layer 60, with the source electrode 51 and the drain electrode 52 spaced apart. The source electrode 51 is connected to one end of the oxide semiconductor layer 20 through a via, and the drain electrode 52 is connected to the other end of the oxide semiconductor layer 20 through a via.

[0109] Table 1. Device performance of conventional thin-film transistors and thin-film transistors according to the embodiments of this application.

[0110]

[0111] As can be seen from Table 1, the thin-film transistors of the array substrate in this application embodiment have higher mobility and better stability compared to conventional thin-film transistors.

[0112] Please see Figure 13 This application also provides a display device, which includes a counter substrate 200, a liquid crystal layer 300 and an array substrate 100 as described above. The counter substrate 200 and the array substrate 100 are disposed at a distance from each other, and the liquid crystal layer 300 is disposed between the counter substrate 200 and the array substrate 100.

[0113] The above provides a detailed description of an array substrate, a method for manufacturing the array substrate, and a display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for fabricating an array substrate, characterized in that, Includes the following steps: A metal layer is formed on a substrate, wherein the material of the metal layer includes modified metal elements; The metal layer is heat-treated to transform it into multiple metal particles, forming a diffusion layer; wherein the thickness of the metal layer is less than or equal to 10 nanometers. A metal oxide layer is formed on the substrate, the metal oxide layer covering the diffusion layer, and the material of the metal oxide layer includes at least two metal elements; The diffusion layer and the metal oxide layer are heat-treated, and the modified metal element diffuses into the metal oxide layer, so that the proportion of the modified metal element in the metal oxide layer in all metal elements gradually decreases from the substrate towards the metal oxide layer, thereby obtaining an oxide semiconductor layer. Wherein, the metal layer is an aluminum layer, the modified metal element is aluminum, and the material of the metal oxide layer is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide.

2. A method for fabricating an array substrate, characterized in that, Includes the following steps: A metal oxide layer is formed on a substrate, wherein the material of the metal oxide layer comprises at least two metal elements; A metal layer is formed on the metal oxide layer, wherein the material of the metal layer includes modified metal elements; The metal layer is heat-treated to transform it into multiple metal particles, forming a diffusion layer; wherein the thickness of the metal layer is less than or equal to 10 nanometers. The diffusion layer and the metal oxide layer are heat-treated, and the modified metal element diffuses into the metal oxide layer, so that the proportion of the modified metal element in the metal oxide layer in all metal elements gradually decreases from the metal oxide layer toward the substrate, thereby obtaining an oxide semiconductor layer. Wherein, the metal layer is an aluminum layer, the modified metal element is aluminum, and the material of the metal oxide layer is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide.

3. An array substrate prepared by the fabrication method according to claim 1 or 2, characterized in that, The array substrate includes: substrate; Oxide semiconductor layer; A gate, wherein the gate and the oxide semiconductor layer are disposed on the same side of the substrate, the projections of the gate and the oxide semiconductor layer on the substrate at least partially overlap, and the gate and the oxide semiconductor layer are spaced apart; The oxide semiconductor layer is made of modified metal elements, and the proportion of the modified metal elements in all metal elements gradually decreases from the gate towards the oxide semiconductor layer.

4. The array substrate as described in claim 3, characterized in that, The material of the oxide semiconductor layer is selected from at least one of aluminum zinc oxide and aluminum gallium zinc oxide; The modified metal element is aluminum, and the proportion of aluminum in all metal elements gradually decreases from the gate towards the oxide semiconductor layer.

5. The array substrate as described in claim 3 or 4, characterized in that, The gate is disposed on the substrate, and the array substrate further includes: A gate insulating layer is disposed on the substrate and covers the gate; an oxide semiconductor layer is disposed on the gate insulating layer and is correspondingly disposed to the gate; and The source and drain are disposed at a distance between the gate insulating layer and the oxide semiconductor layer, with the source connected to one end of the oxide semiconductor layer and the drain connected to the other end of the oxide semiconductor layer.

6. The array substrate as described in claim 3 or 4, characterized in that, The oxide semiconductor layer is disposed on the substrate, and the array substrate further includes: A gate insulating layer is disposed on the oxide semiconductor layer, and the gate is disposed on the gate insulating layer; An interlayer insulating layer covers the gate, the gate insulating layer, and the oxide semiconductor layer; and The source and drain are disposed on the interlayer insulating layer, with the source connected to one end of the oxide semiconductor layer and the drain connected to the other end of the oxide semiconductor layer.

7. A display device, characterized in that, The display device includes a counter substrate, a liquid crystal layer, and an array substrate as described in any one of claims 3 to 6, wherein the counter substrate and the array substrate are disposed opposite to each other at a distance, and the liquid crystal layer is disposed between the counter substrate and the array substrate.

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