Display device

Abstract

A display device is provided. The display device includes a substrate, the substrate including an active region and a passive region. The display device also includes a transistor, an anode electrode, an organic light-emitting layer, and a cathode electrode disposed in the active region. The display device also includes circuit units, a dam, and a reference power voltage line disposed in the passive region. The reference power voltage line includes a first conductive layer to a third conductive layer, and the first conductive layer to the third conductive layer are formed in an overlapping manner.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0166082, filed with the Korean Intellectual Property Office on December 1, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices such as organic light-emitting display devices. Background Technology

[0004] In recent years, with the advent of the information age, the field of display technology, which visually expresses electrical information signals, has developed rapidly. In response, various display devices with excellent performance characteristics such as thinness, light weight, and low power consumption have been developed.

[0005] Specific examples of display devices may include liquid crystal display devices (LCD), organic light-emitting display devices (OLED), quantum dot display devices, etc.

[0006] Organic light-emitting diodes (OLEDs) are self-emissive devices that can be manufactured thin by using a thin light-emitting layer between electrodes. A typical organic light-emitting display device has a structure in which pixel driving circuitry and organic light-emitting diodes are formed on a substrate, and light emitted from the organic light-emitting diodes passes through the substrate or blocking layer to display an image.

[0007] Recently, with the reduction in size and increase in resolution of organic light-emitting display devices, the necessary wiring has increased, but the space available for wiring has become insufficient. In this situation, it is important to ensure sufficient space for the installation of various components, including wires. Furthermore, research has been conducted on methods for efficiently installing various parts and components. This research primarily focuses on new designs and UI / UX, and also aims to reduce the peripheral area of ​​display devices. Summary of the Invention

[0008] The purpose of this disclosure is to propose a peripheral structure for an organic light-emitting display device.

[0009] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art through the following description.

[0010] According to one aspect of this disclosure, the display device includes: a substrate including an active region and a passive region; a transistor, an anode electrode, an organic light-emitting layer, and a cathode electrode disposed in the active region; and a circuit unit, a dam, and a reference power voltage line disposed in the passive region, the reference power voltage line including a first conductive layer to a third conductive layer, and the first conductive layer to the third conductive layer being formed in an overlapping manner.

[0011] According to one aspect of this disclosure, the display device includes: a substrate including an active region and a passive region; a plurality of organic light-emitting diodes disposed in the active region; a plurality of trenches disposed in the passive region; and a reference power voltage line disposed in the passive region for providing reference power to drive the plurality of organic light-emitting diodes; wherein the reference power voltage line includes a first conductive layer, a second conductive layer, and a third conductive layer; the first conductive layer, the second conductive layer, and the third conductive layer are formed to overlap; and the second conductive layer contacts the first conductive layer and the third conductive layer at each of the plurality of trenches.

[0012] Further details of the exemplary embodiments are included in the detailed specification and accompanying drawings.

[0013] According to an exemplary embodiment of the display device based on the present disclosure, the structure of the reference power voltage line is modified to reduce voltage variations in each area of ​​the display panel due to resistance generated in the reference power voltage line.

[0014] According to the exemplary embodiment of the display device based on the present disclosure, the voltage change of the cathode electrode when the VSS rise phenomenon occurs can be reduced. Attached Figure Description

[0015] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a diagram showing the front surface of a display panel according to an exemplary embodiment of the present disclosure;

[0017] Figure 2 This shows the effect of magnification. Figure 1 A plan view of the active region of region A;

[0018] Figure 3 It is along Figure 1 A cross-sectional view of the passive region intercepted by the I-I' line;

[0019] Figure 4A and Figure 4B It's enlarged. Figure 1 A plan view of the reference power voltage lines in region B;

[0020] Figure 5 It is along Figure 4A A cross-sectional view of the reference power voltage line taken from line II-II';

[0021] Figure 6 It's enlarged. Figure 1 A plan view of another exemplary embodiment of the reference power voltage line in region B'; and

[0022] Figure 7 It is along Figure 6 A cross-sectional view of the reference power voltage line taken from line III-III'. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below and the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0024] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally indicate similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless explicitly stated otherwise, any reference to the singular may include the plural.

[0025] Even if not explicitly stated, components are interpreted as including the normal tolerance range.

[0026] When using terms such as “above,” “over,” “below,” and “adjacent” to describe the positional relationship between two parts, one or more parts may be located between the two parts unless the terms “immediately adjacent” or “directly” are used.

[0027] When an element or layer is placed "on" another element or layer, the other layer or element may be placed directly on or between the other element.

[0028] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0029] Throughout the specification, similar reference numerals generally denote similar elements.

[0030] The dimensions and thicknesses of each component shown in the accompanying drawings are for illustrative purposes only, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0031] Features of various embodiments of this disclosure may be partially or completely dependent on or combined with each other, and may be linked and operated in technically different ways, and may be implemented independently or in association with each other.

[0032] In this disclosure, the display device may include a liquid crystal module (LCM), an organic light-emitting display module (OLED module), and a quantum dot module (QD module). The liquid crystal module includes a display panel and a driver for driving the display panel. Furthermore, the display device may also include a device display device, which includes complete or final products of LCM, OLED, or QD modules, such as notebook computers, televisions, computer monitors, automotive display devices or other vehicle display devices, as well as set electronic devices or kit devices (kit devices) of mobile electronic devices such as smartphones or tablets.

[0033] Therefore, the display device according to this disclosure may include application products or kit devices, such as end products including LCM, OLED or QD modules and display devices such as LCM, OLED or QD modules.

[0034] If needed, an LCM, OLED, or QD module, driver, etc., configured as a display panel can be referred to as a "display device," and an electronic device comprising an LCM, OLED, or QD module as a final product can be referred to as a "kit device." For example, a display device may include an LCD, OLED, or QD display panel, and a source printed circuit board (source PCB) serving as a controller for driving the display panel. Simultaneously, a kit device may also include a kit PCB serving as a kit controller, electrically connected to the source PCB to control the entire kit device.

[0035] The display panel used in this exemplary embodiment can be any type of display panel, such as a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a quantum dot (QD) display panel, an electroluminescent display panel, etc. The display panel is not limited to a specific display panel including a flexible substrate for an OLED display panel and a backplate support structure disposed beneath the display panel, thereby enabling bezel bending. The display panel used in the display device according to the exemplary embodiment of this disclosure is not limited in shape and size.

[0036] More specifically, when the display panel is an OLED display panel, the display panel may include multiple gate lines, multiple data lines, and multiple pixels PXL disposed at various intersections between the gate lines and data lines. Additionally, the display panel may include: an array comprising thin-film transistors as elements for selectively applying voltage to each pixel; an OLED layer disposed on the array; and an encapsulation substrate or encapsulation layer disposed on the array to cover the OLED layer. The encapsulation layer protects the thin-film transistors and the OLED layer from external impacts and inhibits the permeation of moisture or oxygen into the OLED layer. Layers formed on the array may include inorganic light-emitting layers, such as nanoscale material layers or quantum dot layers.

[0037] In this instruction manual, Figure 1 An exemplary organic light-emitting diode (OLED) display panel that can be integrated into a display device is shown.

[0038] Figure 1 An exemplary display device that may be included in an electronic device is shown.

[0039] Reference Figure 1 The display device 100 includes at least one active region, and a pixel array is formed within the active region. One or more passive regions may be disposed around the active region. That is, the passive regions may be adjacent to one or more side surfaces of the active region. Figure 1 In this context, the passive region surrounds the quadrilateral active region. However, the shape of the active region, as well as the shape and arrangement of the passive regions adjacent to the active region, are not limited to... Figure 1 Examples are shown below. The active and passive regions can have shapes suitable for the design of an electronic device on which the display device 100 is mounted. Exemplary shapes of the active regions are pentagons, hexagons, circles, ellipses, etc.

[0040] Each pixel in the active region may be associated with a pixel circuit. The pixel circuit may include one or more switching transistors and one or more driving transistors on substrate 101. Each pixel circuit may be electrically connected to gate lines and data lines to communicate with one or more driving circuits (e.g., gate drivers and data drivers) located in the passive region. The pixel may include an organic light-emitting diode.

[0041] The drive circuit can be made of Figure 1The thin-film transistor (TFT) is implemented in the passive region shown. The driving circuitry can be referred to as an in-board gate-in-package (GIP). Furthermore, some components (e.g., data driver ICs) are mounted on separate printed circuit boards and coupled to connection interfaces (pads / bumps or pins) located in the passive region using circuit films (e.g., flexible printed circuit boards (FPCBs), chip-on-film (COF), or tape-on-package (TCP)). The passive region is bent along with the connection interfaces, allowing the printed circuit board (COF or PCB) to be located on the rear side of the display device 100.

[0042] The display device 100 may also include a power controller that supplies or controls the pixel circuitry, data drivers, gate drivers, etc., to provide various voltages or currents. Such a power controller is also called a power management IC (PMIC). Furthermore, as shown, the display device 100 may include: a high potential voltage VDD associated with driving the pixel circuitry, a reference power voltage line (VSS) 210, and a voltage line providing a reference voltage VRFE.

[0043] Additionally, the display device 100 may include various additional components for generating various signals in the active region or driving organic light-emitting diodes (OLEDs). The additional components for driving the OLEDs may include inverter circuits, multiplexers, electrostatic discharge circuits, etc. The display device 100 may also include additional components associated with functions other than driving the OLEDs. For example, the display device 100 may include additional components providing touch sensing functions, user authentication functions (e.g., fingerprint recognition), multi-level pressure sensing functions, haptic feedback functions, etc.

[0044] The aforementioned additional components may be located in external circuitry connected to the passive area and / or connection interface.

[0045] The reference power voltage line VSS 210 can be disposed in the external passive region I / A of the display device 100 to surround the active region A / A. The reason for this arrangement is to easily provide reference power to the cathode electrodes of all organic light-emitting diodes disposed in the active region A / A with the shortest possible distance, thereby minimizing resistance.

[0046] However, the resistance of the reference power voltage line 210, which is farther from the power supply or the connection interface (pad / bump or pin) to which the power supply is connected, is higher than the resistance of the reference power voltage line 210 closer to the power supply. Therefore, a VSS rise occurs, which can cause irregularities in the brightness of the organic light-emitting diode. Refer to Figure 4 to... Figure 7 Describe in detail the structure used to solve the above problems.

[0047] Figure 2 This is a cross-sectional view showing the active region A / A of the display device. Figure 2The display device 100 has an exemplary structure with two planarization layers. In the display device 100, thin-film transistors, organic light-emitting diodes, and various functional layers are located on a substrate 101.

[0048] The substrate 101 can be a glass or plastic substrate. When the substrate is a plastic substrate, a polyimide-based or polycarbonate-based material is used, which allows the substrate to be flexible. Specifically, polyimide can be used in high-temperature processes and can be coated, making polyimide frequently used in plastic substrates.

[0049] Buffer layer 130 is a functional layer that protects electrodes / wires from impurities such as alkali ions leaking from substrate 101 or layers beneath it. The buffer layer can be formed of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof. Buffer layer 130 may include multiple buffers 131 and / or active buffers 132. Multiple buffers 131 can be formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx), delaying the diffusion of moisture and / or oxygen penetrating into substrate 101. Active buffers 132 protect the semiconductor layer 102 of the transistor and block various types of defects from entering from substrate 101. Active buffers 132 can be formed of amorphous silicon (a-Si).

[0050] A thin-film transistor can be formed by sequentially arranging a semiconductor layer 102, a gate insulating layer 103, a gate electrode 104, an interlayer insulating layer 105, a source electrode 106, and a drain electrode 108. The semiconductor layer 102 is located on a buffer layer 130. The semiconductor layer 102 can be made of polycrystalline silicon (p-Si). In this case, predetermined regions can be doped with impurities. Alternatively, the semiconductor layer 102 can be made of amorphous silicon (a-Si) or various organic semiconductor materials (e.g., pentacene). Furthermore, the semiconductor layer 102 can be made of oxide. The gate insulating layer 103 can be formed of an insulating inorganic material (e.g., silicon oxide SiOx or silicon nitride SiNx) or other insulating organic materials. The gate electrode 104 can be formed of various conductive materials (e.g., magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof).

[0051] The interlayer insulating layer 105 may be formed of an insulating material (such as silicon oxide SiOx or silicon nitride SiNx) or other insulating organic materials. The interlayer insulating layer 105 and the gate insulating layer 103 are selectively removed to form a contact hole through which the source region and the drain region are exposed.

[0052] The source electrode 106 and the drain electrode 108 are formed on the interlayer insulating layer 105 as a single layer or multiple layers of electrode material. If necessary, a passivation layer made of inorganic insulating material may cover the source electrode 106 and the drain electrode 108.

[0053] The first planarization layer 107-1 is located on the thin-film transistor. The first planarization layer 107-1 protects the thin-film transistor and planarizes its upper part. The first planarization layer 107-1 can be configured in various forms and can be formed from one or more of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin and polyphenylene sulfide resin, but is not limited thereto.

[0054] Various metal layers used as wires / electrodes can be disposed above the first planarization layer 107-1.

[0055] The second planarization layer 107-2 is located above the first planarization layer 107-1. As the display device 100 has evolved to have higher resolution, various signal lines have been added, thus providing two planarization layers. Therefore, it is difficult to place all wiring on one layer while ensuring minimum spacing, thus providing an additional layer. By providing this additional layer (the second planarization layer), there is leeway in the wiring arrangement, which makes it easier to design wire / electrode arrangements. Furthermore, when a dielectric material is used for planarization layers 107-1 and 107-2, planarization layers 107-1 and 107-2 can be used to form capacitors between the metal layers.

[0056] An organic light-emitting diode (OLED) can be formed such that an anode electrode 112, an organic light-emitting layer 114, and a cathode electrode 116 are arranged sequentially. That is, an OLED can be composed of an anode electrode 112 formed on a planarization layer 107, an organic light-emitting layer 114 located on the anode electrode 112, and a cathode electrode 116 located on the organic light-emitting layer 114.

[0057] The anode electrode 112 can be electrically connected to the drain electrode of the driving thin-film transistor via a connecting electrode. When the organic light-emitting display device 100 is a top-emitting type, the anode electrode 112 can be formed of an opaque conductive material with high reflectivity. For example, the anode electrode 112 can be formed of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or alloys thereof. The connecting electrode 108-2 can be made of the same material as the source electrode 106 and the drain electrode 108.

[0058] A dam 110 is formed in the region other than the emission region. Therefore, the dam 110 has dam openings that expose the anode electrode 112 corresponding to the emission region. The dam 110 can be made of an inorganic insulating material (e.g., a silicon nitride film (SiNx) or a silicon oxide film (SiOx)) or an organic insulating material (e.g., BCB, acrylic resin, or imide resin).

[0059] The organic light-emitting layer 114 is located on the anode electrode 112 exposed through the embankment 110. The organic light-emitting layer 114 may include a light-emitting layer, an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, etc.

[0060] The cathode electrode 116 is located on the organic light-emitting layer 114. When the organic light-emitting display device 100 is a top-emitting type, the cathode electrode 116 is formed of a transparent conductive material (e.g., indium tin oxide ITO or indium zinc oxide IZO) to emit light generated in the organic light-emitting layer 114 above the cathode electrode 116.

[0061] Encapsulation layer 120 is located on cathode electrode 116. Encapsulation layer 120 inhibits the penetration of oxygen and moisture from the outside to suppress oxidation of the light-emitting material and electrode material. When an organic light-emitting diode is exposed to moisture or oxygen, it can cause pixel shrinkage, resulting in a reduction in the light-emitting area, or the formation of dark spots in the light-emitting area. The encapsulation layer can be composed of an inorganic film formed from glass, metal, alumina (AlOx), or silicon (Si)-based materials, or have a structure with alternating layers of organic and inorganic films. The inorganic film is used to prevent the penetration of moisture or oxygen, and the organic film is used to planarize the surface of the inorganic film. The encapsulation layer is composed of multiple thin film layers to make the movement path of moisture or oxygen longer and more complex than that of a single layer, thus making it difficult for moisture / oxygen to penetrate into the organic light-emitting diode.

[0062] Specifically, the encapsulation layer 120 may include a first inorganic insulating layer 121, an organic insulating layer 122, and a second inorganic insulating layer 123, and the first inorganic insulating layer 121, the organic insulating layer 122, and the second inorganic insulating layer 123 may be arranged sequentially.

[0063] A barrier film 140 is located on the encapsulation layer 120 to encapsulate the entire substrate 101 including the organic light-emitting diode. The barrier film 140 can be a retardation film or an optically isotropic film. When the barrier film is optically isotropic, light incident on the barrier film can be directly transmitted without phase delay. Furthermore, an organic or inorganic film can also be located on the upper or lower surface of the barrier film. The organic or inorganic film formed on the upper or lower surface of the barrier film can prevent moisture or oxygen from permeating from the outside.

[0064] An adhesive layer 145 may be located between the barrier film 140 and the encapsulation layer 120. The adhesive layer 145 bonds the encapsulation layer 120 and the barrier film 140 to each other. The adhesive layer 145 may be a thermosetting adhesive or a naturally curing adhesive. For example, the adhesive layer 145 may be made of a material such as barrier pressure-sensitive adhesive (B-PSA). Touch panels (films), polarizing films, top covers, etc., may also be located on the barrier film 140.

[0065] Figure 3This is a cross-sectional view showing a section taken along a cut portion I-I', which is part of the passive region of the display device. As shown, the passive region I / A can be located at the periphery of the active region A / A, and circuit units (e.g., GIPs) or power lines can be disposed thereon. The circuit units can be disposed between the end of the substrate 101 and the active region A / A and include a transmit signal driver 310 and a scan signal driver 320. A reference power voltage line 210 is disposed between the circuit unit and the end of the substrate 101, and a dam 190 can be disposed above the reference power voltage line 210. The reference power voltage line 210 is connected to the cathode electrode 116 of the active region A / A to provide a reference power for driving the organic light-emitting diode. The dam 190 can suppress the organic insulating layer 122 of the encapsulation layer 120 from overflowing to the periphery of the substrate 101. The reference power voltage line 210 can be electrically connected to a connection electrode 220 disposed on the circuit unit. To connect the connection electrode to the reference power voltage line 210, the planarization layer 107 covering the circuit unit can be removed. The connecting electrode 220 extends to contact the reference power voltage line 210 exposed by removing the planarization layer 107. The connecting electrode 220 connected to the reference power voltage line 210 extends to the active region A / A to be disposed on the circuit unit, and can be electrically connected to the cathode electrode 116 by means of removing a portion of the embankment 110 covering the connecting electrode 220.

[0066] The first inorganic insulating layer 121, the organic insulating layer 122, and the second inorganic insulating layer 123, serving as encapsulation layers 120, are located above the cathode electrode 116, thereby covering not only the active region A / A but also the vicinity of the dam 190 in the passive region I / A. Furthermore, the first inorganic insulating layer 121, the organic insulating layer 122, and the second inorganic insulating layer 123 can also cover the position adjacent to the end of the substrate 101 by surrounding the dam 190. However, the dam 190 is a structure used to suppress the overflow of the organic insulating layer 122, such that the organic insulating layer 122 can be configured to avoid passing through the dam 190 as much as possible.

[0067] Figure 4A and Figure 4B By magnification Figure 1 The plan view obtained in region B serves as an example for reference power voltage line 210. (Refer to...) Figure 4A and Figure 4B The upper portion is the area adjacent to the connection interface (pad / bump or pin), and the lower portion is close to the lower surface of the display device 100 away from the connection interface (pad / bump or pin). In an exemplary embodiment, a reference power voltage line 210 is shown to have a triple metal structure.

[0068] The reference voltage line 210 may include a first reference voltage line 211, a second reference voltage line 212, and a third reference voltage line 213.

[0069] The first reference voltage line 211 can be formed from a single conductive material, and the second reference voltage line 212 can be formed from the same material and using the same process as the gate electrode 104 of the thin-film transistor. The third reference voltage line 213 can be formed from the same material and using the same process as the source electrode 106 and drain electrode 108 of the thin-film transistor. The reference voltage line 210 has a triple metal structure and can be configured such that an insulating layer is disposed between the electrodes to electrically connect the electrodes via contact holes in the insulating layer. Detailed structure will be referred to... Figure 5 The cross-sectional view is used for description.

[0070] The structure of the insulating layer will be briefly described. A multi-buffer layer 131 is disposed on the substrate 101, and an active buffer layer 132, a gate insulating layer 103, and an interlayer insulating layer 105 are disposed in the middle and below the reference power voltage line 210. In the reference power voltage line 210, the third reference power voltage line 213 can be directly electrically connected to a power supply or a connection interface (pad / bump or pin). The first reference voltage line 211 and the second reference voltage line 212 are formed to overlap with the third reference voltage line 213, but can be configured to float so as not to receive individual electrical signals. However, the method of electrically connecting the first to third reference voltage lines 211, 212, and 213 to the power supply is not limited to this, and for example, the second reference voltage line 212 can be directly connected to the power supply or the first reference voltage line 211 can be directly connected to the power supply.

[0071] The reference voltage line 210 has a triple-metal structure in which the first reference voltage line 211, which is the lowest layer, has the largest width, and the width gradually decreases until the third reference voltage line 213 has the smallest width. The reason for the different widths of the voltage lines is that the first reference voltage line 211, as the lowest layer, is formed by a single conductive material on a lower layer than the circuit unit forming layer, resulting in a relatively large width. The larger the width, the lower the resistance. In contrast, the second reference voltage line 212 and the third reference voltage line 213 share the conductive material constituting the circuit unit, allowing the widths of the second and third reference voltage lines to be relatively small to avoid interference with the circuit unit.

[0072] By applying this triple structure, the thickness of the reference power voltage line 210 is increased. Furthermore, the greater the thickness of the wiring, the larger its cross-section, allowing the resistance to decrease inversely. Even with the reduced resistance of the reference power voltage line 210, the phenomenon that the wiring resistance increases as it is spaced from the power supply or connection interface (pad / bump or pin) remains unchanged. To eliminate brightness irregularities based on the reduced resistance, the total resistance of the reference power voltage line 210 can be kept constant.

[0073] For reference Figure 1As stated, when the reference power voltage line 210 is far from the power supply or connection interface (pad / bump or pin), the voltage may vary at each point due to the resistance of the wiring. Therefore, VSS rises, causing irregular screen brightness in the display device 100. To minimize this phenomenon, according to... Figure 4A and Figure 4B In an exemplary implementation, a vertical groove 400 may be provided to overlap with the third reference voltage line 213.

[0074] The vertical trench 400 has a structure extending along the length of the reference power voltage line 210. (Refer to...) Figure 4A The vertical groove 400 may include a first vertical groove 410, a second vertical groove 420, a third vertical groove 430, a fourth vertical groove 440, and a fifth vertical groove 450. The grooves can serve as contact holes that remove the insulation layer between the first reference voltage line 211, the second reference voltage line 212, and the third reference voltage line 213 for electrical connection.

[0075] A power supply voltage is applied from the starting point of the reference power voltage line 210 through the third reference voltage line 213. Furthermore, the third vertical groove 430 is configured such that the first reference voltage line 211, the second reference voltage line 212, and the third reference voltage line 213 are in contact with each other.

[0076] The second vertical trench 420 and the fourth vertical trench 440 are configured with a predetermined distance between them, thereby widening the connection points. When the second vertical trench 420 and the fourth vertical trench 440 are further spaced apart by a larger distance, the first vertical trench 410 and the fifth vertical trench 450 are further formed to have more connection points. Therefore, the increased resistance due to the distance can be offset by the increased cross-section. In other words, by forming a three-conductive structure through the vertical trench 400, the increased resistance due to the distance can be offset by increasing the cross-section.

[0077] Figure 4B A plan view of another exemplary embodiment is shown, wherein the vertical groove 400 is as follows: Figure 4AThe vertical trenches are configured as described above. Regardless of the distance between the power supply and the connection interface (pad / bump or pin), the vertical trenches are configured considering the active region A / A, the power supply, and the connection interface (pad / bump or pin), while maintaining the resistance of the reference power voltage line 210. For example, trenches are not configured in areas close to the power supply or connection interface (pad / bump or pin) and adjacent to the active region A / A, but vertical trenches can be configured away from the active region A / A. Vertical trenches can be additionally configured along the reference power voltage line 210 to be close to the active region A / A near a pre-configured trench, wherein the trench is a predetermined distance from the power supply or connection interface (pad / bump or pin). Specifically, the first vertical trench 410, the second vertical trench 420, the third vertical trench 430, the fourth vertical trench 440, and the fifth vertical trench 450 can be configured in order from the outermost periphery of the reference power voltage line 210 closer to the active region A / A.

[0078] exist Figure 4B In the arrangement, the trench is first placed around the reference power voltage line 210, which has relatively high resistance due to its distance from the power supply or connection interface (pad / bump or pin) and its distance from the active area A / A, in order to reduce the resistance.

[0079] Figure 5 It is shown Figure 4A A cross-sectional view of the reference power voltage line II-II' shown. (Refer to...) Figure 5 In the cross-section II-II' of the reference power voltage line 210 provided in the passive region I / A, a multi-buffer buffer 131 can be provided on the substrate 101, and an active buffer 132 can be provided on the multi-buffer buffer 131. In the active buffer 132, grooves corresponding to the second vertical trench 420, the third vertical trench 430, and the fourth vertical trench 440 can be formed. The first reference voltage line 211 is provided on the active buffer 132 to form on the lower and side surfaces of the grooves formed in the active buffer 132 without interruption.

[0080] A gate insulating layer 103 may be disposed on the first reference voltage line 211, and similarly to the active buffer 132, it forms grooves corresponding to the second vertical trench 420, the third vertical trench 430, and the fourth vertical trench 440 to expose the top surface of the first reference voltage line 211. A second reference voltage line 212 is disposed on the gate insulating layer 103 and contacts the first reference voltage line 211 exposed by the grooves formed in the gate insulating layer 103. The second reference voltage line 212 may be configured to have a width smaller than that of the first reference voltage line 211. An interlayer insulating layer 105 may be disposed on the second reference voltage line 212. Similar to the active buffer 132 or the gate insulating layer 103, grooves corresponding to the second vertical trench 420, the third vertical trench 430, and the fourth vertical trench 440 are formed in the interlayer insulating layer 105 to expose the top surface of the second reference voltage line 212. The third reference voltage line 213 is disposed on the interlayer insulation layer 105 and contacts the second reference voltage line 212 exposed through a groove formed in the interlayer insulation layer 105. The third reference voltage line 213 may have a smaller width than the first reference voltage line 211 and the second reference voltage line 212. The first reference voltage line 211, the second reference voltage line 212 and the third reference voltage line 213 are electrically connected at the second vertical groove 420, the third vertical groove 430 and the fourth vertical groove 440.

[0081] Figure 6 By magnification Figure 1 The plan view obtained from region B serves as another exemplary embodiment of the reference power voltage line 210. (Refer to...) Figure 6 The upper portion is the area adjacent to the connection interface (pad / bump or pin), and the lower portion is near the lower surface of the display device 100 away from the connection interface (pad / bump or pin). In an exemplary embodiment, a reference power voltage line 210 is shown to have a triple metal structure.

[0082] The reference power voltage line 210 may include a first reference power voltage line 211, a second reference power voltage line 212, and a third reference power voltage line 213.

[0083] The first reference voltage line 211 can be formed from a single conductive material, and the second reference voltage line 212 can be formed from the same material and using the same process as the gate electrode 104 of the thin-film transistor. The third reference voltage line 213 can be formed from the same material and using the same process as the source electrode 106 and drain electrode 108 of the thin-film transistor. The reference voltage line 210 is provided with a triple metal structure and can be configured such that an insulating layer is disposed between the electrodes to form an electrical connection between the electrodes via contact holes in the insulating layer.

[0084] The structure of the insulating layer will be briefly described. A multi-buffer layer 131 is disposed on the substrate 101, and an active buffer layer 132, a gate insulating layer 103, and an interlayer insulating layer 105 are disposed in the middle of and below the reference power voltage line 210. In the reference power voltage line 210, a third reference voltage line 213 is directly electrically connected to a power supply or a connection interface (pad / bump or pin). The first reference voltage line 211 and the second reference voltage line 212 are formed to overlap with the third reference voltage line 213, but can be configured to float so as not to receive individual electrical signals. However, the method of electrically connecting the first to third reference voltage lines 211, 212, and 213 to the power supply is not limited to this; for example, the second reference voltage line 212 can be directly connected to the power supply, or the first reference voltage line 211 can be directly connected to the power supply.

[0085] The reference voltage line 210 has a triple-metal structure with the widest first reference voltage line 211 (serving as the lowest layer), and the widths gradually decrease until the width of the third reference voltage line 213 is the smallest. The voltage lines have different widths because the first reference voltage line 211, as the lowest layer, is formed from a single conductive material on a lower layer than the circuit unit formation layer, resulting in a relatively large width. A larger width leads to lower resistance. In contrast, the second reference voltage line 212 and the third reference voltage line 213 share the conductive material constituting the circuit unit, allowing their widths to be smaller to avoid interference with the circuit unit.

[0086] By applying this triple structure, the thickness of the reference power voltage line 210 is increased. Furthermore, the greater the thickness of the wiring, the larger its cross-section, allowing the resistance to decrease inversely. Even with the reduced resistance of the reference power voltage line 210, the phenomenon that the wiring resistance increases as it is spaced from the power supply or connection interface (pad / bump or pin) remains unchanged. To eliminate brightness irregularities based on the reduced resistance, the total resistance of the reference power voltage line 210 can be kept constant.

[0087] For reference Figure 1 As stated, when the reference power voltage line 210 is far from the power supply or connection interface (pad / bump or pin), the voltage may vary at each point due to the resistance of the wiring. Therefore, a VSS rise phenomenon occurs, causing irregular screen brightness in the display device 100. To minimize this phenomenon, according to... Figure 6 In an exemplary implementation, a horizontal trench 500 may be provided to overlap with the third reference voltage line 213.

[0088] The horizontal trench 500 may have a structure extending horizontally along the reference voltage line 210. The horizontal direction is perpendicular to the vertical direction and traverses the cross-section of the reference voltage line 210. (Refer to...) Figure 6The horizontal trench 500 may include a first horizontal trench 510, a second horizontal trench 520, a third horizontal trench 530, a fourth horizontal trench 540, a fifth horizontal trench 550, a sixth horizontal trench 560, a seventh horizontal trench 570, and an eighth horizontal trench 580. According to this exemplary embodiment, as an example of the horizontal trench 500, first to eighth horizontal trenches 510, 520, 530, 540, 550, 560, 570, and 580 are provided, but the embodiment is not limited thereto; fewer or more horizontal trenches may be provided. In the trench, the length of the wiring can be locally increased by creating uneven portions in a structure in which holes are formed by removing the insulating layer between the first reference voltage line 211, the second reference voltage line 212, and the third reference voltage line 213, and these lines are electrically connected.

[0089] A power supply voltage is applied from the starting point of the reference power voltage line 210 through the third reference voltage line 213. Furthermore, the horizontal trench 500 is configured such that the first reference voltage line 211, the second reference voltage line 212, and the third reference voltage line 213 are partially in contact with each other.

[0090] Based on the principle that resistance increases proportionally with distance, the horizontal trench 500 locally increases in distance as it moves closer to the power supply or connection interface (pad / bump or pin), resulting in a corresponding increase in resistance. To reduce the natural increase in resistance due to distance from the power supply or connection interface (pad / bump or pin), the arrangement of the horizontal trench 500, which increases the wiring distance, can be minimized. (Refer to...) Figure 6 In the upper portion near the power supply or connection interface (pad / bump or pin), the first to third horizontal trenches 510, 520, and 530 are configured with narrow spacing. In contrast, in the lower portion away from the power supply or connection interface (pad / bump or pin), the sixth to eighth horizontal trenches 560, 570, and 580 are configured with larger spacing than the first to third horizontal trenches 510, 520, and 530.

[0091] Figure 7 It shows along Figure 6 A cross-sectional view of the section taken from line III-III' of the reference power voltage line 210. (Refer to...) Figure 7 In the cross-section III-III' of the reference power voltage line 210 disposed in the passive region I / A, a multi-buffer buffer 131 is disposed on the substrate 101, and an active buffer buffer 132 is disposed on the multi-buffer buffer 131. In the active buffer buffer 132, grooves corresponding to the first horizontal trench 510, the second horizontal trench 520, and the third horizontal trench 530 can be formed. The first reference voltage line 211 can be disposed on the active buffer buffer 132, and can be formed on the lower and side surfaces of the grooves in the active buffer buffer 132 without interruption.

[0092] A gate insulating layer 103 may be disposed on the first reference voltage line 211, and similarly to the active buffer 132, it forms grooves corresponding to the first horizontal trench 510, the second horizontal trench 520, and the third horizontal trench 530 to expose the top surface of the first reference voltage line 211. A second reference voltage line 212 may be disposed on the gate insulating layer 103 and may contact the first reference voltage line 211 exposed through the grooves formed in the gate insulating layer 103. An interlayer insulating layer 105 may be disposed on the second reference voltage line 212. Similar to the active buffer 132 or the gate insulating layer 103, grooves corresponding to the first horizontal trench 510, the second horizontal trench 520, and the third horizontal trench 530 are formed in the interlayer insulating layer 105 to expose the top surface of the second reference voltage line 212. A third reference voltage line 213 may be disposed on the interlayer insulating layer 105 and may contact the second reference voltage line 212 exposed through the grooves formed in the interlayer insulating layer 105. The first reference voltage line 211, the second reference voltage line 212, and the third reference voltage line 213 are electrically connected at the first horizontal trench 510, the second horizontal trench 520, and the third horizontal trench 530.

[0093] As described above, the horizontal trench 500 is configured such that an uneven portion is formed between the trenches, and an uneven portion is formed between the first reference voltage line 211, the second reference voltage line 212, and the third reference voltage line 213, thereby increasing the length of the wiring. Furthermore, as the lengths of the first reference voltage line 211, the second reference voltage line 212, and the third reference voltage line 213 increase, the resistance locally increases.

[0094] Display devices according to exemplary embodiments of this disclosure may include liquid crystal display devices (LCD), field emission display devices (FED), organic light-emitting diode (OLED), and quantum dot display devices.

[0095] The display device according to the exemplary embodiments of this disclosure may also include a device display device, which includes complete or final products of LCM, OLED or QD modules, such as notebook computers, televisions, computer monitors, automotive display devices or other vehicle display devices, as well as set electronic devices or kit devices (kit devices) of mobile electronic devices such as smartphones or tablets.

[0096] Exemplary embodiments of this disclosure can also be described as follows:

[0097] According to one aspect of this disclosure, a display device is provided. The display device includes a substrate comprising an active region and a passive region. The display device further includes a transistor, an anode electrode, an organic light-emitting layer, and a cathode electrode disposed in the active region. The display device also includes circuit units, a dam, and a reference power voltage line disposed in the passive region. The reference power voltage line includes a first conductive layer to a third conductive layer, and the first conductive layer to the third conductive layer are formed in an overlapping manner.

[0098] The first to third conductive layers can be formed with different widths.

[0099] The reference power voltage line can be set on the first and second insulating layers, the third insulating layer can be set between the first and second conductive layers, and the fourth insulating layer can be set between the second and third conductive layers, with the third and fourth insulating layers overlapping each other.

[0100] At least one trench can be formed by creating overlapping holes at the same locations in the second to fourth insulating layers, through which the first to third conductive layers contact each other.

[0101] At least one trench can be formed by creating overlapping holes at the same positions in the second to fourth insulating layers, through which the second conductive layer contacts the first and third conductive layers.

[0102] At least one groove can be multiple grooves, and unevenness can be formed between multiple grooves.

[0103] At least one trench may be a vertical trench parallel to the length direction of the reference power voltage line.

[0104] At least one trench may be a horizontal trench parallel to the width direction of the reference power voltage line.

[0105] At least one vertical groove may be composed of multiple grooves, and some of the vertical grooves may have different lengths.

[0106] At least one horizontal trench may be composed of multiple horizontal trenches, which may have the same length, and at least one of the arrangement distances between the multiple horizontal trenches may be different from the other arrangement distances.

[0107] According to another aspect of this disclosure, a display device is provided. The display device includes a substrate comprising an active region and a passive region. The display device includes a transistor, an anode electrode, an organic light-emitting layer, and a cathode electrode disposed in the active region. The display device includes a reference power voltage line disposed in the passive region. The reference power voltage line includes a first conductive layer to a third conductive layer, and the first conductive layer to the third conductive layer have different widths.

[0108] The passive region may also include the dam section and the circuit unit.

[0109] The first to third conductive layers can be formed with different widths.

[0110] The first conductive layer may overlap at least partially with the circuit unit.

[0111] The reference power voltage line can be disposed on the first and second insulating layers, and the third and fourth insulating layers can be disposed between the first and third conductive layers to overlap.

[0112] Multiple trenches can be formed by creating overlapping holes at the same positions in the second to fourth insulating layers, with the first to third conductive layers in contact with each other through the multiple trenches.

[0113] Multiple trenches can be formed by creating overlapping holes at the same positions in the second to fourth insulating layers, and the second conductive layer contacts the first and third conductive layers through the multiple trenches.

[0114] Multiple trenches can be vertical trenches parallel to the length direction of the reference power voltage line.

[0115] Multiple trenches can be horizontal trenches parallel to the width direction of the reference power voltage line.

[0116] At least one of the multiple vertical grooves may have a different width.

[0117] Multiple horizontal trenches may have the same length, and at least one of the arrangement distances between multiple horizontal trenches may be different from the other arrangement distances.

[0118] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalents should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: The substrate includes active regions and passive regions; The transistor, anode electrode, organic light-emitting layer, and cathode electrode are disposed in the active region; as well as At least one trench, circuit unit, dam, and reference power voltage line are provided in the passive region. The reference power voltage line includes a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer, the second conductive layer, and the third conductive layer are formed in an overlapping manner; and The second conductive layer is in contact with the first conductive layer and the third conductive layer at each of the at least one trench.

2. The display device according to claim 1, wherein, The first conductive layer to the third conductive layer are formed with different widths.

3. The display device according to claim 1, wherein, The reference power voltage line is disposed on the first insulating layer and the second insulating layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the third conductive layer, and the third insulating layer and the fourth insulating layer are disposed overlapping each other.

4. The display device according to claim 3, wherein, The at least one trench is formed by creating holes that overlap at the same positions in the second to the fourth insulating layers.

5. The display device according to claim 4, wherein, The at least one groove is a plurality of grooves, and an uneven portion is formed between the plurality of grooves.

6. The display device according to claim 4, wherein, The at least one trench is a vertical trench parallel to the length direction of the reference power voltage line.

7. The display device according to claim 4, wherein, The at least one trench is a horizontal trench parallel to the width direction of the reference power voltage line.

8. The display device according to claim 6, wherein, The at least one vertical groove is composed of multiple grooves, and some of the multiple vertical grooves have different lengths.

9. The display device according to claim 7, wherein, The at least one horizontal trench is composed of a plurality of horizontal trenches having the same length, and at least one of the arrangement distances between the plurality of horizontal trenches is different from the other arrangement distances.

10. A display device, comprising: The substrate includes active regions and passive regions; The transistor, anode electrode, organic light-emitting layer, and cathode electrode are disposed in the active region; as well as Multiple trenches and reference power voltage lines are provided in the passive region. The reference power voltage line includes a first conductive layer, a second conductive layer, and a third conductive layer, and the first conductive layer, the second conductive layer, and the third conductive layer have different widths; and The second conductive layer is in contact with the first conductive layer and the third conductive layer at each of the plurality of trenches.

11. The display device according to claim 10, wherein, The passive region also includes the dam section and the circuit unit.

12. The display device according to claim 11, wherein, The first conductive layer to the third conductive layer are formed with different widths.

13. The display device according to claim 12, wherein, The first conductive layer overlaps at least partially with the circuit unit.

14. The display device according to claim 10, wherein, The reference power voltage line is disposed on the first and second insulating layers, and the third and fourth insulating layers are disposed between the first conductive layer and the third conductive layer to overlap.

15. The display device according to claim 14, wherein, The plurality of trenches are formed by creating holes that overlap at the same positions in the second to the fourth insulating layers.

16. The display device according to claim 15, wherein, The plurality of grooves are vertical grooves parallel to the length direction of the reference power voltage line.

17. The display device according to claim 15, wherein, The plurality of trenches are horizontal trenches parallel to the width direction of the reference power voltage line.

18. The display device according to claim 16, wherein, At least one of the vertical grooves has a different width.

19. The display device according to claim 17, wherein, The plurality of horizontal trenches have the same length, and at least one of the arrangement distances between the plurality of horizontal trenches is different from the other arrangement distances.

20. A display device, comprising: The substrate includes active regions and passive regions; Multiple organic light-emitting diodes are disposed in the active region; Multiple trenches are provided in the passive region; as well as A reference power voltage line is provided in the passive region to provide reference power for driving the plurality of organic light-emitting diodes; The reference power voltage line includes a first conductive layer, a second conductive layer, and a third conductive layer; The first conductive layer, the second conductive layer, and the third conductive layer are formed in an overlapping manner; and The second conductive layer is in contact with the first conductive layer and the third conductive layer at each of the plurality of trenches.

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