A differential operational amplifier and chip

Abstract

This invention discloses a differential operational amplifier and chip. The differential operational amplifier includes a current mirror circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, and a common-mode feedback circuit. The current mirror circuit, the first-stage amplifier circuit, and the second-stage amplifier circuit all support differential input and differential output. The differential output terminal of the first-stage amplifier circuit is connected to the differential input terminal of the second-stage amplifier circuit. The differential output terminal of the first-stage amplifier circuit is also connected to the feedback terminal of the current mirror circuit via the common-mode feedback circuit. The differential output terminal of the second-stage amplifier circuit is connected to the feedback terminal of the second-stage amplifier circuit via the common-mode feedback circuit. The differential output terminal of the second-stage amplifier circuit is the output terminal of the differential operational amplifier. The output terminal of the current mirror circuit is connected to the power supply terminal of the first-stage amplifier circuit. The input terminal of the current mirror circuit is used to receive signals from external input to the differential operational amplifier.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of differential amplifier, and particularly relates to a differential operational amplifier and a chip. BACKGROUND

[0002] At present, the common technologies for designing amplifiers mainly include source follower structure, common source amplifier structure and resistance negative feedback structure, etc., wherein the source follower structure and the resistance negative feedback structure are commonly used for driving analog small signals, low resistance value loads and capacitor loads due to high linearity and low output resistance, and the common source amplifier is commonly used for driving high power signals and full swing signals. However, the common source amplifier structure will deteriorate the linearity of the driving circuit and the stability of the amplified signal due to the existence of the parasitic capacitance at high frequency. In a multi-stage operational amplifier, the output stage of the operational amplifier is usually required to provide a large output range, but the voltage output is unstable due to the cascading of many MOS tubes as the power voltage gradually decreases. SUMMARY

[0003] In view of the above technical defects, the application proposes a differential operational amplifier by designing a working loop between a two-stage amplification circuit and a common mode feedback circuit, and the specific technical scheme is as follows:

[0004] The differential operational amplifier comprises a current mirror circuit, a first-stage amplification circuit, a second-stage amplification circuit and a common mode feedback circuit; wherein the current mirror circuit, the first-stage amplification circuit and the second-stage amplification circuit all support differential input and differential output; the differential output end of the first-stage amplification circuit is connected to the differential input end of the second-stage amplification circuit in correspondence; the differential output end of the first-stage amplification circuit is further connected to the feedback end of the current mirror circuit through the common mode feedback circuit; the differential output end of the second-stage amplification circuit is connected to the feedback end of the second-stage amplification circuit through the common mode feedback circuit; the differential output end of the second-stage amplification circuit is the output end of the differential operational amplifier; the output end of the current mirror circuit is connected to the power supply end of the first-stage amplification circuit; and the input end of the current mirror circuit is used for receiving an external input signal of the differential operational amplifier.

[0005] Further, the common mode feedback circuit comprises a first common mode feedback circuit and a second common mode feedback circuit; the differential output end of the first-stage amplification circuit is connected to the differential input end of the second-stage amplification circuit in correspondence; the differential output end of the first-stage amplification circuit is further connected to the feedback end of the current mirror circuit through the first common mode feedback circuit; the differential output end of the second-stage amplification circuit is connected to the feedback end of the second-stage amplification circuit through the second common mode feedback circuit; and the differential output end of the second-stage amplification circuit is the output end of the differential operational amplifier.

[0006] Further, the differential operational amplifier is a four-input operational amplifier, wherein the positive input end of the differential operational amplifier comprises a first positive input end of the differential operational amplifier and a second positive input end of the differential operational amplifier, and the negative input end of the differential operational amplifier comprises a first negative input end of the differential operational amplifier and a second negative input end of the differential operational amplifier; the first positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are used to access a pair of differential signals to be processed; the first negative input end of the differential operational amplifier and the second positive input end of the differential operational amplifier are both accessed to a common-mode reference voltage; the first positive input end of the differential operational amplifier, the first negative input end of the differential operational amplifier, the second positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are all input ends of the current mirror circuit; wherein the power supply accessed by the power supply end of the second-stage amplification circuit is equal to the power supply accessed by the power supply end of the current mirror circuit; and the ground end of the second-stage amplification circuit and the ground end of the first-stage amplification circuit share a ground wire.

[0007] Further, the current mirror circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; the gate of the third PMOS tube is the first positive input end of the differential operational amplifier, the gate of the fifth PMOS tube is the second positive input end of the differential operational amplifier, the gate of the fourth PMOS tube is the first negative input end of the differential operational amplifier, and the gate of the sixth PMOS tube is the second negative input end of the differential operational amplifier; the drain of the third PMOS tube is connected with the drain of the fifth PMOS tube, and the connection node of the drain of the third PMOS tube and the drain of the fifth PMOS tube is the first output end of the current mirror circuit; the drain of the fourth PMOS tube is connected with the drain of the sixth PMOS tube, and the connection node of the drain of the fourth PMOS tube and the drain of the sixth PMOS tube is the second output end of the current mirror circuit; wherein the output end of the current mirror circuit comprises the first output end of the current mirror circuit and the second output end of the current mirror circuit; the source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the drain of the first PMOS tube, and the source of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the drain of the second PMOS tube; the gate of the first PMOS tube is the first feedback end of the current mirror circuit, the gate of the second PMOS tube is the second feedback end of the current mirror circuit, and the gate of the first PMOS tube and the gate of the second PMOS tube are both connected to the output end of the first common-mode feedback circuit; the feedback end of the current mirror circuit comprises the first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit; the source of the first PMOS tube is the first power supply end of the current mirror circuit, and the source of the second PMOS tube is the second power supply end of the current mirror circuit; the power supply end of the current mirror circuit comprises the first power supply end of the current mirror circuit and the second power supply end of the current mirror circuit.

[0008] Further, the first-stage amplifier circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the source of the seventh PMOS transistor is the first power supply terminal of the first-stage amplifier circuit, and the first power supply terminal of the first-stage amplifier circuit is connected to the first output terminal of the current mirror circuit; the source of the eighth PMOS transistor is the second power supply terminal of the first-stage amplifier circuit, and the second power supply terminal of the first-stage amplifier circuit is connected to the second output terminal of the current mirror circuit; the gate of the seventh PMOS transistor is connected to a first bias voltage provided externally; the gate of the eighth PMOS transistor is connected to a first bias voltage provided externally; wherein, the power supply terminal of the first-stage amplifier circuit includes the first power supply terminal and the second power supply terminal of the first-stage amplifier circuit; the output terminal of the current mirror circuit includes the first output terminal and the second output terminal of the current mirror circuit; the drain of the seventh PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to a second bias voltage provided externally, the source of the first NMOS transistor is connected to the drain of the third NMOS transistor, and the gate of the third NMOS transistor is connected to a third bias voltage provided externally; the... The sources of the three NMOS transistors are grounded; the drain of the eighth PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to a second bias voltage provided externally, the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to a third bias voltage provided externally, and the source of the fourth NMOS transistor is grounded; the connection point between the drain of the seventh PMOS transistor and the drain of the first NMOS transistor is the positive output terminal of the first-stage amplifier circuit, and the connection point between the drain of the eighth PMOS transistor and the drain of the second NMOS transistor is the negative output terminal of the first-stage amplifier circuit. The output terminal; wherein, the differential output terminal of the first stage amplifier circuit includes the positive output terminal and the negative output terminal of the first stage amplifier circuit; the positive output terminal and the negative output terminal of the first stage amplifier circuit are respectively connected to the differential input terminal of the first common-mode feedback circuit, and the first feedback terminal and the second feedback terminal of the current mirror circuit are both connected to the output terminal of the first common-mode feedback circuit to adjust the differential output result of the first stage amplifier circuit; wherein, the feedback terminal of the current mirror circuit includes the first feedback terminal and the second feedback terminal of the current mirror circuit.

[0009] Further, the second-stage amplifier circuit includes a ninth PMOS transistor, a tenth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the source of the ninth PMOS transistor is connected to the first power supply terminal of the current mirror circuit, the drain of the ninth PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the ninth PMOS transistor is the positive input terminal of the second-stage amplifier circuit, the gate of the ninth PMOS transistor is connected to the positive output terminal of the first-stage amplifier circuit, and the source of the fifth NMOS transistor is grounded; the connection point between the drains of the ninth and fifth NMOS transistors is the positive output terminal of the second-stage amplifier circuit; the source of the tenth PMOS transistor is connected to the second power supply terminal of the current mirror circuit, the drain of the tenth PMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the tenth PMOS transistor is the negative input terminal of the second-stage amplifier circuit, the gate of the tenth PMOS transistor is connected to the negative output terminal of the first-stage amplifier circuit, and the source of the sixth NMOS transistor is grounded; the connection point between the drains of the tenth and sixth NMOS transistors is the negative output terminal of the second-stage amplifier circuit; the second-stage amplifier... The positive output terminal of the circuit and the negative output terminal of the second-stage amplifier circuit are respectively connected to the differential input terminal of the second common-mode feedback circuit; the gate of the fifth NMOS transistor is the first feedback terminal of the second-stage amplifier circuit, and the gate of the fourth NMOS transistor is the second feedback terminal of the second-stage amplifier circuit. Both the first and second feedback terminals of the second-stage amplifier circuit are connected to the output terminal of the second common-mode feedback circuit to adjust the differential output result of the second-stage amplifier circuit; wherein, the differential input terminal of the second-stage amplifier circuit includes the positive and negative input terminals of the second-stage amplifier circuit; the differential output terminal of the second-stage amplifier circuit includes the positive and negative output terminals of the second-stage amplifier circuit; the differential output terminal of the first-stage amplifier circuit includes the positive and negative output terminals of the first-stage amplifier circuit; the power supply terminal of the current mirror circuit includes the first and second power supply terminals of the current mirror circuit; the feedback terminal of the second-stage amplifier circuit includes the first and second feedback terminals of the second-stage amplifier circuit.

[0010] Furthermore, the first bias voltage, the second bias voltage, and the third bias voltage are not equal to each other, so as to form a voltage difference between different pairs of MOSFETs; wherein, the voltage difference between any two of the first bias voltage, the second bias voltage, and the third bias voltage remains constant; the first bias voltage, the second bias voltage, and the third bias voltage are all provided by corresponding bias voltage sources.

[0011] Furthermore, the first common-mode feedback circuit and the second common-mode feedback circuit belong to the same type of common-mode feedback structure. The first common-mode feedback circuit and the second common-mode feedback circuit are connected to the same common-mode reference voltage so that the output of the differential operational amplifier is stabilized to the same common-mode level.

[0012] Furthermore, the first common-mode feedback circuit is used to generate a feedback control signal to the feedback terminal of the current mirror circuit to adjust the average voltage of the differential signal output by the first-stage amplifier circuit to be equal to the common-mode reference voltage; the second common-mode feedback circuit is used to generate a feedback control signal to the feedback terminal of the second-stage amplifier circuit to adjust the average voltage of the differential signal output by the second-stage amplifier circuit to be equal to the common-mode reference voltage.

[0013] A chip that contains the differential operational amplifier.

[0014] Compared with the prior art, the present invention designs the operational amplifier as an operational amplifier with four input terminals, supporting two pairs of differential inputs and one pair of differential outputs. It has both a current mirror load structure and a common-mode feedback circuit, which can form the working loop of the first-stage amplifier circuit, the second-stage amplifier circuit and their common-mode feedback circuit. Since only two-stage amplifier circuits are designed, the driving capability of the operational amplifier is improved while ensuring that the circuit complexity is not high, ensuring the stability of the amplified signal, and the generated common-mode voltage is not easy to deviate from the common-mode reference voltage. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the differential operational amplifier disclosed in an embodiment of the present invention.

[0016] Figure 2 This is a schematic diagram of the connection structure of the first common-mode feedback circuit CMFB1 and the second common-mode feedback circuit CMFB2. Detailed Implementation

[0017] The technical solutions of the present invention will now be described in detail with reference to the accompanying drawings.

[0018] As one embodiment, this invention discloses a differential operational amplifier, which includes a current mirror circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, and a common-mode feedback circuit. The current mirror circuit, the first-stage amplifier circuit, and the second-stage amplifier circuit all support differential input and differential output. The differential output terminal of the first-stage amplifier circuit is connected to the differential input terminal of the second-stage amplifier circuit, cascading the two stages. The differential output terminal of the first-stage amplifier circuit is also connected to the feedback terminal of the current mirror circuit via the common-mode feedback circuit. The differential output terminal of the second-stage amplifier circuit is connected to the feedback terminal of the second-stage amplifier circuit via the common-mode feedback circuit. The differential output terminal of the second-stage amplifier circuit is the output terminal of the differential operational amplifier. The output terminal of the current mirror circuit is connected to the power supply terminal of the first-stage amplifier circuit, providing a drive signal source for the first-stage amplifier circuit. The input terminal of the current mirror circuit receives signals from externally input differential operational amplifiers, including at least one pair of differential input signals, to accommodate the differential amplification requirements of the two-stage amplifier circuit.

[0019] In some embodiments, the first-stage amplifier circuit and the second-stage amplifier circuit are both connected to the same common-mode feedback circuit, which reduces the complexity of the circuit structure compared to the common-mode feedback circuit of two-stage operational amplifiers. In other embodiments, the same common-mode feedback circuit can be equivalent to two independent traditional common-mode feedback structures, serving the first-stage amplifier circuit and the second-stage amplifier circuit respectively, without involving the port multiplexing problem of differential input and differential output terminals.

[0020] Preferably, the differential interface between the common-mode feedback circuit and the differential output terminal of the first-stage amplifier circuit is different from the differential interface between the common-mode feedback circuit and the differential output terminal of the second-stage amplifier circuit; the differential input terminal connected to the differential output terminal of the common-mode feedback circuit and the first-stage amplifier circuit is different from the differential input terminal connected to the differential output terminal of the common-mode feedback circuit and the second-stage amplifier circuit; the output terminal connected to the feedback terminal of the common-mode feedback circuit and the current mirror circuit is different from the output terminal connected to the feedback terminal of the common-mode feedback circuit and the current mirror circuit. In this case, the common-mode feedback circuit is configured as a circuit with four differential input terminals and two output terminals.

[0021] As one example, such as Figure 1As shown, the differential operational amplifier includes a current mirror circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, a first common-mode feedback circuit, and a second common-mode feedback circuit. The current mirror circuit, the first-stage amplifier circuit, and the second-stage amplifier circuit all support differential input and differential output. The differential output terminal of the first-stage amplifier circuit is connected to the differential input terminal of the second-stage amplifier circuit, thus cascading the first-stage and second-stage amplifier circuits. The differential output terminal of the first-stage amplifier circuit is also connected to the feedback terminal of the current mirror circuit through the first common-mode feedback circuit to stabilize the output level of this stage. Therefore, the current mirror circuit and the first-stage amplifier circuit preferably constitute a complete amplifier stage. The differential output of the second-stage amplifier circuit is connected to the feedback terminal of the second-stage amplifier circuit through a second common-mode feedback circuit. The differential output of the second-stage amplifier circuit is the output terminal of the differential operational amplifier. The first positive input terminal, the first negative input terminal, the second positive input terminal, and the second negative input terminal of the differential operational amplifier are all input terminals of the current mirror circuit, corresponding to two pairs of differential input terminals. The output terminal of the current mirror circuit is connected to the power supply terminal of the first-stage amplifier circuit, providing a driving signal source for the first-stage amplifier circuit. This forms a first loop of the first-stage amplifier circuit and the first common-mode feedback circuit, and a second loop of the second-stage amplifier circuit and the second common-mode feedback circuit. The first loop and the second loop together maintain the stability of the differential signal output by the differential operational amplifier, enabling both the differential output of the first-stage amplifier circuit and the differential output of the second-stage amplifier circuit to stabilize to a reasonable and identical common-mode level.

[0022] Compared with the prior art, the aforementioned embodiment designs the operational amplifier as an operational amplifier with four input terminals, supporting two pairs of differential inputs and one pair of differential outputs. It has both a current mirror load structure and a common-mode feedback circuit, which can form the working loop of the first-stage amplifier circuit, the second-stage amplifier circuit, and their common-mode feedback circuit. Since only two-stage amplifier circuits are designed, the driving capability of the operational amplifier is improved while ensuring that the circuit complexity is not high, ensuring the stability of the amplified signal, and the generated common-mode voltage is not easy to deviate from the common-mode reference voltage.

[0023] It should be noted that the differential operational amplifier is a four-input operational amplifier, wherein the positive input terminal of the differential operational amplifier includes a first positive input terminal and a second positive input terminal, and the negative input terminal includes a first negative input terminal and a second negative input terminal; optionally, the first positive input terminal and the second negative input terminal of the differential operational amplifier are used to input a pair of differential signals to be processed, corresponding to... Figure 1In this embodiment, the first positive input terminal of the differential operational amplifier is used to receive the differential signal VIP1, and the second negative input terminal of the differential operational amplifier is used to receive the differential signal VIN2; both the first negative input terminal and the second positive input terminal of the differential operational amplifier are connected to a common-mode reference voltage. The power supply connected to the power supply terminal of the second-stage amplifier circuit is equal to the power supply connected to the power supply terminal of the current mirror circuit (VDD); the ground terminal of the second-stage amplifier circuit and the ground terminal of the first-stage amplifier circuit share a common ground line GND. This embodiment designs the differential operational amplifier as an operational amplifier with four input terminals, supporting two pairs of differential inputs and one pair of differential outputs to meet the stability requirements of differential input and output; thereby improving the input impedance of the differential operational amplifier while maintaining low circuit complexity.

[0024] Preferably, the first common-mode feedback circuit and the second common-mode feedback circuit can be regarded as two independent common-mode feedback circuits, wherein these two common-mode feedback circuits support differential input and single-ended output; the first common-mode feedback circuit and the second common-mode feedback circuit can also be combined into an integrated circuit module, that is, forming one common-mode feedback circuit; wherein, the differential input terminal of the first common-mode feedback circuit is connected to the differential output terminal of the first amplifier circuit, and the output terminal of the first common-mode feedback circuit is connected to the current mirror circuit, forming the first loop; the differential input terminal of the second common-mode feedback circuit is connected to the differential output terminal of the second amplifier circuit, and the output terminal of the second common-mode feedback circuit is connected to the second amplifier circuit, forming the second loop.

[0025] In some embodiments, the current mirror circuit can be a MOS-type current mirror circuit, in which the first-stage amplifier circuit and the second-stage amplifier circuit are both connected by MOS transistors, particularly using an inverter structure to form a two-stage amplifier circuit; the current mirror circuit can also be a transistor-type current mirror, in which the first-stage amplifier circuit and the second-stage amplifier circuit are both connected by transistors. When the current mirror circuit is a MOS-type current mirror circuit, the channel length modulation effect in the current mirror circuit is suppressed, wherein the substrates of the relevant PMOS transistors in the current mirror circuit, the first-stage amplifier circuit, and the second-stage amplifier circuit are all connected to the power supply VDD, and the substrates of the relevant NMOS transistors are all grounded to GND; in addition, when the current mirror circuit is a transistor-type current mirror circuit, the base width modulation effect in the current mirror circuit is suppressed.

[0026] As one example, such as Figure 1As shown, the current mirror circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The gate of the third PMOS transistor MP3 is the first positive input terminal of the differential operational amplifier, used to input the differential analog signal VIP1. The gate of the fifth PMOS transistor MP5 is the second positive input terminal of the differential operational amplifier, used to input the differential analog signal VIP2. The gate of the fourth PMOS transistor MP4 is the first negative input terminal of the differential operational amplifier, used to input the differential analog signal VIN1. The gate of the sixth PMOS transistor is the second negative input terminal of the differential operational amplifier, used to input the differential analog signal VIN2. It should be noted that the source of the first PMOS transistor MP1 is the first power supply terminal of the current mirror circuit, and the source of the second PMOS transistor MP2 is the second power supply terminal of the current mirror circuit. The power supply terminals of the current mirror circuit include both the first and second power supply terminals. The drain of the third PMOS transistor MP3 is connected to the drain of the fifth PMOS transistor MP5. The connection point between the drains of the third PMOS transistor MP3 and the fifth PMOS transistor MP5 is the first output terminal of the current mirror circuit, providing a current source for the pair of differential MOS transistors set up inside the first-stage amplifier circuit. The drain of the fourth PMOS transistor MP4 is connected to the drain of the sixth PMOS transistor MP6. The connection point between the drains of the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 is the second output terminal of the current mirror circuit, providing a current source for the other pair of differential MOS transistors in the first-stage amplifier circuit, thus forming a current mirror load structure and improving the driving capability of the first-stage amplifier circuit. The output terminals of the current mirror circuit include the first output terminal and the second output terminal of the current mirror circuit. The sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are both connected to the drain of the first PMOS transistor MP1, and the sources of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both connected to the drain of the second PMOS transistor MP2. The gate of the first PMOS transistor MP1 is the first feedback terminal of the current mirror circuit, used to receive the common-mode feedback control signal Vfb1; the gate of the second PMOS transistor MP2 is the second feedback terminal of the current mirror circuit, used to receive the common-mode feedback control signal Vfb1. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the output terminal of the first common-mode feedback circuit. The feedback terminal of the current mirror circuit includes the first feedback terminal and the second feedback terminal of the current mirror circuit, thus forming the working loop of the current mirror circuit, the first-stage amplifier circuit, and the first common-mode feedback circuit. As long as the loop is stable, the average voltage (common-mode voltage) of the differential signal output by the first-stage amplifier circuit is equal to the common-mode reference voltage.

[0027] As one example, such asFigure 1As shown, the first-stage amplifier circuit includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The source of the seventh PMOS transistor MP7 is the first power supply terminal of the first-stage amplifier circuit, which is connected to the first output terminal of the aforementioned current mirror circuit. The source of the eighth PMOS transistor MP8 is the second power supply terminal of the first-stage amplifier circuit, which is connected to the second output terminal of the current mirror circuit. The gate of the seventh PMOS transistor MP7 is connected to a first bias voltage Vb1 provided externally. MOSFET MP7 provides bias current. When the first bias voltage Vb1 is constant, a constant bias current is generated in the branch where the seventh PMOS transistor MP7 is located. The gate of the eighth PMOS transistor MP8 is connected to the first bias voltage Vb1 provided externally, providing bias current for the eighth PMOS transistor MP8. When the first bias voltage Vb1 is constant, a constant bias current is generated in the branch where the eighth PMOS transistor MP8 is located. The power supply terminals of the first stage amplifier circuit include a first power supply terminal and a second power supply terminal. The output terminals of the current mirror circuit include a first output terminal and a second output terminal. The drain of the seventh PMOS transistor MP7 is connected to the drain of the first NMOS transistor NM1. The gate of the first NMOS transistor NM1 is connected to the second bias voltage Vb2 provided by the outside, which provides bias current for the first NMOS transistor NM1. The source of the first NMOS transistor NM1 is connected to the drain of the third NMOS transistor NM3. The gate of the third NMOS transistor NM3 is connected to the third bias voltage Vb3 provided by the outside, which provides bias current for the third NMOS transistor NM3. The source of the third NMOS transistor NM3 is grounded to GND. If necessary, the substrates of the first NMOS transistor NM1 and the substrates of the third NMOS transistor NM3 are both grounded to GND. The drain of the eighth PMOS transistor MP8 is connected to the drain of the second NMOS transistor NM2; the gate of the second NMOS transistor NM2 is connected to a second bias voltage Vb2 provided externally, providing bias current for the second NMOS transistor NM2; the source of the second NMOS transistor NM2 is connected to the drain of the fourth NMOS transistor NM4; the gate of the fourth NMOS transistor NM4 is connected to a third bias voltage Vb3 provided externally, providing bias current for the fourth NMOS transistor NM4; the source of the fourth NMOS transistor NM4 is grounded to GND. Necessarily, the substrates of both the second NMOS transistor NM2 and the fourth NMOS transistor NM4 are grounded to GND.The connection node 41 between the drain of the seventh PMOS transistor MP7 and the drain of the first NMOS transistor NM1 is the positive output terminal of the first-stage amplifier circuit, used to output the differential output signal VOP1; the connection node 42 between the drain of the eighth PMOS transistor MP8 and the drain of the second NMOS transistor NM2 is the negative output terminal of the first-stage amplifier circuit, used to output the differential output signal VON1; wherein, the differential output terminal of the first-stage amplifier circuit includes both the positive and negative output terminals. The average values ​​of the differential output signals VON1 and VOP1, i.e., the common-mode voltages of the differential output signals VON1 and VOP1, are both adjusted and stabilized to the common-mode reference voltage under the action of the first common-mode feedback circuit.

[0028] In the foregoing embodiments, such as Figure 1 As shown, the first bias voltage Vb1, the second bias voltage Vb2, and the third bias voltage Vb3 are not equal to each other, so as to form a voltage difference between different pairs of MOSFETs. The voltage difference between any two of the first, second, and third bias voltages remains constant, ensuring a constant voltage difference and helping to suppress channel length modulation effects. It should be noted that the first, second, and third bias voltages are all provided by corresponding bias voltage sources. It should also be noted that the above bias voltage sources can also be implemented using voltage regulator devices or voltage regulator circuits. This embodiment does not limit this. For input power supply circuits, the aforementioned bias voltages can be designed to be stable relative to ground.

[0029] Combination Figure 2It is known that the positive and negative output terminals of the first-stage amplifier circuit are respectively connected to the differential input terminals (including the positive and negative input terminals) of the first common-mode feedback circuit. The positive input terminal of the first common-mode feedback circuit CMFB1 is used to receive the differential output signal VOP1 output from the positive output terminal of the first-stage amplifier circuit, and the negative input terminal of the first common-mode feedback circuit CMFB1 is used to receive the differential output signal VON1 output from the negative output terminal of the first-stage amplifier circuit. The first feedback terminal and the second feedback terminal of the current mirror circuit are both connected to the output terminal of the first common-mode feedback circuit CMFB1. The first common-mode feedback circuit CMFB1 provides a feedback control signal Vfb1 to the first and second feedback terminals of the current mirror circuit to adjust the differential output result of the first-stage amplifier circuit, specifically making the common-mode voltage of the first-stage amplifier circuit output equal to the common-mode reference voltage Vcom. It should be noted that the feedback terminals of the current mirror circuit include the first and second feedback terminals of the current mirror circuit. When the operating loop of the current mirror circuit, the first-stage amplifier circuit, and the first common-mode feedback circuit is stable, the differential output of the first-stage amplifier circuit stabilizes at the common-mode reference voltage, thereby enabling the voltage of the differential output signal VOP1 to be equal to the common-mode reference voltage, and the voltage of the differential output signal VON1 to be equal to the common-mode reference voltage.

[0030] As one example, such as Figure 1As shown, the second-stage amplifier circuit includes a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6. The source of the ninth PMOS transistor MP9 is connected to the first power supply terminal of the current mirror circuit, which is used to connect to the power supply VDD. The gate of the ninth PMOS transistor MP9 is the positive input terminal of the second-stage amplifier circuit, and the gate of the ninth PMOS transistor MP9 is connected to the positive output terminal of the first-stage amplifier circuit. It is used to receive the differential signal VOP1 output from the positive output terminal of the first-stage amplifier circuit or the common-mode reference voltage Vcom adjusted by the first common-mode feedback circuit, so that the second-stage amplifier circuit and the first-stage amplifier circuit are cascaded. The output of the first-stage amplifier circuit can be used as the bias signal of the second-stage amplifier circuit, which plays a role in controlling the second-stage amplifier circuit. Thus, the input impedance of the differential operational amplifier is improved due to the cascaded structure of the multi-stage amplifier circuit. The source of the fifth NMOS transistor NM5 is grounded to GND. The drain of the ninth PMOS transistor MP9 is connected to the drain of the fifth NMOS transistor NM5. The connection point between the drains of the ninth PMOS transistor MP9 and the fifth NMOS transistor NM5 is the positive output terminal of the second-stage amplifier circuit, used to output the differential output signal VOP2, which serves as the differential signal output from the positive output terminal of the differential operational amplifier. The source of the tenth PMOS transistor MP10 is connected to the second power supply terminal of the current mirror circuit, used to connect to the power supply VDD. The gate of the tenth PMOS transistor MP10 is the negative input terminal of the second-stage amplifier circuit. The gate of the tenth PMOS transistor MP10 is connected to the negative output terminal of the first-stage amplifier circuit, used to receive the differential signal VON1 output from the negative output terminal of the first-stage amplifier circuit or the common-mode reference voltage Vcom adjusted by the first common-mode feedback circuit. This allows the second-stage amplifier circuit to be cascaded with the first-stage amplifier circuit, thus increasing the input impedance of the differential operational amplifier due to the cascaded structure of the multi-stage amplifier circuit. The source of the sixth NMOS transistor NM6 is grounded; the drain of the tenth PMOS transistor MP10 is connected to the drain of the sixth NMOS transistor NM6. The connection point between the drains of the tenth PMOS transistor MP10 and the sixth NMOS transistor NM6 is the negative output terminal of the second-stage amplifier circuit, used to output the differential output signal VON2, which serves as the differential signal output from the negative output terminal of the differential operational amplifier. Figure 1 and Figure 2It can be seen that the positive output terminal and the negative output terminal of the second-stage amplifier circuit are respectively connected to the differential input terminal (including the positive input terminal and the negative input terminal) of the second common-mode feedback circuit; the positive input terminal of the second common-mode feedback circuit CMFB2 is used to receive the differential output signal VOP2 output from the positive output terminal of the second-stage amplifier circuit, and the negative input terminal of the second common-mode feedback circuit CMFB2 is used to receive the differential output signal VON2 output from the negative output terminal of the second-stage amplifier circuit. The gate of the fifth NMOS transistor NM5 is the first feedback terminal of the second-stage amplifier circuit, and the gate of the fourth NMOS transistor NM4 is the second feedback terminal of the second-stage amplifier circuit. Both the first and second feedback terminals of the second-stage amplifier circuit are connected to the output terminal of the second common-mode feedback circuit. The second common-mode feedback circuit CMFB2 provides a feedback control signal Vfb2 to the first and second feedback terminals of the second-stage amplifier circuit to adjust the differential output of the second-stage amplifier circuit. Specifically, it ensures that the common-mode voltage of the second-stage amplifier circuit output (the average voltage of the differential output signals VON2 and VOP2) is equal to the common-mode reference voltage Vcom. When the working loop formed by the current mirror circuit, the first-stage amplifier circuit, the first common-mode feedback circuit, the second-stage amplifier circuit, and the second common-mode feedback circuit is stable, the differential output of the second-stage amplifier circuit stabilizes at the common-mode reference voltage. This allows the voltage of the differential output signal VOP2 to be equal to the common-mode reference voltage, and the voltage of the differential output signal VON2 to be equal to the common-mode reference voltage. In summary, in the aforementioned embodiments, the output of the first-stage amplifier circuit provides bias for the input of the second-stage amplifier circuit, and both stages of the amplifier circuit have their own matched common-mode feedback circuits to adjust the differential signal output by the operational amplifier of this stage, so that the corresponding common-mode voltage is equal to the common-mode reference voltage. In this way, the two stages of the amplifier circuit can share the current of the current mirror circuit, increase the input impedance of the differential operational amplifier, thereby increasing the overall gain and expanding the output range.

[0031] It should be noted that the feedback terminals of the current mirror circuit include the first feedback terminal and the second feedback terminal of the current mirror circuit; the differential input terminals of the second-stage amplifier circuit include the positive input terminal and the negative input terminal of the second-stage amplifier circuit; the differential output terminals of the second-stage amplifier circuit include the positive output terminal and the negative output terminal of the second-stage amplifier circuit; the differential output terminals of the first-stage amplifier circuit include the positive output terminal and the negative output terminal of the first-stage amplifier circuit; the power supply terminals of the current mirror circuit include the first power supply terminal and the second power supply terminal of the current mirror circuit; the feedback terminals of the second-stage amplifier circuit include the first feedback terminal and the second feedback terminal of the second-stage amplifier circuit. Therefore, the differential input terminals of the second-stage amplifier circuit receive the output of the first-stage amplifier circuit and the feedback control signal Vfb2 provided by the second common-mode feedback circuit CMFB2, respectively.

[0032] Combination Figure 2 It can be seen that the first common-mode feedback circuit CMFB1 and the second common-mode feedback circuit CMFB2 belong to the same type of common-mode feedback structure. Both CMFB1 and CMFB2 are connected to the same common-mode reference voltage Vcom. CMFB1 compares the differential signal output from the first-stage amplifier circuit with the common-mode reference voltage, generating a feedback control signal for the feedback terminal of the current mirror circuit. This ensures that the output of the differential operational amplifier is stabilized at the same common-mode level, i.e., the differential signal output from the first-stage amplifier circuit is stabilized at the common-mode reference voltage. The common-mode reference voltage Vcom is such that the average voltage of the differential signal output by the first-stage amplifier circuit (the common-mode voltage corresponding to the differential signal) is equal to the common-mode reference voltage Vcom. The second common-mode feedback circuit CMFB2 is used to compare the differential signal output by the second-stage amplifier circuit with the common-mode reference voltage, and generate a feedback control signal to the feedback terminal of the second-stage amplifier circuit, so that the differential signal output by the second-stage amplifier circuit is stabilized at the common-mode reference voltage Vcom, and the average voltage of the differential signal output by the second-stage amplifier circuit (the common-mode voltage corresponding to the differential signal) is equal to the common-mode reference voltage Vcom.

[0033] It should be noted that the common-mode feedback structure can be classified into continuous-time common-mode feedback circuits and switched-capacitor common-mode feedback circuits. Continuous-time common-mode feedback circuits perform continuous calibration of the output common-mode voltage offset. However, switched-capacitor common-mode feedback circuits provide discrete feedback control of the output common-mode voltage, completing the calibration within half a clock cycle of each charge transfer. Continuous-time common-mode feedback circuits are mainly used in continuous-time circuits, but they have disadvantages such as limiting the differential-mode output signal swing, increasing differential-mode load, increasing static power consumption, and nonlinearity in common-mode voltage detection. Switched-capacitor common-mode feedback circuits have advantages in these aspects, but they are unsuitable for continuous-time circuits because they introduce clock coupling and discrete operating states that cause glitches in the differential output signal. Switched-capacitor common-mode feedback circuits have been successfully applied in data sampling systems, especially in fully differential switched-capacitor circuits. Specifically, a common-mode feedback circuit is generally divided into two parts: a common-mode detection circuit and a comparator amplifier circuit. The common-mode detection circuit detects the output common-mode voltage, which is then input to the comparator amplifier circuit and compared with a pre-specified common-mode reference voltage. The difference between them is amplified and returned to the original circuit to correct the offset of the output common-mode voltage.

[0034] In one implementation method, when the average voltage of the differential signal output from the differential output terminal of the first-stage amplifier circuit is greater than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal to lower the average voltage of the differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and to stably equal the common-mode reference voltage. When the average voltage of the differential signal output from the first-stage amplifier circuit is less than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal to raise the average voltage of the differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and to stably equal the common-mode reference voltage. Therefore, in this embodiment, the voltage of the differential input to the first-stage amplifier circuit often cannot reach the expected voltage value during production due to process deviations or other factors. The common-mode feedback circuit is needed to adjust the average voltage of the output differential signal, i.e., the common-mode voltage, to the expected voltage, i.e., the common-mode reference voltage.

[0035] As a second implementation method, when the voltage of the first differential signal output from the differential output terminal of the first-stage amplifier circuit is greater than the common-mode reference voltage, and the voltage of the second differential signal output from the first-stage amplifier circuit is less than the common-mode reference voltage, the first common-mode feedback circuit generates a corresponding feedback control signal to pull down the voltage of the first differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and simultaneously pull up the voltage of the second differential signal output from the first-stage amplifier circuit to reach the common-mode reference voltage, and ensure that the adjusted voltages of the first and second differential signals are both equal to the common-mode reference voltage, and remain stable at the common-mode reference voltage.

[0036] In combination with embodiments one and two, the first common-mode feedback circuit is used to generate a feedback control signal to the feedback terminal of the current mirror circuit, so as to adjust the average voltage of the differential signal output by the first-stage amplifier circuit to be equal to the common-mode reference voltage.

[0037] In one implementation method three, when the average voltage of the differential signal output from the differential output terminal of the second-stage amplifier circuit is greater than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal to lower the average voltage of the differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage, and ensures that the average voltage is stably equal to the common-mode reference voltage. When the average voltage of the differential signal output from the second-stage amplifier circuit is less than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal to raise the average voltage of the differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage, and ensures that the average voltage is stably equal to the common-mode reference voltage. Therefore, in this embodiment, the voltage of the differential input second-stage amplifier circuit often cannot reach the expected voltage value during production due to process deviations or other factors. The common-mode feedback circuit is needed to adjust the average voltage of the output differential signal, i.e., the common-mode voltage, to the expected voltage, i.e., the common-mode reference voltage.

[0038] In one implementation method four, when the voltage of the first differential signal output from the differential output terminal of the second-stage amplifier circuit is greater than the common-mode reference voltage, and the voltage of the second differential signal output from the second-stage amplifier circuit is less than the common-mode reference voltage, the second common-mode feedback circuit generates a corresponding feedback control signal to pull down the voltage of the first differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage, and simultaneously pull up the voltage of the second differential signal output from the second-stage amplifier circuit to reach the common-mode reference voltage. Then, the adjusted voltages of the first and second differential signals are both equal to the common-mode reference voltage and kept stable at the common-mode reference voltage.

[0039] In combination with embodiments three and four, the second common-mode feedback circuit is used to generate a feedback control signal to the feedback terminal of the second-stage amplifier circuit, so as to adjust the average voltage of the differential signal output by the second-stage amplifier circuit to be equal to the common-mode reference voltage.

[0040] Based on the foregoing embodiments, the present invention also discloses a chip internally equipped with the differential operational amplifier described in the foregoing embodiments. This differential operational amplifier can be applied to the front-end (or input stage) of the chip as a driver amplifier or the first-stage amplifier in an analog-to-digital converter (ADC). In this case, the differential operational amplifier determines the signal gain of the chip and the signal stability at the output stage. Preferably, the differential input and output terminals of the differential operational amplifier can be connected to external resistors and capacitors to construct an operational architecture suitable for adders, subtractors, integrators, and the currently required operational functions.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications can still be made to the specific implementation of the present invention or equivalent substitutions can be made to some technical features without departing from the spirit of the technical solutions of the present invention, and all such modifications and substitutions should be covered within the scope of the technical solutions claimed in the present invention.

Claims

1. A differential operational amplifier characterized by comprising: The differential operational amplifier comprises a current mirror circuit, a first-stage amplification circuit, a second-stage amplification circuit and a common-mode feedback circuit; wherein the current mirror circuit, the first-stage amplification circuit and the second-stage amplification circuit all support differential input and differential output; The differential output end of the first-stage amplification circuit is connected to the differential input end of the second-stage amplification circuit in correspondence; the differential output end of the first-stage amplification circuit is also connected to the feedback end of the current mirror circuit through the common-mode feedback circuit; The differential output end of the second-stage amplification circuit is connected to the feedback end of the second-stage amplification circuit through the common-mode feedback circuit; the differential output end of the second-stage amplification circuit is the output end of the differential operational amplifier; The output end of the current mirror circuit is connected to the power supply end of the first-stage amplification circuit; the input end of the current mirror circuit is used for receiving an external input signal of the differential operational amplifier; The common-mode feedback circuit comprises a first common-mode feedback circuit and a second common-mode feedback circuit; The differential output end of the first-stage amplification circuit is connected to the differential input end of the second-stage amplification circuit in correspondence; the differential output end of the first-stage amplification circuit is also connected to the feedback end of the current mirror circuit through the first common-mode feedback circuit; The differential output end of the second-stage amplification circuit is connected to the feedback end of the second-stage amplification circuit through the second common-mode feedback circuit; the differential output end of the second-stage amplification circuit is the output end of the differential operational amplifier; The current mirror circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; The gate of the third PMOS tube is the first positive input end of the differential operational amplifier, the gate of the fifth PMOS tube is the second positive input end of the differential operational amplifier, the gate of the fourth PMOS tube is the first negative input end of the differential operational amplifier, and the gate of the sixth PMOS tube is the second negative input end of the differential operational amplifier; The drain of the third PMOS tube is connected to the drain of the fifth PMOS tube, and the connection node of the drain of the third PMOS tube and the drain of the fifth PMOS tube is the first output end of the current mirror circuit; the drain of the fourth PMOS tube is connected to the drain of the sixth PMOS tube, and the connection node of the drain of the fourth PMOS tube and the drain of the sixth PMOS tube is the second output end of the current mirror circuit; wherein the output end of the current mirror circuit comprises the first output end of the current mirror circuit and the second output end of the current mirror circuit; The source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the drain of the first PMOS tube, and the source of the fifth PMOS tube and the source of the sixth PMOS tube are both connected to the drain of the second PMOS tube; The gate of the first PMOS tube is the first feedback end of the current mirror circuit, the gate of the second PMOS tube is the second feedback end of the current mirror circuit, and the gate of the first PMOS tube and the gate of the second PMOS tube are both connected to the output end of the first common-mode feedback circuit; the feedback end of the current mirror circuit comprises the first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit; The source of the first PMOS transistor is a first power supply end of the current mirror circuit, and the source of the second PMOS transistor is a second power supply end of the current mirror circuit; the power supply ends of the current mirror circuit include the first power supply end of the current mirror circuit and the second power supply end of the current mirror circuit.

2. The differential operational amplifier of claim 1, wherein, The differential operational amplifier is a four-input operational amplifier, wherein the positive input end of the differential operational amplifier includes the first positive input end of the differential operational amplifier and the second positive input end of the differential operational amplifier, and the negative input end of the differential operational amplifier includes the first negative input end of the differential operational amplifier and the second negative input end of the differential operational amplifier; The first positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are used to access a pair of differential signals to be processed; The first negative input end of the differential operational amplifier and the second positive input end of the differential operational amplifier are both accessed to a common-mode reference voltage; The first positive input end of the differential operational amplifier, the first negative input end of the differential operational amplifier, the second positive input end of the differential operational amplifier and the second negative input end of the differential operational amplifier are all input ends of the current mirror circuit. The power supply accessed by the power supply end of the second-stage amplification circuit is equal to the power supply accessed by the power supply end of the current mirror circuit; and the ground end of the second-stage amplification circuit and the ground end of the first-stage amplification circuit share a ground wire.

3. The differential operational amplifier of claim 2, wherein, The first-stage amplification circuit includes a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The source of the seventh PMOS transistor is a first power supply end of the first-stage amplification circuit, and the first power supply end of the first-stage amplification circuit is connected with a first output end of the current mirror circuit; the source of the eighth PMOS transistor is a second power supply end of the first-stage amplification circuit, and the second power supply end of the first-stage amplification circuit is connected with a second output end of the current mirror circuit; the gate of the seventh PMOS transistor is accessed to a first bias voltage provided by an external environment; the gate of the eighth PMOS transistor is accessed to the first bias voltage provided by the external environment; wherein the power supply ends of the first-stage amplification circuit include the first power supply end of the first-stage amplification circuit and the second power supply end of the first-stage amplification circuit; and the output ends of the current mirror circuit include the first output end of the current mirror circuit and the second output end of the current mirror circuit; The drain of the seventh PMOS transistor is connected with the drain of the first NMOS transistor, the gate of the first NMOS transistor is accessed to a second bias voltage provided by an external environment, the source of the first NMOS transistor is connected with the drain of the third NMOS transistor, the gate of the third NMOS transistor is accessed to a third bias voltage provided by the external environment, and the source of the third NMOS transistor is grounded; The drain of the eighth PMOS transistor is connected with the drain of the second NMOS transistor, the gate of the second NMOS transistor is accessed to the second bias voltage provided by the external environment, the source of the second NMOS transistor is connected with the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is accessed to the third bias voltage provided by the external environment, and the source of the fourth NMOS transistor is grounded; The connection node of the drain of the seventh PMOS tube and the drain of the first NMOS tube is a positive output end of the first-stage amplification circuit, and the connection node of the drain of the eighth PMOS tube and the drain of the second NMOS tube is a negative output end of the first-stage amplification circuit; wherein the differential output end of the first-stage amplification circuit comprises the positive output end of the first-stage amplification circuit and the negative output end of the first-stage amplification circuit; The positive output end of the first-stage amplification circuit and the negative output end of the first-stage amplification circuit are connected with the differential input end of the first common-mode feedback circuit respectively, and the first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit are connected with the output end of the first common-mode feedback circuit, so as to adjust the differential output result of the first-stage amplification circuit; wherein the feedback end of the current mirror circuit comprises the first feedback end of the current mirror circuit and the second feedback end of the current mirror circuit.

4. The differential operational amplifier of claim 2, wherein, The second-stage amplification circuit comprises a ninth PMOS tube, a tenth PMOS tube, a fifth NMOS tube and a sixth NMOS tube; The source of the ninth PMOS tube is connected with the first power supply end of the current mirror circuit, the drain of the ninth PMOS tube is connected with the drain of the fifth NMOS tube, the gate of the ninth PMOS tube is a positive input end of the second-stage amplification circuit, the gate of the ninth PMOS tube is connected with the positive output end of the first-stage amplification circuit, and the source of the fifth NMOS tube is grounded; the connection node of the drain of the ninth PMOS tube and the drain of the fifth NMOS tube is a positive output end of the second-stage amplification circuit; The source of the tenth PMOS tube is connected with the second power supply end of the current mirror circuit, the drain of the tenth PMOS tube is connected with the drain of the sixth NMOS tube, the gate of the tenth PMOS tube is a negative input end of the second-stage amplification circuit, the gate of the tenth PMOS tube is connected with the negative output end of the first-stage amplification circuit, and the source of the sixth NMOS tube is grounded; The connection node of the drain of the tenth PMOS tube and the drain of the sixth NMOS tube is a negative output end of the second-stage amplification circuit; The positive output end of the second-stage amplification circuit and the negative output end of the second-stage amplification circuit are connected with the differential input end of the second common-mode feedback circuit respectively; The gate of the fifth NMOS tube is a first feedback end of the second-stage amplification circuit, the gate of the fourth NMOS tube is a second feedback end of the second-stage amplification circuit, and the first feedback end of the second-stage amplification circuit and the second feedback end of the second-stage amplification circuit are connected with the output end of the second common-mode feedback circuit, so as to adjust the differential output result of the second-stage amplification circuit; Wherein the differential input end of the second-stage amplification circuit comprises the positive input end of the second-stage amplification circuit and the negative input end of the second-stage amplification circuit; the differential output end of the second-stage amplification circuit comprises the positive output end of the second-stage amplification circuit and the negative output end of the second-stage amplification circuit; the differential output end of the first-stage amplification circuit comprises the positive output end of the first-stage amplification circuit and the negative output end of the first-stage amplification circuit; the power supply end of the current mirror circuit comprises the first power supply end of the current mirror circuit and the second power supply end of the current mirror circuit; and the feedback end of the second-stage amplification circuit comprises the first feedback end of the second-stage amplification circuit and the second feedback end of the second-stage amplification circuit.

5. The differential operational amplifier of claim 3, wherein, The first bias voltage, the second bias voltage and the third bias voltage are different from each other to form voltage differences between different pairs of MOS transistors. Among the first bias voltage, the second bias voltage and the third bias voltage, the voltage difference between any two bias voltages is kept constant; the first bias voltage, the second bias voltage and the third bias voltage are all provided by corresponding bias voltage sources.

6. The differential operational amplifier of claim 1, wherein, The first common-mode feedback circuit and the second common-mode feedback circuit belong to the same type of common-mode feedback structure, and the first common-mode feedback circuit and the second common-mode feedback circuit are connected to the same common-mode reference voltage, so that the output of the differential operational amplifier is stabilized to the same common-mode level.

7. The differential operational amplifier of claim 6, wherein, The first common-mode feedback circuit is used to generate a feedback control signal to the feedback end of the current mirror circuit, so as to adjust the voltage average of the differential signal output by the first-stage amplification circuit to be equal to the common-mode reference voltage. The second common-mode feedback circuit is used to generate a feedback control signal to the feedback end of the second-stage amplification circuit, so as to adjust the voltage average of the differential signal output by the second-stage amplification circuit to be equal to the common-mode reference voltage.

8. A chip, characterized by The chip internally has the differential operational amplifier of any one of claims 1 to 7.

Images