Printed circuit board and electronic component package

Abstract

A printed circuit board and an electronic component package are provided. The printed circuit board includes a first insulating layer, an external connection pad embedded in a first surface of the first insulating layer and having a first external exposure surface disposed at substantially the same height as a height of the first surface of the first insulating layer, a second insulating layer disposed on a second surface of the first insulating layer and having a first surface in contact with the second surface of the first insulating layer, and a first wiring pattern embedded in the second insulating layer and exposed from a first surface of the second insulating layer to be in contact with a second external exposure surface of the external connection pad opposite the first external exposure surface.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0166989, filed on December 2, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to a printed circuit board and an electronic component package. Background Technology

[0003] As the pitch of semiconductor chip nodes decreases, the pitch of the connection pads formed on the printed circuit board (PCB) that connects to the semiconductor chip also becomes finer. Furthermore, due to the limitations of electronic product thickness, PCBs used in small electronic products (such as mobile phones) are packaged by mounting semiconductor chips, including single-chip and stacked chips.

[0004] Embedded Track Substrate (ETS) is used as a method for manufacturing printed circuit boards to produce thin printed circuit boards with ultra-fine pitch connection pads, and printed circuit boards manufactured by this ETS method have been commercialized.

[0005] Because the wire bonding pads and the insulating layer in which the wire bonding pads are embedded may be uneven in printed circuit boards manufactured by the ETS method, the bonding of chips connected to the wire bonding pads is not excellent.

[0006] In situations where the thickness of electronic products is limited, there is a need to provide techniques to increase the number of wire bonding pads per unit area by minimizing the pitch of the wire bonding pads connected to extremely small chip nodes. Summary of the Invention

[0007] One aspect of this disclosure is to provide a printed circuit board including an external connection pad formed as flat and an insulating layer embedded therein.

[0008] One aspect of this disclosure is to provide a printed circuit board in which only external connection pads are formed in a single insulating layer without other wiring patterns, and wiring patterns connected to the external connection pads are formed in another insulating layer, so as to form external connection pads with ultra-fine pitch in a single insulating layer.

[0009] One aspect of this disclosure is to provide an electronic component package including a printed circuit board in which external connection pads are formed in a single insulating layer without other wiring patterns and have ultra-fine pitch.

[0010] According to one aspect of this disclosure, a printed circuit board includes: a first insulating layer; an external connection pad embedded in a first surface of the first insulating layer and having a first external exposed surface disposed at a height substantially the same as the height of the first surface of the first insulating layer; a second insulating layer disposed on a second surface of the first insulating layer and having a first surface in contact with the second surface of the first insulating layer; and a first wiring pattern embedded in the second insulating layer and exposed from the first surface of the second insulating layer to contact a second external exposed surface of the external connection pad opposite to the first external exposed surface.

[0011] Furthermore, according to another aspect of this disclosure, a printed circuit board includes: a first insulating layer; a first external connection pad and a second external connection pad embedded in the first insulating layer, the second external connection pad being spaced apart from the first external connection pad; and a second insulating layer including a first wiring pattern connected to each of the first external connection pad and the second external connection pad, wherein a first surface of the first external connection pad and a first surface of the second external connection pad are exposed to a first surface of the first insulating layer and are substantially coplanar with the first surface of the first insulating layer, and the first insulating layer and the second insulating layer are different layers from each other.

[0012] Furthermore, according to another aspect of this disclosure, an electronic component package includes: a printed circuit board including a first insulating layer and a second insulating layer, an external connection pad embedded in the first insulating layer, the first insulating layer having a thickness substantially the same as the thickness of the external connection pad, the second insulating layer contacting the first insulating layer and including a first wiring pattern connected to the external connection pad; a semiconductor chip connected to the external connection pad; and an encapsulation layer encapsulating the semiconductor chip. Attached Figure Description

[0013] The above and other aspects, features, and advantages of this disclosure will be more clearly understood from the accompanying drawings and the following detailed description, in which:

[0014] Figure 1 This is a schematic diagram showing a cross-section of a printed circuit board according to an exemplary embodiment of the present disclosure;

[0015] Figures 2A to 2I It shows the manufacturing process. Figure 1 A cross-sectional view of the method for making printed circuit boards;

[0016] Figure 3 and Figure 4 This is a schematic diagram illustrating an electronic component package formed by combining a semiconductor chip and a printed circuit board according to an example embodiment. Detailed Implementation

[0017] Preferred exemplary embodiments of this disclosure will be described with reference to the accompanying drawings.

[0018] Various modifications may be made to the exemplary embodiments, and the exemplary embodiments are provided to help those skilled in the art to obtain a thorough and comprehensive understanding. Therefore, for clarity, the shape and size of the elements in the drawings may be exaggerated, and elements indicated by the same reference numerals in the drawings refer to the same elements.

[0019] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on" another element, "connected" to another element, or "bonded" to another element, the element may be directly "on" the other element, directly "connected" to the other element, or directly "bonded" to the other element, or there may be one or more other elements in between. In contrast, when an element is described as being "directly on" another element, "directly connected" to another element, or "directly bonded" to another element, there are no other elements in between.

[0020] Although terms such as “first” and “second” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts are not limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Therefore, without departing from the teachings of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as the first component, first assembly, first region, first layer, or first part may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0021] The terminology used herein is for the purpose of describing various examples only and is not intended to limit this disclosure. In this context, unless otherwise stated, singular expressions include plural expressions.

[0022] Printed Circuit Board

[0023] Figure 1 This is a schematic diagram showing a cross-section of a printed circuit board according to an exemplary embodiment of the present disclosure.

[0024] Reference Figure 1 The printed circuit board 1 includes a first insulating layer 10, external connection pads 50 and 55, a second insulating layer 20, and a first wiring pattern 22.

[0025] External connection pads 50 and 55 are embedded in the first insulating layer 10, and the first insulating layer 10 has substantially the same thickness as the external connection pads 50 and 55. The external connection pads include a plurality of external connection pads (including the first external connection pad 50 and the second external connection pad 55), and the distance between the first external connection pad 50 and the second external connection pad 55 can form an ultra-fine pitch. Furthermore, the fact that the first insulating layer 10 has substantially the same thickness as the external connection pads 50 and 55 means that the first surface 10a of the first external connection pad 50 and the first surface 10a of the second external connection pad 55 are set at substantially the same height and formed as the first surface 10a of the first insulating layer, thus having substantially the same thickness. The statement "substantially the same" means that the process errors, positional offsets, and measurement errors occurring in the manufacturing process are the same within permissible ranges.

[0026] The thicknesses of the external connection pads 50 and 55 are substantially the same as the thickness of the first insulating layer 10, and the external connection pads 50 and 55 are exposed from the first surface 10a and the second surface 10b of the first insulating layer opposite to the first surface 10a. In a semiconductor chip package, the external connection pads 50 and 55 exposed from the first surface 10a of the first insulating layer 10 can be wire bonding pads through which the semiconductor chip is wire-bonded to the printed circuit board, or connection pads through which the semiconductor chip is flip-chip bonded to the printed circuit board. The fact that the thicknesses are substantially the same means that the thicknesses are within the allowable range of process errors, positional offsets, and measurement errors that occur during the manufacturing process.

[0027] The second insulating layer 20 is disposed on the second surface 10b of the first insulating layer 10, and the first surface 20a of the second insulating layer 20 is in contact with the second surface 10b of the first insulating layer 10. The first insulating layer 10 and the second insulating layer 20 are different layers and can be distinguished from each other.

[0028] The second insulating layer 20 includes a first wiring pattern 22 embedded therein. The first wiring pattern 22 is exposed from a first surface 20a of the second insulating layer 20 to contact the opposite surface of the exposed external surface of the external connection pad 50. Furthermore, a second wiring pattern 24, spaced apart from the first wiring pattern 22, is embedded in the second insulating layer 20. Here, compared to the first wiring pattern 22, the second wiring pattern 24 does not directly contact and is not connected to the external connection pads 50 and 55. The second wiring pattern 24 can be connected via a via 60 to a third wiring pattern 42 embedded in a third insulating layer 40, which is disposed on a second surface 20b of the second insulating layer 20 opposite to the first surface 20a of the second insulating layer 20. Figure 1As shown, the surface of the first wiring pattern 22 opposite to the portion of the first wiring pattern 22 connected to the external connection pad is spaced apart from the second surface 20b of the second insulating layer 20, and the second surface 20b of the second insulating layer 20 is opposite to the first surface 20a of the second insulating layer 20.

[0029] The second insulating layer 20 and the third insulating layer 40 are repeatedly stacked to form a multilayer circuit board, and the number of layers of the second insulating layer 20 and the third insulating layer 40 can be determined as needed. In addition, the third wiring pattern 42 of the third insulating layer 40 can be the outermost wiring pattern (specifically, the bottommost wiring pattern) as in this example embodiment.

[0030] The external connection pads 50 and 55 are exposed to the outside and are configured to have a structure in which a first metal layer 52 and a second metal layer 54 are stacked sequentially from the outside to the inside in the thickness direction of the first insulating layer 10 and the second insulating layer 20.

[0031] The first metal layer 52 may include any one of a gold (Au) layer, a silver (Ag) layer, and a nickel (Ni) layer. The first metal layer 52 is a metal pad electrically connected to the semiconductor chip during the formation of the package, and may be a metal layer formed by plating Au to facilitate wire bonding.

[0032] The second metal layer 54 may include any one of a gold (Au) layer, a silver (Ag) layer, and a nickel (Ni) layer. The second metal layer 54 is not specifically limited, as long as it is a metal layer electrically connectable to the first wiring pattern 22 of the second insulating layer 20, and the second metal layer 54 may be a metal layer formed by plating Ni. Optionally, the second metal layer may be formed as a multilayer structure in which Ag layers and Ni layers are stacked.

[0033] Since the first metal layer 52 is formed to a depth that allows for wire bonding, the second metal layer 54 is thicker than the first metal layer 52.

[0034] The outer bonding pads 50, including the first metal layer 52 and the second metal layer 54, have a thickness substantially the same as that of the first insulating layer 10, and the upper surface of the first metal layer 52 is formed to be substantially coplanar with the first surface 10a of the first insulating layer. This improves the reliability of wire bonding. The fact that the thickness is substantially the same means that the thickness is within the allowable range of process errors, positional offsets, and measurement errors that occur during the manufacturing process.

[0035] The printed circuit board 1 according to this example embodiment may further include a solder resist layer 45 located on the first insulating layer 10 to protect the external connection pads 50. The solder resist layer 45 may be laminated using photosensitive solder resist (PSR) ink via screen printing. The area and size of the solder resist coating are determined according to the pattern shape and size of the designed external connection pads 50, and the solder resist layer 45 includes openings 452 that expose the external connection pads 50. When the openings 452 are formed using a laser, a non-photosensitive thermosetting resin is used as the material for the solder resist layer 45.

[0036] Furthermore, the first insulating layer 10 may include a thermosetting insulating resin or a photosensitive insulating resin. The first insulating layer 10 may include a photosensitive solder resist ink of the same material as the solder resist layer 45, and protect the external connection pads 50 and 55 embedded in the first insulating layer 10.

[0037] The second insulating layer 20 may include a glass-containing insulating material or an inorganic insulating layer that does not contain glass.

[0038] Figures 2A to 2I It shows the manufacturing process. Figure 1 A cross-sectional view of a method for making printed circuit boards.

[0039] Figures 2A to 2I This is a diagram illustrating an embodiment of a method for manufacturing a printed circuit board according to an example embodiment. Unless a specific order is explicitly stated in the context, the various processes may be performed in a different order.

[0040] exist Figure 2A The invention provides an insulating core 100 on at least one surface of which a base copper layer 102 is stacked. In this example embodiment, the insulating core 100 may be a carrier board on which the base copper layers 102 are stacked on both sides. A first insulating layer 10 is then stacked on the base copper layer 102. In the first insulating layer 10, contact holes 15 are formed according to a designed circuit pattern, and the base copper layer 102 is selectively exposed. The base copper layer 102 serves as a plating seed layer for forming external connection pads.

[0041] The first insulating layer 10 may comprise a thermosetting insulating resin or a photosensitive insulating resin. Photosensitive solder resist ink may be used as the photosensitive insulating resin, and contact holes 15 of the first insulating layer 10 can be formed with ultra-fine pitches by performing photolithography on the first insulating layer 10.

[0042] Reference Figure 2B The process of forming the first external connection pad 50 is performed by plating the base copper layer 102 exposed by the finely patterned contact holes 15 to fill the contact holes 15. The plating is performed by electroplating, chemical plating or sputtering, and the first external connection pad 50 eventually becomes an external connection pad such as a wire bonding pad or a flip chip connection pad.

[0043] The first external connection pad 50 includes a first metal layer 52 formed by first plating a base copper layer 102 and a second metal layer 54 formed by replating after the formation of the first metal layer 52. Although not shown in the figures, the second external connection pad may be formed during the process of forming the first external connection pad 50.

[0044] The first metal layer 52 can be formed by plating any one of a gold (Au) layer, a silver (Ag) layer, and a nickel (Ni) layer. The first metal layer 52 is a metal pad electrically connected to the semiconductor chip during the formation of the package, and can be a metal layer formed by plating Au to facilitate wire bonding.

[0045] The second metal layer 54 may also include any one of a gold (Au) layer, a silver (Ag) layer, and a nickel (Ni) layer. The second metal layer 54 may be a metal layer formed by plating nickel (Ni). Optionally, the second metal layer may be formed as multiple layers in which Ag layers and Ni layers are stacked.

[0046] Since the first metal layer 52 is formed thin enough to allow wire bonding, the second metal layer 54 is thicker than the first metal layer 52.

[0047] Reference Figure 2C and Figure 2D The process of stacking wiring patterns on the first insulating layer 10 is performed.

[0048] First of all, Figure 2C In this process, a resist pattern layer 200 is stacked on a first insulating layer 10. The resist pattern layer 200 includes contact holes 25 that expose a first external connection pad 50 and wiring pattern holes 27 in which wiring patterns will be formed. A base copper layer (not shown) for wiring pattern plating is formed on the lower surface of the resist pattern layer 200. The contact holes 25 and wiring pattern holes 27 of the resist pattern layer 200 can be plated using the base copper layer to form wiring patterns 22 and 24. As a method for forming the contact holes 25 and wiring pattern holes 27, photolithography, laser drilling, etc., can be performed. Plating for forming wiring patterns 22 and 24 can be performed by electroplating, chemical plating, or sputtering, and copper (Cu) can be used as the material for forming wiring patterns 22 and 24.

[0049] A first wiring pattern 22 is formed through contact hole 25, and a second wiring pattern 24 spaced apart from the first wiring pattern 22 is formed through wiring pattern hole 27.

[0050] Reference Figure 2D After forming the first wiring pattern 22 and the second wiring pattern 24, the resist pattern layer 200 is removed. The base copper layer (not shown) is also removed by etching or physical polishing according to a pre-designed circuit pattern.

[0051] Reference Figure 2E The process of forming the second insulating layer 20 on the first insulating layer 10 begins. The first insulating layer 10 and the second insulating layer 20 are different layers and can be distinguished from each other.

[0052] A first wiring pattern 22 and a second wiring pattern 24 spaced apart from the first wiring pattern 22 are embedded in a second insulating layer 20. The second insulating layer 20 may include a glass-containing insulating material or a glass-free inorganic insulating layer (which may include a resin). Prepreg (PPG) may be used as a glass-containing insulating material, and Ajinomoto Epoxy Flavoring (ABF) may be used as a glass-free inorganic insulating resin. The insulating material is not specifically limited.

[0053] Reference Figure 2F A via 60 is formed in the second insulating layer 20, and the via 60 is subjected to the following process: a third wiring pattern 42 formed on another surface of the second insulating layer 20 by plating is connected to the second wiring pattern 24 (inner layer pattern).

[0054] By stacking resist pattern layers ( Figure 2F Not shown in the image, but can be referenced. Figure 2C The third wiring pattern 42 is formed by plating a base copper layer 300 (as a seed layer) formed on the outer surface of the second insulating layer 20. After the third wiring pattern 42 is formed, the resist pattern layer is removed by etching or the like. Then, the base copper layer 300 is also removed according to the designed circuit pattern.

[0055] As described above, a desired number of layers for a printed circuit board can be stacked by repeatedly stacking insulating layers, forming vias, and connecting inner and outer layer patterns. In this example embodiment, the third wiring pattern 42 is the outermost wiring pattern.

[0056] Reference Figure 2G and Figure 2H The insulating core 100 is removed to separate the unit plate structures formed on the first and second surfaces of the insulating core 100. By separating the unit plate structures, the first external connection pad 50 and the second external connection pad 55, which are embedded in the first insulating layer 10 with ultra-fine pitch, are exposed to the outside.

[0057] Reference Figure 2I The solder resist layer 45 is stacked to selectively expose the external connection pads, including the first external connection pad 50 and the second external connection pad 55. Additionally, a third insulating layer 40 is also stacked on the second insulating layer 20 to protect the third wiring pattern 42.

[0058] A third insulating layer 40 and a solder resist layer 45 can be stacked using photosensitive solder resist (PSR) ink via screen printing to protect the external connection pads 50. The area and size of the solder resist coating are determined based on the pattern shape and size of the designed external connection pads 50. The solder resist layer 45 may have openings 452 that expose the first external connection pads 50. When the openings 452 are formed by laser, a non-photosensitive thermosetting resin is used as the forming material for the solder resist layer 45.

[0059] Refer again Figure 1 as well as Figures 2A to 2I The printed circuit board 1 according to an example embodiment of the present disclosure includes a first insulating layer 10 and a second insulating layer 20.

[0060] The first external connection pad 50 and the second external connection pad 55, which are spaced apart from each other or arranged with an ultra-fine pitch, are embedded in the first insulating layer 10.

[0061] The second insulating layer 20 includes a first wiring pattern 22 connected to each of the first external connection pad 50 and the second external connection pad 55.

[0062] Furthermore, in the printed circuit board 1 of this example embodiment, the first surface 10a of the first external connection pad 50 and the first surface 10a of the second external connection pad 55 are exposed to the first surface 10a of the first insulating layer 10 and are substantially coplanar with the first surface 10a of the first insulating layer 10. The first insulating layer 10 and the second insulating layer 20 form different layers that are distinct from each other.

[0063] The thickness of the first external connection pad 50 and the thickness of the second external connection pad 55 are substantially the same as the thickness of the first insulating layer 10. A first metal layer 52 comprising gold (Au) and a second metal layer 54 comprising nickel (Ni) are stacked from the outside to the inside in the stacking direction of the first and second insulating layers. The second metal layer 54 is thicker than the first metal layer 52. The meaning of the expression "substantially the same" has been defined in other embodiments, therefore repeated descriptions will be omitted.

[0064] The second insulating layer 20 includes a second wiring pattern 24 spaced apart from the first wiring pattern 22 on the same layer, and the second wiring pattern 24 is connected to a third wiring pattern 42 formed on the second insulating layer 20 through a via 60, wherein the third wiring pattern 42 may be the outermost wiring pattern.

[0065] The printed circuit board 1 in this example embodiment also includes a solder resist layer 45, which is disposed on the first insulating layer 10 and protects the first external connection pad 50 and the second external connection pad 55.

[0066] In addition, the solder resist layer 45 is formed with an opening 452 that exposes the first external connection pad 50 and the second external connection pad 55, such that the solder resist layer 45 is located between the first external connection pad 50 and the second external connection pad 55.

[0067] In addition, the first insulating layer 10 may include a thermosetting insulating resin or a photosensitive insulating resin, and the second insulating layer 20 may include a glass-containing insulating material or a glass-free inorganic insulating resin.

[0068] Electronic component packages

[0069] Figure 3 and Figure 4 This is a schematic diagram illustrating an electronic component package formed by combining a semiconductor chip and a printed circuit board according to an example embodiment.

[0070] Reference Figure 3 and Figure 4 The electronic component package 1000 according to an example embodiment of the present disclosure includes the above-described printed circuit board, semiconductor chip 1100 and encapsulation layer 1200.

[0071] The printed circuit board may include: a first insulating layer 10, in which external connection pads 50 are embedded, and the first insulating layer 10 has a thickness substantially the same as that of the external connection pads 50; and a second insulating layer 20, in contact with the first insulating layer 10 and including a first wiring pattern 22 connected to the external connection pads 50. The fact that the thicknesses are substantially the same means that the thicknesses are identical within the permissible range of process errors, positional offsets, and measurement errors that occur during the manufacturing process.

[0072] Semiconductor chip 1100 can be connected to external connection pads 50 on a printed circuit board to exchange electrical signals with the printed circuit board. External connection pads 50 can be connected to semiconductor chip 1100 via at least one of wire bonding (such as using lead 1500) and flip chip bonding. In the case of flip chip bonding, connection terminals 1400 of semiconductor chip 1100 are connected to external connection pads 50 on the printed circuit board via solder bumps 1420.

[0073] Figure 4The encapsulation layer 1200 shown encapsulates the semiconductor chip 1100 to protect the electronic component from the external environment. Additionally, a connection structure 1600, such as solder balls, may be disposed on the third wiring pattern 42 (the outermost wiring pattern). In this example, the electronic component package 1000 according to an exemplary embodiment of the present disclosure may further include: a third insulating layer 40 disposed on the second insulating layer 20, covering the third wiring pattern 42, and having an opening for exposing a portion of the third wiring pattern 42; and a connection structure 1600 disposed in the opening of the third insulating layer 40 and connected to the third wiring pattern 42.

[0074] As described above, according to the printed circuit board of this disclosure, the external connection pads formed with ultra-fine pitch and embedded in a single insulating layer can be disposed at substantially the same height as the insulating layer and formed flat together with the insulating layer.

[0075] According to the printed circuit board disclosed herein, only the external connection pads are embedded in a single insulating layer without other wiring patterns, which enables ultra-fine pitch between adjacent external connection pads and increases the number of wire bonding pads per unit area.

[0076] According to the electronic component package including the printed circuit board of this disclosure, the distance between the external connection pads forms an ultra-fine pitch, and the external connection pads and the insulating layer are disposed at substantially the same height and are formed flat together with the insulating layer, thereby improving the design freedom and integration of semiconductor chip nodes and ensuring the reliability of wire bonding.

[0077] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A printed circuit board, comprising: First insulating layer; An external connection pad is embedded in a first surface of the first insulating layer and has a first external exposed surface, which is disposed at a height substantially the same as the height of the first surface of the first insulating layer. A second insulating layer is disposed on a second surface of the first insulating layer and has a first surface that contacts the second surface of the first insulating layer; as well as A first wiring pattern is embedded in the second insulating layer and exposed from the first surface of the second insulating layer to contact the second external exposed surface of the external connection pad opposite to the first external exposed surface. The external connection pad includes a first metal layer and a second metal layer stacked in the thickness direction of the first insulating layer. The second metal layer is in contact with one surface of the first wiring pattern, and the second metal layer is formed using a material different from the material of the first wiring pattern. The second insulating layer at least partially covers the other surface of the first wiring pattern opposite to one surface of the first wiring pattern.

2. The printed circuit board according to claim 1, further comprising a second wiring pattern, the second wiring pattern being embedded in the second insulating layer and spaced apart from the first wiring pattern. in, The second wiring pattern is connected to the third wiring pattern disposed on the second insulating layer via a via.

3. The printed circuit board according to claim 2, wherein, The third wiring pattern is the outermost wiring pattern.

4. The printed circuit board according to claim 1, wherein, The external connection pads are exposed to the outside, the first metal layer includes a gold layer, the second metal layer includes a nickel layer, and The second metal layer is thicker than the first metal layer.

5. The printed circuit board according to any one of claims 1-4, the printed circuit board further comprising a solder resist layer disposed on the first insulating layer to protect the external connection pads.

6. The printed circuit board according to claim 5, wherein, The solder resist layer includes openings that expose the external connection pads.

7. The printed circuit board according to any one of claims 1-4, wherein, The first insulating layer comprises a thermosetting insulating resin or a photosensitive insulating resin.

8. The printed circuit board according to any one of claims 1-4, wherein, The second insulating layer includes a glass-containing insulating material or an inorganic insulating layer that does not contain glass.

9. A printed circuit board, comprising: First insulating layer; The first external connection pad and the second external connection pad are embedded in the first insulating layer, and the second external connection pad is spaced apart from the first external connection pad; as well as The second insulating layer includes a first wiring pattern connected to each of the first external connection pad and the second external connection pad. Wherein, the first surface of the first external connection pad and the first surface of the second external connection pad are exposed on the first surface of the first insulating layer and are substantially coplanar with the first surface of the first insulating layer, and The first insulating layer and the second insulating layer are different layers from each other. Each of the first and second external connection pads includes a first metal layer and a second metal layer stacked in the thickness direction of the first insulating layer, the second metal layer contacting a surface of the first wiring pattern, and the second metal layer being formed using a material different from the material of the first wiring pattern. The second insulating layer at least partially covers the other surface of the first wiring pattern opposite to one surface of the first wiring pattern.

10. The printed circuit board according to claim 9, wherein, The thickness of the first external connection pad and the second external connection pad is substantially the same as the thickness of the first insulating layer. The first metal layer comprises a gold layer, the second metal layer comprises a nickel layer, and The second metal layer is thicker than the first metal layer.

11. The printed circuit board according to claim 9, wherein, The second insulating layer includes a second wiring pattern spaced apart from the first wiring pattern in the same layer, and The second wiring pattern is connected to the third wiring pattern via a via.

12. The printed circuit board according to claim 11, wherein, The third wiring pattern is the outermost wiring pattern.

13. The printed circuit board according to claim 12, further comprising a solder resist layer disposed on the first insulating layer to protect the first external connection pad and the second external connection pad.

14. The printed circuit board according to claim 13, wherein, The solder resist layer is disposed on the portion of the first insulating layer located between the first external connection pad and the second external connection pad.

15. The printed circuit board according to any one of claims 9-14, wherein, The first insulating layer comprises a thermosetting insulating resin or a photosensitive insulating resin.

16. The printed circuit board according to any one of claims 9-14, wherein, The second insulating layer includes a glass-containing insulating material or an inorganic insulating layer that does not contain glass.

17. An electronic component package, comprising: A printed circuit board includes a first insulating layer and a second insulating layer, an external connection pad is embedded in the first insulating layer, the first insulating layer has a thickness substantially the same as the thickness of the external connection pad, and the second insulating layer has a first surface in contact with the first insulating layer and includes a first wiring pattern connected to the external connection pad. as well as The semiconductor chip is connected to the external connection pad, and The external connection pad includes a first metal layer and a second metal layer stacked in the thickness direction of the first insulating layer. The second metal layer is in contact with one surface of the first wiring pattern, and the second metal layer is formed using a material different from the material of the first wiring pattern. The second insulating layer at least partially covers the other surface of the first wiring pattern opposite to one surface of the first wiring pattern.

18. The electronic component package according to claim 17, wherein, The external connection pads are connected to the semiconductor chip via at least one of a combination of leads, connection terminals, and solder bumps.

19. The electronic component package of claim 17, further comprising a second wiring pattern embedded in the second insulating layer and spaced apart from the first wiring pattern. in, The second wiring pattern is connected to the third wiring pattern disposed on the second insulating layer via a via.

20. The electronic component package of claim 19, further comprising: A third insulating layer is disposed on the second insulating layer, covers the third wiring pattern, and has an opening for exposing a portion of the third wiring pattern; as well as A connection structure is disposed in the opening of the third insulating layer and connected to the third wiring pattern.

21. The electronic component package according to claim 17, wherein, The surface of the first wiring pattern opposite to the portion of the first wiring pattern connected to the external connection pad is spaced apart from the second surface of the second insulating layer, and the second surface of the second insulating layer is opposite to the first surface of the second insulating layer.

22. The electronic component package according to any one of claims 17-21, wherein the electronic component package further comprises an encapsulation layer encapsulating the semiconductor chip.

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