Systems and methods for defragmentation of memory devices

Abstract

In some aspects, the memory controller includes: a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file; and a controller processor configured to control the memory device, receive mapping update commands, and update the L2P address mapping table according to the mapping update commands by: replacing the original logical address of the file's LBA segment with a new contiguous logical address of the merged logical block address (LBA) segment; and changing the original mapping between the original logical address of the file's LBA segment and the file's physical address to a new mapping between the new contiguous logical address of the file's merged LBA segment and the file's physical address.

Description

Technical Field

[0001] This disclosure relates to systems and methods for defragmentation of memory devices. Background Technology

[0002] Data stored in systems and storage devices becomes fragmented over time. This slows down system and storage device performance by reducing access and processing speed. Sometimes, it can further lead to unwanted corruption and data loss. Defragmentation is the process of reducing fragmentation by reorganizing data on storage devices to achieve faster access and better system performance. Summary of the Invention

[0003] In one aspect, a memory controller includes: a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file; and a controller processor configured to control the memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by: replacing the original logical address of the file's LBA segment with a new contiguous logical address of the merged logical block address (LBA) segment; and changing the original mapping between the original logical address of the file's LBA segment and the file's physical address to a new mapping between the new contiguous logical address of the file's merged LBA segment and the file's physical address.

[0004] In some implementations, the controller memory includes a volatile controller memory for storing an L2P address mapping table corresponding to the file.

[0005] In some implementations, the controller memory also includes non-volatile controller memory. The controller processor is configured to store the updated L2P address map in the non-volatile controller memory as a non-volatile L2P address map.

[0006] In some implementations, the controller processor is configured to send a command to the host confirming that the L2P address mapping table has been updated.

[0007] In some implementations, the controller processor is configured to generate a merge log by recording a new mapping between the new consecutive logical addresses in the merged LBA segment of the file and the physical addresses of the file.

[0008] In some implementations, in response to a sudden power outage, the controller processor is configured to rebuild the volatile L2P address mapping table based on the merge log after the memory system is restarted. The merge log records the new mapping between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file.

[0009] In some implementations, the controller processor is configured to scan the physical-to-logical (P2L) address mapping table of the metadata block and the merge log, and in response to the merge log being updated, the controller processor is configured to rebuild the L2P address mapping table based on the merge log.

[0010] In another aspect, a memory system includes: a memory device comprising physical data blocks; and a memory controller comprising: a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to a file; and a controller processor configured to control the memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by: replacing the original logical address of a file's LBA segment with a new contiguous logical address of the merged logical block address (LBA) segment; and changing the original mapping between the original logical address of the file's LBA segment and the file's physical address to a new mapping between the new contiguous logical address of the file's merged LBA segment and the file's physical address.

[0011] In some implementations, the controller memory includes a volatile controller memory for storing an L2P address mapping table corresponding to the file.

[0012] In some implementations, the controller memory also includes non-volatile controller memory. The controller processor is configured to store the updated L2P address map in the non-volatile controller memory as a non-volatile L2P address map.

[0013] In some implementations, the controller processor is configured to send a command to the host confirming that the L2P address mapping table has been updated.

[0014] In some implementations, the controller processor is configured to generate a merge log by recording a new mapping between the new consecutive logical addresses in the merged LBA segment of the file and the physical addresses of the file.

[0015] In some implementations, in response to a sudden power outage, the controller processor is configured to rebuild the volatile L2P address mapping table based on the merge log after the memory system is restarted. The merge log records the new mapping between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file.

[0016] In some implementations, the controller processor is configured to scan the physical-to-logical (P2L) address mapping table of the metadata block and the merge log, and in response to the merge log being updated, the controller processor is configured to rebuild the L2P address mapping table based on the merge log.

[0017] In another aspect, a system includes: a host, the host including: a host memory configured to store files; and a host processor configured to execute a merge LBA command to rearrange the original logical addresses of logical block address (LBA) segments of the file to new contiguous logical addresses of the merged LBA segments of the file and send a mapping update command; and a memory system including: a memory device including physical data blocks; and a memory controller including: a controller memory for storing a logical-to-physical (L2P) address mapping table corresponding to the file; and a controller processor configured to control the memory device, receive the mapping update command, and update the L2P address mapping table according to the mapping update command by: replacing the original logical addresses of the LBA segments of the file with the new contiguous logical addresses of the merged LBA segments of the file; and changing the original mapping relationship between the original logical addresses of the LBA segments of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file.

[0018] In some implementations, the controller memory includes a volatile controller memory for storing an L2P address mapping table corresponding to the file.

[0019] In some implementations, the host processor is configured to rearrange the original logical addresses of the file's LBA segments into the new logical addresses of the file's merged LBA segments by rewriting all logical addresses of the file's LBA segments to free or unused LBA segments with consecutive and sequential logical addresses, such that the free or unused LBA segments become the new consecutive logical addresses of the file's merged LBA segments.

[0020] In some implementations, the host processor is configured to send a mapping update command, causing the memory controller to update the L2P address mapping table based on the new contiguous logical addresses of the merged LBA segments of the file.

[0021] In some implementations, the host processor is configured to receive an instruction from the memory controller confirming that the L2P address mapping table has been updated.

[0022] In some implementations, the host processor is configured to update the file's inode after confirming that the L2P address mapping table has been updated.

[0023] In some implementations, the host processor is configured to update the file's inode by pointing to a new LBA segment with a new contiguous logical address that merges the LBA segments.

[0024] In another aspect, a method for operating a memory controller includes: receiving a mapping update command from a host; and updating a logical-to-physical (L2P) address mapping table according to the mapping update command by replacing the original logical addresses of the LBA segments of the file with new contiguous logical addresses of the merged LBA segments of the file; and changing the original mapping relationship between the original logical addresses of the LBA segments of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file.

[0025] In some implementations, the method also includes sending a command to the host confirming that the L2P address mapping table has been updated.

[0026] In some implementations, the method further includes: recording in the merge log a new mapping between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file; and reconstructing the L2P address mapping table based on the merge log after the memory system is restarted in response to a sudden power outage.

[0027] In some implementations, rebuilding the L2P address mapping table includes: scanning the physical-to-logical (P2L) address mapping table of the metadata blocks and the merge log; and rebuilding the L2P address mapping table based on the merge log in response to determining that the merge log has been updated. Attached Figure Description

[0028] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the specification, further serve to explain this disclosure and enable those skilled in the art to make and use it.

[0029] Figure 1 A block diagram of an exemplary system having a host and a memory system according to some aspects of this disclosure is shown.

[0030] Figure 2A A diagram of an exemplary memory card having a memory device according to some aspects of this disclosure is shown.

[0031] Figure 2B A diagram of an exemplary solid-state drive (SSD) having a memory device is shown according to some aspects of this disclosure.

[0032] Figure 3 A schematic diagram of an exemplary memory device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0033] Figure 4A A block diagram of an exemplary memory system including a memory controller and a memory device is shown, according to some aspects of this disclosure.

[0034] Figure 4B A block diagram of an exemplary memory system including a memory controller and a memory device is shown, according to some aspects of this disclosure.

[0035] Figure 5 A block diagram of an exemplary system including a host and a memory controller is shown according to some aspects of this disclosure.

[0036] Figure 6 A block diagram illustrating an exemplary defragmentation scheme according to some aspects of this disclosure is shown.

[0037] Figure 7 A block diagram illustrating an exemplary defragmentation scheme according to some aspects of this disclosure is shown.

[0038] Figure 8 A block diagram illustrating an exemplary defragmentation scheme in the event of a sudden power outage, according to some aspects of this disclosure, is shown.

[0039] Figure 9 A flowchart illustrating an exemplary method for operating a memory controller according to some aspects of this disclosure is shown.

[0040] Figure 10 A flowchart illustrating an exemplary method for operating a host according to some aspects of this disclosure is shown.

[0041] Aspects of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0042] While specific configurations and arrangements have been described, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be adopted in a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified in ways not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0043] Generally, terms can be understood at least in part based on their usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "the" can also be understood to express either a singular or a plural usage. Additionally, also depending at least in part on the context, the term "based on" can be understood not necessarily to express an exclusive set of elements, but rather to allow for the presence of additional elements that are not necessarily explicitly described.

[0044] Disk defragmentation is a technique that allows users to defragment not only hard disk drives (HDDs) but also other removable storage devices. For example, Windows systems (such as Windows 7) include a disk defragmentation utility called Microsoft Drive Optimizer or Disk Defragmenter, which allows users to defragment their hard drives by rearranging files stored on the disk to occupy contiguous storage locations, thereby improving data access speeds and overall computer performance. However, disk defragmentation is not considered efficient for solid-state drives (SSDs). In fact, defragmenting SSDs is generally not recommended, as it can exhaust the SSD's write cycles and potentially lead to premature SSD failure. However, with the development of SSDs and the increase in storage capacity within them, the software (SW) input / output stack (I / O stack) has become a bottleneck for the system. That is, logically fragmented files degrade system performance.

[0045] One solution to logical-level fragmentation is to use a defragmenter, such as e2defrag. e2defrag reads each segment of a file's logical address and selects contiguous logical address blocks for writing. However, e2defrag may not only update the logical address blocks but also the physical blocks each time a logical address block is updated, thus increasing the impact of write amplification. This is an undesirable phenomenon associated with flash memory and solid-state drives, where the actual amount of information physically written to the storage medium is many times the logical amount intended to be written. This write amplification can burn out an SSD faster than expected and shorten its lifespan. Furthermore, regular e2defrag is very time-consuming due to its lengthy segment reading process and the routine update of physical address blocks each time a logical address block is updated. Therefore, solving logical-level fragmentation is not efficient enough.

[0046] Furthermore, conventional defragmentation tools may not be well-designed for power loss protection to ensure that data is not lost while the SSD is being written in the event of a sudden power failure. A sudden power outage during defragmentation can lead to serious system damage or data loss. Mechanisms to prevent data loss due to sudden power outages during defragmentation are highly desirable.

[0047] To address one or more of the aforementioned problems, this disclosure introduces a solution in which the Merge Logical Block Address (LBA) command is designed to merge segments of LBAs in a file into a merged LBA segment of the file, and update the logical-to-physical (L2P) address mapping table based on the merged LBA segment of the file. Furthermore, before updating the L2P address mapping table, a merge log is created to record the mapping relationship between the L2P address mapping table and the physical-to-logical (P2L) address mapping table. Therefore, after a sudden power outage, L2P can be rebuilt or recovered using the merge log and the P2L address mapping table.

[0048] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include host 108 having host memory 110 and host processor 112, and memory system 102 having one or more memory devices 104 and memory controller 106.

[0049] Host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 108 may be coupled to memory controller 106 and configured to send data to or receive data from memory device 104 via memory controller 106. For example, host 108 may send program data in a programming operation or receive read data in a read operation. Host processor 112 may be a control unit (CU) or an arithmetic logic unit (ALU). Host memory 110 may be a memory cell including registers or cache memory. Host 108 is configured to receive instructions and commands from and send instructions and commands to memory controller 106 of memory device 102, and to perform or implement a number of functions and operations provided in this disclosure, which will be described below.

[0050] Memory device 104 can be any memory device disclosed in this disclosure, such as a NAND flash memory device including a page buffer having multiple sections (e.g., four sections). Note that, for illustrative purposes, NAND flash memory is merely one example of a memory device. Memory device 104 can include any suitable solid-state non-volatile memory, such as NOR flash memory, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), spin-torque magnetic random access memory (STT-RAM), or resistive random access memory (RRAM), etc. In some implementations, memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0051] The memory controller 106 may be implemented by the following: a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0052] According to some implementations, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some implementations, memory controller 106 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, memory controller 106 is designed to operate SSDs in high duty cycle environments or as an embedded multimedia card (eMMC) for data storage devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory device 104 by providing instructions such as read instructions to memory device 104, such as read, erase, and program operations. For example, memory controller 106 can be configured to provide read instructions to peripheral circuitry of memory device 104 to control read operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to handle error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable function, such as formatting the memory device 104.

[0053] The memory controller 106 can communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0054] The storage controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connector for linking the memory card to a host computer (e.g., ...). Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0055] The memory control 106 is configured to receive commands from and send commands to the host 108, and to perform or implement a number of functions and operations provided in this disclosure, which will be described below.

[0056] Figure 3 A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Note that, for illustrative purposes, the NAND flash memory disclosed herein is merely one example of a memory device. Memory device 300 may include any suitable solid-state, non-volatile memory, such as NOR flash, FeRAM, PCM, MRAM, STT-RAM, or RRAM. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value (e.g., voltage or charge) depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0057] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one unit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to represent a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of the three possible nominal storage values ​​to the cell to represent one of the three possible programming levels from the erase state. A fourth nominal storage value can be used for the erase state.

[0058] like Figure 3 As shown, each NAND memory string 308 may include a source-select-gate (SSG) transistor 310 at its source end and a drain-select-gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some implementations, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some implementations, the drain of the DSG transistor 312 of each NAND memory string 308 is coupled to a corresponding bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the DSG transistor 312) or a deselection voltage (e.g., 0V) to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313, and / or by applying a selection voltage (e.g., higher than the threshold voltage of the SSG transistor 310) or a deselection voltage (e.g., 0V) to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0059] like Figure 3As shown, the NAND memory string 308 can be organized into multiple blocks 304, each block of which can have a common source line 314, for example, coupled to the ACS. In some implementations, each block 304 is the basic data unit used for erase operations (i.e., all memory cells 306 on the same block 304 are erased simultaneously). To erase memory cells 306 in a selected block 304, the source line 314 can be biased using an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)), which is coupled to the selected block 304 and unselected blocks 304 in the same plane as the selected block 304. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, which is the basic data unit used for programming and read operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled through word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupling the control gates at each memory cell 306 in the corresponding page 320. Peripheral circuitry 302 can be coupled to memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry used to facilitate the operation of memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0060] Figure 4A A block diagram of an exemplary memory system 102, including a memory controller 106 and a memory device 104, is shown according to some aspects of this disclosure. Figure 4AAs shown, the memory controller 106 may include a controller processor 408, such as a memory chip controller (MCC) or a memory controller unit (MCU). The controller processor 408 is configured to control the module to execute commands or instructions to perform the functions disclosed in this disclosure. The controller processor 408 may also be configured to control the operation of each peripheral circuit by generating and sending various control signals (e.g., read commands for read operations). The controller processor 408 may also send clock signals to other peripheral circuits 302 at a desired frequency, period, and duty cycle to coordinate the operation of each peripheral circuit 302, for example, for synchronization. The memory controller 106 may also include a volatile controller memory 411 and a non-volatile controller memory. The volatile controller memory 411 may include registers or cache memory, such that the volatile controller memory 411 allows for faster access and processing speeds to read, write, or erase data stored therein, while the volatile controller memory 411 may not retain the stored information after power is removed. In some implementations, the volatile controller memory 411 includes dynamic random access memory (DRAM) and static random access memory (SRAM). The non-volatile controller memory 413 can retain stored information even after power is removed. In some implementations, the non-volatile controller memory 413 includes NAND, NOR, FeRAM, PCM, MRAM, STT-RAM, or RRAM. The memory device 104 may include a memory cell array, for example, Figure 3 The memory cell array 301 is located within the memory controller 106. In some implementations, the non-volatile controller memory 413 may not be located within the memory controller 106; for example, the non-volatile controller memory 413 may be located externally to the memory controller 106 but coupled to it. In some implementations, the controller memory (e.g., 411 or 413) is configured to store an L2P address mapping table (e.g., 4271, 4273) corresponding to a file (e.g., 129).

[0061] Figure 4B A block diagram of an exemplary memory system 102, including a memory controller 106 and a memory device 104, is shown according to some aspects of this disclosure. Figure 4B As shown, memory controller 106 may include memory controller interface 429, which is configured to be used by a host (e.g., Figure 1 The host 108 receives commands or instructions and sends commands or instructions to the host. In some implementations, the memory controller interface 429 is coupled to the controller processor 408 and receives and sends commands or instructions that cause the controller processor 408 to perform the functions disclosed in this disclosure.

[0062] The memory controller 106 may further include an update module 421 configured to generate and update a volatile L2P address mapping table 4271, a volatile merge log 4251, a non-volatile L2P mapping table 4273, and a non-volatile merge log 4253. The update module 421 may be implemented via firmware in the firmware of the controller processor 408. In some implementations, the update module 421 is configured to update physical data blocks 431 and / or metadata blocks 433 in the memory device 104. In some implementations, the update module 421 is in or coupled to the controller processor 408 and may be controlled by the controller processor 408 to execute commands and instructions from the host 108. For example, the update module 421 is configured to execute a mapping update command received from the host 108 and update the volatile L2P address mapping table 4271 according to the mapping update command. In some implementations, the update module 421 is configured to update the volatile L2P address mapping table 4271 by rewriting the contiguous logical addresses of the merged LBA segments of the file into the volatile L2P address mapping table 4271. In some implementations, the update module 421 is configured to update the volatile L2P address mapping table 4271 by: replacing the original logical addresses of the LBA segments of file 129 with the new contiguous logical addresses of the merged LBA segments of the file; and changing the original mapping relationship between the original logical addresses of the LBA segments of the file and the physical addresses of the file to a new mapping relationship between the new contiguous logical addresses of the merged LBA segments of the file and the physical addresses of the file. The process of forming the contiguous logical addresses of the merged LBA segments of the file will be described later. Furthermore, after updating the L2P address mapping table 4271, the update module 421 in the controller processor 408 will correspondingly send an instruction to the host 108 confirming that the volatile L2P address mapping table 4271 has been updated, enabling the host 108 to update the inode of the file in the host memory 110.

[0063] In some implementations, the volatile L2P address map 4271 is stored and processed in the volatile controller memory 411 and configured to be sent and updated to the non-volatile L2P address map 4273 stored in the physical data block 431, so that the data is not erased after power failure. In some implementations, after the system is restarted, the volatile L2P address map 4271 in the volatile controller memory 411 can be periodically loaded from the non-volatile L2P address map 4273 in the physical data block 431 to achieve faster access and processing speeds. In some implementations, the non-volatile L2P address map 4273 may also be stored in the non-volatile controller memory 413 of the memory controller 106.

[0064] The merge log (e.g., volatile merge log 4251 and non-volatile merge log 4253) is configured to record the mapping between the L2P address mapping table (e.g., 4271 or 4273) and the physical address of the physical data block 431 before updating the L2P address mapping table. In some implementations, the merge log is configured to record a new mapping between the new contiguous logical addresses of the merged LBA segments of file 129 and the physical addresses of file 129 each time the L2P address mapping table is updated. Therefore, after a sudden power outage, the volatile L2P address mapping table 4271 (which may not have been updated) can be rebuilt or restored after the system (e.g., 100) is restarted using the non-volatile merge log 4253 and the physical address of the physical data block 431. Note that in some implementations, the update rate of the non-volatile merge log 4253 is faster than that of the non-volatile L2P address map 4273, allowing the non-volatile merge log 4253 to be recorded during a sudden power outage without causing excessive write amplification, as the non-volatile merge log 4253 is relatively small compared to the non-volatile L2P address map 4273. Specifically, in response to a sudden power outage, the recovery module 423 in the controller processor 408 can scan the physical-to-logical (P2L) address map 435 and the non-volatile merge log 4253 in the metadata block 433 of the memory device 104, and in response to an update to the non-volatile merge log 4253, reconstruct the volatile L2P address map 4271 based on the non-volatile merge log 4253 retained before the sudden power outage and the physical address of the physical data block 431. Furthermore, in response to the non-volatile merge log 4253 not being updated, the volatile L2P address mapping table 4271 is reconstructed based on the physical-to-logical (P2L) address mapping table 435 of the metadata block 433 retained before the sudden power failure and the physical address of the physical data block 431. Note that the metadata block 433 is a relatively small data block in the memory cell array 301. The metadata block 433 is configured to store the logical address information of the data stored in the physical data block 431. The logical address information is written to the metadata block 433 at the same time as the data is written to the physical data block 431, so that the data can be recovered after a sudden power failure. In some implementations, the volatile merge log 4251 is stored and processed in the volatile controller memory 411 and is configured to be sent and updated to the non-volatile merge log 4253 stored in the physical data block 431, so that the data will not be erased after a power failure. In some implementations, after the system is restarted, the volatile merge 4251 in the volatile controller memory 411 can be periodically loaded from the non-volatile merge log 4253 in the physical data block 431 to achieve faster access and processing speeds.In some implementations, the non-volatile merged log 4253 can also be stored in the non-volatile controller memory 413 of the memory controller 106. The recovery module 423 can be implemented through firmware in the firmware of the controller processor 408.

[0065] Figure 5 A block diagram of an exemplary system 100 including a host 108 and a memory controller 106, according to some aspects of this disclosure, is shown. Figure 5 As shown, host 108 may include host interface 125, host memory 110, and host processor 112. Host interface 125 is configured to receive commands or instructions from a user to perform or implement specific functions or operations. Host memory 110 may store logical addresses, such as logical block addresses (LBAs) of files (e.g., file 129) and inodes 127 of files (e.g., inodes). Host processor 112 may include or be coupled to inode update module 121 (e.g., inode update module) and LBA merging module 123. Inode update module 121 is configured to operate within the controller processor 408 of memory controller 106 (e.g., in...). Figure 4B After sending an instruction to host 108 confirming that the volatile L2P address mapping table 4271 has been updated, the inode 127 of the file is updated. The inode update module 121 can also update the file's inode 127 upon receiving physical data blocks 431 (e.g., in...). Figure 4B The inode 127 of file 129 is updated after an instruction has been updated. Note that an inode (e.g., an inode) can be a data structure in a Unix-style file system that describes a file system object such as a file or directory. The inode can be a file data structure that stores information about any Linux file (besides the Linux file's name and data). The inode stores metadata about the file, including the file size, the device on which the file is stored, the user and group IDs associated with the file, or the permissions required to access the file. In some implementations, the host processor 112 is configured to update the inode 127 of file 129 by pointing to a new LBA segment with contiguous logical addresses that have merged LBA segments.

[0066] The merge LBA module 123, included or coupled to the host processor 112, is configured to execute merge LBA commands to rearrange LBA segments (e.g., segments of logical addresses within logical blocks) of file 129 into merged LBA segments. For example, as Figure 6As shown, file A 129 may include one or more LBA segments (e.g., LBA segment 1, LBA segment 2, LBA segment 3, ..., LBA segment N). Each time the file is modified in the operating system, the number of LBA segments increases, and the file becomes fragmented. When using a conventional e2defrag tool, as mentioned above, it may be necessary to read multiple LBA segments one by one and find contiguous logical address blocks to write to the file's Segment New. The e2defrag tool then updates the physical data blocks based on the file's Segment New. Therefore, each time a logical address block is updated, a physical data block is also updated, resulting in excessive write amplification. The merge LBA module 123 provided in this disclosure can therefore execute merge LBA commands to rearrange the LBA segments of file 129 into merged LBA segments. Specifically, rearranging the LBA segments of file 129 involves rewriting all logical addresses of the LBA segments of file 129 into contiguous and sequential blocks of free or unused logical addresses (e.g., free or unused LBA segments), making these logical address blocks contiguous logical address blocks (e.g., merging LBA segments). Unlike the regular e2defrag tool, merging LBA segments will not be used to update physical data blocks (e.g., ...). Figure 4B Physical data block 431 in the middle. Merging LBA segments is only used for updating. Figure 4B The volatile L2P address mapping table 4271 is used. By doing so, write amplification is minimized because the physical data block is not updated each time the logical address block is updated.

[0067] After executing the merge LBA command, the host processor 112 can send a mapping update command, causing the controller processor in the memory controller 106 (e.g., Figure 4A (408) Update the volatile L2P address mapping table 4271 based on the merged LBA segments. For example... Figure 7As shown, the volatile L2P address mapping table 4271, which originally had discontinuous and discrete logical addresses (e.g., LBA 9, LBA 11, LBA 13, LBA 18) (corresponding to the logical addresses of the LBA segments (e.g., LBA 9, LBA 11, LBA 13, LBA 18) in file 129), is updated to become a contiguous block of logical addresses (e.g., LBA 114, LBA 115, LBA 116, LBA 117). The physical addresses (e.g., PA 333, PA337, PA 339, PA 440) of the updated volatile L2P address mapping table 4271 point to the corresponding physical addresses of physical data blocks 431, which remain unchanged during the above update process. Therefore, after the defragmentation process, physical data block 431 has not been written and remains unchanged.

[0068] Figure 8 A block diagram illustrating an exemplary defragmentation scheme in the event of a sudden power outage is shown, according to some aspects of this disclosure. As mentioned above, when a sudden power outage occurs, the volatile L2P address mapping table 4271 may not be updated or may not be able to complete the current update; therefore, data may be lost because the physical data is also not updated. The metadata blocks of the memory device (e.g., memory device 104) (e.g., Figure 4B Metadata block 433 in the document may contain outdated and incorrect P2L mapping tables (e.g., Figure 4B The P2L address mapping table 435 records the physical addresses of outdated L2P address mapping tables (e.g., LBA 9, LBA 11, LBA 13, LBA 18). Because after each update of the volatile L2P address mapping table 4271, the non-volatile merge log 4253 stores the mapping relationship between the P2L address mapping table 435 and the volatile L2P address mapping table 4271 (e.g., P2L's LBA 9 points to the new L2P's LBA 114, P2L's LBA 11 points to the new L2P's LBA 115, P2L's LBA 13 points to the new L2P's LBA 116, and P2L's LBA 18 points to the new L2P's LBA 117), a new volatile L2P address mapping table 4271 can be reconstructed based on the mapping relationship using the non-volatile merge log 4253 and the retained P2L address mapping table 435.

[0069] Figure 9 A flowchart illustrating an exemplary method for operating a memory controller according to some aspects of this disclosure is shown. The memory controller can be any suitable memory controller disclosed herein, for example, Figure 4BThe memory controller 106 in the middle. Method 900 can be partially or completely determined by, for example, Figure 4A The memory controller 106 is implemented in [the system]. It should be understood that the operations shown in method 900 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations in the operation may be performed simultaneously, or in conjunction with [other operations]. Figure 9 The different orders of execution are shown in the diagram.

[0070] refer to Figure 9 Method 900 begins with operation 902, at which point the memory controller (e.g., ...) ... Figure 4A The memory controller 106 in the memory controller is located in the host (e.g., Figure 5 The host 108 receives the mapping update command. In some implementations, the mapping update command can cause the memory controller 106 to start the update module 421.

[0071] Method 900 proceeds to operation 904, such as... Figure 9 As shown, at operation 904, the L2P address mapping table stored in memory controller 106 is updated according to the mapping update command (e.g., ...). Figure 4B The volatile L2P address mapping table 4271 in the document. In some implementations, updating the L2P address mapping table includes updating the file (e.g., ...). Figure 5-7 The contiguous logical addresses of the merged LBA segments in file 129 are rewritten into the L2P address mapping table.

[0072] Method 900 proceeds to operation 906, such as... Figure 9 As shown, at operation 906, after updating the L2P address mapping table, a command acknowledging that the L2P address mapping table has been updated is sent to the host. In some implementations, once the L2P address mapping table update is complete, the update module is configured to communicate via an interface (e.g., ...). Figure 4B The memory controller interface 429 sends instructions to the host. The host can then update the inode of the file stored in the host memory.

[0073] Furthermore, method 900 may also include operations for implementing sudden power outage protection. Specifically, method 900 may also include merging logs (e.g., Figure 4B The non-volatile merged log (4253) is recorded in the metadata block (e.g., Figure 4B The P2L address mapping table in metadata block 433 (e.g., Figure 4BThe mapping relationship between the P2L address mapping table and the L2P address mapping table. After a sudden power outage and when the system is restarted, method 900 may further include scanning the P2L address mapping table of the metadata block and the merge log. And in response to determining that the merge log has been updated, the L2P address mapping table is reconstructed based on the merge log and the P2L address mapping table of the metadata block. Furthermore, in response to determining that the merge log has not been updated, the L2P address mapping table is restored based on the P2L address mapping table of the metadata block. These operations can be performed by, for example... Figure 4B The recovery module 423 is implemented in the middle.

[0074] Figure 10 A flowchart illustrating an exemplary method for operating a host according to some aspects of this disclosure is shown. The host can be any suitable host disclosed herein. Method 1000 can be partially or entirely... Figure 5 The host 108 is implemented in this way. It should be understood that the operations shown in method 1000 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations in the operation may be performed simultaneously, or in conjunction with... Figure 10 The different orders of execution are shown in the diagram.

[0075] refer to Figure 10 Method 1000 begins with operation 1002, where a merge LBA command is executed to merge the LBA stored in host memory (e.g., ...). Figure 5 Files in host memory 110 (e.g., Figure 5 The LBA segment in document 129) is rearranged into a merged LBA segment. In some implementations, the merged LBA command can cause the host processor (e.g., Figure 5 The host processor 112 in the middle starts the merged LBA module (e.g., Figure 5 (The merged LBA module 123 in the document). In some implementations, rearranging the LBA segments of a file into merged LBA segments involves rewriting the LBA segments of the file, which have logical addresses in a non-contiguous or discrete order, into merged LBA segments with logical addresses in a contiguous and sequential order. In some implementations, rearranging the LBA segments of a file into merged LBA segments involves sequentially reading the logical addresses of the LBA segments of the file before rewriting the logical addresses of the merged LBA segments, such that it becomes a merged LBA segment containing each LBA segment of the file.

[0076] Method 1000 proceeds to operation 1004, such as... Figure 10 As shown in the diagram, at operation 1004, a mapping update command is sent to the memory controller (e.g., ...). Figure 4A The memory controller 106 in the memory controller enables the controller processor of the memory controller (e.g., Figure 4AThe controller processor 408 updates the L2P address mapping table based on the merged LBA segments (e.g., Figure 4B (The volatile L2P address mapping table in 4271). In some implementations, updating the L2P address mapping table involves rewriting the contiguous logical addresses of the merged LBA segments of the file into the L2P address mapping table.

[0077] Method 1000 proceeds to operation 1006, such as... Figure 10 As shown, at operation 1006, an instruction confirming that the L2P address mapping table has been updated is received from the controller processor. In some implementations, after receiving the instruction, an inode update module (e.g., inode update module 121) is initiated.

[0078] Method 1000 proceeds to operation 1008, such as... Figure 10 As shown in the diagram, at operation 1008, after confirming that the L2P address mapping table has been updated, the file's inode is updated.

[0079] The foregoing description of the specific implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation.

[0080] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory controller, comprising: A controller memory, wherein the controller memory is used to store a logical-to-physical L2P address mapping table corresponding to a file; as well as A controller processor configured to control a memory device, receive a mapping update command, and update the L2P address mapping table according to the mapping update command by performing the following operations: Replace the original logical address of the LBA segment of the file with the new contiguous logical address of the merged logical block address (LBA) segment of the file, and The original mapping relationship between the original logical address of the LBA segment in the file and the physical address of the file is changed to a new mapping relationship between the new contiguous logical address of the merged LBA segment in the file and the physical address of the file in the original mapping relationship, wherein... The controller processor is also configured to: A merge log is generated by recording the new mapping relationship between the new consecutive logical addresses of the merged LBA segments in the file and the physical addresses of the file; and In response to a sudden power outage, after the memory system is restarted, the physical-to-logical (P2L) address mapping table of the metadata blocks and the merge log are scanned, and in response to the merge log being updated, the L2P address mapping table is reconstructed based on the merge log.

2. The memory controller according to claim 1, wherein, The controller memory includes a volatile controller memory, which is used to store the L2P address mapping table corresponding to the file.

3. The memory controller according to claim 2, wherein, The controller memory also includes: A non-volatile controller memory, wherein the controller processor is configured to store an updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

4. The memory controller according to any one of claims 1-3, wherein, The controller processor is configured to send a command to the host confirming that the L2P address mapping table has been updated.

5. A memory system, comprising: A memory device, the memory device comprising physical data blocks; as well as The memory controller includes: Controller memory, the controller memory being used to store logical-to-physical L2P address mapping tables corresponding to files; and A controller processor configured to control the memory device, receive mapping update commands, and update the L2P address mapping table according to the mapping update commands by performing the following operations: Replace the original logical address of the LBA segment of the file with the new contiguous logical address of the merged logical block address (LBA) segment of the file, and The original mapping relationship between the original logical address of the LBA segment in the file and the physical address of the file is changed to a new mapping relationship between the new contiguous logical address of the merged LBA segment in the file and the physical address of the file in the original mapping relationship, wherein... The controller processor is also configured to: A merge log is generated by recording the new mapping relationship between the new consecutive logical addresses of the merged LBA segments in the file and the physical addresses of the file; and In response to a sudden power outage, after the memory system is restarted, the physical-to-logical (P2L) address mapping table of the metadata blocks and the merge log are scanned, and in response to the merge log being updated, the L2P address mapping table is reconstructed based on the merge log.

6. The memory system according to claim 5, wherein, The controller memory includes a volatile controller memory, which is used to store the L2P address mapping table corresponding to the file.

7. The memory system according to claim 5, wherein, The controller memory also includes: A non-volatile controller memory, wherein the controller processor is configured to store an updated L2P address mapping table in the non-volatile controller memory as a non-volatile L2P address mapping table.

8. The memory system according to any one of claims 5-7, wherein, The controller processor is configured to send a command to the host confirming that the L2P address mapping table has been updated.

9. The memory system according to claim 5, wherein, The memory device includes a three-dimensional (3D) NAND flash memory device.

10. A system for defragmenting a memory device, comprising: The host, the host comprising: Host memory, configured to store files; and A host processor configured to execute a merge logical block address (LBA) command to rearrange the original logical addresses of the LBA segments of the file to new contiguous logical addresses of the merged LBA segments of the file and send a mapping update command; and The memory system includes: A memory device, the memory device including physical data blocks; and The memory controller includes: Controller memory, the controller memory being used to store a logical-to-physical L2P address mapping table corresponding to the file; and A controller processor configured to control the memory device, receive the mapping update command, and update the L2P address mapping table according to the mapping update command by performing the following operations: Replace the original logical address of the LBA segment of the file with the new contiguous logical address of the merged LBA segment of the file, and The original mapping relationship between the original logical address of the LBA segment of the file and the physical address of the file is changed to a new mapping relationship between the new contiguous logical address of the merged LBA segment of the file and the physical address of the file in the original mapping relationship, wherein... The controller processor is also configured to: A merge log is generated by recording the new mapping relationship between the new consecutive logical addresses of the merged LBA segments in the file and the physical addresses of the file; and In response to a sudden power outage, after the memory system is restarted, the physical-to-logical (P2L) address mapping table of the metadata blocks and the merge log are scanned, and in response to the merge log being updated, the L2P address mapping table is reconstructed based on the merge log.

11. The system according to claim 10, wherein, The controller memory includes a volatile controller memory, which is used to store the L2P address mapping table corresponding to the file.

12. The system according to claim 10 or 11, wherein, The host processor is configured to rearrange the original logical addresses of the LBA segments of the file into the new logical addresses of the merged LBA segments of the file by rewriting all logical addresses of the LBA segments of the file into free or unused LBA segments having consecutive and sequential logical addresses, such that the free or unused LBA segments become the new consecutive logical addresses of the merged LBA segments of the file.

13. The system according to claim 10, wherein, The host processor is configured to send the mapping update command, causing the memory controller to update the L2P address mapping table based on the new contiguous logical address of the merged LBA segment of the file.

14. The system according to claim 10, wherein, The host processor is configured to receive an instruction from the memory controller confirming that the L2P address mapping table has been updated.

15. The system according to claim 14, wherein, The host processor is configured to update the inode of the file after confirming that the L2P address mapping table has been updated.

16. The system according to claim 15, wherein, The host processor is configured to update the inode of the file by pointing to a new LBA segment that has the new contiguous logical address of the merged LBA segment.

17. A method for operating a memory controller, comprising: Receive mapping update commands from the host; The mapping update command updates the logical-to-physical L2P address mapping table corresponding to the file using the following operations: Replace the original logical address of the LBA segment of the file with the new contiguous logical address of the merged LBA segment, and The original mapping relationship between the original logical address of the LBA segment of the file and the physical address of the file is changed to a new mapping relationship between the new consecutive logical address of the merged LBA segment of the file and the physical address of the file in the original mapping relationship; The new mapping relationship between the new consecutive logical addresses of the merged LBA segments in the file and the physical addresses of the file is recorded in the merge log; In response to a sudden power outage, after the memory system is restarted, the physical-to-logical (P2L) address mapping table of the metadata blocks and the merge log are scanned; and In response to determining that the merge log has been updated, the L2P address mapping table is reconstructed based on the merge log.

18. The method of claim 17, further comprising: Send an instruction to the host confirming that the L2P address mapping table has been updated.

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