Staircase structures in three-dimensional memory devices and methods for forming the same

Abstract

Embodiments of a 3D memory device having a staircase structure and a method for forming the same are disclosed. In an example, the 3D memory device includes a memory array structure and a staircase structure in an intermediate body of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase region and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase region includes a first pair of staircases facing each other at different depths in a first lateral direction. Each staircase includes a plurality of steps. Each staircase includes partitions at different depths in a second lateral direction perpendicular to the first lateral direction. At least one step in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to three-dimensional (3D) storage devices and methods of manufacturing them. Background Technology

[0002] Planar memory cells can be miniaturized to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the storage density for planar memory cells is approaching its upper limit.

[0003] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture includes memory arrays and peripheral devices for controlling signals going to and from the memory arrays. Summary of the Invention

[0004] This document discloses embodiments of 3D storage devices having a stepped structure and methods for forming them.

[0005] In one example, a 3D storage device includes a storage array structure and a stepped structure, the stepped structure being located within an intermediate portion of the storage array structure and laterally dividing the storage array structure into a first storage array structure and a second storage array structure. The stepped structure includes a first stepped region and a bridging structure connecting the first and second storage array structures. The first stepped region includes a first pair of steps facing each other in a first lateral direction and at different depths. Each step includes multiple steps. Each step in the first pair of steps includes multiple sections at different depths in a second lateral direction perpendicular to the first lateral direction. At least one step in the first pair of steps is electrically connected to at least one of the first and second storage array structures via the bridging structure.

[0006] In another example, a 3D storage device includes a storage array structure and a stepped structure, the stepped structure being located in an intermediate portion of the storage array structure and laterally dividing the storage array structure into a first storage array structure and a second storage array structure. The stepped structure includes a first stepped region and a bridging structure connecting the first and second storage array structures. The first stepped region includes a first step comprising multiple partitions in a second lateral direction. Each partition includes multiple steps in the first lateral direction perpendicular to the second lateral direction. Each step in one partition is located above or below any step in another partition. At least one step in the first step is electrically connected to at least one of the first and second storage array structures via the bridging structure.

[0007] In another example, a method for forming a stepped structure for a 3D storage device is disclosed. In an intermediate of a stacked structure comprising vertically interlaced first and second material layers, a stepped region mask including openings for the first and second stepped regions is patterned. In each of the first and second stepped regions, at least one pair of steps facing each other in a first lateral direction are formed at the same depth, such that a bridging structure is formed between the first and second stepped regions in a second lateral direction perpendicular to the first lateral direction. After forming at least one pair of steps, in each of the first and second stepped regions, multiple partitions in the second lateral direction are formed at different depths, such that each step in the at least one pair of steps includes multiple partitions at different depths. In each of the first and second stepped regions, each step in the at least one pair of steps is cut to different depths. Attached Figure Description

[0008] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the detailed description below, are intended to further explain the principles of the present disclosure and to enable those skilled in the art to make and use the present disclosure.

[0009] Figure 1 A schematic diagram of a 3D storage device with a stepped structure is shown.

[0010] Figure 2 Schematic diagrams of exemplary 3D storage devices with a stepped structure are shown according to some embodiments of this disclosure.

[0011] Figure 3 A plan view of an exemplary 3D storage device with a stepped structure is shown according to some embodiments of this disclosure.

[0012] Figure 4 A top front perspective view of an exemplary stepped structure of a 3D storage device is shown according to some embodiments of this disclosure.

[0013] Figures 5A-5F Various exemplary masks for forming exemplary ladder structures for 3D storage devices are shown according to some embodiments of this disclosure.

[0014] Figures 6A-6E Various embodiments of this disclosure illustrate manufacturing processes for forming exemplary stepped structures of 3D storage devices.

[0015] Figures 7A-7D According to some embodiments of this disclosure, various exemplary schemes are shown for cutting steps to different depths in a stepped structure.

[0016] Figure 8 This is a flowchart of a method for forming an exemplary ladder structure for a 3D storage device according to some embodiments.

[0017] Figure 9 This is a flowchart of another method for forming an exemplary ladder structure for 3D storage devices according to some embodiments.

[0018] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0019] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0020] It should be noted that references to "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0021] Generally, terms can be understood at least in part based on their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage. Additionally, depending at least in part on the context, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to take into account the presence of other factors that are not necessarily explicitly described.

[0022] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on something” but also includes the meaning of “on something” with an intermediate feature or layer between them, and that “above” or “over” means not only “above something” but also includes the meaning of “above something” or “over something” without an intermediate feature or layer between them (i.e., directly on something).

[0023] Furthermore, for ease of description in illustrating the relationship between one element or feature and another (as shown in the figures), spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” etc., are used herein. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0024] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and so on. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0025] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Further, a layer may be a region of a uniform or non-uniform continuous structure, wherein the non-uniform continuous structure has a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed in the contact layers) and one or more dielectric layers.

[0026] As used herein, the term "nominal / nominally" refers to an expected or target value, along with a range of values ​​higher and / or lower than the expected value, set during the design phase of a product or process for a feature or parameter of a component or process operation. The range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "approximately" indicates a given number of values ​​that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "approximately" may indicate a given number of values ​​that vary within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0027] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND memory strings) on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally perpendicular to the lateral surface of the substrate.

[0028] In some 3D storage devices, memory cells for storing data are vertically stacked via stacked memory structures (e.g., memory stacks). 3D storage devices typically include stepped structures formed on one or more sides (edges) of the stacked memory structures for purposes such as word line fan-out. Since the stepped structures are typically formed at the edges of each storage plane, the memory cells are unilaterally driven by line decoders (also called "x-decoders") that are also arranged at the edges of each storage plane via word lines and corresponding stepped structures.

[0029] For example, Figure 1 A schematic diagram of a 3D memory device 100 having a stepped structure 104 is shown. The 3D memory device 100, such as a 3D NAND memory device, includes two memory planes 102, each memory plane 102 having an array of memory cells in a memory array structure 106. It should be noted that in... Figure 1The diagram includes x-axis and y-axis to show two orthogonal (vertical) directions in the wafer plane. The x-direction is the word line direction of the 3D memory device 100, and the y-direction is the bit line direction of the 3D memory device 100. The 3D memory device 100 also includes two step structures 104 on opposite sides of each memory array structure 106 in the x-direction. Each word line of the memory plane 102 extends laterally across the entire memory plane 102 in the x-direction, reaching its respective step (horizontal) in the step structure 104. Row decoders (not shown) are formed directly above, below, or near each step structure 104 to reduce interconnect length. That is, each row decoder drives half of the memory cells unilaterally (in the positive x-direction or negative x-direction, but not both) through half of the word lines, where each word line spans the entire memory plane 102.

[0030] Therefore, the load of a unilateral word line drive scheme includes the resistance across the entire word line across the memory plane 102. Furthermore, with the increasing demand for higher memory capacities, the number of vertical horizontal stacks of the memory structure is increasing, and the thickness of the stack body including each word line film is decreasing. This may introduce even higher resistance into the load, resulting in significant RC delay. Therefore, a unilateral word line drive scheme with a side-step structure 104 may affect the performance of the 3D memory device 100, such as read and write speeds.

[0031] Various embodiments of this disclosure provide a stepped structure in the middle of a memory plane and a method of manufacturing the same, to achieve a bidirectional word line driving scheme for reducing RC latency. By utilizing, for example, a central stepped structure instead of a conventional side stepped structure, each row decoder can drive word lines bidirectionally from the middle of the memory plane in opposite directions, thereby reducing resistance in the load because the length of the word line to be driven by the row decoder is reduced to, for example, half. In some embodiments, a bridging structure is introduced as part of the stepped structure to connect word lines separated by the central stepped structure. In some embodiments, a multi-partition stepped structure (in which each step of the stepped structure includes multiple partitions for fanning out multiple word lines) is used to increase the utilization of the stepped structure and reduce manufacturing complexity. In some embodiments, multiple chop processes are used to form multiple steps at different depths to reduce the number of trimming etch processes, thereby further reducing manufacturing complexity and increasing yield. In some embodiments, partitions are formed after the steps are formed to reduce the number of material layer pairs (e.g., silicon nitride and silicon oxide pairs) in the stacked structure to be etched, thereby reducing the thickness requirements of the hard mask for areas (e.g., bridging structures) used to cover areas outside the steps.

[0032] Figure 2A schematic diagram of an exemplary 3D storage device 200 having a stepped structure 204 is shown according to some embodiments of the present disclosure. In some embodiments, the 3D storage device 200 includes a plurality of storage planes 202. Each storage plane 102 may include storage array structures 206-1 / 206-2 and a stepped structure 204 that laterally divides the storage array structures 206-1 / 206-2 into a first storage array structure 206-1 and a second storage array structure 206-2 in the x-direction (word line direction) of the storage array structures 206-1 / 206-2. According to some embodiments, with Figure 1 The 3D memory device 100 (in which the step structure 104 is on opposite sides of each memory array structure 106) differs in that the step structure 204 in the 3D memory device 200 is located in the middle between the first memory array structure 206-1 and the second memory array structure 206-2. In some embodiments, the step structure 204 is located in the middle of the memory array structures 206-1 / 206-2 for each memory plane 202. That is, the step structure 204 may be a central step structure that equally divides the memory array structures 206-1 / 206-2 into a first memory array structure 206-1 and a second memory array structure 206-2 having the same number of memory cells. For example, the first memory array structure 206-1 and the second memory array structure 206-2 may be symmetrical in the x-direction with respect to the central step structure 204. It should be understood that, in some examples, the step structure 204 may be in the middle, but not in the center, of the memory array structures 206-1 / 206-2, such that the first memory array structure 206-1 and the second memory array structure 206-2 may have different sizes and / or numbers of memory cells. In some embodiments, the 3D memory device 200 is a NAND flash memory device, wherein memory cells are provided in the form of NAND memory strings (not shown) in the first memory array structure 206-1 and the second memory array structure 206-2. The first memory array structure 206-1 and the second memory array structure 206-2 may include any other suitable components, including but not limited to gate line gaps (GLS), through-array contacts (TAC), array common source (ACS), etc.

[0033] Each word line (not shown) extending laterally in the x-direction of the storage plane 202 can be divided into two parts by a step structure 204: a first word line portion spanning the first storage array structure 206-1 and a second word line portion spanning the second word line storage array structure 206-2. As described in detail below, the two parts of each word line can be electrically connected at their respective steps in the step structure 204 via a bridging structure (not shown) in the step structure 204. Row decoders (not shown) can be formed directly above, below, or near the respective step structure 104 to reduce interconnect length. As a result, compared with... Figure 1 Unlike the row decoders of the 3D memory device 100, the row decoders of the 3D memory device 200 can bidirectionally (in both the positive x-direction and the negative x-direction) drive the memory cells in the first memory array structure 206-1 and the second memory array 206-2. That is, by utilizing, for example, a step structure 204 in the intermediate of the memory array structures 206-1 / 206-2 instead of a conventional side step structure (e.g., in...). Figure 1 In step 104), each row decoder can bidirectionally drive word lines in a direction opposite to the intermediate body of storage plane 202, thereby reducing resistance in the load. This is because when the staircase structure 204 is in the middle of storage array structures 206-1 / 206-2, the length of the portion of each word line to be driven by the row decoder is reduced to, for example, half. That is, according to some embodiments, the row decoder of 3D storage device 200 only needs to drive the first or second word line portion of each word line.

[0034] Although Figure 2 In this design, the stepped structures 204, all located within the intermediate layers of their respective memory planes 202, are functional stepped structures for landing interconnects (e.g., word line contacts). However, it should be understood that additional stepped structures (e.g., dummy stepped structures, not shown) may also be formed on one or more sides to balance the load during etching or chemical mechanical polishing (CMP) processes during manufacturing and to separate adjacent memory planes 202. Since the stepped structures 204, all located within the intermediate layers of their respective memory planes 202, can increase the total area of ​​the memory planes 202, steeper dummy stepped structures with smaller areas can be formed to reduce die size.

[0035] Figure 3 A plan view of an exemplary 3D storage device 300 having a stepped structure 301 is shown according to some embodiments of this disclosure. The 3D storage device 300 may be in... Figure 2 An example of a portion of a storage plane 202 including a stepped structure 204, and an example of a stepped structure 301 in a 3D storage device 300 being a stepped structure 204 in a storage plane 202. Figure 3 As shown, the 3D memory device 300 may include a plurality of blocks 302 separated by parallel GLS 308 in the y-direction (bit line direction). In some embodiments where the 3D memory device 300 is a NAND flash memory device, each block 302 is the smallest erasable cell of the NAND flash memory device. Each block 302 may also include a plurality of fingers 304 separated in the y-direction by some of the GLS 308 having “H” notches 310.

[0036] In some embodiments, the stepped structure 301 is located in the middle (e.g., in the middle) of the 3D storage device 300 in the x-direction (word line direction). In some embodiments, Figure 3 A pair of peripheral regions 303 of the memory array structure adjacent to the step structure 301 are also shown. Top Select Gates (TSGs) can be formed using the peripheral regions 303 separated by the step structure 301, which can be driven independently or electrically connected via interconnects on the step structure 301. As described in detail below, the step structure 301 may include multiple step regions, each corresponding to a respective finger 304, and multiple bridging structures 306 located in the y-direction between two adjacent step regions. Each step region may be in one or two blocks 302. The 3D memory device 300 may include multiple dummy channel structures 314 and bridging structures 306 in the step regions to provide mechanical support and / or load balancing. The 3D memory device 300 may also include word line contacts 312 in the step regions of the step structure 301, each landing on a respective word line (not shown) at each step of the step structure 301 for word line driving.

[0037] To achieve a bidirectional word line driving scheme, according to some embodiments, each bridging structure 306 (both physical and electrical grounds) connects the first memory array structure and the second memory array structure (not shown). That is, according to some embodiments, the step structure 301 does not completely sever the memory array structures in the intermediate body, but instead leaves the first and second memory array structures connected through its bridging structure 306. Therefore, each word line can be driven bidirectionally from its respective word line contact 312 (in both the positive and negative x directions) within the step region of the step structure 301 in the intermediate body of the 3D memory device 300 via the bridging structure 306. For example, Figure 3 An exemplary current path for a bidirectional word line driving scheme with bridging structure 306 is further illustrated. The first current path, indicated by a solid arrow, and the second current path, indicated by a hollow arrow, represent the current passing through two separate word lines at different levels.

[0038] Figure 4A top front perspective view of an exemplary stepped structure 400 of a 3D storage device is shown according to some embodiments of this disclosure. The stepped structure 400 may be in Figure 2 The stepped structure 204 of the 3D storage device 200 or in Figure 3 An example of a stepped structure 301 in a 3D memory device 300. The stepped structure 400 may include a stacked structure 401 on a substrate (not shown), which may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0039] It should be noted that, in Figure 4 The x, y, and z axes are included to further illustrate the spatial relationships of the components in the stepped structure 400. The substrate of the 3D memory device includes two sides extending laterally in the xy plane: a top surface on the front side of the wafer (on which the stepped structure 400 may be formed), and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, when the substrate is disposed in the lowest plane of the 3D memory device in the z direction, whether a component (e.g., a layer or device) is “on,” “above,” or “below” another component (e.g., a layer or device) of the 3D memory device is determined relative to the substrate of the 3D memory device in the z direction (a direction perpendicular to the xy plane). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0040] The stacked structure 401 may include a first material layer that is vertically staggered and a second material layer that is different from the first material layer. The first material layer and the second material layer may alternate in the vertical direction. In some embodiments, the stacked structure 401 may include a plurality of material layer pairs that are vertically stacked in the z-direction, wherein each material layer pair includes a first material layer and a second material layer. The number of material layer pairs in the stacked structure 401 (e.g., 32, 64, 96, 128, 160, 192, 224, or 256) can determine the number of storage cells in the 3D storage device.

[0041] In some embodiments, the 3D memory device is a NAND flash memory device, and the stacked structure 401 is a memory structure through which NAND memory strings are stacked. Each first material layer in the first material layer includes a conductive layer, and each second material layer in the second material layer includes a dielectric layer. That is, the stacked structure 401 may include staggered conductive and dielectric layers (not shown). In some embodiments, each conductive layer may serve as a gate line and a word line of the NAND memory string, the word line extending laterally from the gate line and terminating at a step structure 400 for word line fan-out. The conductive layer may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicide, or any combination thereof. The dielectric layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layer includes a metal (such as tungsten), and the dielectric layer includes silicon oxide.

[0042] Each step of the stepped structure 400 (as indicated by "layer") may comprise one or more pairs of material layers. In some embodiments, the top material layer of each step is a conductive layer for interconnection in the vertical direction. In some embodiments, every two adjacent steps of the stepped structure 400 are offset by a nominally equal distance in the z-direction and by a nominally equal distance in the x-direction. Thus, each offset can form a word line contact for interaction with the 3D memory device in the z-direction (e.g., in...). Figure 3 312 in Figure 4 (Not shown in the image) Interconnected "landing zones".

[0043] like Figure 4As shown, the stepped structure 400 may include a first stepped region 402, a second stepped region 412, and a bridging structure 404 between the first stepped region 402 and the second stepped region 412 in the y-direction (word line direction). In some embodiments, the first stepped region 402 includes multiple pairs of steps, including a first pair of steps 406-1 and 406-2, a second pair of steps 410-1 and 410-2, a third pair of steps 414-1 and 414-2, and a fourth pair of steps 416-1 and 416-2 in the x-direction (word line direction). According to some embodiments, each step 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2 includes multiple steps in the x-direction. In some embodiments, each of the steps 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2 is a functional step for landing an interconnect (e.g., word lines via contacts) compared to a dummy step. In other words, according to some embodiments, steps 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, and 416-2 in the first step region 402 are not dummy steps.

[0044] In some embodiments, the pairs of steps 406-1 / 406-2, 410-1 / 410-2, 414-1 / 414-2, or 416-1 / 416-2 face each other in the x-direction and at different depths. In one example, the first pair of steps 406-1 / 406-2 may face each other in the x-direction, for example, step 406-1 is inclined towards the negative x-direction, and step 406-2 is inclined towards the positive x-direction. Similarly, in another example, the second pair of steps 410-1 / 410-2 may face each other in the x-direction, for example, step 410-1 is inclined towards the negative x-direction, and step 410-2 is inclined towards the positive x-direction. It should be understood that since a staircase may include multiple steps, the depth of the steps disclosed herein may refer to the depth of the same step in the z-direction (at the same opposite level), such as the top step, middle step, or bottom step. In one example, the first pair of steps 406-1 / 406-2 may be at different depths; for example, the top step of step 406-1 may be higher than the top step of step 406-2 in the z-direction. Similarly, in another example, the second pair of steps 410-1 / 410-2 may be at different depths; for example, the top step of step 410-2 may be higher than the top step of step 410-1 in the z-direction. In some embodiments, the pairs of steps 406-1 / 406-2, 410-1 / 410-2, 414-1 / 414-2, or 416-1 / 416-2 do not overlap in the z-direction. That is, according to some embodiments, in the same pair, the bottom step of the higher step is not lower than the top step of the lower step.

[0045] It should be understood that, although the number of step pairs in each step region (e.g., the first step region 402) is not limited to... Figure 4The four pairs shown are not identical, but the same step pattern described above (i.e., pairs of steps facing each other in the x-direction and at different depths) can be applied to any number of step pairs. As a result, in some embodiments, each of the steps 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2 in the first step region 402 is at a different depth. That is, according to some embodiments, steps 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, and 416-2 in the first step region 402 do not overlap in the z-direction. Furthermore, since each step in the staircase can be at a different depth, each step in the first step region 402 can be at a different depth. That is, according to some embodiments, all steps in the first step region 402 do not overlap in the z-direction (i.e., are not at the same level). As a result, each step in the stepped area (e.g., the first stepped area 402) can be used to land interconnects (e.g., word line contacts) that are in contact with their respective word lines at different levels.

[0046] like Figure 4 As shown, the stepped structure 400 may be a multi-partition stepped structure comprising multiple partitions in the y-direction within each stepped region (e.g., a first stepped region 402 or a second stepped region 412). In some embodiments, each step 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2 in the first stepped region 402 comprises multiple partitions in the y-direction, and each partition within a partition comprises multiple steps in the x-direction. By introducing multiple partitions in the y-direction, the size (e.g., length) of the stepped structure 400 in the x-direction can be reduced without reducing the total number of steps. In some embodiments, in each step 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2, each step in one partition is located above or below two steps in another partition within the partition. In other words, within each step, the depth of the step first changes along the x-direction (for example, in...). Figure 4 (Increases along the negative x-direction), then changes along the y-direction (e.g., in...) Figure 4 (Increases along the negative y-direction). As a result, for any partition within the step, the depth of all steps can be outside the depth range of their neighboring partitions. The step depth pattern within the partitions described above can be set based on the order in which the trimming etching process and the partitioning process are applied. Specifically, the step depth pattern within the partitions disclosed herein can be achieved by applying the partitioning process after the trimming etching process, as described in detail below regarding the manufacturing process. For example, as Figure 4As shown, the stepped structure 400 can be a three-section stepped structure, wherein each step in a stepped region (e.g., each step 406-1, 406-2, 410-1, 410-2, 414-1, 414-2, 416-1, or 416-2 in the first stepped region 402) can include three sections 408-1, 408-2, and 408-3 in the y-direction. In one example, in step 406-2, each step in section 408-2 is below any step in section 408-1 and above any step in section 408-3. It should be understood that the number of sections is not limited by... Figure 4 The examples are limited, and they can be any positive integer (i.e., 1, 2, 3, 4, 5, ...).

[0047] Although the first stepped region 402 has been described in detail above, it should be understood that the arrangement of steps in the first stepped region 402 disclosed herein can be similarly applied to the second stepped region 412 or any other stepped region in the stepped structure 400. For example, the second stepped region 412 may include a pair of steps (e.g., multi-section steps) facing each other in the x-direction and at different depths, similar to the first stepped region 402.

[0048] like Figure 4 As shown, according to some embodiments, the first stepped region 402 and the second stepped region 412 are symmetrical in the y-direction. For example, the stepped patterns in the first stepped region 402 and the second stepped region 412 may be symmetrical with respect to the bridging structure 404. It should be understood that in other examples, the first stepped region 402 and the second stepped region 412 may also be asymmetrical with respect to the bridging structure 404 in the y-direction. By arranging the steps asymmetrically in adjacent stepped regions, the mechanical stress introduced by the stepped structure 400 can be distributed more evenly.

[0049] As part of the stacked structure 401, the bridging structure 404 may include vertically interleaved conductive and dielectric layers (not shown), and the conductive layer (e.g., a metal layer or a polysilicon layer) may serve as part of a word line. Unlike at least some steps in the first step region 402 and the second step region 412 (where word lines therein are cut off from the memory array structure in the x-direction (e.g., in the positive x-direction, the negative x-direction, or both), word lines may be retained in the bridging structure 404 to bridge word line contacts landing on the steps and the memory array structure to enable a bidirectional word line driving scheme. In some embodiments, at least one step in the steps of the first step region 402 or the second step region 412 is electrically connected to at least one of the first memory array structure and the second memory array structure via the bridging structure 404. At least one word line may extend laterally in the memory array structure and the bridging structure 404 such that at least one step can be electrically connected to at least one of the first memory array structure and the second memory array structure via the bridging structure 404 through at least one word line. In one example, the steps in staircase 406-1 can be electrically connected to the first memory array structure (in the negative x direction) by their respective word line portions extending through the bridging structure 404 in the negative x direction. However, it may not be necessary for the bridging structure 404 to electrically connect the same step (in the positive x direction) to the second memory array structure because the respective word line portions extending in the positive x direction are not cut off. In another example, the steps in staircase 416-2 can be electrically connected to the second memory array structure (in the positive x direction) by their respective word line portions extending through the bridging structure 404 in the positive x direction. However, it may not be necessary for the bridging structure 404 to electrically connect the same step (in the negative x direction) to the first memory array structure because the respective word line portions extending in the negative x direction are not cut off.

[0050] In some embodiments, at least one step in the steps of the first step region 402 or the second step region 412 is electrically connected to each of the first and second memory array structures via a bridging structure 404. For example, such as Figure 4 As shown, the steps in step 410-2 can be electrically connected to both the first and second memory array structures via bridging structure 404 through their respective word line portions extending in the negative x direction and the positive x direction, as indicated by the current paths (indicated by arrows).

[0051] Figures 5A-5F Various exemplary masks for forming exemplary ladder structures for 3D storage devices are shown according to some embodiments of this disclosure. Figures 6A-6E Various embodiments of this disclosure illustrate manufacturing processes for forming exemplary stepped structures of 3D storage devices. Figure 8This is a flowchart of a method 800 for forming an exemplary ladder structure for a 3D storage device according to some embodiments. Figure 9 This is a flowchart of another method 900 for forming an exemplary ladder structure for a 3D storage device according to some embodiments. Figures 6A-6E , Figure 8 and Figure 9 Examples of stepped structures depicted include Figure 4 The stepped structure 400 depicted in the text will be described together. Figures 5A-5F , Figures 6A-6E , Figure 8 and Figure 9 It should be understood that the operations shown in methods 800 and 900 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations in an operation may be performed simultaneously, or in conjunction with... Figure 8 and 9 The different orders shown will be executed.

[0052] Reference Figure 8 Method 800 begins at operation 802, whereby a stepped region mask is patterned, the stepped region mask including openings for first and second stepped regions in an intermediate body of the stacked structure. In some embodiments, the stepped region mask includes a hard mask. The stacked structure may include first and second material layers that are vertically staggered. In some embodiments, the stacked structure is a dielectric stack, and each of the first material layers includes a first dielectric layer (also referred to as a “sacrificial layer”), and each of the second material layers includes a second dielectric layer different from the first dielectric layer. The staggered first and second dielectric layers may be deposited alternately over a substrate.

[0053] See Figure 6A A stacked structure 602 is formed over a silicon substrate (not shown). The stacked structure 602 includes multiple pairs of first dielectric layers (also referred to as "sacrificial layers," not shown) and second dielectric layers (collectively referred to herein as "dielectric layer pairs," not shown). That is, according to some embodiments, the stacked structure 602 includes staggered sacrificial and dielectric layers. The dielectric and sacrificial layers can be deposited alternately on the silicon substrate to form the stacked structure 602. In some embodiments, each dielectric layer comprises a layer of silicon oxide, and each sacrificial layer comprises a layer of silicon nitride. The stacked structure 602 can be formed by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0054] In some embodiments, the stacked structure is a memory stack, and each first material layer in the first material layer includes a conductive layer, and each second material layer in the second material layer includes a dielectric layer. Interleaved conductive layers (e.g., polysilicon layers) and dielectric layers (e.g., silicon oxide layers) can be deposited alternately over the substrate. The interleaved conductive layers (e.g., metal layers) and dielectric layers (e.g., silicon oxide layers) can also be formed by a gate replacement process that utilizes conductive layers to replace sacrificial layers in the dielectric stack. That is, a stepped structure can be formed on the dielectric stack or before or after a gate replacement process on the memory stack.

[0055] See Figure 6A The stacked structure 602 may include multiple pairs of conductive and dielectric layers (collectively referred to herein as “conductive / dielectric layer pairs”). That is, according to some embodiments, the stacked structure 602 includes staggered conductive and dielectric layers. In some embodiments, each dielectric layer includes a layer of silicon oxide, and each conductive layer includes a layer of a metal such as tungsten or a layer of a semiconductor such as polycrystalline silicon. In some embodiments, to form the stacked structure 602, a slot opening (not shown) may be formed in the dielectric stack, a sacrificial layer in the dielectric stack may be etched by applying an etchant through the slot opening to form a plurality of lateral grooves, and a conductive layer may be deposited in the lateral grooves using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0056] Reference Figure 5A ,exist( Figure 6A A patterned stepped region mask 502 is shown on a stacked structure 602. The stepped region mask 502 includes openings 508-1 and 508-2 for a plurality of stepped regions, including a first stepped region and a second stepped region in the middle (e.g., the middle) of the stacked structure 602 in the x-direction (word line direction). The stacked structure 602 may include a plurality of blocks 504 separated by parallel GLS 506 in the y-direction (bit line direction). According to some embodiments, each opening 508-1 or 508-2 is in two blocks 504 spanning the respective GLS 506 therebetween, as shown in some embodiments. Figure 5A As shown in the diagram. It should be understood that, in another example, each opening 508-1 or 508-2 can be within a block 504 without spanning GLS506. Since the stepped region mask 502 can be used to define stepped regions in the stepped structure via openings 508-1 and 508-2, each stepped region can correspond to one or two blocks in the final product of the 3D storage device. Figure 5AAs shown, according to some embodiments, the stepped region mask 502 covers the bridging structure 510 between adjacent openings 508-01 and 508-2 in the y-direction. The bridging structure 510 in the stepped region mask 502 can define a region of the bridging structure in the stepped structure that can be formed therein in the final product of the 3D storage device, and the openings 508-1 and 508-2 in the stepped region mask 502 can define a region of the step in the stepped structure that can be formed therein in the final product of the 3D storage device. (Refer to...) Figure 6A According to some embodiments, stepped regions 604 and 616 are defined by openings 508-1 and 508-2 in stepped region mask 502, respectively, and a bridging structure 614 between stepped regions 604 and 616 in the y direction is covered by a bridging structure 510 in stepped region mask 502.

[0057] In some embodiments, the stepped region mask 502 is a hard mask compared to a soft mask (e.g., a photoresist mask), and it can be made of a material capable of sustaining various processes until the stepped structure is formed (e.g., it can be retained until at least the shaving process at operation 808 described below). Therefore, the stepped region mask 502 can protect the covered portion of the stacked structure 602 (e.g., the bridging structure 614) during subsequent processes until the stepped region mask 502 is removed, leaving the covered portion of the stacked structure 602 (and the first and second material layers interlaced therein) intact. The stepped region mask 502 can be made of, for example, polysilicon, a high-k dielectric, titanium nitride (TiN), or any other suitable hard mask material. The stepped region mask 502 can be formed by first depositing a hard mask material layer on the stacked structure 602 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The hard mask material layer can then be patterned to form openings 508-1 and 508-2 using photolithography and dry etching and / or wet etching processes (such as reactive ion etching (RIE)). In some embodiments, prior to forming the stepped region mask 502, openings 508-1 and 508-2 are formed adjacent to each pair of peripheral regions in the x-direction (e.g., in...). Figure 3 The TSG reduction ladder in the outer region 303) of the middle.

[0058] like Figure 8As shown, method 800 proceeds to operation 804, wherein at least one pair of steps facing each other in a first lateral direction are formed at the same depth in each of the first and second step regions, such that a bridging structure is formed between the first and second step regions in a second lateral direction perpendicular to the first lateral direction. In some embodiments, each step in the at least one pair of steps includes a plurality of steps in the first lateral direction. (Refer to...) Figure 9 In order to form the steps, at operation 902, the step mask including the opening in the first lateral direction is patterned, and at operation 904, according to the step mask, at least one pair of steps are formed at the same depth by multiple trimming etch cycles.

[0059] like Figure 5B As shown, a step mask 512 is patterned on a step region mask 502. According to some embodiments, the step mask 512 includes openings 514-1, 514-2, 514-3, and 514-4 in the x-direction, each opening for forming a pair of steps facing each other at the same depth. It should be understood that the number of openings 514-1, 514-2, 514-3, and 514-4 determines the number of pairs of facing steps to be formed, and therefore, depending on the arrangement of the step structure in the final product of the 3D storage device, it can be any suitable number. In some embodiments, the step mask 512 is a soft mask (e.g., a photoresist mask) that can be trimmed in a trimming etching process to form steps in the x-direction. Each opening 514-1, 514-2, 514-3, or 514-4 may have a nominally rectangular shape and extend across openings 508-1 and 508-2 in the step region. Figure 5B The solid lines of openings 514-1, 514-2, 514-3, and 514-4 indicate the stacked structure 602 underneath (in... Figure 6A The boundary of the photoresist layer (shown in the figure). In some embodiments, the step mask 512 is formed by spin-coating a photoresist layer onto the step region mask 502 and patterning the coated photoresist layer using photolithography and development processes. The step mask 512 can be used as an etching mask to etch exposed portions of the stacked structure 602.

[0060] like Figure 6A As shown, according to the stepped mask 512 (in Figure 5BAs shown in the figure, multiple pairs of steps (e.g., four pairs of steps 606-1 / 606-2, 608-1 / 608-2, 610-1 / 610-2, and 612-1 / 612-2) are formed at the same depth in each step region 604 or 616 through multiple trimming etching cycles. According to some embodiments, a bridging structure 614 is formed between step regions 604 and 616 in the y-direction. According to some embodiments, each pair of steps 606-1 / 606-2, 608-1 / 608-2, 610-1 / 610-2, or 612-1 / 612-2 faces each other in the x-direction and is at the same depth. Taking a pair of steps 606-1 / 606-2 as an example, step 606-1 may be inclined towards the negative x-direction, and step 606-2 may be inclined towards the positive x-direction. Each step 606-1 / 606-2, 608-1 / 608-2, 610-1 / 610-2, or 612-1 / 612-2 may include the same number of steps in the x-direction. In some embodiments, the number of step pairs (e.g., four pairs of steps 606-1 / 606-2, 608-1 / 608-2, 610-1 / 610-2, or 612-1 / 612-2) in each step region 604 or 616 is determined based on the number of openings in the step mask 512 (e.g., four openings 514-1, 514-2, 514-3, and 514-4), and the number of steps in each step is determined based on the number of trimming etch cycles.

[0061] Having openings 514-1, 514-2, 514-3 and 514-4 (in Figure 5B A stepped mask 512 (represented by solid lines) can be used as a first etching mask. Wet and / or dry etching processes can be used to etch portions of the stacked structure 602 not covered by the first etching mask, using a step depth. Any suitable etchant (e.g., wet and / or dry etching) can be used to remove a certain thickness (e.g., step depth) of the stacked structure 602 in the exposed portions. The thickness of the etching (e.g., step depth) can be controlled by the etching rate and / or etching time. In some embodiments, the step depth is nominally the same as the thickness of the material layer pair (e.g., dielectric layer pair or conductive / dielectric layer pair). It should be understood that in some embodiments, the step depth is a multiple of the thickness of the material layer pair.

[0062] Once the first step depth has been etched, the partition mask 516 can then be trimmed (e.g., incrementally and inwardly etched). Each of the openings 514-1, 514-2, 514-3, and 514-4 is trimmed in the x-direction but not in the y-direction because each opening 514-1, 514-2, 514-3, or 514-4 extends in the y-direction to the edge of the partition mask 516. The trimmed openings 514-1, 514-2, 514-3, and 514-4 (in...) Figure 5B The partition mask 516 (not shown) can be used as a second etch mask. The amount of photoresist layer trimmed from the first etch mask can be controlled by the trimming rate and / or trimming time, and can be directly related to the size of the resulting staircase (e.g., a determinant). The trimming of the first etch mask can be performed using any suitable etch process (e.g., isotropic dry etching or wet etching). Trimming the first etch mask can enlarge the portion of the stacked structure 602 not covered by the first etch mask.

[0063] The trimmed first etch mask can be used as a second etch mask to etch the enlarged uncovered portion of the stacked structure 602 again to form more steps at different depths in each step region 604 or 616. Any suitable etchant (e.g., wet and / or dry etching) can be used to remove a certain thickness (e.g., step depth) of the stacked structure 602 in the enlarged exposed portion. The thickness of the etch (e.g., step depth) can be controlled by the etch rate and / or etch time. In some embodiments, the thickness of the etch is nominally the same as the thickness of the etch in the previous etch step. As a result, the depth offset between adjacent steps is nominally the same. It should be understood that in some embodiments, the thickness of the etch is different in different etch steps, such that the depth offset is different between adjacent steps. The trimming process of the photoresist mask is followed by the etch process of the stacked structure, referred to herein as the trimming etch cycle. The number of trimming etching cycles can determine the number of steps in each of the steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1 or 612-2 formed according to the step mask 512.

[0064] In some embodiments, the amount of photoresist layer trimmed in each trimming etch cycle is nominally the same, so that the dimensions of each step in the x-direction of steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, and 612-2 are nominally the same. In some embodiments, the etch thickness in each cycle is nominally the same, such that the depth of each step in steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, and 612-2 is nominally the same. Because the same trimming etch process (e.g., the same number of trimming etch cycles) is applied simultaneously through openings 514-1, 514-2, 514-3, and 514-4 of the stepped mask 512, each step 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, or 612-2 can have the same depth. For example, a first pair of steps 606-1 / 606-2 can be formed through opening 514-1, a second pair of steps 608-1 / 608-2 can be formed through opening 514-2, a third pair of steps 610-1 / 610-2 can be formed through opening 514-3, and a fourth pair of steps 612-1 / 612-2 can be formed through opening 514-4. In some embodiments, due to the influence of the stepped region mask 502 (in Figure 5B The bridging structure 510 shown in the figure is protected so that the bridging structure 614 remains intact after multiple trimming etch cycles to form steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1 and 612-2.

[0065] like Figure 8 As shown, method 800 proceeds to operation 806, wherein after forming at least one pair of steps, in each of the first and second step regions, a plurality of partitions are formed at different depths in a second lateral direction, such that each step in the at least one pair of steps includes the plurality of partitions at different depths. (See reference...) Figure 9 In order to form partitions, at operation 906, a partition mask including openings in the first step region and the second step region is patterned, and at operation 908, multiple partitions at different depths are formed according to the partition mask through one or more trimming etch cycles.

[0066] like Figure 5C As shown, once steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, and 612-2 are formed, the step mask 512 is removed (in...). Figure 5B(as shown in the diagram), and patterning of a partition mask 516 on a stepped region mask 502. According to some embodiments, the partition mask 516 includes openings 518-1 and 518-2 respectively in openings for the first stepped region 508-1 and the second stepped region 508-2, due to partitioning in the y-direction. In some embodiments, the partition mask 516 is a soft mask (e.g., a photoresist mask), which may be trimmed in a trimming etching process for forming partitions in the y-direction. Each opening 518-1 or 518-2 may have a nominally rectangular shape. Figure 5B The solid lines of openings 518-1 and 518-2 in the diagram indicate the stacked structure 602 that is used to cover the underlying structure. Figure 6A The boundary of the photoresist layer (shown in the diagram). According to some embodiments, the bridging structure 510 remains on the partition mask 516 to cover the underlying bridging structure 614 (shown in the diagram). Figure 6B (as shown in the diagram). In some embodiments, a partition mask 516 is formed by spin-coating a photoresist layer onto a stepped region mask 502 and patterning the coated photoresist layer using photolithography and development processes. The partition mask 516 can be used as an etching mask to etch exposed portions of the stacked structure 602.

[0067] like Figure 6B As shown, by according to partition mask 516 (in Figure 5C (As shown in the diagram) One or more trimming etch cycles are performed in the y-direction to form multiple partitions (e.g., three partitions 618-1, 618-2, and 618-3) at different depths. A partition mask 516 with openings 518-1 and 518-2 (indicated by solid lines) can be used as a first etch mask. Wet and / or dry etching processes can be used to etch portions of the stacked structure 602 not covered by the first etch mask, according to the partition depth. Any suitable etchant (e.g., wet and / or dry etching) can be used to remove a certain thickness (e.g., partition depth) of the stacked structure 602 in the exposed portions. The thickness of the etch (e.g., partition depth) can be controlled by the etch rate and / or etch time. In some embodiments, the partition depth is nominally the same as the thickness of the material layer pair (e.g., dielectric layer pair or conductive / dielectric layer pair). It should be understood that in some embodiments, the partition depth is a multiple of the thickness of the material layer pair.

[0068] like Figure 5CAs shown, the partition mask 516 can be trimmed (e.g., incrementally and inwardly etched). The dashed lines of openings 518-1 and 518-2 indicate the boundaries of the trimmed photoresist layer used to cover the underlying stacked structure 602. Each of openings 518-1 and 518-2 can be trimmed in both the x and y directions due to its rectangular shape. The partition mask 516 with trimmed openings 518-1 and 518-2 (indicated by dashed lines) can be used as a second etch mask.

[0069] like Figure 6B As shown, the amount of photoresist layer trimmed from the first etch mask can be controlled by the trimming rate and / or trimming time, and can be directly related to the size of the resulting partitions (e.g., a determinant). Trimming the first etch mask can be performed using any suitable etching process (e.g., isotropic dry etching or wet etching). Trimming the first etch mask can enlarge the portion of the stacked structure 602 not covered by the first etch mask. The trimmed first etch mask can be used as a second etch mask to etch the enlarged uncovered portion of the stacked structure 602 again to form more partitions at different depths in the respective step regions 604 or 616. Any suitable etchant (e.g., wet etching and / or dry etching) can be used to remove a certain thickness (e.g., partition depth) of the stacked structure 602 in the enlarged exposed portion. The thickness of the etch (e.g., partition depth) can be controlled by the etch rate and / or etch time. In some embodiments, the thickness of the etch is nominally the same as the thickness of the etch in the previous etch step. As a result, the depth offset between adjacent partitions is nominally the same. It should be understood that in some embodiments, the etch thickness is different in different etch steps, thus the depth offset is different between adjacent partitions. The number of trimming etch cycles can determine the number of partitions formed according to the partition mask 516. In some embodiments, due to the untrimmed partition mask 516 (e.g., Figure 5C The bridging structure 510 shown in the diagram is protected, and the bridging structure 614 remains intact after partitions 618-1, 618-2 and 618-3 are formed through one or more trimming etch cycles.

[0070] In some embodiments, such as Figure 6BAs shown, after forming steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1 and 612-2, multiple partitions 618-1, 618-2 and 618-3 are formed, such that each step 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1 or 612-2 includes multiple partitions 618-1, 618-2 and 618-3 at different depths. Furthermore, since sections 618-1, 618-2, and 618-3 are formed after steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, and 612-2, each step in one of sections 618-1, 618-2, and 618-3 is located above or below any step in the other section of sections 618-1, 618-2, and 618-3, as... Figure 6B As shown in the diagram. To achieve this effect, in some embodiments, the partition depth etched in each trimming etch cycle is determined based on the number of steps in each of the steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, or 612-2 formed in the previous trimming etch process. For example, the partition depth may not be less than the total depth of all steps in each of the steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, or 612-2 formed in the previous trimming etch process. In one example, for each of n steps having a nominally identical step depth D, the partition depth may be (n+1)×D.

[0071] Although Figure 6B An example of forming a three-partition stepped structure is shown, which includes four partitions 618-1, 618-2, and 618-3 at different depths in each stepped region 604 or 616. However, it should be understood that multi-partition stepped structures and their manufacturing methods are not limited to three partitions, and can be any integer greater than 1 by changing the number of trimming etch cycles and the design of the partition mask 516.

[0072] like Figure 8 As shown, method 800 proceeds to operation 808, wherein in operation 808, in each of the first and second stepped regions, each step of at least one pair of steps is cut to a different depth. In some embodiments, after cutting each step, at least one step of each step is connected via a bridging structure to the remainder of the stacked structure covered by the stepped region mask, through at least one sacrificial layer in the sacrificial layers or through at least one conductive layer in the conductive layers. (Refer to...) Figure 9To reduce the steps, at operation 910, a first reduction mask is patterned, the first reduction mask including a first opening in a first step region and a second step region, and at operation 912, according to the first reduction mask, a first set of steps exposed by the first opening is reduced to a first depth through multiple etch cycles. In some embodiments, to reduce the steps, at operation 914, a second reduction mask is patterned, the second reduction mask including a second opening in a first step region and a second step region, and at operation 916, according to the second reduction mask, a second set of steps exposed by the second opening is reduced to a second depth through multiple etch cycles.

[0073] like Figure 5D As shown, once partitions 618-1, 618-2, and 618-3 are formed, the partition mask 516 is removed (in... Figure 5C (shown in the image), and patterning of a first reduction mask 520 on a stepped region mask 502. According to some embodiments, the first reduction mask 520 includes openings 522-1 and 522-2 in the openings of the first stepped region 508-1 and the second stepped region 508-2, respectively, for reducing the first set of steps exposed by openings 522-1 and 522-2 to the same first depth. The openings 522-1 and 522-2 in the first reduction mask 520 correspond to steps 610-1, 610-2, 612-1 and 612-2 (in the image shown in the image), and patterning of a first reduction mask 520 on a stepped region mask 502. Figure 6C (as shown in the diagram) so that only steps 610-1, 610-2, 612-1, and 612-2 can be reduced to a first depth according to the first reduction mask 520. Since no trimming of the first reduction mask 520 is required, the first reduction mask 520 can be a hard mask or a soft mask. Each opening 522-1 or 522-2 has a nominally rectangular shape and is located within the respective opening of the step region 508-1 or 508-2. In some embodiments where the first reduction mask 520 is a soft mask, the first reduction mask 520 is formed by spin-coating a photoresist layer onto the step region mask 502 and patterning the coated photoresist layer using photolithography and development processes. In some embodiments where the first reduction mask 520 is a hard mask, the first reduction mask 520 is formed by first depositing a hard mask material layer on a stepped region mask 502 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The hard mask material layer can then be patterned using photolithography and dry etching and / or wet etching processes (such as RIE) to form openings 522-1 and 522-2. The first reduction mask 520 can be used as an etching mask to reduce the exposed first set of steps 610-1, 610-2, 612-1, and 612-2 to the same first depth.

[0074] As used herein, a “reduction” process is a process that reduces the depth of one or more steps through multiple etch cycles. Each etch cycle may include one or more dry and / or wet etch processes that etch a step (i.e., reduce the depth by a step depth). As described in detail above, according to some embodiments, the purpose of a reduction process is to place the steps (and their steps) in the final product of the 3D memory device at different depths. Therefore, depending on the number of steps, a certain number of reduction processes may be required.

[0075] like Figure 5E As shown, once the first set of steps 610-1, 610-2, 612-1, and 612-2 have been cut, the first cut mask 520 is removed (in... Figure 5D (As shown in the diagram), a second reduction mask 524 is patterned on a stepped region mask 502. According to some embodiments, the second reduction mask 524 includes openings 526-1 and 526-2 in the openings of the first stepped region 508-1 and the second stepped region 508-2, respectively, for reducing the second set of steps exposed by openings 526-1 and 526-2 to the same second depth. The openings 526-1 and 526-2 in the second reduction mask 524 correspond to steps 606-2, 608-1, 610-2, and 612-1 (in...). Figure 6D (as shown in the diagram) so that only steps 606-2, 608-1, 610-2, and 612-1 can be cut to a second depth according to the second cutting mask 524. Similar to the first cutting mask 520, the second cutting mask 524 can be a hard mask or a soft mask. The second cutting mask 524 can be used as an etching mask to cut the exposed second set of steps 606-2, 608-1, 610-2, and 612-1 to the same second depth. After the second cutting process according to the second cutting mask 524, some steps (e.g., 610-2 and 612-1) are cut twice to the sum of the first and second depths, some steps (e.g., 610-1 and 612-2) are cut once to the first depth, some steps (e.g., 608-1 and 606-2) are cut once to the second depth, and some steps (e.g., 606-1 and 608-2) have not yet been cut.

[0076] One or more cut masks and cut processes may be needed to allow the various steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, or 612-2 to be at different depths. For example, as... Figure 5F As shown, once the second set of steps 606-2, 608-1, 610-2, and 612-1 are formed, the second reduction mask 524 can be removed (in... Figure 5E(shown in the figure), and a third reduction mask 528 can be patterned on the stepped region mask 502. According to some embodiments, the third reduction mask 528 includes openings 530-1 and 530-2 in the openings of the first stepped region 508-1 and the second stepped region 508-2, respectively, for reducing the third set of steps exposed by the openings 530-1 and 530-2 to the same third depth. The openings 530-1 and 530-2 in the third reduction mask 528 correspond to steps 608-1, 608-2, 610-1 and 610-2 (in the figure). Figure 6E (As shown in the diagram), so that only steps 608-1, 608-2, 610-1, and 610-2 can be cut to a third depth according to the third cutting mask 528. Similar to the first cutting mask 520 and the second cutting mask 524, the third cutting mask 528 can be a hard mask or a soft mask. The third cutting mask 528 can be used as an etching mask to cut the exposed third set of steps 608-1, 608-2, 610-1, and 610-2 to the same third depth. As a result, after the third cutting process according to the third cutting mask 528, each step 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, or 612-2 can have different depths.

[0077] In some embodiments, after the third shaving process (i.e., after the shaving process is complete), the stepped region mask 502 is removed, for example using wet etching and / or dry etching processes. That is, according to some embodiments, the stepped region mask 502 remains on the stacked structure 602 until at least the shaving process at operation 808, to protect the interleaved first and second material layers in the bridging structure 614 of the stepped structure and the memory array structure from being etched by various trimming etching processes and shaving processes.

[0078] It should be understood that the first, second, and third reduction masks 520, 524, and 528 described above, and the first, second, and third reduction processes described above, are examples of reduction steps 606-1, 606-2, 608-1, 608-2, 610-1, 610-2, 612-1, and 612-2, and the same result can be achieved using other suitable reduction schemes (including various reduction masks and reduction processes). It should be further understood that various reduction schemes can achieve the same effect, i.e., that the steps in the stepped structure in the final product of the 3D storage device have different depths. For example, Figures 7A-7D According to some embodiments of this disclosure, various exemplary schemes for cutting stairs to different depths in a staircase structure are shown. Figures 7A-7D The figures illustrate an exemplary reduction scheme that can reduce six steps (by...) Figures 7A-7D(The dashed lines in the diagram indicate) cuts to different depths. As mentioned above, the number of cut masks, the order of the cut masks, the design of each cut mask (e.g., the number and pattern of openings) and / or the depth reduced by each cut process (e.g., the number of etch cycles) can affect the specific depth of each step after the cut process, even though the steps are at different depths.

[0079] According to one aspect of this disclosure, a 3D storage device includes: a storage array structure and a stepped structure, the stepped structure being located in an intermediate portion of the storage array structure and laterally dividing the storage array structure into a first storage array structure and a second storage array structure. The stepped structure includes a first stepped region and a bridging structure connecting the first and second storage array structures. The first stepped region includes a first pair of steps facing each other in a first lateral direction and at different depths. Each step includes multiple steps. Each step in the first pair of steps includes multiple partitions at different depths in a second lateral direction perpendicular to the first lateral direction. At least one step in the first pair of steps is electrically connected to at least one of the first and second storage array structures via the bridging structure.

[0080] In some embodiments, each step in one partition of a partition is located above or below any step in another partition of a partition.

[0081] In some embodiments, the storage array structure includes multiple blocks in a second lateral direction. In some embodiments, the first stepped region is located in one or two blocks.

[0082] In some embodiments, the stepped structure further includes a second stepped region. In some embodiments, the bridging structure is located between the first stepped region and the second stepped region in the second lateral direction.

[0083] In some embodiments, the second stepped region includes a second pair of steps facing each other in the first lateral direction and at different depths. In some embodiments, the first stepped region and the second stepped region are symmetrical in the second lateral direction.

[0084] In some embodiments, the first stepped area includes a second pair of steps facing each other in a first lateral direction and at different depths. In some embodiments, each step in the first pair of steps and the second pair of steps is at a different depth. In some embodiments, each step in the first pair of steps and the second pair of steps is at a different depth.

[0085] In some embodiments, the 3D storage device further includes at least one word line extending laterally in the storage array structure and the bridging structure, such that at least one step is electrically connected via the at least one word line to at least one of the first storage array structure and the second storage array structure through the bridging structure.

[0086] In some embodiments, at least one step in the first pair of steps is electrically connected to each of the first and second memory array structures via a bridging structure.

[0087] In some embodiments, the bridging structure includes vertically interleaved conductive and dielectric layers.

[0088] According to another aspect of this disclosure, a 3D storage device includes: a storage array structure and a stepped structure, the stepped structure being located in an intermediate portion of the storage array structure and laterally dividing the storage array structure into a first storage array structure and a second storage array structure. The stepped structure includes a first stepped region and a bridging structure connecting the first and second storage array structures. The first stepped region includes a first step comprising multiple partitions in a second lateral direction. Each partition includes multiple steps in a first lateral direction perpendicular to the second lateral direction. Each step in one partition is located above or below any step in another partition. At least one step in the first step is electrically connected to at least one of the first and second storage array structures via the bridging structure.

[0089] In some embodiments, the first step area further includes a second step. In some embodiments, the first step and the second step face each other in a first lateral direction and have different depths.

[0090] In some embodiments, the steps in the first and second steps are at different depths. In some embodiments, the steps in the first and second steps are electrically connected to at least one of the first and second memory array structures via a bridging structure.

[0091] In some embodiments, the storage array structure includes multiple blocks in a second lateral direction. In some embodiments, the first stepped region is located in one or two blocks.

[0092] In some embodiments, the stepped structure further includes a second stepped region. In some embodiments, the bridging structure is located between the first stepped region and the second stepped region in a second lateral direction.

[0093] In some embodiments, the 3D storage device further includes at least one word line extending laterally in the storage array structure and the bridging structure, such that at least one step is electrically connected via the at least one word line to at least one of the first storage array structure and the second storage array structure through the bridging structure.

[0094] In some embodiments, at least one step in the first pair of steps is electrically connected to each of the first and second memory array structures via a bridging structure.

[0095] In some embodiments, the bridging structure includes vertically interleaved conductive and dielectric layers.

[0096] In some embodiments, the stepped structure is located in the middle of the storage array structure.

[0097] According to another aspect of this disclosure, a method for forming a stepped structure for a 3D storage device is disclosed. In an intermediate of a stacked structure comprising vertically interlaced first and second material layers, a stepped region mask including openings for first and second stepped regions is patterned. In each of the first and second stepped regions, at least one pair of steps facing each other in a first lateral direction are formed at the same depth, such that a bridging structure is formed between the first and second stepped regions in a second lateral direction perpendicular to the first lateral direction. After forming at least one pair of steps, in each of the first and second stepped regions, multiple partitions in the second lateral direction are formed at different depths, such that each step in the at least one pair of steps includes multiple partitions at different depths. In each of the first and second stepped regions, each step in the at least one pair of steps is cut to different depths.

[0098] In some embodiments, in order to form at least one pair of steps, a partition mask including openings in a first step region and a second step region is patterned, and multiple partitions are formed at different depths according to the partition mask through one or more trimming etch cycles.

[0099] In some embodiments, in order to form multiple partitions, a partition mask including openings in a first stepped region and a second stepped region is patterned, and multiple partitions are formed at different depths by one or more trimming etch cycles according to the partition mask.

[0100] In some embodiments, after multiple partitions are formed, each step in one partition is located above or below any step in another partition.

[0101] In some embodiments, the bridging structure is covered by a stepped area mask or a partition mask.

[0102] In some embodiments, in order to cut each step, a second cut mask including a second opening in a first step region and a second step region is patterned, and a second set of steps that expose the second opening is cut to a second depth according to the second cut mask through multiple etch cycles.

[0103] In some embodiments, in order to cut each step, a second cut mask is formed including a second opening in a first step region and a second step region, and according to the second cut mask, a second set of steps exposed by the second opening is cut to a second depth through multiple etch cycles.

[0104] In some embodiments, each first material layer in the first material layer includes a sacrificial layer, and each second material layer in the second material layer includes a dielectric layer.

[0105] In some embodiments, each first material layer in the first material layer includes a conductive layer, and each second material layer in the second material layer includes a dielectric layer.

[0106] In some embodiments, each step in at least one pair of steps includes a plurality of steps in a first lateral direction. In some embodiments, after each step is cut, at least one step in each step is connected to the remainder of the stacked structure covered by the step region mask via a bridging structure through at least one sacrificial layer in the sacrificial layers or at least one conductive layer in the conductive layers.

[0107] In some embodiments, the stepped area mask is maintained until at least each step is cut off. In some embodiments, the stepped area mask includes a hard mask.

[0108] The foregoing description of specific embodiments will reveal the general nature of this disclosure. Without departing from the general concept of this disclosure, those skilled in the art can readily modify and / or adjust various applications of such specific embodiments using knowledge within the scope of the art, without excessive experimentation. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limitation, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on the teachings and guidance.

[0109] The foregoing description uses functional building blocks to illustrate the implementation of specific functions and their relationships to describe embodiments of this disclosure. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries may be defined, as long as the specified functions and their relationships are appropriately performed.

[0110] The summary and abstract may set forth one or more, but not all, exemplary embodiments of this disclosure as contemplated by the inventors, and therefore are not intended to limit this disclosure and the appended claims in any way.

[0111] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined only by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) storage device, comprising: Storage array structure; as well as A stepped structure, located in the middle of the storage array structure, laterally divides the storage array structure into a first storage array structure and a second storage array structure. The stepped structure includes a first stepped region, a second stepped region, and a bridging structure connecting the first storage array structure and the second storage array structure. The first stair area includes at least one pair of first staircases, the pair of first staircases including two first staircases facing each other in the first transverse direction and at different depths, the first staircase including multiple steps; Each of the at least one pair of first steps includes multiple sections at different depths in a second lateral direction perpendicular to the first lateral direction, wherein each step in one of the multiple sections is either above any step in another of the multiple sections or below any step in another of the multiple sections; At least one step of the pair of first steps is electrically connected via the bridging structure to at least one of the first memory array structure and the second memory array structure; and The first stepped region and the second stepped region are asymmetrical with respect to the bridging structure in the second transverse direction.

2. The three-dimensional storage device according to claim 1, wherein, The storage array structure includes multiple blocks in the second lateral direction; and The first stepped region is located in one or both of the blocks.

3. The three-dimensional storage device according to claim 1, wherein, The bridging structure is located between the first stepped region and the second stepped region in the second lateral direction.

4. The three-dimensional storage device according to claim 1, wherein, At least one step in the pair of first steps is electrically connected to each of the first and second memory array structures via the bridging structure.

5. The three-dimensional storage device according to any one of claims 1-4, wherein, Each step in each of the at least one pair of first steps is at a different depth.

6. The three-dimensional storage device according to any one of claims 1-3, further comprising at least one word line extending laterally in the storage array structure and the bridging structure, such that at least one step of the pair of first steps is electrically connected via the at least one word line to at least one of the first storage array structure and the second storage array structure through the bridging structure.

7. The three-dimensional memory device of any one of claims 1-4, wherein, The bridging structure includes vertically interleaved conductive and dielectric layers.

8. A three-dimensional (3D) storage device, comprising: Storage array structure; as well as A stepped structure, located in the middle of the storage array structure, laterally divides the storage array structure into a first storage array structure and a second storage array structure. The stepped structure includes a first stepped region, a second stepped region, and a bridging structure connecting the first storage array structure and the second storage array structure. The first step area includes multiple first steps, each including multiple partitions in the second lateral direction, and each partition in each of the multiple first steps includes multiple steps in the first lateral direction perpendicular to the second lateral direction. Each step in one of the plurality of partitions is either above any step in another of the plurality of partitions, or below any step in another of the plurality of partitions; and At least one step in the first staircase is electrically connected via the bridging structure to at least one of the first memory array structure and the second memory array structure; and The first stepped region and the second stepped region are asymmetrical with respect to the bridging structure in the second transverse direction.

9. The three-dimensional storage device according to claim 8, wherein, Two first steps facing each other in the first transverse direction and at different depths constitute a pair of first steps.

10. The three-dimensional storage device according to claim 9, wherein, At least one step of the pair of first steps is electrically connected to each of the first and second memory array structures via the bridging structure.

11. The three-dimensional storage device according to claim 8, wherein, The storage array structure includes multiple blocks in the second lateral direction; and The first stepped region is located in one or both of the blocks.

12. The three-dimensional storage device according to any one of claims 8-11, wherein, The bridging structure is located between the first stepped region and the second stepped region in the second lateral direction.

13. The three-dimensional storage device according to any one of claims 8-11, further comprising at least one word line extending laterally in the storage array structure and the bridging structure, such that the at least one step in each first step is electrically connected via the at least one word line to at least one of the first storage array structure and the second storage array structure via the bridging structure.

14. The three-dimensional storage device according to any one of claims 8-11, wherein, The bridging structure includes vertically interleaved conductive and dielectric layers.

15. The three-dimensional storage device according to any one of claims 8-11, wherein, The stepped structure is located in the middle of the storage array structure.

16. A method for forming a stepped structure for a three-dimensional (3D) storage device, comprising: In an intermediate body comprising a stacked structure of vertically intersecting first and second material layers, a stepped region mask comprising openings for the first and second stepped regions is patterned. In each of the first stepped region and the second stepped region, at least one pair of steps facing each other are formed at the same depth in the first lateral direction, such that the bridging structure is formed between the first stepped region and the second stepped region in a second lateral direction perpendicular to the first lateral direction. After the formation of the at least one pair of steps, in each of the first and second step regions, a plurality of partitions are formed at different depths in the second lateral direction, such that each step in the at least one pair of steps includes the plurality of partitions at different depths, wherein, after the formation of the plurality of partitions, each step in one of the plurality of partitions is either above any step in the other of the plurality of partitions, or below any step in the other of the plurality of partitions; and In both the first and second stepped areas, each step in the at least one pair of steps is cut to a different depth, such that the first stepped area includes at least one pair of first steps. The pair of first steps includes two first steps that face each other in the first transverse direction and are located at different depths. At least one step of the at least one pair of first steps is electrically connected to at least one of the first and second memory array structures via the bridging structure, and The first stepped region and the second stepped region are asymmetrical with respect to the bridging structure in the second transverse direction.

17. The method according to claim 16, wherein, Forming the at least one pair of steps includes: Patterning of a stepped mask including an opening in the first lateral direction; and According to the stepped mask, the at least one pair of first steps are formed at the same depth through multiple trimming etch cycles.

18. The method according to claim 16, wherein, Forming the multiple partitions includes: Patterning of a partition mask including openings in the first and second stepped regions; and Based on the partition mask, the plurality of partitions are formed at different depths through one or more trimming etch cycles.

19. The method according to claim 18, wherein, The bridging structure is covered by the stepped region mask or the partition mask.

20. The method according to any one of claims 16-19, wherein, The reduction of each step includes: Patterning of a first reduction mask including a first opening in the first stepped region and a second stepped region; and Based on the first reduction mask, the first set of steps exposed by the first opening is reduced to a first depth through multiple etch cycles.

21. The method according to claim 20, wherein, Reducing the ladder also includes: Patterning of a second reduction mask including a second opening in the first stepped region and the second stepped region; and According to the second cut mask, the second set of steps exposed by the second opening is cut to a second depth through multiple etch cycles.

22. The method according to any one of claims 16-19 and 21, wherein, Each of the first material layers in the first material layer includes a sacrificial layer, and each of the second material layers in the second material layer includes a dielectric layer.

23. The method according to any one of claims 16-19 and 21, wherein, Each of the first material layers in the first material layer includes a conductive layer, and each of the second material layers in the second material layer includes a dielectric layer.

24. The method according to claim 22, wherein, Each step in the at least one pair of stairs includes a plurality of steps in the first transverse direction; and After each step is cut, at least one step of each step is connected via the bridging structure to the remaining portion of the stacked structure covered by the step area mask, through at least one of the sacrificial layers.

25. The method according to claim 23, wherein, Each step in the at least one pair of stairs includes a plurality of steps in the first transverse direction; and After each step is cut, at least one step of each step is connected to the remaining portion of the stacked structure covered by the step area mask via the bridging structure through at least one of the conductive layers.

26. The method according to any one of claims 16-19, 21, and 24-25, wherein, The stepped area mask remains in place until at least each step is cut off.

27. The method according to claim 26, wherein, The stepped region mask includes a hard mask.

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