Display substrate, display panel and display device

Abstract

A display substrate, a display panel, and a display device are provided. The display substrate includes a substrate; and a first transistor disposed on the substrate. The first transistor includes a first active layer, a first bottom gate, and a first top gate. The first bottom gate is located between the substrate and the first active layer, and the first top gate is located on the side of the first active layer away from the substrate. The orthographic projections of any two of the first active layer, the first bottom gate, and the first top gate on the substrate at least partially overlap each other. A third gate insulating layer is disposed between the first bottom gate and the first active layer. The first active layer includes an oxide semiconductor material, and the third gate insulating layer includes a silicon oxide material. The surface of the first top gate away from the substrate is in direct contact with the silicon oxide material, and the surface of the first active layer near the substrate is in direct contact with the silicon oxide material.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display substrate, a display panel, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are a type of display device that uses OLEDs to display images and other information. OLED displays feature characteristics such as low power consumption, high brightness, and high response speed. Low-temperature poly-oxide-slim TFT (LTPO TFT) technology is an emerging thin-film transistor technology in recent years. Theoretically, LTPO TFT can save 5-15% of power compared to traditional low-temperature poly-silicon TFT (LTPS TFT) technology, resulting in lower overall power consumption for the display screen.

[0003] The information disclosed in this section is only for understanding the background of the technical concept of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, wherein the display substrate comprises:

[0005] Substrate; and

[0006] The first transistor disposed on the substrate.

[0007] The first transistor includes a first active layer, a first bottom gate, and a first top gate. The first bottom gate is located between the substrate and the first active layer, and the first top gate is located on the side of the first active layer away from the substrate. The orthographic projections of any two of the first active layer, the first bottom gate, and the first top gate on the substrate at least partially overlap each other. A third gate insulating layer is disposed between the first bottom gate and the first active layer. The first active layer includes an oxide semiconductor material, and the third gate insulating layer includes a silicon oxide material. The surface of the first top gate away from the substrate is in direct contact with the silicon oxide material, and the surface of the first active layer near the substrate is in direct contact with the silicon oxide material.

[0008] According to some exemplary embodiments, the display substrate includes:

[0009] A first semiconductor layer disposed on the substrate; and

[0010] The second semiconductor layer is disposed on the side of the first semiconductor layer away from the substrate.

[0011] The display substrate further includes a third transistor.

[0012] The third transistor includes a third active layer and a third gate. The third active layer includes a polycrystalline silicon semiconductor material. The third active layer is located in the first semiconductor layer, and the first active layer is located in the second semiconductor layer.

[0013] According to some exemplary embodiments, the distance between the surface of the first active layer near the substrate and the surface of the first bottom gate away from the substrate is greater than the distance between the surface of the first active layer away from the substrate and the surface of the first top gate near the substrate.

[0014] According to some exemplary embodiments, the distance between the surface of the first active layer near the substrate and the surface of the first bottom gate away from the substrate is greater than the distance between the surface of the third active layer away from the substrate and the surface of the third gate near the substrate.

[0015] According to some exemplary embodiments, the distance between the surface of the first active layer away from the substrate and the surface of the first top gate near the substrate is approximately equal to the distance between the surface of the third active layer away from the substrate and the surface of the third gate near the substrate.

[0016] According to some exemplary embodiments, the display substrate further includes a second transistor, the second transistor including a second bottom gate and a second top gate, the second bottom gate being located between the substrate and the active layer of the second transistor, the second top gate being located on the side of the active layer of the second transistor away from the substrate, and any two of the active layer of the second transistor, the second bottom gate and the second top gate having orthographic projections on the substrate at least partially overlapping each other.

[0017] According to some exemplary embodiments, the display substrate includes a storage capacitor, the storage capacitor including a first capacitor structure, a second capacitor structure, and a third capacitor structure disposed on the substrate, the third capacitor structure being located on the side of the first capacitor structure away from the substrate, the second capacitor structure being located between the first capacitor structure and the third capacitor structure, and the orthographic projections of any two of the first capacitor structure, the second capacitor structure, and the third capacitor structure onto the substrate at least partially overlap; and

[0018] The first capacitor structure and the third capacitor structure are electrically connected to each other to form the first capacitor electrode of the storage capacitor, and the second capacitor structure forms the second capacitor electrode of the storage capacitor.

[0019] According to some exemplary embodiments, the display substrate includes a first conductive layer disposed on the substrate, the first conductive layer being located on the side of the first semiconductor layer away from the substrate; and the first capacitor structure and the third gate of the third transistor are both located on the first conductive layer.

[0020] According to some exemplary embodiments, the display substrate includes a second conductive layer disposed on the substrate, the second conductive layer being located between the first conductive layer and the second semiconductor layer; and the first bottom gate and the second capacitor structure are both located on the second conductive layer.

[0021] According to some exemplary embodiments, the display substrate includes a third conductive layer disposed on the substrate, the third conductive layer being located on the side of the second semiconductor layer away from the substrate; and the first top gate and the third capacitor structure are both located on the third conductive layer.

[0022] According to some exemplary embodiments, the display substrate includes a first buffer layer located between the substrate and the first semiconductor layer, the first buffer layer comprising silicon oxide or silicon nitride.

[0023] According to some exemplary embodiments, the display substrate includes a first gate insulating layer located between the first semiconductor layer and the first conductive layer, the first gate insulating layer comprising silicon oxide.

[0024] According to some exemplary embodiments, the display substrate includes a second gate insulating layer located between the first conductive layer and the second conductive layer, the second gate insulating layer comprising silicon nitride.

[0025] According to some exemplary embodiments, a single insulating layer is provided between the first capacitor structure and the second capacitor structure, the single insulating layer including a portion of the second gate insulating layer.

[0026] According to some exemplary embodiments, the display substrate includes a third gate insulating layer located between the second conductive layer and the second semiconductor layer, the third gate insulating layer comprising silicon oxide.

[0027] According to some exemplary embodiments, the display substrate includes a fourth gate insulating layer located between the second semiconductor layer and the third conductive layer, the fourth gate insulating layer comprising silicon oxide.

[0028] According to some exemplary embodiments, a single insulating layer is provided between the second capacitor structure and the third capacitor structure, the single insulating layer including a portion of the fourth gate insulating layer.

[0029] According to some exemplary embodiments, two insulating layers are provided between the second capacitor structure and the third capacitor structure, the two insulating layers including a portion of the third gate insulating layer and a portion of the fourth gate insulating layer.

[0030] According to some exemplary embodiments, the display substrate further includes a second buffer layer disposed between the second gate insulating layer and the second conductive layer; and two insulating layers are disposed between the first capacitor structure and the second capacitor structure, the two insulating layers including a portion of the second gate insulating layer and a portion of the second buffer layer.

[0031] According to some exemplary embodiments, the third capacitor structure is located in the second semiconductor layer, and the third capacitor structure includes a structure formed of a conductive oxide semiconductor material.

[0032] According to some exemplary embodiments, the display substrate includes a third gate insulating layer located between the second conductive layer and the second semiconductor layer, the third gate insulating layer comprising silicon oxide; and a single insulating layer is disposed between the second capacitor structure and the third capacitor structure, the single insulating layer comprising a portion of the third gate insulating layer.

[0033] According to some exemplary embodiments, the display substrate includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; and each of the plurality of thin-film transistors includes a source and a drain, the source and drain of each thin-film transistor being located on the fourth conductive layer.

[0034] According to some exemplary embodiments, the display substrate includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; and the fifth conductive layer includes a light-shielding layer whose orthogonal projection on the substrate at least covers the orthogonal projection of the active layer of each of the first transistor and the second transistor on the substrate.

[0035] According to some exemplary embodiments, the fourth conductive layer includes a first conductive sublayer and a second conductive sublayer, the first conductive sublayer being disposed on the interlayer insulating layer, the second conductive sublayer being disposed on the side of the first conductive sublayer away from the substrate, and the first conductive sublayer and the second conductive sublayer being in contact with each other.

[0036] In another aspect, a display panel is provided, including the display substrate as described above.

[0037] In another aspect, a display device is provided, comprising a display substrate as described above or a display panel as described above.

[0038] In another aspect, a method for manufacturing a display substrate is provided, wherein the manufacturing method includes the following steps:

[0039] Provide substrates;

[0040] A first semiconductor layer is fabricated on the substrate using a patterning process, the first semiconductor layer comprising polycrystalline silicon semiconductor islands;

[0041] Using a patterning process, a first conductive layer is formed on the side of the first semiconductor layer away from the substrate.

[0042] Using a patterning process, a second conductive layer is formed on the side of the first conductive layer away from the substrate.

[0043] An insulating layer is formed on the side of the second conductive layer away from the substrate; and

[0044] Using a patterning process, a second semiconductor layer is formed on the side of the second conductive layer away from the substrate. The second semiconductor layer comprises oxide semiconductor silicon islands.

[0045] The display substrate includes a plurality of thin-film transistors disposed on the substrate, wherein the plurality of thin-film transistors include at least a first transistor, a second transistor, and a third transistor.

[0046] Each of the plurality of thin-film transistors includes an active layer, the active layer of the third transistor is located in the first semiconductor layer, and the active layer of at least one of the first transistor and the second transistor is located in the second semiconductor layer; and

[0047] The first transistor includes a first active layer, a first bottom gate, and a first top gate. The first bottom gate is located between the substrate and the first active layer. The first top gate is located on the side of the first active layer away from the substrate. The orthographic projections of any two of the first active layer, the first bottom gate, and the first top gate on the substrate at least partially overlap each other. A third gate insulating layer is disposed between the first bottom gate and the first active layer. The first active layer includes the oxide semiconductor silicon island. The third gate insulating layer includes silicon oxide material. The surface of the first top gate away from the substrate is in direct contact with the silicon oxide material. The surface of the first active layer near the substrate is in direct contact with the silicon oxide material.

[0048] According to some exemplary embodiments, the manufacturing method further includes:

[0049] An interlayer insulating layer is formed on the side of the first top gate away from the substrate.

[0050] A plurality of first vias are formed in the interlayer insulating layer, the plurality of first vias exposing at least a portion of the active layer of each of the first transistor and the second transistor;

[0051] A first conductive material layer is deposited on the side of the interlayer insulating layer away from the substrate.

[0052] A plurality of second vias are formed, the plurality of second vias exposing at least a portion of the active layer of the third transistor;

[0053] A second conductive material layer is deposited on the side of the first conductive material layer away from the substrate; and

[0054] The first and second conductive material layers are patterned in a single patterning process to form the source and drain of the plurality of thin-film transistors. Attached Figure Description

[0055] The features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0056] Figure 1 This is a plan view of a display device according to some embodiments of the present disclosure;

[0057] Figure 2 This is a plan view of a display substrate included in a display device according to some embodiments of the present disclosure;

[0058] Figure 3 The display substrate according to some embodiments of this disclosure is in Figure 2 A magnified view of part I in the image;

[0059] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0060] Figure 5 This is a schematic diagram showing a planar structure of a pixel driving circuit for a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure;

[0061] Figure 6 It is shown Figure 5 A schematic diagram of the planar structure of the first semiconductor layer of the pixel driving circuit shown;

[0062] Figure 7 It is shown Figure 5A schematic diagram of the planar structure of the first conductive layer of the pixel driving circuit shown.

[0063] Figure 8 It is shown Figure 5 A schematic diagram of the planar structure of the second conductive layer of the pixel driving circuit shown;

[0064] Figure 9 It is shown Figure 5 A schematic diagram of the planar structure of the second semiconductor layer of the pixel driving circuit shown;

[0065] Figure 10 It is shown Figure 5 A schematic diagram of the planar structure of the third conductive layer of the pixel driving circuit shown.

[0066] Figure 11 It is shown Figure 5 A schematic diagram of the planar structure of the fourth conductive layer of the pixel driving circuit shown.

[0067] Figure 12 It is shown Figure 5 A schematic diagram of the planar structure of the fifth conductive layer of the pixel driving circuit shown.

[0068] Figure 13 This illustrates the edge of a display substrate according to some exemplary embodiments of the present disclosure. Figure 5 A schematic diagram of the cross-sectional structure intercepted by lines AA' and BB' is shown below. For ease of description, the structure will be shown along... Figure 5 The cross-sectional structures intercepted by lines AA' and BB' are shown in the same schematic diagram;

[0069] Figure 14 This is a schematic diagram illustrating a planar structure of a display substrate according to some exemplary embodiments of the present disclosure, wherein the planar structure of the first electrode of the light-emitting device is schematically shown;

[0070] Figure 15 This is a schematic diagram illustrating the cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0071] Figure 16 This is a schematic diagram illustrating the planar structure of a pixel driving circuit for a sub-pixel of a display substrate according to some other exemplary embodiments of the present disclosure;

[0072] Figure 17 It is shown Figure 16 A schematic diagram of the planar structure of the second semiconductor layer of the pixel driving circuit shown;

[0073] Figure 18 It is shown Figure 16 A schematic diagram of the planar structure of the third conductive layer of the pixel driving circuit shown.

[0074] Figure 19 This is a schematic diagram illustrating the cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0075] Figure 20 This is a schematic diagram illustrating the cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0076] Figure 21 This is a schematic diagram illustrating the cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0077] Figure 22 This is a schematic diagram illustrating the cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0078] Figure 23 This is a flowchart illustrating a method for manufacturing a display substrate according to some exemplary embodiments of the present disclosure; and

[0079] Figures 24 to 28 They are Figure 23 A schematic diagram of the cross-sectional structure of the display substrate formed after some steps in the manufacturing method are performed. Detailed Implementation

[0080] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0081] It should be noted that, for clarity and / or descriptive purposes, the dimensions and relative dimensions of components may be enlarged in the accompanying drawings. Therefore, the dimensions and relative dimensions of the individual components are not necessarily limited to those shown in the drawings. In the specification and accompanying drawings, the same or similar reference numerals indicate the same or similar parts.

[0082] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0083] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0084] For ease of description, spatial relation terms, such as “above,” “below,” “left,” “right,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figure. It should be understood that spatial relation terms are intended to cover other orientations of the device in use or operation besides those described in the figure. For example, if the device in the figure were inverted, an element described as “below” or “under” other elements or features would be oriented “above” or “on top” other elements or features.

[0085] In this document, the terms “substantially,” “approximately,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” as used herein includes stated values ​​and indicates that a particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0086] It should be noted that in this paper, "same layer" refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same mask to pattern that film layer in a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. That is, multiple elements, components, structures, and / or portions located in the "same layer" are made of the same material and formed by the same single patterning process. Typically, multiple elements, components, structures, and / or portions located in the "same layer" have approximately the same thickness.

[0087] Those skilled in the art will understand that, unless otherwise stated herein, the terms “height” or “thickness” refer to the dimensions along the surface of each film layer disposed perpendicular to the display substrate, i.e., the dimensions along the light-emitting direction of the display substrate, or the dimensions along the normal direction of the display device.

[0088] This disclosure provides at least one display substrate. The display substrate includes: a substrate; a first semiconductor layer disposed on the substrate; and a second semiconductor layer disposed on the side of the first semiconductor layer away from the substrate. The display substrate further includes a plurality of thin-film transistors disposed on the substrate, the plurality of thin-film transistors including at least a first transistor, a second transistor, and a third transistor. Each of the plurality of thin-film transistors includes an active layer. The active layer of at least one of the first transistor and the second transistor comprises an oxide semiconductor material, the active layer of the third transistor comprises a polysilicon semiconductor material, the active layer of the third transistor is located on the first semiconductor layer, and the active layer of at least one of the first transistor and the second transistor is located on the second semiconductor layer. The first transistor and at least one of the second transistor have a dual-gate structure. In the embodiments of this disclosure, the active layer of at least one of the first transistor and the second transistor is formed using an oxide semiconductor material such as LTPO, and a dual-gate structure is adopted, thereby improving the display performance of the display panel.

[0089] Figure 1 This is a plan view of a display device according to some embodiments of the present disclosure. For example, the display device may be an OLED display device. (Refer to...) Figure 1 The display device 1000 may include a display panel 110, a gate driver 120, a data driver 130, a controller 140, and a voltage generator 150. For example, the display device 1000 may be an OLED display device. The display panel 110 may include an array substrate 100 and a plurality of pixels PX. The array substrate 100 may include a display area AA and a non-display area NA. The plurality of pixels PX are arranged in an array in the display area AA. The signal generated by the gate driver 120 can be applied to the pixel PX through a signal line, for example, a scan signal line GL. The signal generated by the data driver 130 can be applied to the pixel PX through a signal line, for example, a data line DL. For example, a first voltage VDD and a second voltage, for example, VSS, can be applied to the pixel PX. For example, the first voltage VDD may be higher than the second voltage, for example, VSS. Optionally, the first voltage, for example, VDD, can be applied to the anode of a light-emitting device (e.g., OLED), and the second voltage, for example, VSS, can be applied to the cathode of the light-emitting device, so that the light-emitting device can emit light.

[0090] For example, each pixel PX can include multiple sub-pixels, such as red sub-pixels, green sub-pixels, and blue sub-pixels, or it can include white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels.

[0091] Figure 2This is a plan view of a display substrate included in a display device according to some embodiments of the present disclosure. For example, the display substrate may be an array substrate for an OLED display panel.

[0092] Reference Figure 2 The display substrate may include a display area AA and a non-display area NA. For example, the display area AA and the non-display area NA may include multiple boundaries, such as... Figure 2 AAS1, AAS2, AAS3, and AAS4 are shown in the diagram. The display substrate may also include a driver located within the non-display area NA. For example, the driver may be located on at least one side of the display area AA. Figure 2 In the illustrated embodiment, the driving circuits are located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides can refer to the left and right sides of the display substrate (screen) as viewed by the human eye during display. The driver can be used to drive individual pixels in the display substrate for display. For example, the driver may include the gate driver 120 and data driver 130 described above. The data driver 130 is used to sequentially latch the input data according to a clock signal and convert the latched data into analog signals before inputting them to the data lines of the display substrate. The gate driver 120 is typically implemented by a shift register, which converts the clock signal into on / off voltages and outputs them to the scan signal lines of the display substrate, respectively.

[0093] It should be noted that, although Figure 2 The diagram shows the driver located on the left and right sides of the display area AA; however, embodiments of this disclosure are not limited thereto, and the driver circuit can be located at any suitable location outside the display area NA.

[0094] For example, the driver can employ GOA (Gate Driver on Array) technology. In GOA, the gate driving circuit is directly mounted on the array substrate, replacing an external driving chip. Each GOA unit acts as a first-stage shift register, with each stage connected to a gate line. The sequential output of turn-on voltages by each stage shift register enables line-by-line scanning of pixels. In some embodiments, each stage shift register can also be connected to multiple gate lines. This adapts to the trend towards higher resolution and narrower bezels in display substrates.

[0095] Reference Figure 2On the display substrate, a left-side GOA circuit DA1, multiple pixels P located in the display area AA, and a right-side GOA circuit DA2 are disposed. The left-side GOA circuit DA1 and the right-side GOA circuit DA2 are electrically connected to a display IC via signal lines, and the display IC controls the supply of GOA signals. The display IC is, for example, located on the lower side of the display substrate (in the direction of human eye viewing). The left-side GOA circuit DA1 and the right-side GOA circuit DA2 are also electrically connected to each pixel via signal lines (e.g., scan signal lines GL) to supply driving signals to each pixel.

[0096] Figure 3 The display substrate according to some embodiments of this disclosure is in Figure 2 The image shows a partial enlarged view of section I. It should be noted that the figure exemplarily shows the orthographic projection of a sub-pixel onto the substrate as a rounded rectangle; however, the embodiments of this disclosure are not limited to this. For example, the orthographic projection of a sub-pixel onto the substrate can be other shapes such as rectangle, hexagon, pentagon, square, or circle. Furthermore, the arrangement of the three sub-pixels in a pixel unit is not limited to... Figure 3 As shown in the diagram.

[0097] Combined with reference Figure 1 , Figure 2 and Figure 3 Each pixel unit PX may include multiple sub-pixels, such as a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For ease of understanding, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be described as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively; however, the embodiments of this disclosure are not limited thereto.

[0098] The plurality of sub-pixels are arranged in an array along the row direction X and the column direction Y on the substrate 1. It should be noted that, although the row direction X and the column direction Y are perpendicular to each other in the illustrated embodiment, the embodiments disclosed herein are not limited thereto.

[0099] It should be understood that in the embodiments of this disclosure, each sub-pixel includes a pixel driving circuit and a light-emitting device. For example, the light-emitting device may be an OLED light-emitting device, including a stacked anode, an organic light-emitting layer, and a cathode. The pixel driving circuit may include a plurality of thin-film transistors and at least one storage capacitor.

[0100] The structure of the pixel driving circuit will be described in detail below, taking the 7T1C pixel driving circuit as an example. However, the embodiments of this disclosure are not limited to the 7T1C pixel driving circuit. In the absence of conflict, other known pixel driving circuit structures can be applied to the embodiments of this disclosure.

[0101] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Figure 4 As shown, the pixel driving circuit may include multiple thin-film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light-emitting diode (OLED). The multiple thin-film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0102] The display substrate may also include multiple signal lines, such as: a scan signal line 61 for transmitting a scan signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (i.e., the scan signal of the previous row), a light emission control line 63 for transmitting a light emission control signal En, a data line 64 for transmitting a data signal Dm, a drive voltage line 65 for transmitting a drive voltage VDD, an initialization voltage line 66 for transmitting an initialization voltage Vint, and a power supply line 67 for transmitting a VSS voltage.

[0103] The gate G1 of the first transistor T1 is electrically connected to the reset signal line 62, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. Furthermore, the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3, as shown below. Figure 4 As shown, the drain D1 of the first transistor T1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected at node N1. The first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset signal line 62 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also called the initialization transistor.

[0104] The gate G2 of the second transistor T2 is electrically connected to the scan signal line 61, the source S2 of the second transistor T2 is electrically connected to node N3, and the drain D2 of the second transistor T2 is electrically connected to node N1. The second transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61, so as to electrically connect the gate G3 and drain D3 of the third transistor T3 to each other, thereby performing the diode connection of the third transistor T3.

[0105] The gate G3 of the third transistor T3 is electrically connected to node N1, the source S3 of the third transistor T3 is electrically connected to node N2, and the drain D3 of the third transistor T3 is electrically connected to node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. That is, the third transistor T3 is also called the driving transistor.

[0106] The gate G4 of the fourth transistor T4 is electrically connected to the scan signal line 61, the source S4 of the fourth transistor T4 is electrically connected to the data line 64, and the drain D4 of the fourth transistor T4 is electrically connected to node N2, that is, electrically connected to the source S3 of the third transistor T3. The fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3.

[0107] The gate G5 of the fifth transistor T5 is electrically connected to the light-emitting control line 63, and the source S5 of the fifth transistor T5 is electrically connected to the drive voltage line 65. Furthermore, the drain D5 of the fifth transistor T5 is electrically connected to node N2.

[0108] The gate G6 of the sixth transistor T6 is electrically connected to the light-emitting control line 63, the source S6 of the sixth transistor T6 is electrically connected to node N3, and the drain D6 of the sixth transistor T6 is electrically connected to node N4, i.e., electrically connected to the anode of the OLED. The fifth transistor T5 and the sixth transistor T6 are turned on concurrently (e.g., simultaneously) according to the light-emitting control signal En transmitted through the light-emitting control line 63 to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED.

[0109] The gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66.

[0110] One end of the storage capacitor Cst (hereinafter referred to as the first capacitor electrode) Cst1 is electrically connected to node N1, and the other end (hereinafter referred to as the second capacitor electrode) Cst2 is electrically connected to the drive voltage line 65.

[0111] The OLED's anode is electrically connected to node N4, and its cathode is electrically connected to power line 67 to receive a common voltage VSS. Accordingly, the OLED receives a drive current Id from the third transistor T3 to emit light, thereby displaying an image.

[0112] It should be noted that, in Figure 4In the present disclosure, each of the thin-film transistors T1, T2, T3, T4, T5, T6 and T7 is a p-channel field-effect transistor. However, the embodiments of the present disclosure are not limited thereto, and at least some of the thin-film transistors T1, T2, T3, T4, T5, T6 and T7 may be n-channel field-effect transistors.

[0113] During operation, in the initialization phase, a low-level reset control signal RESET is supplied via reset signal line 62. Subsequently, the first transistor T1 is turned on based on the low level of the reset control signal RESET, and the initialization voltage Vint from the initialization voltage line 66 is transmitted to the gate G1 of the third transistor T3 via the first transistor T1. Therefore, the third transistor T3 is initialized due to the initialization voltage Vint.

[0114] During the data programming phase, a low-level scan signal Sn is supplied through scan signal line 61. Subsequently, the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal Sn. Therefore, the third transistor T3 is placed in a diode-connected state and biased in the positive direction through the turned-on second transistor T2.

[0115] Subsequently, a compensation voltage Dm+Vth (e.g., Vth is negative) obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal Dm supplied via data line 64 is applied to the gate G3 of the third transistor T3. Then, the drive voltage VDD and the compensation voltage Dm+Vth are applied to the two terminals of the storage capacitor Cst, such that the charge corresponding to the voltage difference between the respective terminals is stored in the storage capacitor Cst.

[0116] During the light-emitting phase, the light-emitting control signal En from the light-emitting control line 63 changes from a high level to a low level. Subsequently, during the light-emitting phase, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light-emitting control signal En.

[0117] Subsequently, a drive current is generated based on the difference between the voltage at the gate G3 of the third transistor T3 and the drive voltage VDD. The drive current Id, corresponding to the difference between the drive current and the bypass current, is supplied to the OLED through the sixth transistor T6.

[0118] During the light-emitting phase, based on the current-voltage relationship of the third transistor T3, the gate-source voltage of the third transistor T3 is maintained at (Dm+Vth)-VDD due to the storage capacitor Cst. The drive current Id is related to (Dm-VDD). 2 Proportional. Therefore, the drive current Id is unaffected by variations in the threshold voltage Vth of the third transistor T3.

[0119] Figure 5This is a schematic diagram showing a planar structure of a pixel driving circuit for a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure. Figure 6 It is shown Figure 5 A schematic diagram of the planar structure of the first semiconductor layer of the pixel driving circuit shown. Figure 7 It is shown Figure 5 A schematic diagram of the planar structure of the first conductive layer of the pixel driving circuit shown. Figure 8 It is shown Figure 5 A schematic diagram of the planar structure of the second conductive layer of the pixel driving circuit shown. Figure 9 It is shown Figure 5 A schematic diagram of the planar structure of the second semiconductor layer of the pixel driving circuit shown. Figure 10 It is shown Figure 5 A schematic diagram of the planar structure of the third conductive layer of the pixel driving circuit shown. Figure 11 It is shown Figure 5 A schematic diagram of the planar structure of the fourth conductive layer of the pixel driving circuit shown. Figure 12 It is shown Figure 5 A schematic diagram of the planar structure of the fifth conductive layer of the pixel driving circuit shown. Figure 13 This illustrates the edge of a display substrate according to some exemplary embodiments of the present disclosure. Figure 5 A schematic diagram of the cross-sectional structure intercepted by lines AA' and BB' is shown below. For ease of description, the structure will be shown along... Figure 5 The cross-sectional structures cut by lines AA' and BB' are shown in the same schematic diagram.

[0120] Combined with reference Figures 5 to 13 The display substrate includes a substrate 10 and a plurality of film layers disposed on the substrate 10. In some embodiments, the plurality of film layers include at least a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70, and a fifth conductive layer 90. The first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60, the fourth conductive layer 70, and the fifth conductive layer 90 are disposed sequentially away from the substrate 10.

[0121] For example, the first semiconductor layer 20 can be formed of a semiconductor material such as low-temperature polycrystalline silicon, and its film thickness can be in the range of 400 to 800 angstroms, for example, 500 angstroms. The second semiconductor layer 50 can be formed of an oxide semiconductor material, such as polycrystalline silicon oxide semiconductor material like IGZO, and its film thickness can be in the range of 300 to 600 angstroms, for example, 400 angstroms. The first conductive layer 30 can be formed of a conductive material that forms the gate of the thin-film transistor, for example, the conductive material can be Mo, and its film thickness can be in the range of 2000 to 3000 angstroms, for example, 2500 angstroms. The second conductive layer 40 can be formed of a conductive material that forms the source and drain of the thin-film transistor, for example, the conductive material can include Ti, Al, etc. The second conductive layer 40 can have a stacked structure formed of Ti / Al / Ti, and its film thickness can be in the range of 7000 to 9000 angstroms. For example, when the second conductive layer 40 has a stacked structure formed of Ti / Al / Ti, the thickness of each Ti / Al / Ti layer can be approximately 500 angstroms, 5500 angstroms, and 500 angstroms, respectively. The third conductive layer 60 can be formed of a conductive material that forms the gate of the thin-film transistor, for example, Mo, and its film thickness can be in the range of 2000–3000 angstroms, such as 2500 angstroms. The fourth conductive layer 70 can be formed of a conductive material that forms the source and drain of the thin-film transistor, for example, Ti, Al, etc. The fourth conductive layer 70 can have a stacked structure formed of Ti / Al / Ti, and its film thickness can be in the range of 7000–9000 angstroms. For example, when the fourth conductive layer 70 has a stacked structure formed of Ti / Al / Ti, the thickness of each Ti / Al / Ti layer can be approximately 500 angstroms, 5500 angstroms, and 300 angstroms, respectively. The fifth conductive layer 90 can be formed of a conductive material that forms the source and drain of the thin film transistor, such as Ti, Al, etc., and the fourth conductive layer 70 can have a stacked structure formed of Ti / Al / Ti.

[0122] The display substrate includes scan signal lines 61, reset signal lines 62, light emission control lines 63, and initialization voltage lines 66 arranged along the row direction to apply scan signal Sn, reset control signal RESET, light emission control signal En, and initialization voltage Vint to sub-pixels respectively. The display substrate may also include data lines 64 and driving voltage lines 65 that intersect with scan signal lines 61, reset signal lines 62, light emission control lines 63, and initialization voltage lines 66 to apply data signal Dm and driving voltage VDD to sub-pixels respectively.

[0123] In conjunction with the above, regarding Figure 4According to the description, the pixel driving circuit of the display substrate may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and a storage capacitor Cst.

[0124] The first transistor T1 and the second transistor T2 can be along the following path: Figure 9 The second semiconductor layer shown is formed. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be formed along the path shown. Figure 6 The first semiconductor layer 20 shown is formed.

[0125] like Figure 6 As shown, the first semiconductor layer 20 may have a bent or folded shape, and may include a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

[0126] For example, the first semiconductor layer 20 may include polycrystalline silicon, such as low-temperature polycrystalline silicon. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may be undoped or have a different doping type than the source and drain regions, and therefore possess semiconductor characteristics. The source and drain regions are located on opposite sides of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0127] The third transistor T3 includes a third active layer 20c and a third gate G3. The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in opposite directions relative to the third channel region 201c.

[0128] The fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4. The fourth active layer 20d includes a fourth source region 203d, a fourth drain region 205d, and a fourth channel region 201d connecting the fourth source region 203d and the fourth drain region 205d. The fourth source region 203d and the fourth drain region 205d extend in opposite directions relative to the fourth channel region 201d.

[0129] The fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5. The fifth active layer 20e includes a fifth source region 203e, a fifth drain region 205e, and a fifth channel region 201e connecting the fifth source region 203e and the fifth drain region 205e. The fifth source region 203e and the fifth drain region 205e extend in opposite directions relative to the fifth channel region 201e.

[0130] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6. The sixth active layer 20f includes a sixth source region 203f, a sixth drain region 205f, and a sixth channel region 201f connecting the sixth source region 203f and the sixth drain region 205f. The sixth source region 203f and the sixth drain region 205f extend in opposite directions relative to the sixth channel region 201f.

[0131] The seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7. The seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g connecting the seventh source region 203g and the seventh drain region 205g. The seventh source region 203g and the seventh drain region 205g extend in opposite directions relative to the seventh channel region 201g.

[0132] like Figure 7 As shown, scan signal line 61, reset signal line 62, and light emission control line 63 are all located in the first conductive layer 30. Gate structure CG1 is also located in the first conductive layer 30. The portion of gate structure CG1 overlapping with the first semiconductor layer 20 forms the third gate G3 of the third transistor T3. The portion of scan signal line 61 overlapping with the first semiconductor layer 20 forms the fourth gate G4 of the fourth transistor T4. The portion of light emission control line 63 overlapping with the first semiconductor layer 20 forms the fifth gate G5 of the fifth transistor T5. Another portion of light emission control line 63 overlapping with the first semiconductor layer 20 forms the sixth gate G6 of the sixth transistor T6. The portion of reset signal line 62 overlapping with the first semiconductor layer 20 forms the seventh gate G7 of the seventh transistor T7. Gate structure CG1 also forms part of a first capacitor structure, such as a capacitor electrode (e.g., the first capacitor electrode Cst1) of a storage capacitor Cst. That is, gate structure CG1 serves simultaneously as the gate of the third transistor T3 and an electrode of the storage capacitor Cst.

[0133] like Figure 8 As shown, the second conductive layer 40 includes a first bottom gate structure BG1, a second bottom gate structure BG2, and a second capacitor structure CP2. The initialization voltage line 66 is also located in the second conductive layer 40.

[0134] Continue to refer to Figure 8The second conductive layer 40 includes a via 40H, which is formed in the second capacitor structure CP2.

[0135] like Figure 9 As shown, the second semiconductor layer 50 includes a first active layer 20a corresponding to the first transistor T1 and a second active layer 20b corresponding to the second transistor T2. For example, the first active layer 20a of the first transistor T1 and the second active layer 20b of the second transistor T2 extend in the same direction as the data line, that is, they both extend in the vertical direction shown in the figure.

[0136] For example, the second semiconductor layer 50 may include an oxide semiconductor material, such as low-temperature polycrystalline silicon oxide semiconductor material (LTPO). The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may be undoped or have a different doping type than the source and drain regions, and therefore possess semiconductor characteristics. The source and drain regions are located on opposite sides of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0137] The first active layer 20a of the first transistor T1 includes a first source region 203a, a first drain region 205a, and a first channel region 201a connecting the first source region 203a and the first drain region 205a. The first source region 203a and the first drain region 205a extend in opposite directions relative to the first channel region 201a.

[0138] The second active layer 20b of the second transistor T2 includes a second source region 203b, a second drain region 205b, and a second channel region 201b connecting the second source region 203b and the second drain region 205b. The second source region 203b and the second drain region 205b extend in opposite directions relative to the second channel region 201b.

[0139] Combined with reference Figure 5 , Figure 8 and Figure 9 The orthographic projection of the first active layer 20a on the substrate 10 at least partially overlaps with the orthographic projection of the first bottom gate structure BG1 on the substrate 10. The overlapping portion of the first bottom gate structure BG1 and the first active layer 20a constitutes the first bottom gate G11 of the first transistor T1.

[0140] The orthographic projection of the second active layer 20b on the substrate 10 at least partially overlaps with the orthographic projection of the second bottom gate structure BG2 on the substrate 10. The overlapping portion of the second bottom gate structure BG2 and the second active layer 20b constitutes the second bottom gate G21 of the second transistor T2.

[0141] For example, continue to refer to Figure 8 and Figure 9 The first bottom gate structure BG1 includes a first bottom gate body portion BG11 and a first bottom gate extension portion BG12. The orthographic projection of the first bottom gate body portion BG11 onto the substrate 10 is rectangular. The orthographic projection of the first bottom gate body portion BG11 onto the substrate 10 at least partially overlaps with the orthographic projection of the active layer of the first transistor T1 onto the substrate 10, and the first bottom gate BG11 includes the portion where the first bottom gate body portion BG11 overlaps with the active layer of the first transistor T1.

[0142] The second bottom gate structure BG2 includes a second bottom gate body portion BG21 and a second bottom gate extension portion BG22. The orthographic projection of the second bottom gate body portion BG21 onto the substrate 10 is rectangular. The orthographic projection of the second bottom gate body portion BG21 onto the substrate 10 at least partially overlaps with the orthographic projection of the active layer of the second transistor T2 onto the substrate 10, and the second bottom gate BG21 includes the portion where the second bottom gate body portion BG21 overlaps with the active layer of the second transistor T2.

[0143] In the embodiment shown in the figure, both the first bottom gate extension BG12 and the second bottom gate extension BG22 extend in the row direction, that is, in the left-right direction shown in the figure. That is, the extension directions of the first bottom gate extension BG12 and the second bottom gate extension BG22 are approximately parallel to the extension direction of the initialization voltage line 66.

[0144] Reference Figure 9 The second semiconductor layer 50 also includes a third capacitor structure CP3. The third capacitor structure CP3 comprises a portion of the conductive second semiconductor layer 50. For example, after forming a second semiconductor layer 50 such as IGZO, it can be H-doped with SiH4 in the film-forming gas to reduce its resistivity, thereby forming a portion of the conductive second semiconductor layer 50 to form the third capacitor structure CP3.

[0145] Combined with reference Figure 5 , Figure 7 , Figure 8 and Figure 9 as well as Figure 13A first capacitor structure CG1, a second capacitor structure CP2, and a third capacitor structure CP3 are spaced apart and disposed opposite to each other. The orthographic projections of the first capacitor structure CG1, the second capacitor structure CP2, and the third capacitor structure CP3 on the substrate 10 at least partially overlap each other. The first capacitor structure CG1 is electrically connected to the third capacitor structure CP3 through a conductive plug formed in a through-hole 40H. Thus, the first capacitor structure CG1 and the third capacitor structure CP3, electrically connected to each other, form the first capacitor electrode Cst1 of the storage capacitor. The second capacitor structure CP2 is located between the first capacitor structure CG1 and the third capacitor structure CP3, forming the second capacitor electrode Cst2 of the storage capacitor. (Refer to reference...) Figure 4 The first capacitor electrode Cst1 can be electrically connected to node N1, and the second capacitor electrode Cst2 can be electrically connected to VDD, thus forming a storage capacitor between the first capacitor electrode Cst1 and the second capacitor electrode Cst2. In this way, capacitors can be formed between the first capacitor structure CG1 and the second capacitor structure CP2, and between the second capacitor structure CP2 and the third capacitor structure CP3, respectively. The sum of the capacitance values ​​of the two capacitors equals the capacitance value of the storage capacitor. In other words, this method helps to increase the capacitance value of the storage capacitor, thereby improving the performance of the pixel driving circuit.

[0146] like Figure 10 As shown, the third conductive layer 60 includes a first top gate structure TG1 and a second top gate structure TG2.

[0147] The orthographic projection of each of the first active layer 20a and the first bottom gate structure BG1 onto the substrate 10 at least partially overlaps with the orthographic projection of the first top gate structure TG1 onto the substrate 10. The overlapping portion of the first top gate structure TG1 and the first active layer 20a constitutes the first top gate G12 of the first transistor T1. (Refer to reference...) Figure 13 In the direction perpendicular to the upper surface of the substrate 10 (i.e. along) Figure 12 (As shown in the vertical direction), the first active layer 20a is located between the first bottom gate G11 and the first top gate G12. Thus, the first transistor T1 has a dual-gate structure.

[0148] Continue to refer to Figure 10 The first top gate structure TG1 along Figure 10The first top gate structure TG1 extends horizontally. It may include a first widened portion TG11, the vertical dimension of which is larger than the vertical dimension of the remaining portion of the first top gate structure TG1. The orthographic projection of the first widened portion TG11 onto the substrate 10 at least partially overlaps with the orthographic projection of the active layer 20a of the first transistor T1 onto the substrate 10. The first top gate G12 includes the portion where the first widened portion TG11 overlaps with the active layer 20a of the first transistor T1.

[0149] The orthographic projection of each of the second active layer 20b and the second bottom gate structure BG2 onto the substrate 10 at least partially overlaps with the orthographic projection of the second top gate structure TG2 onto the substrate 10. The overlapping portion of the second top gate structure TG2 and the second active layer 20b constitutes the second top gate G22 of the second transistor. (Refer to reference...) Figure 12 In the direction perpendicular to the upper surface of the substrate 10 (i.e. along) Figure 12 (As shown in the vertical direction), the second active layer 20b is located between the second bottom gate G21 and the second top gate G22. Thus, the second transistor T2 has a dual-gate structure.

[0150] Continue to refer to Figure 10 The second top grid structure TG2 along Figure 10 The second top gate structure TG2 extends horizontally. The second top gate structure TG2 may include a second widened portion TG21, the vertical dimension of which is larger than the vertical dimension of the remaining portion of the second top gate structure TG2. The orthographic projection of the second widened portion TG21 onto the substrate 10 at least partially overlaps with the orthographic projection of the active layer 20b of the second transistor T2 onto the substrate 10. The second top gate G22 includes the portion where the second widened portion TG21 overlaps with the active layer 20b of the second transistor T2.

[0151] like Figure 11 As shown, the fourth conductive layer 70 includes a driving voltage line 65, a first conductive component 701, a second conductive component 702, a third conductive component 703, a fourth conductive component 704, and a fifth conductive component 705.

[0152] The driving voltage line 65 is electrically connected to the source region 203e of the fifth transistor T5 through the via VAH12. The overlapping portion of the driving voltage line 65 and the source region 203e of the fifth transistor T5 constitutes the source of the fifth transistor T5.

[0153] One end of the first conductive component 701 is electrically connected to the source region 203a of the first transistor T1 through via VAH2. A portion of the first conductive component 701 is also electrically connected to the initialization voltage line 66 through via VAH3. The other end of the first conductive component 701 is electrically connected to the first conductive member 401 through via VAH4. In this way, the source of the first transistor T1 is electrically connected to the drain of the seventh transistor T7, and both are electrically connected to the initialization voltage line 66. Thus, the initialization voltage Vint can be applied to the source of the first transistor T1 and the drain of the seventh transistor T7.

[0154] One end of the second conductive component 702 is electrically connected to the drain region 205b of the second transistor T2 through via VAH7. The other end of the second conductive component 702 is electrically connected to the drain region 203a of the first transistor T1 and the third conductive component 703 through via VAH6. One end of the third conductive component 703 is electrically connected to the second conductive component 702 through via VAH6. The other end of the third conductive component 703 is electrically connected to the gate G1 of the third transistor T3 and the first capacitor electrode Cst1 through via VAH8, thus forming... Figure 4 Node N1 in the diagram. This allows for the electrical connection between the drain of the first transistor T1, the drain of the second transistor T2, the gate of the third transistor T3, and the first capacitor electrode Cst1, as shown in the diagram. Figure 4 All are electrically connected to node N1.

[0155] One end of the fourth conductive component 704 is electrically connected to the source region 203b of the second transistor T2 through via VAH9, and the other end of the fourth conductive component 704 is electrically connected to the source region 203b of the sixth transistor T6 through via VAH10. This achieves an electrical connection between the source of the second transistor T2 and the source of the sixth transistor T6. (Refer to...) Figure 4 All are electrically connected to node N3.

[0156] One end of the fifth conductive member 705 is electrically connected to the drain region 205f of the sixth transistor T6 and the source region 203g of the seventh transistor T7 through via VAH13, and the other end is electrically connected to the first electrode (e.g., the anode, described below) of the light-emitting device through via VAH14. This allows for the electrical connection between the drain of the sixth transistor T6, the source of the seventh transistor T7, and the first electrode of the light-emitting device, as described below. Figure 4 All are electrically connected to node N4.

[0157] like Figure 12 As shown, the fifth conductive layer 90 includes a data line 64 and a light-shielding layer 902.

[0158] Data line 64 is electrically connected to the source region 203d of the fourth transistor T4 through via VAH1 to apply the data signal Dm to the source of the fourth transistor T4. That is, the overlapping portion of data line 64 and the source region 203d of the fourth transistor T4 constitutes the source of the fourth transistor T4.

[0159] The orthographic projection of the light-shielding layer 902 onto the substrate 10 covers the orthographic projections of each of the first transistor T1 and the second transistor T2 onto the substrate 10. For example, the orthographic projection of the light-shielding layer 902 onto the substrate 10 covers the orthographic projections of each of the active layers 20a of the first transistor T1 and the active layers 20b of the second transistor T2 onto the substrate 10. By designing the light-shielding layer 902, the active layers 20a of the first transistor T1 and 20b of the second transistor T2 can be protected from the influence of external light, which is beneficial to maintaining the performance stability of the first and second transistors.

[0160] For example, the light-shielding layer 902 can be electrically connected to a fixed voltage to prevent its potential from being floating, thereby avoiding any adverse effects of the light-shielding layer on the transistor's performance. For example, the light-shielding layer 902 can be electrically connected to the second capacitor electrode Cst2 through the via VAH15, that is, electrically connected to the VDD voltage.

[0161] In embodiments of this disclosure, the active layers of both the first transistor T1 and the second transistor T2 are formed using an oxide semiconductor material such as LTPO, which can improve the performance of node N1 in the pixel driving circuit (e.g., Figure 4 The voltage stability at the point shown is improved, thereby enhancing the display performance of the display panel. Furthermore, both the first transistor T1 and the second transistor T2 have a dual-gate structure, which improves the stability of the first transistor T1 and the second transistor T2, as well as the uniformity of the threshold voltage (Vth), thereby further improving the performance of the display panel.

[0162] It should also be noted that in the embodiments disclosed herein, the bottom gates G11 and G21 of transistors T1 and T2 serve not only as bottom gates but also as light-shielding layers, which can prevent external light from interfering with the active layers 20a and 20b of transistors T1 and T2, thus further improving the performance of the transistors.

[0163] Figure 14 This is a schematic diagram illustrating a planar structure of a display substrate according to some exemplary embodiments of the present disclosure, wherein the planar structure of the first electrode of the light-emitting device is schematically shown. Figure 15 This is a schematic diagram illustrating the cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure.

[0164] For example, the light-emitting device may be an organic light-emitting diode (OLED), which may include a first electrode, an organic light-emitting layer, and a second electrode disposed on the substrate 10. The first electrode may be one of an anode and a cathode, and the second electrode may be the other of an anode and a cathode. The first electrode, the organic light-emitting layer, and the second electrode may be disposed sequentially away from the substrate 10.

[0165] like Figure 14 As shown, the first electrode 80 may include an electrode body portion 801 and an electrode connection portion 802. Figure 13 In the illustrated embodiment, the electrode body 801 may have a generally rectangular shape, that is, the orthographic projection of the electrode body 801 onto the substrate 10 is generally rectangular. However, the embodiments of this disclosure are not limited thereto, and the electrode body 801 may have any suitable shape, such as hexagonal, octagonal, etc.

[0166] The electrode body 801 and the electrode connection 802 can be connected as a single unit. The electrode connection 802 is electrically connected to one end of the fifth conductive component 705 through a via VAH14. As described above, the other end of the fifth conductive component 705 is electrically connected to the drain of the sixth transistor T6 and the source of the seventh transistor T7 through a via VAH13. In this way, the first electrode 80 is electrically connected to the drain of the sixth transistor T6 and the source of the seventh transistor T7.

[0167] For example, the orthographic projection of the first electrode 80 on the substrate 10 at least covers the orthographic projection of the active layer 20a of the first transistor T1 on the substrate 10. The orthographic projection of the first electrode 80 on the substrate 10 is spaced apart from the orthographic projection of the active layer 20b of the second transistor T2 on the substrate 10.

[0168] Below, we will combine Figure 13 and Figure 15 Other film layers (e.g., insulating layers) of the display substrate according to embodiments of this disclosure are described.

[0169] In an exemplary embodiment, the display substrate may include a barrier layer 161 disposed on a substrate 10; and a first buffer layer 162 disposed on the side of the barrier layer 161 away from the substrate 10.

[0170] For example, the barrier layer 161 may be formed of silicon oxide and have a thickness of approximately 5,500 angstroms. The first buffer layer 162 may be formed of silicon nitride and have a thickness of approximately 1,000 angstroms; or, the first buffer layer 162 may be composed of a stack of silicon nitride and silicon oxide. For example, the first buffer layer 162 may include a first buffer sublayer disposed on the barrier layer 161 and a second buffer sublayer disposed on the side of the first buffer sublayer away from the substrate 10, the first buffer sublayer comprising silicon nitride material and the second buffer sublayer comprising silicon oxide material.

[0171] The display substrate may include a first gate insulating layer GI1 disposed between the first semiconductor layer 20 and the first conductive layer 30. For example, the first gate insulating layer GI1 may be formed of silicon oxide.

[0172] The display substrate may include a second gate insulating layer GI2 disposed between the first conductive layer 30 and the second conductive layer 40. For example, the second gate insulating layer GI2 may be formed of silicon nitride. In this way, the second gate insulating layer GI2 formed of silicon nitride can supplement hydrogen (H) to the first transistor to improve the performance of the first transistor.

[0173] The display substrate may include a second buffer layer 163 disposed between the second gate insulating layer GI2 and the second conductive layer 40. For example, the second buffer layer 163 may be formed of silicon nitride or silicon oxide.

[0174] The display substrate may include a third gate insulating layer GI3 disposed between the second conductive layer 40 and the second semiconductor layer 50. For example, the third gate insulating layer GI3 may be formed of silicon oxide. In this way, the third gate insulating layer GI3 formed of silicon oxide can block hydrogen (H) from penetrating into the oxide semiconductor transistors (i.e., T1, T2) to improve the performance of the oxide semiconductor transistors (i.e., T1, T2).

[0175] The display substrate may include a fourth gate insulating layer GI4 disposed between the second semiconductor layer 50 and the third conductive layer 60. For example, the fourth gate insulating layer GI4 may be formed of silicon oxide. In this way, the fourth gate insulating layer GI4 formed of silicon oxide can block hydrogen (H) from penetrating into the oxide semiconductor transistors (i.e., T1, T2) to improve the performance of the oxide semiconductor transistors (i.e., T1, T2).

[0176] In embodiments of this disclosure, the first active layer 20a is close to the surface of the substrate 10 (e.g., Figure 13 The lower surface of the first active layer 20a) and the surface of the first bottom gate G11 away from the substrate 10 (e.g., the surface of the first active layer 20a) and the surface of the first bottom gate G11 away from the substrate 10. Figure 13 The distance between the upper surface of the first bottom gate G11 and the first active layer 20a is greater than the surface of the first active layer 20a away from the substrate (e.g., the surface of the first active layer 20a away from the substrate). Figure 13The upper surface of the first active layer 20a) and the surface of the first top gate G12 near the substrate 10 (e.g.) Figure 13 The distance between the lower surfaces of the first top gate G12 and the middle gate.

[0177] For example, the first active layer 20a is close to the surface of the substrate 10 (e.g. Figure 13 The lower surface of the first active layer 20a) and the surface of the first bottom gate G11 away from the substrate 10 (e.g., the surface of the first active layer 20a) and the surface of the first bottom gate G11 away from the substrate 10. Figure 13 The distance between the upper surface of the first bottom gate G11 and the first active layer 20a can be in the range of 3000 to 6000 angstroms, such as 3500 angstroms, 4000 angstroms, or 4500 angstroms. The first active layer 20a is located away from the surface of the substrate (e.g., the surface of the substrate). Figure 13 The upper surface of the first active layer 20a) and the surface of the first top gate G12 near the substrate 10 (e.g.) Figure 13 The distance between the lower surfaces of the first top grid G12 can be in the range of 1000 to 2000 angstroms, such as 1300 angstroms or 1500 angstroms.

[0178] In embodiments of this disclosure, the first active layer 20a is close to the surface of the substrate 10 (e.g., Figure 13 The lower surface of the first active layer 20a) and the surface of the first bottom gate G11 away from the substrate 10 (e.g., the surface of the first active layer 20a) and the surface of the first bottom gate G11 away from the substrate 10. Figure 13 The distance between the upper surface of the first bottom gate G11 is greater than the distance between the surface of the third active layer 20c away from the substrate 10 and the surface of the third gate G3 near the substrate 10.

[0179] For example, the distance between the surface of the third active layer 20c away from the substrate 10 and the surface of the third gate G3 near the substrate 10 can be in the range of 1000 to 2000 angstroms, such as 1300 angstroms or 1500 angstroms.

[0180] In embodiments of this disclosure, the first active layer 20a is located away from the surface of the substrate (e.g., Figure 13 The upper surface of the first active layer 20a) and the surface of the first top gate G12 near the substrate 10 (e.g.) Figure 13 The distance between the lower surface of the first top gate G12 and the third active layer 20c (away from the substrate 10) is approximately equal to the distance between the surface of the third active layer 20c away from the substrate 10 and the surface of the third gate G3 (close to the substrate 10).

[0181] The display substrate may include an interlayer insulating layer (ILD) disposed between the third conductive layer 60 and the fourth conductive layer 70, and between the second semiconductor layer 50 and the fourth conductive layer 70. For example, the ILD may be formed of a single layer of silicon oxide, or it may be formed of a stacked structure of silicon oxide and silicon nitride. For example, the ILD may include a first interlayer insulator layer formed of silicon oxide and a second interlayer insulator layer formed of silicon nitride, wherein the first interlayer insulator layer is closer to the substrate 10 than the second interlayer insulator layer.

[0182] In embodiments of this disclosure, in transistors with a dual-gate structure, for example, in the first transistor T1, only a third gate insulating layer GI3 is disposed between the bottom gate G11 and the active layer 20a, without any other insulating layers. This reduces the distance between the bottom gate G11 and the active layer 20a, which is beneficial for forming a good dual-gate drive in the first transistor, improving the transistor's driving capability, and thus enhancing the transistor's carrier mobility and electrical reliability. It should be understood that the second transistor T2 also has the same structure and effects.

[0183] Figure 16 This is a schematic diagram illustrating the planar structure of a pixel driving circuit for a sub-pixel of a display substrate according to some other exemplary embodiments of the present disclosure. Figure 17 It is shown Figure 16 A schematic diagram of the planar structure of the second semiconductor layer of the pixel driving circuit shown. Figure 18 It is shown Figure 16 A schematic diagram of the planar structure of the third conductive layer of the pixel driving circuit shown.

[0184] It should be noted that the following will mainly describe Figure 16 The display substrate in the illustrated embodiment differs from the display substrates in the above embodiments in that other structures can refer to the structure of the display substrates in the above embodiments.

[0185] Similarly, as Figure 16 As shown, the display substrate includes a substrate 10 and a plurality of film layers disposed on the substrate 10. In some embodiments, the plurality of film layers include at least a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70, and a fifth conductive layer 90. The first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60, the fourth conductive layer 70, and the fifth conductive layer 90 are disposed sequentially away from the substrate 10. The first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the fourth conductive layer 70, and the fifth conductive layer 90 can be referred to the description above.

[0186] like Figure 17 As shown, the second semiconductor layer 50' includes a first active layer 20a corresponding to the first transistor T1 and a second active layer 20b corresponding to the second transistor T2. For example, the first active layer 20a of the first transistor T1 and the second active layer 20b of the second transistor T2 extend in the same direction as the data line, that is, they both extend in the vertical direction shown in the figure.

[0187] The third conductive layer 60' includes a first top gate structure TG1 and a second top gate structure TG2.

[0188] The first active layer 20a, the second active layer 20b, the first top gate structure TG1, and the second top gate structure TG2 can be referred to the description above, and will not be repeated here.

[0189] In this embodiment, the third capacitor structure CP3 is formed in the third conductive layer 60', and not in the second semiconductor layer 50'. Figure 18 As shown, the third conductive layer 60' includes a third capacitor structure CP3.

[0190] Figure 19 This is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure. (See reference 1) Figures 16 to 19 A first capacitor structure CG1, a second capacitor structure CP2, and a third capacitor structure CP3 are spaced apart and disposed opposite to each other. The orthographic projections of the first capacitor structure CG1, the second capacitor structure CP2, and the third capacitor structure CP3 on the substrate 10 at least partially overlap each other. The first capacitor structure CG1 is electrically connected to the third capacitor structure CP3 through a conductive plug formed in a through-hole 40H. Thus, the first capacitor structure CG1 and the third capacitor structure CP3, electrically connected to each other, form the first capacitor electrode Cst1 of the storage capacitor. The second capacitor structure CP2 is located between the first capacitor structure CG1 and the third capacitor structure CP3, forming the second capacitor electrode Cst2 of the storage capacitor. (Refer to reference...) Figure 4The first capacitor electrode Cst1 can be electrically connected to node N1, and the second capacitor electrode Cst2 can be electrically connected to VDD, thus forming a storage capacitor between the first capacitor electrode Cst1 and the second capacitor electrode Cst2. In this way, capacitors can be formed between the first capacitor structure CG1 and the second capacitor structure CP2, and between the second capacitor structure CP2 and the third capacitor structure CP3, respectively, and the sum of the capacitance values ​​of the two capacitors equals the capacitance value of the storage capacitor. In the embodiments of this disclosure, a second gate insulating layer GI2 and a second buffer layer 163 are provided between the first capacitor structure CG1 and the second capacitor structure CP2. A third gate insulating layer GI3 and a fourth gate insulating layer GI4 are provided between the second capacitor structure CP2 and the third capacitor structure CP3. In this way, a storage capacitor with an increased capacitance value is formed. That is, this method is beneficial for increasing the capacitance value of the storage capacitor, thereby improving the performance of the pixel driving circuit.

[0191] Figure 20 This is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure. Figure 20 In the illustrated embodiment, the second buffer layer 163 is removed. A third gate insulating layer GI3 is provided between the bottom gate (e.g., G11 or G21) of the transistor and the active layer (20a or 20b). This third gate insulating layer GI3 comprises silicon oxide material and can prevent hydrogen (H) from penetrating into the channel region of the transistor.

[0192] Reference Figure 20 Between the first capacitor structure CG1 and the second capacitor structure CP2, only a second gate insulating layer GI2 is provided. This reduces the distance between the first capacitor structure CG1 and the second capacitor structure CP2, thus increasing the capacitance value of the capacitor formed between them, thereby increasing the overall capacitance value of the storage capacitor.

[0193] Figure 21 This is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure. Figure 21 In the illustrated embodiment, the third gate insulating layer GI3 between the second capacitor structure CP2 and the third capacitor structure CP3 is removed; that is, only the fourth gate insulating layer GI4 is provided between the second capacitor structure CP2 and the third capacitor structure CP3. This reduces the distance between the second capacitor structure CP2 and the third capacitor structure CP3, thus increasing the capacitance value of the capacitor formed between them, thereby further increasing the overall capacitance value of the storage capacitor.

[0194] Figure 22This is a schematic diagram illustrating a cross-sectional structure of a display substrate according to some exemplary embodiments of the present disclosure. Figure 22 In the illustrated embodiment, the fourth conductive layer 70 may have a stacked structure. For example, the fourth conductive layer 70 may include a first conductive sublayer 70A and a second conductive sublayer 70B. The first conductive sublayer 70A is disposed on the interlayer insulating layer (ILD), and the second conductive sublayer 70B is disposed on the side of the first conductive sublayer 70A away from the substrate 10, and the first conductive sublayer 70A and the second conductive sublayer 70B are in contact with each other.

[0195] For example, the material of the first conductive sublayer 70A may include Mo, or it may include Ti, Al, etc. The material of the second conductive sublayer 70B may be formed of a conductive material that forms the source and drain of a thin-film transistor, such as Ti, Al, etc.

[0196] Figure 23 This is a flowchart of a method for manufacturing a display substrate according to some exemplary embodiments of the present disclosure. Figures 24 to 28 They are Figure 23 A schematic diagram of the cross-sectional structure of the display substrate formed after some steps in the manufacturing method are performed. (Refer to reference...) Figures 22 to 28 The manufacturing method of the display substrate can be performed according to the following steps.

[0197] Reference Figure 24 In step S231, a substrate 10 is prepared. For example, the substrate 10 can be an organic flexible substrate formed from materials such as polyimide (PI), polyethylene terephthalate (PET), polycarbonate, polyethylene, polyacrylate, polyetherimide, or polyethersulfone. The substrate 10 can be a single-layer structure or a double-layer structure. For example, the substrate 10 may include a first substrate, a first barrier layer, and a second substrate, with the first barrier layer disposed between the first and second substrates. The thickness of the substrate 10 is approximately in the range of 5 to 20 micrometers.

[0198] Then, a barrier layer 161, a first buffer layer 162, a first semiconductor layer 20, a first gate insulating layer GI1, a first conductive layer 30, a second gate insulating layer GI2, a second conductive layer 40, a third gate insulating layer GI3, a second semiconductor layer 50, a fourth gate insulating layer GI4, a third conductive layer 60, and an interlayer insulating layer IDL are sequentially fabricated on the substrate 10.

[0199] Reference Figure 25 In step S232, a plurality of vias VA1 and VA2 are formed in the interlayer insulating layer IDL. The plurality of vias VA1 and VA2 penetrate the interlayer insulating layer IDL to expose the source region and drain region of the active layer of the oxide semiconductor transistor (i.e., the first transistor and the second transistor mentioned above), respectively.

[0200] Reference Figure 26 In step S233, a first conductive material layer CL1 is deposited on the side of the interlayer insulating layer IDL away from the substrate 10. For example, the first conductive material layer CL1 may include Mo. The first conductive material layer CL1 may fill the plurality of vias VA1, VA2 to contact the source and drain regions of the active layer of the first transistor or the second transistor.

[0201] Reference Figure 27 In step S234, a plurality of vias VA3 and VA4 are formed. Each of the plurality of vias VA3 and VA4 penetrates the first conductive material layer CL1, the interlayer insulating layer IDL, the third gate insulating layer GI3, the second gate insulating layer GI2 and the first gate insulating layer GI1, so as to expose the source region and drain region of the active layer of the polysilicon semiconductor transistor (i.e. the third to seventh transistors mentioned above).

[0202] In this step, the plurality of vias VA3 and VA4 are formed by dry etching, and then cleaning is required using an etching solution. Under the protection of the first conductive material layer CL1, the etching solution will not damage the interlayer insulating layer IDL and the active layers of the oxide semiconductor transistor (i.e., the active layers 20a and 20b).

[0203] Reference Figure 28 In step S235, a second conductive material layer CL2 is deposited on the side of the first conductive material layer CL1 away from the substrate 10. For example, the second conductive material layer CL2 may include Ti, Al, etc. The second conductive material layer CL2 is stacked on the first conductive material layer CL1 and also fills the plurality of vias VA3 and VA4 to contact the source and drain regions of the active layer of the polysilicon semiconductor transistor.

[0204] Reference Figure 22 In step S236, the first conductive material layer CL1 and the second conductive material layer CL2 are patterned through a single patterning process to form the source and drain of multiple transistors. This reduces the number of patterning processes, thereby saving the number of photomasks.

[0205] Reference Figure 1 At least some embodiments of this disclosure also provide a display device. The display device may include the display substrate described above.

[0206] The display device may include any device or product with display functionality. For example, the display device may be a smartphone, mobile phone, e-book reader, desktop computer (PC), laptop PC, netbook PC, personal digital assistant (PDA), portable multimedia player (PMP), digital audio player, mobile medical device, camera, wearable device (e.g., head-mounted device, electronic clothing, electronic bracelet, electronic necklace, electronic accessory, electronic tattoo, or smartwatch), television set, etc.

[0207] It should be understood that the display panel and display device according to the embodiments of this disclosure have all the features and advantages of the display substrate described above, which can be found in the above description and will not be repeated here.

[0208] While some embodiments of the overall technical concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein, The display substrate comprises: a substrate substrate; and a first transistor disposed on the substrate substrate, wherein the first transistor comprises a first active layer, a first bottom gate and a first top gate, the first bottom gate is located between the substrate substrate and the first active layer, the first top gate is located on a side of the first active layer away from the substrate substrate, the orthogonal projections of any two of the first active layer, the first bottom gate and the first top gate on the substrate substrate at least partially overlap with each other, a third gate insulating layer is disposed between the first bottom gate and the first active layer, the first active layer comprises an oxide semiconductor material, the third gate insulating layer comprises a silicon oxide material, the surface of the first top gate away from the substrate substrate is in direct contact with the silicon oxide material, and the surface of the first active layer close to the substrate substrate is in direct contact with the silicon oxide material; The display substrate comprises a storage capacitor, the storage capacitor comprises a first capacitor structure, a second capacitor structure and a third capacitor structure disposed on the substrate substrate, the third capacitor structure is located on a side of the first capacitor structure away from the substrate substrate, the second capacitor structure is located between the first capacitor structure and the third capacitor structure, and the orthogonal projections of any two of the first capacitor structure, the second capacitor structure and the third capacitor structure on the substrate substrate at least partially overlap; The first capacitor structure and the third capacitor structure are electrically connected to each other to form a first capacitor electrode of the storage capacitor, and the second capacitor structure forms a second capacitor electrode of the storage capacitor; The display substrate comprises a first conductive layer disposed on the substrate substrate, and further comprises a third transistor, the third transistor comprises a third gate electrode, and the first capacitor structure and the third gate electrode of the third transistor are both located on the first conductive layer; The display substrate comprises a second conductive layer and a second semiconductor layer disposed on the substrate substrate, the second conductive layer is located between the first conductive layer and the second semiconductor layer, and the first bottom gate and the second capacitor structure are both located on the second conductive layer; The display substrate comprises a third conductive layer disposed on the substrate substrate, and the third conductive layer is located on a side of the second semiconductor layer away from the substrate substrate; The first top gate and the third capacitor structure are both located on the third conductive layer, or the first active layer and the third capacitor structure are both located on the second semiconductor layer. 2.The display substrate of claim 1, wherein, The display substrate comprises: a first semiconductor layer disposed on the substrate substrate; and a second semiconductor layer disposed on a side of the first semiconductor layer away from the substrate substrate, wherein the third transistor comprises a third active layer, the third active layer comprises a polysilicon semiconductor material, the third active layer is located on the first semiconductor layer, and the first active layer is located on the second semiconductor layer. 3.The display substrate of claim 2, wherein, The distance between the surface of the substrate base plate close to the first active layer and the surface of the substrate base plate away from the first bottom gate is greater than the distance between the surface of the substrate base plate away from the first active layer and the surface of the substrate base plate close to the first top gate. 4.The display substrate of claim 2, wherein, The distance between the surface of the substrate base plate close to the first active layer and the surface of the substrate base plate away from the first bottom gate is greater than the distance between the surface of the substrate base plate away from the third active layer and the surface of the substrate base plate close to the third gate. 5.The display substrate of claim 2, wherein, The distance between the surface of the substrate base plate away from the first active layer and the surface of the substrate base plate close to the first top gate is substantially equal to the distance between the surface of the substrate base plate away from the third active layer and the surface of the substrate base plate close to the third gate. 6.The display substrate according to any one of claims 2-5, wherein, The display substrate further comprises a second transistor, the second transistor comprises a second bottom gate and a second top gate, the second bottom gate is located between the substrate base plate and the active layer of the second transistor, the second top gate is located on the side of the active layer of the second transistor away from the substrate base plate, and the orthogonal projections of any two of the active layer of the second transistor, the second bottom gate and the second top gate on the substrate base plate at least partially overlap with each other. 7.The display substrate of claim 2, wherein, The display substrate comprises a first buffer layer located between the substrate base plate and the first semiconductor layer, and the first buffer layer comprises silicon oxide, silicon nitride or silicon oxynitride. 8.The display substrate of claim 7, wherein, The display substrate comprises a first gate insulating layer located between the first semiconductor layer and the first conductive layer, and the first gate insulating layer comprises silicon oxide. 9.The display substrate of claim 8, wherein, The display substrate comprises a second gate insulating layer located between the first conductive layer and the second conductive layer, and the second gate insulating layer comprises silicon nitride. 10.The display substrate of claim 9, wherein, The display substrate comprises a fourth gate insulating layer located between the second semiconductor layer and the third conductive layer, and the fourth gate insulating layer comprises silicon oxide. 11.The display substrate of claim 9, wherein, The display substrate further comprises a second buffer layer arranged between the second gate insulating layer and the second conductive layer; and The first capacitor structure and the second capacitor structure are provided with two layers of insulating layers, and the two layers of insulating layers comprise a part of the second gate insulating layer and a part of the second buffer layer. 12.The display substrate of claim 1, wherein, The display substrate comprises a fourth conductive layer located on the side of the third conductive layer away from the substrate base plate; and The display substrate comprises a plurality of thin film transistors arranged on the substrate base plate, and each of the plurality of thin film transistors comprises a source and a drain, and the source and the drain of each thin film transistor are located on the fourth conductive layer. 13.The display substrate of claim 12, wherein, The display substrate comprises a fifth conductive layer located on the side of the fourth conductive layer away from the substrate base plate; and The display substrate further comprises a second transistor, the fifth conductive layer comprises a light shielding layer, and the orthogonal projection of the light shielding layer on the substrate base plate at least covers the orthogonal projection of the active layer of each of the first transistor and the second transistor on the substrate base plate. 14.The display substrate of claim 12, wherein, The display substrate further comprises an interlayer insulating layer disposed between the third conductive layer and the fourth conductive layer, the fourth conductive layer comprises a first conductive sublayer and a second conductive sublayer, the first conductive sublayer is disposed on the interlayer insulating layer, the second conductive sublayer is disposed on a side of the first conductive sublayer away from the substrate, and the first conductive sublayer and the second conductive sublayer are in contact with each other.

15. A display panel comprising the display substrate according to any one of claims 1-14.

16. A display device comprising the display substrate according to any one of claims 1-14 or the display panel according to claim 15.

17. A method for manufacturing a display substrate, wherein The manufacturing method comprises the following steps: providing a substrate; forming a first transistor on the substrate; preparing a first semiconductor layer on the substrate by a patterning process, the first semiconductor layer comprising polycrystalline silicon semiconductor silicon islands; forming a first conductive layer on a side of the first semiconductor layer away from the substrate by a patterning process; forming a second conductive layer on a side of the first conductive layer away from the substrate by a patterning process; forming an insulating layer on a side of the second conductive layer away from the substrate; forming a second semiconductor layer on a side of the second conductive layer away from the substrate by a patterning process, the second semiconductor layer comprising oxide semiconductor silicon islands; and forming a third conductive layer on a side of the second semiconductor layer away from the substrate by a patterning process, wherein the display substrate comprises a plurality of thin film transistors disposed on the substrate, the plurality of thin film transistors at least comprising a first transistor, a second transistor and a third transistor, each of the plurality of thin film transistors comprises an active layer, the active layer of the third transistor is located in the first semiconductor layer, and the active layer of at least one of the first transistor and the second transistor is located in the second semiconductor layer; and the first transistor comprises a first active layer, a first bottom gate and a first top gate, the first bottom gate is located between the substrate and the first active layer, the first top gate is located on a side of the first active layer away from the substrate, the orthogonal projections of any two of the first active layer, the first bottom gate and the first top gate on the substrate at least partially overlap with each other, a third gate insulating layer is disposed between the first bottom gate and the first active layer, the first active layer comprises the oxide semiconductor silicon islands, the third gate insulating layer comprises silicon oxide material, and a surface of the first top gate away from the substrate is in direct contact with the silicon oxide material, and a surface of the first active layer close to the substrate is in direct contact with the silicon oxide material. The display substrate comprises a storage capacitor, the storage capacitor comprises a first capacitor structure, a second capacitor structure and a third capacitor structure disposed on the substrate, the third capacitor structure is located on the side of the first capacitor structure away from the substrate, the second capacitor structure is located between the first capacitor structure and the third capacitor structure, and the orthogonal projection of any two of the first capacitor structure, the second capacitor structure and the third capacitor structure on the substrate at least partially overlaps; The first capacitor structure and the third capacitor structure are electrically connected to each other to form a first capacitor electrode of the storage capacitor, and the second capacitor structure forms a second capacitor electrode of the storage capacitor; The third transistor comprises a third gate, and the first capacitor structure and the third gate of the third transistor are both located on the first conductive layer; The first bottom gate and the second capacitor structure are both located on the second conductive layer; The first top gate and the third capacitor structure are both located on the third conductive layer, or the first active layer and the third capacitor structure are both located on the second semiconductor layer.

18. The method for manufacturing a display substrate according to claim 17, wherein The manufacturing method further comprises: forming an interlayer insulating layer on the side of the first top gate away from the substrate; forming a plurality of first vias in the interlayer insulating layer, the plurality of first vias exposing at least a portion of the active layer of each of the first transistor and the second transistor; depositing a first conductive material layer on the side of the interlayer insulating layer away from the substrate; forming a plurality of second vias, the plurality of second vias exposing at least a portion of the active layer of at least the third transistor; depositing a second conductive material layer on the side of the first conductive material layer away from the substrate; and patterning the first conductive material layer and the second conductive material layer by a one-time patterning process to form the source and drain of the plurality of thin film transistors.

Images