Integrated circuit performing dynamic voltage and frequency scaling operations and method of operation thereof

Abstract

An integrated circuit includes a plurality of sub-blocks configured to process instructions according to operating conditions, a plurality of activity counters configured to count an active time that is a time during which each of the plurality of sub-blocks processes the instructions, and a dynamic voltage and frequency scaling (DVFS) controller configured to calculate a power consumption of the plurality of sub-blocks during a sampling period based on the active time and adjust the operating conditions of the plurality of sub-blocks based on the power consumption.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0168724, filed on December 4, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to integrated circuits, and more specifically, to integrated circuits that perform dynamic voltage and frequency regulation (DVFS) operation with regard to power consumption and methods of operating them. Background Technology

[0004] With technological advancements, power management and user experience are becoming increasingly important for computing systems in mobile devices. To improve multithreaded performance in mobile environments, the number of competing entities using memory is diversifying as the number of cores increases and proprietary intellectual property (IP) is continuously added to application processors for various multimedia scenarios. Therefore, application processors perform Dynamic Voltage and Frequency Scaling (DVFS) operations to adjust the frequency and voltage within the application processor, thereby controlling performance and power consumption. Summary of the Invention

[0005] This disclosure relates to a computing system, a computing system including an integrated circuit, and a method of operating the integrated circuit. By performing dynamic voltage and frequency regulation (DVFS) operation taking into account the power consumption of sub-blocks, the integrated circuit reflects a power margin within performance improvements.

[0006] According to one aspect of this disclosure, an integrated circuit includes: a plurality of sub-blocks configured to process instructions according to operating conditions; a plurality of activity counters configured to count activity time, the activity time being the time for processing each instruction in the plurality of sub-blocks; and a dynamic voltage and frequency regulation (DVFS) controller configured to calculate the power consumption of the plurality of sub-blocks during a sampling period based on the activity time, and to adjust the operating conditions of the plurality of sub-blocks based on the power consumption.

[0007] According to another aspect of this disclosure, a method for operating an integrated circuit comprising a plurality of sub-blocks that process instructions according to operating conditions includes: obtaining a workload based on a sampling period and a total activity time of at least one of the plurality of sub-blocks; obtaining a power utilization rate based on the power consumption of the plurality of sub-blocks during the sampling period; and adjusting operating conditions according to the ratio between the workload and the power utilization rate.

[0008] According to another aspect of this disclosure, a computing system includes: a plurality of sub-blocks, each sub-block configured to process instructions; an activity counter, corresponding to each of the plurality of sub-blocks and configured to count sub-activity times, the sub-activity time being the activity time of each corresponding sub-block; a total counter, configured to count the total activity time of at least one activity in the plurality of sub-blocks; a clock management unit, configured to generate a clock signal applied to the plurality of sub-blocks; a power management unit, configured to generate a power supply voltage applied to the plurality of sub-blocks; and a dynamic voltage and frequency regulation (DVFS) controller, configured to calculate the power consumption consumed by the plurality of sub-blocks during a sampling period based on the sub-activity time and the total activity time, and control the clock management unit or the power management unit such that the frequency of the clock signal or the amplitude of the power supply voltage is adjusted based on the power consumption. Attached Figure Description

[0009] The embodiments of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a system according to exemplary embodiments of the present disclosure;

[0011] Figure 2 This is a diagram illustrating the power consumption of a sub-block according to an exemplary embodiment of the present disclosure;

[0012] Figure 3 This is a diagram illustrating the power consumption of a sub-block according to an exemplary embodiment of the present disclosure;

[0013] Figure 4 This is a block diagram illustrating a computing system according to exemplary embodiments of the present disclosure;

[0014] Figure 5 This is a diagram illustrating a power factor table according to an exemplary embodiment of the present disclosure;

[0015] Figure 6 This is a flowchart illustrating a method of operating an IP device according to an exemplary embodiment of the present disclosure;

[0016] Figure 7 This is a block diagram illustrating a system including a gating circuit according to an exemplary embodiment of the present disclosure;

[0017] Figure 8 This is a flowchart illustrating a method of operating an IP device according to an exemplary embodiment of the present disclosure;

[0018] Figure 9 This is a flowchart illustrating a method for calculating power utilization according to an exemplary embodiment of the present disclosure;

[0019] Figure 10This is a diagram illustrating the changes in operating conditions according to exemplary embodiments of the present disclosure;

[0020] Figure 11 It is a graph used to describe the responsiveness of dynamic voltage and frequency regulation (DVFS) operation according to exemplary embodiments of the present disclosure;

[0021] Figure 12 This is a block diagram illustrating a system comprising multiple clusters according to exemplary embodiments of the present disclosure;

[0022] Figure 13 This is a block diagram illustrating a system according to exemplary embodiments of the present disclosure; and

[0023] Figure 14 This is a block diagram illustrating a communication device including an application processor according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0024] In the following description, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram illustrating a system according to an exemplary embodiment of the present disclosure.

[0026] Reference Figure 1 The system 10 may include an intellectual property (IP) device 11, a clock management unit (CMU) 12, a power management unit (PMU) 13, and a memory 14.

[0027] System 10 can correspond to various types of data processing devices, and as an example, it can correspond to mobile devices. Furthermore, System 10 can correspond to laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, portable multimedia players (PMPs), personal navigation devices or portable navigation devices (PNDs), handheld game consoles, mobile internet devices (MIDs), wearable computers, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, or e-books.

[0028] System 10 may include various types of memory devices. For example, memory 14 may correspond to various types of semiconductor memory devices and may be dynamic random access memory (DRAM), such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, and Rambus dynamic random access memory (RDRAM). Furthermore, memory 14 may also be any of flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FeRAM).

[0029] In some embodiments, system 10 can be implemented as a system-on-a-chip (SoC). The SoC may include a system bus that applies a protocol with a predetermined standard bus standard, and components included in system 10 can be connected to the system bus. For example, the Advanced Microcontroller Bus Architecture (AMBA) protocol for Advanced RISC Machines (ARM) can be applied as a standard system bus. Bus types for the AMBA protocol may include Advanced High Performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced Extensible Interface (AXI), AXI4, AXI Coherence Extension (ACE), etc. Furthermore, other types of protocols, such as the open core protocols of SonicsuNetwork, IBM CoreConnect, and OCP-IP, can be applied.

[0030] IP device 11 may include multiple sub-blocks 11_1, multiple activity counters 11_2, a total counter 11_3, and a DVFS controller 11_4. IP device 11 may be designed as an integrated circuit implemented with multiple transistors. IP device 11 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or an image signal processor (ISP). Figure 1 An IP device 11 is shown, but the type and number of IP devices included in system 10 are not limited to this. In some embodiments, at least some of the multiple activity counters 11_2, total counters 11_3, and DVFS controllers 11_4 may be located outside of IP device 11.

[0031] Each of the multiple sub-blocks 11_1 can independently process commands. Sub-block 11_1 can be a CPU core, GPU core, NPU core, or ISP core. Because IP device 11 includes multiple cores, system 10 can also be referred to as a multi-core processor. Sub-block 11_1 can also be referred to as a sub-functional block. The state in which sub-block 11_1 processes instructions can be called an active state, and the state in which sub-block 11_1 does not process instructions can be called an idle state. The time that sub-block 11_1 is active can be called sub-active time, and the time that sub-block 11_1 is idle can be called idle time.

[0032] Each of the plurality of sub-blocks 11_1 can process instructions based on a clock signal CLK and a power supply voltage VDD. The performance of sub-block 11_1 can depend on the clock signal CLK and the power supply voltage VDD. As the amplitude of the power supply voltage VDD increases and the frequency of the clock signal CLK increases, the performance of the IP device 11 can be improved and the power consumption of the IP device 11 can increase. In this specification, the frequency of the clock signal CLK and the amplitude of the power supply voltage VDD can be defined as the operating conditions of the IP device 11. Furthermore, the frequency of the clock signal CLK can be referred to as the operating frequency. Hereinafter, for ease of description, exemplary embodiments of the present disclosure will be described primarily with reference to the operating conditions corresponding to the frequency of the clock signal CLK.

[0033] Each of the multiple activity counters 11_2 can count the sub-activity time corresponding to sub-block 11_1. For example, the first activity counter can count the sub-activity time of the first sub-block, and the second activity counter can count the sub-activity time of the second sub-block. In this specification, the activity time of a sub-block can be referred to as the sub-activity time. The multiple activity counters 11_2 can each correspond to multiple sub-blocks 111. In one example, see the following reference... Figure 7 The activity counter 11_2 can count the sub-activity time based on a gating signal of the clock signal CLK applied to the sub-block or a control signal for the supply of the power supply voltage VDD. In another example, when the sub-block is active, the activity counter 11_2 can obtain the sub-activity time by counting the number of cycles of the clock signal CLK applied to the sub-block. See below for further details. Figure 3 Describe the duration of the sub-activity.

[0034] The total counter 11_3 can count the total activity time. In this specification, the total activity time can mean the time that IP device 110 is active. Specifically, the total activity time can be the activity time of at least one of the multiple sub-blocks 11_1. See below for further details. Figure 3 Describe the total activity time.

[0035] The DVFS controller 11_4 can output control signals CTRL_CLK and CTRL_VDD in each sampling period SP to control the operating conditions of the IP device 11. Specifically, the DVFS controller 11_4 can output a clock control signal CTRL_CLK to control the frequency of the clock signal CLK, and a voltage control signal CTRL_VDD to control the level of the power supply voltage VDD.

[0036] The DVFS controller 11_4 can calculate the power consumed by the multiple sub-blocks 11_1 during the sampling period SP based on the sub-activity time of the multiple sub-blocks 11_1 and the total activity time of the IP device 11. Specifically, as will be discussed later. Figure 4 The DVFS controller 11_4 can calculate the power consumed by multiple sub-blocks 11_1 by referring to the power factor table stored in the internal memory 14.

[0037] The DVFS controller 11_4 can control operating conditions based on the power consumed by the multiple sub-blocks 11_1. For example, when the power consumed by the multiple sub-blocks 11_1 is relatively low, the DVFS controller 11_4 controls the clock management unit 12 to generate a clock signal CLK with a higher frequency, thereby improving the performance of the IP device 11.

[0038] The DVFS controller 11_4 can refer to hardware capable of performing DVFS functions and operations, or it can refer to computer program code capable of performing DVFS functions and operations. However, this disclosure is not limited thereto and can also refer to an electronic recording medium, such as a processor, on which computer program code capable of performing DVFS functions and operations is mounted. That is, the DVFS controller 11_4 can represent a combination of functions and / or structures for hardware used to perform the technical ideas of this disclosure and / or for software used to drive the hardware.

[0039] The clock management unit 12 can generate a clock signal CLK and can adjust the frequency of the clock signal CLK based on the clock control signal CTRL_CLK. For example, the clock manager 120 may include an oscillator that generates the clock signal CLK based on the clock control signal CTRL_CLK. The clock management unit 120 may also be referred to as a clock generator and a clock generation circuit.

[0040] The power management unit 13 can generate a power supply voltage VDD and can adjust the level of the power supply voltage VDD based on the voltage control signal CTRL_VDD. For example, the power management unit 13 may include a switching regulator that generates the power supply voltage VDD based on the control signal CTRL_VDD. The power management unit 13 may also be referred to as a power management integrated circuit (PMIC).

[0041] Memory 14 can be accessed by IP device 11, and IP device 11 can store data in memory 14 or retrieve data stored in memory 140. Memory 14 may include volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM), and may include non-volatile memory devices such as flash memory or resistive random access memory (RRAM). In some embodiments, reference is made as follows. Figure 4 The memory 14 can store a power coefficient table. In some embodiments, with Figure 1 Unlike the example shown, memory 14 can be included in IP device 11.

[0042] Although not shown in the figure, system 10 may include various types of functional blocks, such as input / output (I / O) interface blocks that communicate with IP device 11, Universal Serial Bus (USB) host blocks, USB slave blocks, etc.

[0043] As will be described later with reference to the accompanying drawings, the DVFS controller 11_4 can calculate the power consumed by the IP device 11 during the sampling period based on the total active time and sub-active time, and generate control signals CTRL_CLK and CTRL_VDD based on the power consumption, and provide the generated control signals CTRL_CLK and CTRL_VDD to the clock management unit 12 and the power management unit 13. Therefore, when the power consumption is relatively low, the IP device 11 can reflect the remaining power margin in performance improvement.

[0044] Figure 2 This is a diagram illustrating the power consumption of a sub-block according to an exemplary embodiment of this disclosure. (Refer to...) Figure 2 The power consumption P of the sub-block can be expressed as [Equation 1].

[0045] [Equation 1]

[0046] P = C·V·f 2 ∝C·f 3

[0047] Here, C is the capacitance of the sub-block, V is the amplitude of the power supply voltage applied to the sub-block, and f is the frequency of the clock signal applied to the sub-block. Because the capacitors included in the sub-block can charge faster as the power supply voltage increases, the amplitude of the power supply voltage and the frequency of the clock signal can be proportional. Therefore, the power consumption can be proportional to the cube of the frequency of the clock signal.

[0048] In this specification, among the power-related parameters, all parameters other than the clock signal frequency f and the power supply voltage amplitude V can be collectively referred to as power factors. For example, in [Equation 1], the capacitance of the sub-block can be referred to as the power factor.

[0049] Multiple sub-blocks 11_1 can have different circuit structures, and therefore can have different performance. That is, the number of instructions that multiple sub-blocks 11_1 can process per unit time can be different. Furthermore, due to the different circuit structures, even if the power supply voltage amplitude and the clock signal frequency are the same, the power consumption of the multiple sub-blocks 11_1 can be different. That is, the power coefficients of the multiple sub-blocks can be different.

[0050] Reference Figure 2 The power factor of the first sub-block SB1 can be C1, the power factor of the second sub-block SB2 can be C4, the power factor of the third sub-block SB3 can be C2, and the power factor of the fourth sub-block SB4 can be C3. Furthermore, in some embodiments, different from... Figure 2 The power coefficients of some sub-blocks among multiple sub-blocks SB1, SB2, SB3, and SB4 can be the same. For example, see later. Figure 12 The process involves dividing multiple sub-blocks into multiple clusters, where each cluster is a set of sub-blocks with the same performance. Specifically, the multiple sub-blocks can be divided into sub-blocks included in a first cluster and sub-blocks included in a second cluster. Sub-blocks included in the first cluster consume less power than sub-blocks included in the second cluster, but can provide relatively lower performance.

[0051] Figure 3 This is a diagram illustrating the power consumption of a sub-block according to an exemplary embodiment of this disclosure. See below for further details. Figure 1 Give Figure 3 The description. (Refer to...) Figure 3 When the sampling period SP is reached, the DVFS controller 11_4 can start DVFS operation based on the power consumed by the IP device 11 during the sampling period SP. The DVFS operation can be an operation that adjusts the operating conditions of the IP device 11 (i.e., the frequency of the clock signal CLK or the amplitude of the power supply voltage VDD).

[0052] The IP device 11 includes multiple sub-blocks SB1 to SB4, which can be activated at different times. The first sub-block SB1 can be activated during the first sub-activity time SACT1, the second sub-block SB2 can be activated during the second sub-activity time SACT2, the third sub-block SB3 can be activated during the third sub-activity time SACT3, and the fourth sub-block SB4 can be activated during the fourth sub-activity time SACT4. At least one of the multiple sub-blocks SB1 to SB4 can be activated during the total activity time TACT.

[0053] The power consumed by each sub-block can be determined by the power factor, the frequency of the clock signal CLK, and the amplitude of the power supply voltage VDD, as described above. Figure 2The frequency of the clock signal CLK applied to IP device 11 during the sampling period SP and the amplitude of the power supply voltage VDD can be fixed. Therefore, the power consumed by the sub-block can be proportional to the power factor C corresponding to that sub-block. (Refer to...) Figure 3 The power consumed by the first sub-block SB1 can be P1, the power consumed by the second sub-block SB2 can be P2, the power consumed by the third sub-block SB3 can be P3, and the power consumed by the fourth sub-block SB4 can be P4.

[0054] The energy consumed by IP device 11 during the sampling period SP can be the sum of the energy consumed by multiple sub-blocks. Therefore, the average power consumption Pave of IP device 11 during the total active time TACT during which at least one sub-block is activated can be expressed as [Equation 2].

[0055] [Equation 2]

[0056]

[0057] The DVFS controller 11_4 can calculate the average power consumption Pave of the IP device 11 during the sampling period SP each time the sampling period SP is reached, and can adjust the operating conditions based on the average power consumption Pave.

[0058] To control heat generation or smoothly supply limited power, the maximum power that can be allocated to IP device 11 can be predetermined. The power margin of the maximum power increases when the average power consumption Pave is low during the sampling period SP. The DVFS controller 11_4 according to an exemplary embodiment of this disclosure can improve the performance of IP device 11 by increasing the frequency of the clock signal CLK or the amplitude of the supply voltage VDD.

[0059] Figure 4 This is a block diagram illustrating a computing system according to an exemplary embodiment of the present disclosure. Figure 5 This is a graph illustrating a power factor table according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 4 The computing system 400 includes a DVFS controller 410, multiple active counters 421, 422, and 423, a total counter 430, a memory 440, a clock management unit 451, a power management unit 452, and a timer 460. Figure 1 Descriptions of components that are identical to those in the original document may be omitted. The DVFS controller 410 may include a DVFS regulator module 411, a clock management unit driver 412, and a power management unit driver 413.

[0060] DVFS controller module 411 can control the overall DVFS operation. In some examples, DVFS controller module 411 can obtain sub-activity times from multiple activity counters 421, 422, and 423, and the total activity time from the total counter 430. DVFS controller module 411 can access memory 440 and refer to the power factor table. DVFS controller module 411 can calculate the power consumption of the IP device based on the power factor of the sub-blocks, the sub-activity times, and the total activity time. DVFS controller module 411 can control the clock management unit driver 412 and the power management unit driver 413 so that operating conditions are adjusted based on power consumption.

[0061] The clock management unit driver 412, under the control of the DVFS regulator module 411, can output a clock control signal CTRL_CLK to the clock management unit 451. The clock management unit 451 can output a clock signal CLK with a frequency adjusted according to the clock control signal CTRL_CLK. The power management unit driver 413, under the control of the DVFS regulator module 411, can output a voltage control signal CTRL_VDD to the power management unit 452. The power management unit 452 can output a power supply voltage VDD with an amplitude adjusted according to the voltage control signal CTRL_VDD.

[0062] Memory 440 can store a power factor table. (See reference...) Figure 5 The power factor table can represent the relationship between sub-blocks and power factors. Specifically, see the above reference... Figure 2 The power coefficient table can represent the relationship between the first to fourth sub-blocks SB1 to SB4 and the first to fourth power coefficients C1 to C4.

[0063] The DVFS controller module 411 can obtain the sub-activity time and total activity time from the total counter 430 and multiple activity counters 421, 422 and 423, and calculate the power consumption of the IP device 11 during the sampling period by referring to the power factor table.

[0064] The DVFS controller module 411 can adjust operating conditions based on power consumption. For example, the DVFS controller module 411 can determine the next frequency Fnext of the clock signal CLK using [Equation 3].

[0065] [Equation 3]

[0066]

[0067] Here, Fnext can be the frequency of the clock signal CLK after the sampling period SP, the workload WL can be the workload of IP device 11 during the sampling period SP, the power utilization PU can be the ratio of the power consumed during the sampling period SP to the maximum allowable power, and Fcurrent can be the frequency of the clock signal CLK during the sampling period SP. The frequency of the clock signal CLK can be referred to as the operating frequency. As described above by [Equation 1], because power can be proportional to the cube of the frequency, unlike [Equation 3], in some embodiments, Fnext can be calculated as being inversely proportional to the cube root of the power utilization, as shown in [Equation 4]. On the other hand, it will be apparent to those skilled in the art that constants or variables can be multiplied by or added to the power utilization or workload to adjust Fnext.

[0068] [Equation 4]

[0069]

[0070] According to [Equations 3] and [Equations 4], in order to adjust the frequency of the clock signal CLK, the DVFS controller module 411 can take into account the power utilization and workload during the sampling period SP. That is, when the power consumption of IP device 11 is low, the DVFS controller module 411 can improve the performance of IP device 11 by increasing the operating frequency to a higher level.

[0071] The DVFS controller module 411 can determine the power utilization rate PU according to [Equation 5].

[0072] [Equation 5]

[0073]

[0074] Here, Pave can be calculated as the average power consumption using [Equation 2], and Pmax is the maximum allowable power, which can represent the maximum power that IP device 11 can consume during the sampling period. When the power consumption of IP device 11 exceeds the power limit, the system may fail to operate properly due to overcurrent flowing through it exceeding the reference current or damage to the system caused by the system temperature rising above the reference temperature. Therefore, the maximum allowable power Pmax can be designed as part of the power limit, for example, at 80% of that level.

[0075] Referring to [Equation 3], the power utilization rate can have a value of 1 or less. That is, the power utilization rate can be 1 when all sub-blocks are active during the sampling period, and can be less than 1 in other cases. Referring to [Equation 2], when the power utilization rate is less than 1, the operating frequency can be increased relatively more significantly compared to when only the workload is considered. As a result, the DVFS controller module 411, according to an exemplary embodiment of this disclosure, considers the power utilization rate to determine the operating frequency, thereby improving the performance of the IP device 11 and enabling efficient power management.

[0076] The workload WL can be calculated in several ways. For example, the workload WL can be calculated using [Equation 6], which represents the ratio of the total activity time TACT to the sampling period SP.

[0077] [Equation 6]

[0078]

[0079] However, the embodiments are not limited to this and the workload WL can be calculated based on the number of instructions processed during the sampling period, the number of cache hits, or the number of cache misses.

[0080] Figure 6 This is a flowchart illustrating a method of operating an IP device according to an exemplary embodiment of the present disclosure. Specifically, Figure 6 This is a flowchart illustrating the operation method of an IP device performing DVFS operations. (Refer to...) Figure 6 The method for operating an IP device may include multiple steps S610 to S630. See below for further details. Figure 1 To describe Figure 6 Each step.

[0081] In step S610, multiple activity counters 11_2 and a total counter 11_3 can count the activity time of multiple sub-blocks 11_1 during the sampling period SP. Each activity counter 11_2 can correspond to a different sub-block 11. (Refer to the above.) Figure 3 As mentioned above, the activity counter can count the activity time of the corresponding sub-block. The activity time of a sub-block can be called the sub-activity time (SACT). (Refer to the above.) Figure 3 The total counter 11_3 can count the total activity time TACT of at least one of the multiple sub-blocks 11_1.

[0082] In step S620, the DVFS controller 11_4 can calculate the power consumption of the IP device 11 during the sampling period SP based on the activity time. Specifically, the DVFS controller 11_4 can calculate the power consumption of each of the multiple sub-blocks 11_1 by referring to a power factor table, and calculate the average power consumption of the IP device 11 by dividing the sum of the power consumption of the multiple sub-blocks 11_1 by the total activity time TACT.

[0083] In step S630, the DVFS controller 11_4 can perform DVFS operations based on the power consumption of the IP device 11. Specifically, the DVFS controller 11_4 can calculate the power utilization rate using the average power consumption and the maximum allowable power, and adjust the operating conditions of the IP device 11 based on the calculated power utilization rate. For example, when the power utilization rate is low, the frequency of the clock signal CLK applied to the IP device 11 can be increased, or the IP device 11 can output control signals CTRL_CLK and CTRL_VDD, thereby increasing the amplitude of the power supply voltage VDD applied to the IP device 11.

[0084] By performing DVFS operations based on the power consumption of the IP device, the method of operating the IP device according to exemplary embodiments of this disclosure can improve the performance of the IP device and the efficiency of power management.

[0085] Figure 7 This is a block diagram illustrating a system including a gating circuit according to an exemplary embodiment of the present disclosure.

[0086] Reference Figure 7 System 700 may include a gating circuit 713. The gating circuit 713 controls the clock signal CLK or power supply voltage VDD applied to the sub-blocks in the idle state to be cut off, thereby minimizing power wasted in the idle state. Specifically, the gating circuit 713 outputs multiple gating signals CG1 to CGN and PG1 to PGN, allowing the clock signal CLK or power supply voltage VDD to be selectively applied to multiple sub-blocks 711 and 712.

[0087] System 700 may include multiple switches CS1, CS2, PS1, and PS2. First clock switch CS1 and second clock switch CS2 can switch the clock signal CLK according to clock gating signals GC1 to CGN. For example, when the clock gating signal is at a logic high level, the clock switch can be turned on and the clock signal CLK can be provided to the corresponding sub-block. That is, when the clock gating signal indicates the activation of the clock signal, the clock signal CLK can be provided to the sub-block. However, embodiments are not limited to this, and the clock switches can have various structures. First and second power switches PS1 and PS2 can switch the power supply voltage VDD according to power gating signals PG1 to PGN. For example, when the power gating signal is at a logic high level, the power switch can be turned on and the power supply voltage VDD can be provided to the corresponding sub-block. That is, when the power gating signal indicates the activation of the power supply voltage, the power supply voltage VDD can be provided to the sub-block. However, embodiments are not limited to this, and the clock switches can have various structures. In some embodiments, the power switch can be a head switch implemented as a P-type field-effect transistor (PFET) or a foot switch implemented as an N-type field-effect transistor (NFET).

[0088] Multiple activity counters 741 and 742 can count the sub-activity times of multiple sub-blocks 711 and 712 based on gating signals CG1 to CGN and PG1 to PGN. For example, when the first clock gating signal CG1 is at a logic high level, because the first sub-block 711 is active, the first activity counter 741 can obtain the first sub-activity time SACT1 by counting the periods during which the first clock gating signal CG1 is at a logic high level. That is, the sub-activity time can correspond to the time when the clock gating signal indicates the activation of the clock signal. Alternatively, the sub-activity time can correspond to the time when the power gating signal indicates the activation of the power supply voltage.

[0089] The DVFS controller 750 according to an exemplary embodiment of the present disclosure can perform DVFS operation, in which power consumption is reflected by using sub-activity times acquired based on a gating control signal. Therefore, the performance of system 700 can be improved and the efficiency of power management can be improved. The DVFS controller 750 can output a clock control signal CTRL_CLK and a voltage control signal CTRL_VDD to perform DVFS operation. System 700 may include a clock management unit 720 and a power management unit 730. The clock management unit 720 can output a clock signal CLK having a frequency adjusted according to the clock control signal CTRL_CLK. The power management unit 730 can output a power supply voltage VDD having an amplitude adjusted according to the voltage control signal CTRL_VDD.

[0090] Figure 8This is a flowchart illustrating a method of operating an IP device according to an exemplary embodiment of the present disclosure. Specifically, Figure 8 This is a flowchart illustrating the method of operating the DVFS controller to adjust the operating conditions of sub-blocks. (Refer to...) Figure 8 The method for operating an IP device may include multiple steps S810 to S830. See below for further details. Figure 1 or Figure 4 To describe Figure 8 Each step.

[0091] In step S810, the DVFS controller 11_4 can obtain the workload based on the ratio of the total active time to the sampling period SP. Specifically, the DVFS controller 11_4 can obtain the workload by referring to [Equation 6]. The sampling period SP can correspond to the period during which the DVFS controller 11_4 performs DVFS operations. The timer 460 periodically counts the sampling period SP and outputs a trigger signal Trigger_SG to the DVFS controller 410 each time the sampling period SP has elapsed, thereby indicating the start of the DVFS operation. The total active time can be the time during which at least one of the multiple sub-blocks is active. The method of obtaining the workload is not limited to this and can be calculated based on the number of instructions processed during the sampling period, the number of cache hits, or the number of cache misses.

[0092] In step S820, the DVFS controller 11_4 can obtain the power utilization rate based on the power consumption of multiple sub-blocks during the sampling period SP. For example, the DVFS controller 11_4 can obtain the power utilization rate by referring to [Equation 5]. The power utilization rate can represent the ratio of the actual power consumption used to the maximum power that the IP device 11 can consume.

[0093] In step S830, the DVFS controller 11_4 can adjust the operating conditions of the sub-block based on the workload and power utilization. For example, the DVFS controller 11_4 can adjust the frequency of the clock signal CLK with reference to [Equation 3] or [Equation 4]. That is, the DVFS controller 11_4 according to the exemplary embodiment of this disclosure adjusts the operating conditions based on the power utilization, so that the performance of the IP device can be improved if there is room for power margin. Even if power consumption increases due to performance improvement (increased operating frequency or increased power supply voltage amplitude), efficient power management can be performed because there is a margin in the power margin.

[0094] Figure 9 This is a flowchart illustrating a method for calculating power utilization according to an exemplary embodiment of the present disclosure. Specifically, Figure 9 It can correspond to Figure 8The method for step S820. The method for calculating power utilization may include multiple steps S910 to S930. See below for further details. Figure 1 , Figure 4 or Figure 7 To describe Figure 9 Each step.

[0095] In step S910, the DVFS controller 410 can obtain the sub-activity times SACT1, SACT2, and SACT3 of multiple sub-blocks from multiple activity counters 421 to 423. The sub-activity time can be the time a sub-block is in an active state. (Refer to the above...) Figure 7 The sub-activity time can correspond to the activation time of the gating control signal indicating the clock signal or power supply voltage output from the gating circuit 713.

[0096] In step S920, the DVFS controller 410 can calculate the average power consumption of the IP device during the sampling period based on the sub-activity time and power coefficient. Specifically, the DVFS controller 410 can identify the power coefficient corresponding to each sub-block based on the power coefficient table stored in the memory 440, and use [Equation 1] to calculate the individual power consumption consumed by each sub-block. Thereafter, [Equation 2] can be used to calculate the average power consumption of the IP device. Specifically, the energy consumed by the sub-block can be calculated by multiplying the individual power consumption of the sub-block by the sub-activity time of the sub-block, and the average power consumption can be calculated by dividing the energy consumed by multiple sub-blocks by the total activity time TACT.

[0097] In step S930, the DVFS controller 410 can calculate the power utilization rate based on the ratio between the average power consumption and the maximum allowable power.

[0098] Figure 10 This is a diagram illustrating changes in operating conditions according to exemplary embodiments of the present disclosure. Specifically, Figure 10 This diagram illustrates the active state of the first sub-block 910 among the multiple sub-blocks 910 to 940 included in the IP device 900 during the sampling period SP. Figure 10 In this context, when a sub-block is active, this can be displayed as ON; when a sub-block is idle, this can be displayed as OFF. Figure 10 In this context, it can be assumed that each sub-block consumes the same amount of power. That is, compared to... Figure 2 The diagrams shown may differ, but the power coefficients of multiple sub-blocks can be the same.

[0099] Reference Figure 10 On the left side, during the sampling period SP, a clock signal CLK with a first frequency F1 can be applied to IP device 900. Sub-blocks 910 to 940 can process instructions based on the clock signal CLK. (See reference...) Figure 10On the right side, when the sampling period SP has elapsed, the DVFS controller 11_4 can adjust the frequency of the clock signal CLK to the second frequency F2. Figure 10 The frequency adjustment using [Equation 3] is shown, but the embodiment is not limited to this. For example, the DVFS controller 11_4 can use [Equation 4] to adjust the frequency.

[0100] Because only one sub-block is active during the sampling period SP, the power utilization can be 1 / 4, and because at least one sub-block is always active during the sampling period SP, the workload can be 1. Therefore, the second frequency F2 can be determined to be four times the first frequency F1. However, the embodiment is not limited to this, and parameters can be added to or multiplied by each of the workload and power utilization to optimize frequency adjustment.

[0101] Figure 11 This is a graph used to describe the responsiveness of DVFS operations according to exemplary embodiments of the present disclosure. Specifically, refer to... Figure 11 Solid lines represent curves that take power utilization into account when adjusting operating frequency, while dashed lines represent curves that do not consider power utilization when adjusting operating frequency. For example, a solid line curve could be the same as the one mentioned above. Figure 10 The curves corresponding to the described operation frequency adjustments. Figure 11 In this system, the operating frequency of SP can be adjusted for each sampling period.

[0102] like Figure 11 As shown by the solid line, when adjusting the operating frequency considering power utilization, the operating frequency can be increased from the first frequency F1 to the second frequency F2 after the first sampling period SP1. (Refer to the above...) Figure 10 The aforementioned method can improve the degree of increase in operating frequency caused by power utilization.

[0103] On the other hand, such as Figure 11 As shown by the dashed line, without considering power utilization when adjusting the operating frequency, the operating frequency can increase from the first frequency F1 to the third frequency F3 after the first sampling period SP1. The third frequency F3 can be less than the second frequency F2. Without considering power utilization when adjusting the operating frequency, the operating frequency can reach the second frequency F2 after the nth sampling period SPn. That is, when power utilization is taken into account when adjusting the operating frequency, the operating frequency can be increased rapidly.

[0104] As a result, when DVFS operation is performed using power utilization according to exemplary embodiments of the present disclosure, the responsiveness for improving the performance of IP device 900 can be improved as the range of operating frequencies increases.

[0105] Figure 12This is a block diagram illustrating a system comprising multiple clusters according to exemplary embodiments of the present disclosure. (Refer to...) Figure 12 System 1000 may include an IP device 1100 having a first cluster 1110, a second cluster 1120, a clock management unit 1200, and a DVFS controller 1300. The first cluster 1110 may include first to fourth cores 1111 to 1114, and the second core cluster 1120 may include fifth to eighth cores 1121 to 1124. For ease of description, Figure 12 The first cluster 1110 and the second cluster 1120 are shown to each include four cores, but the embodiments are not limited thereto. Although not shown in the figures, the system 1000 may also include a counter for counting the sub-activity time and total activity time of cores 1111 to 1114 included in the first cluster 1110 and cores 1121 to 1124 included in the second cluster 1120.

[0106] The performance of cores 1111 to 1114 included in the first cluster 1110 may differ from the performance of cores 1121 to 1124 included in the second cluster 1120. In the following, it is assumed that the number of operations per unit time for cores 1111 to 1114 included in the first cluster 1110 is less than the number of operations per unit time for cores 1121 to 1124 included in the second cluster 1120. The clock management unit 1200 can output a first clock signal CLK1 and a second clock signal CLK2. The first cluster 1110 can process commands according to the first clock signal CLK1, and the second cluster 1120 can process commands according to the second clock signal CLK2.

[0107] When the workload of a core exceeds a reference value, the corresponding core can be in a heavily loaded state. For example, the second core 1112 of the first cluster 1110 can be in a heavily loaded state. When the frequency of the first clock signal CLK1 applied to the second core 1112 in the heavily loaded state reaches the reference frequency, at least some of the tasks assigned to the second core 1112 can be migrated to cores included in the second cluster 1120. Since some tasks are migrated to cores with relatively large computational loads, the performance and power management efficiency of the system 1000 can be improved.

[0108] Reaching the reference value more quickly in terms of operation frequency can facilitate task migration. (See above reference.) Figure 11 The DVFS controller 1040 according to an exemplary embodiment of the present disclosure adjusts the operating frequency based on power utilization, thereby improving frequency responsiveness and correspondingly improving task migration performance.

[0109] Figure 13 This is a block diagram illustrating a system according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 13The System 2000 can be implemented as a handheld device, such as a mobile phone, smartphone, tablet computer, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital video camera, portable multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console or e-reader.

[0110] System 2000 may include SoC 2200 and memory device 2300. SoC 2200 may include CPU 2210, GPU 2220, NPU 2230, ISP 2240, memory interface (MIF) 2250, clock management unit (CMU) 2260, and power management unit (PMU) 2270. CPU 2210, GPU 2220, NPU 2230, and ISP 2240 may be referred to as master IP devices, and MIF 2250 may be referred to as slave IP devices. At least one of CPU 2210, GPU 2220, NPU 2230, ISP 2240, and MIF 2250 may be referred to as above. Figures 1 to 12 An example implementation of the described IP device. Therefore, at least one of CPU 2210, GPU 2220, NPU 2230, ISP 2240, and MIF 2250 may include multiple sub-blocks and may include a DVFS controller that performs DVFS operations based on the power consumed by the multiple sub-blocks. The DVFS controller included in CPU 2210, GPU 2220, NPU 2230, ISP 2240, and MIF 2250 can control CMU 2260 or PMU 2270, and CPU 2210, GPU 2220, NPU 2230, ISP 2240, and MIF 2250 receive a clock signal CLK from CMU 2260 and a power supply voltage from PMU 2270 to process instructions.

[0111] CPU 2210 can process or run instructions and / or data stored in memory device 2300 in response to a clock signal generated by CMU 2260.

[0112] GPU 2220 can acquire image data stored in memory device 2300 in response to a clock signal generated by CMU 2260. GPU 2220 can generate image data for output to a display device (not shown) from image data provided from MIF 2250, or it can encode the image data.

[0113] NPU 2230 can refer to any device that runs machine learning models. NPU 2230 can be a hardware block designed to run machine learning models. Machine learning models can be based on artificial neural networks, decision trees, support vector machines, regression analysis, Bayesian networks, or genetic algorithms. As a non-limiting example, artificial neural networks can include convolutional neural networks (CNNs), region-based neural networks (R-CNNs), region proposal networks (RPNs), recurrent neural networks (RNNs), stacked deep neural networks (S-DNNs), state-space dynamic neural networks (S-SDNNs), deconvolutional networks, deep belief networks (DBNs), restricted Boltzmann machines (RBMs), fully convolutional networks, long short-term memory (LSTM) networks, and classification networks.

[0114] The ISP 2240 can perform signal processing operations on raw data received from an image sensor (not shown) located outside the SoC 2200 and generate digital data with improved image quality.

[0115] The MIF 2250 can provide an interface to a memory device 2300 located outside the SoC 2200. The memory device 2300 can be dynamic random access memory (DRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), or flash memory.

[0116] The CMU 2260 generates and supplies clock signals to components of the SoC 2200. The CMU 2260 may include clock generation devices such as phase-locked loops (PLLs), delay-locked loops (DLLs), and crystals. The PMU 2270 converts external power to internal power and supplies this internal power to the components of the SoC 2200 as a power source.

[0117] Figure 14 This is a block diagram illustrating a communication device including an application processor according to an exemplary embodiment of the present disclosure.

[0118] Reference Figure 14 The communication device 3000 may include an application processor 3010, a memory device 3020, a display 3030, an input device 3040, and a radio transceiver 3050. The application processor 3010 may be as described above. Figures 1 to 13 Example implementations of at least one of the described IP devices.

[0119] The radio transceiver 3050 can transmit or receive wireless signals via an antenna. For example, the radio transceiver 3050 can convert wireless signals received via the antenna into signals that can be processed by the application processor 3010.

[0120] Therefore, the application processor 3010 can process the signal output from the radio transceiver 3050 and send the processed signal to the display 3030. Furthermore, the radio transceiver 3250 can convert the signal output from the application processor 3010 into a wireless signal and output the converted wireless signal to an external device via an antenna.

[0121] The input device 3040 is a device capable of inputting control signals for controlling the operation of the application processor 3010 or data to be processed by the application processor 3010, and can be implemented as a pointing device such as a touchpad and computer mouse, keypad or keyboard.

[0122] According to an embodiment, the application processor 3010 may include a DVFS controller that controls a plurality of sub-blocks and the operating conditions of the plurality of sub-blocks. (Refer to the above...) Figures 1 to 13 The DVFS controller can adjust operating conditions based on the power consumed by multiple sub-blocks.

[0123] Although not in Figure 14 As shown, but may further include a clock management unit that provides clock signals to various components included in the communication device 3000 and a power management unit that provides power supply voltage. The clock management unit can output a clock signal having a frequency adjusted according to the control of the DVFS controller, and the power management unit can output a power supply voltage having an amplitude adjusted according to the control of the DVFS controller.

[0124] In the art, it is conventional to describe and illustrate embodiments in terms of blocks that perform one or more described functions. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and may optionally be driven by firmware and / or software. For example, the circuitry may be embodied in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmable microprocessors and associated circuitry), or a combination of dedicated hardware to perform some functions of the block, and may be implemented by a processor to perform other functions of the block. Each block of an embodiment may be physically divided into two or more interactive and discrete blocks without departing from the scope of this disclosure. Similarly, the blocks of an embodiment may be physically combined into more complex blocks without departing from the scope of this disclosure. Aspects of an embodiment may be implemented by instructions stored in a non-transitory storage medium and executed by a processor.

[0125] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit, comprising: Multiple sub-blocks, configured to process instructions based on operation conditions; Multiple activity counters are configured to count activity time, which is the time of each processing instruction in the multiple sub-blocks; A total counter is configured to count the total activity time of at least one of the plurality of sub-blocks that is active. as well as Dynamic Voltage and Frequency Regulation (DVFS) controller, configured as follows: Calculate the workload of the multiple sub-blocks; The energy consumed by the plurality of sub-blocks during the sampling period is calculated by multiplying the activity time of each of the plurality of sub-blocks by the individual power consumption; The total power consumption of the multiple sub-blocks during the sampling period is calculated by dividing the sum of the energy consumed by the multiple sub-blocks by the total activity time; Calculate the power utilization rate based on the total power consumption; as well as The operating conditions of the multiple sub-blocks are adjusted based on the ratio of workload to power utilization.

2. The integrated circuit according to claim 1, wherein, The DVFS controller obtains the workload based on the ratio of the sampling period to the time of activity of at least one of the plurality of sub-blocks.

3. The integrated circuit according to claim 1, wherein, The DVFS controller obtains the power factor corresponding to each of the plurality of sub-blocks by referring to a power factor table stored in external memory, and uses the power factor and operating conditions to calculate individual power consumption.

4. The integrated circuit according to claim 3, wherein, The operating conditions are the frequency of the clock signal applied to the plurality of sub-blocks or the amplitude of the power supply voltage applied to the plurality of sub-blocks.

5. The integrated circuit according to claim 4, further comprising: A gating circuit is used to selectively provide clock signals or power supply voltages to the plurality of sub-blocks using gating control signals, wherein... Each of the plurality of activity counters counts the activity time based on a gating control signal.

6. The integrated circuit according to claim 1, wherein: The plurality of sub-blocks includes: The first sub-block is configured to process instructions according to a first clock signal; and The second sub-block is configured to process instructions according to a second clock signal, and When the frequency of the first clock signal, which is adjusted based on the individual power consumption of the first sub-block, exceeds the reference value, at least one of the second sub-blocks processes the instructions assigned to at least one of the first sub-blocks.

7. The integrated circuit according to claim 1, wherein, Each of the plurality of sub-blocks is one of a central processing unit (CPU) core, a graphics processing unit (GPU) core, a neural processing unit (NPU) core, or an image signal processor (ISP) core.

8. A method of operating an integrated circuit, the integrated circuit comprising a plurality of sub-blocks for processing instructions according to operating conditions, the method comprising: The total activity time of at least one of the plurality of sub-blocks is counted by a total counter. The workload is determined based on the ratio of the sampling period to the total activity time of at least one of the plurality of sub-blocks being active; The energy consumed by the plurality of sub-blocks during the sampling period is calculated by multiplying the activity time of each of the plurality of sub-blocks by the individual power consumption; The total power consumption of the multiple sub-blocks during the sampling period is calculated by dividing the sum of the energy consumed by the multiple sub-blocks by the total activity time; The power utilization rate is obtained based on the total power consumption of the multiple sub-blocks during the sampling period; as well as Adjust operating conditions based on the ratio between workload and power utilization.

9. The method according to claim 8, wherein, Obtaining power utilization includes: Obtain the sub-activity time of each of the plurality of sub-blocks during the sampling period; The average power consumption of the multiple sub-blocks during the sampling period is calculated based on the sub-activity time; and Power utilization is calculated based on the ratio between average power consumption and the predetermined maximum allowable power.

10. The method according to claim 9, wherein, The operating conditions are the frequency of the clock signal applied to the plurality of sub-blocks or the amplitude of the power supply voltage applied to the plurality of sub-blocks.

11. The method according to claim 10, wherein, The sub-activity time is obtained by calculating the sub-activity time based on a clock signal applied to the plurality of sub-blocks or a gating control signal used to control the blocking of the power supply voltage.

12. The method according to claim 9, wherein, The calculation of average power consumption includes: The power coefficient corresponding to each of the plurality of sub-blocks is obtained by referring to the power coefficient table; The power factor and operating conditions are used to calculate the individual power consumption of each of the plurality of sub-blocks during the sampling period; The energy consumed by the plurality of sub-blocks is calculated based on the power consumption and sub-activity time of each of the plurality of sub-blocks; and Average power consumption is calculated by dividing the energy by the total activity time.

13. A computing system, comprising: Multiple sub-blocks, each configured as a processing instruction; An activity counter, corresponding to each of the multiple sub-blocks and configured to count the sub-activity time, where the sub-activity time is the activity time of each corresponding sub-block; A total counter is configured to count the total activity time of at least one activity in the plurality of sub-blocks; A clock management unit is configured to generate clock signals to be applied to the plurality of sub-blocks; A power management unit is configured to generate a power supply voltage applied to the plurality of sub-blocks; as well as Dynamic Voltage and Frequency Regulation (DVFS) Controller: Calculate the workload of the multiple sub-blocks; The energy consumed by the plurality of sub-blocks during the sampling period is calculated by multiplying the activity time of each of the plurality of sub-blocks by the individual power consumption; The total power consumption of the multiple sub-blocks during the sampling period is calculated by dividing the sum of the energy consumed by the multiple sub-blocks by the total activity time; Calculate the power utilization rate based on the total power consumption; as well as Control the clock management unit or power management unit so that the frequency of the clock signal or the amplitude of the power supply voltage is adjusted based on the ratio of workload to power utilization.

14. The computing system according to claim 13, further comprising: The timer is configured to generate a DVFS trigger signal for each sampling period and output the DVFS trigger signal to the DVFS controller. The DVFS controller responds to DVFS trigger signals to control the clock management unit or the power management unit.

15. The computing system according to claim 14, further comprising: The memory is configured to store a power factor table, which indicates the power factor corresponding to each of the plurality of sub-blocks, wherein The DVFS controller calculates the power consumed by the multiple sub-blocks during the sampling period by referring to a power factor table.

16. The computing system according to claim 13, further comprising: The gating circuit is configured to output a gating control signal, which is used to control the clock signal or power supply voltage to be supplied to the plurality of sub-blocks, wherein... The DVFS controller obtains sub-activity times based on gating control signals.

17. The computing system according to claim 13, wherein: The plurality of sub-blocks includes: The first sub-block has relatively low performance; and The second sub-block has relatively high performance, and When the frequency of the clock signal reaches the reference frequency, at least one of the second sub-blocks processes the instructions assigned to at least one of the first sub-blocks.

18. The computing system according to claim 13, wherein, The DVFS controller determines the frequency of the clock signal after the sampling period based on the ratio of total power consumption to the maximum allowable power that the plurality of sub-blocks can consume during the sampling period.

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