Test apparatus, test system and method of operating a test system

Abstract

A test device, a test system, and an operating method of the test system are provided. The test device is configured to test a device under test (DUT) that performs interface communication of a pulse amplitude modulation (PAM) operation, and includes a logic generation / determination device configured to generate a plurality of bits corresponding to a test pattern, a first driver and a second driver configured to generate a first non-return-to-zero (NRZ) signal and a second NRZ signal according to logic states of first and second bits among the plurality of bits, respectively, and output the generated first and second NRZ signals via first and second channels, respectively. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. The first high level and the second high level are different from each other.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0168723, filed with the Korean Intellectual Property Office on December 4, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a test apparatus, and more specifically, to a test apparatus, a test system, and a method of operating the test system for performing interchangeability tests between a non-return-to-zero (NRZ) interface and a pulse amplitude modulation (PAM) interface. Background Technology

[0004] The storage device can receive commands, addresses, and data from external devices. New signaling methods can be used to improve the efficiency of the storage device's input / output interface, and a method based on signals comprising one of three or more voltage levels to improve the efficiency of the input / output interface is proposed.

[0005] During the mass production of storage devices, the storage devices can be tested as devices under test (DUTs) by testing equipment. Summary of the Invention

[0006] The present invention provides an operational method for interface communication based on an N-level pulse amplitude modulation (PAM) method by utilizing a test apparatus that performs (e.g., includes, supports, etc.) interface communication based on 2-level pulse amplitude modulation (hereinafter referred to as non-return-to-zero (NRZ)).

[0007] According to some exemplary embodiments of the present invention, a test apparatus configured to test a device under test (DUT) performing pulse amplitude modulation (PAM) interface communication may include: a logic generation / determination device configured to generate a plurality of bits corresponding to a test mode; a first driver configured to generate a first non-return-to-zero (NRZ) signal based on the logic state of the first bit among the plurality of bits and output the generated first NRZ signal via a first channel; and a second driver configured to generate a second NRZ signal based on the logic state of a second bit among the plurality of bits and output the generated second NRZ signal via a second channel, wherein the first NRZ signal has a first high level or a first low level depending on the logic state of the first bit, and the second NRZ signal has a second high level or a second low level depending on the logic state of the second bit, wherein the first high level is different from the second high level.

[0008] According to some exemplary embodiments of the present invention, a test system may include: a test board configured to communicate with a test apparatus including a non-return-to-zero (NRZ) interface circuit, wherein the test board is configured to: receive, via a first channel, a first NRZ signal having a voltage level according to a logic state of a first bit of a plurality of bits from the test apparatus, and via a second channel, a second NRZ signal having a voltage level according to a logic state of a second bit of the plurality of bits from the test apparatus. The test board may include a superposition line configured to provide a pulse amplitude modulation (PAM) signal as a test signal to a device under test (DUT), the PAM signal being generated to satisfy PAM operation by voltage superposition of the first NRZ signal and the second NRZ signal.

[0009] According to some exemplary embodiments of the present invention, an operating method of a test system configured to test a device under test (DUT) performing pulse amplitude modulation (PAM) interface communication may include: outputting a first non-return-to-zero (NRZ) signal via a first channel according to the logic state of the first bit of a plurality of bits corresponding to a test mode; outputting a second NRZ signal via a second channel according to the logic state of the second bit of the plurality of bits; and providing a PAM signal satisfying the PAM operation, generated by voltage superposition of the first NRZ signal and the second NRZ signal, as a test signal to the DUT, wherein the first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit, wherein the first high level is different from the second high level. Attached Figure Description

[0010] Example embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A and Figure 1B This is a block diagram illustrating a test system according to some example embodiments;

[0012] Figure 2 and Figure 3 This is a block diagram of a test system that illustrates an implementation example of the test apparatus;

[0013] Figure 4 This is a block diagram illustrating an implementation example of a test system according to some example embodiments;

[0014] Figure 5A and Figure 5BThis is a diagram illustrating the logical state of signals transmitted via a first channel, a second channel, and a first DUT channel according to some example embodiments;

[0015] Figure 6 and Figure 7 This is a flowchart of the operation method of a test system according to some example embodiments;

[0016] Figure 8 This is a table showing examples of voltage levels of signals output by a test apparatus according to some example embodiments;

[0017] Figure 9 , Figure 10A and Figure 10B This is a diagram illustrating an example of how a test apparatus determines the logical state of data based on test results, according to some example embodiments;

[0018] Figure 11 , Figure 12A and Figure 12B This is a diagram illustrating an example of a test apparatus determining a logic state according to some example embodiments;

[0019] Figure 13 This is a block diagram illustrating an example of communication between a test apparatus and a storage device that is a DUT, according to some example embodiments;

[0020] Figure 14A , Figure 14B , Figure 15A , Figure 15B and Figure 15C These are diagrams illustrating operational examples of a test system based on some example embodiments; and

[0021] Figure 16 This is a block diagram of an electronic device according to some example embodiments. Detailed Implementation

[0022] In the following, exemplary embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

[0023] It will be understood that, as described in this article, the “level” of a signal, voltage, etc., can be interchangeably referred to as the magnitude of the signal, voltage, etc.

[0024] As described herein, when an operation is described as being performed "by" performing another operation, it will be understood that the operation may be performed "based on" the other operation, which may include performing the other operation alone or in combination with other other operations.

[0025] When the terms “approximately” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value includes a tolerance of ±10% around the stated value. When a range is specified, the range includes all values ​​within a range such as 0.1% increments.

[0026] Figure 1A and Figure 1B This is a block diagram illustrating a test system 10 according to some example embodiments.

[0027] Reference Figure 1A and Figure 1B A test system 10 for testing various types of semiconductor devices, such as memory devices, may include a test apparatus 11 and a test board 12 on which one or more devices under test (DUTs) 14 for performing tests are mounted. Furthermore, various components related to test operations may be mounted on the test board 12, and the test board 12 may be equipped with the test apparatus 11 and the DUTs 14, but the example embodiments are not limited thereto. For example, because the test apparatus 11 is arranged outside the test board 12, the test apparatus 11 can communicate with the DUTs 14 via the test board 12. In some example embodiments, because the DUTs 14 are arranged outside the test board 12, the DUTs 14 can communicate with the test apparatus 11 via the test board 12.

[0028] From the perspective of providing an interface between the test device 11 and the DUT 14, the test board 12 can be referred to as an interface board. For example, the test board 12 may include a printed circuit board (PCB), and the PCB may include multiple wires for transmitting electrical signals, such that test signals from the test device 11 can be transmitted to the DUT 14 via the multiple wires, or test results from the DUT 14 can be transmitted to the test device 11 via the multiple wires. In some example embodiments, at least a portion of the multiple wires may be associated with signaling between the test device 11 and the DUT 14, and the configuration including at least a portion of the multiple wires may be referred to as a wiring circuit (or wiring circuit area 13).

[0029] Test apparatus 11 may include test logic 11_1 and I / F circuit (NRZ) 11_2. Although Figure 1A and Figure 1B Not shown, but the test apparatus 11 may also include various components such as: a communication device for communicating with an external host requesting the test, a memory for temporarily storing various information related to various tests, and a power supply circuit for supplying power to the DUT 14. Furthermore, the test system 10 according to some example embodiments may be defined differently, and as an example, may be defined as... Figure 1A and Figure 1B The configuration components of the test system 10, other than the DUT 14.

[0030] According to some example embodiments, the test apparatus 11 may include semiconductor chips such as field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), and application processors (APs), and as... Figure 1A and Figure 1B As shown, when multiple DUTs 14 are mounted on the test board 12, test operations on multiple DUTs 14 can be performed in parallel. Furthermore, when testing one DUT 14, the test device 11 can provide test signals to the DUT 14 in parallel via multiple channels, and can receive test results from one DUT 14 in parallel via multiple channels.

[0031] The testing process for determining whether a semiconductor device is defective can be performed at various stages of the semiconductor process and may include, for example, wafer-level testing and post-wafer-level testing. Wafer-level testing may correspond to testing a single semiconductor die at the wafer level. Furthermore, post-wafer-level testing may be testing a semiconductor die before packaging, or testing a semiconductor package in which a semiconductor die (or semiconductor chip) has already been packaged. In some example embodiments, testing a semiconductor package may be testing a semiconductor package comprising multiple semiconductor chips.

[0032] In some example embodiments, DUT 14 may include various types of semiconductor devices, and as an example, may include a memory device having an array of semiconductor memory cells. For example, the memory device may include dynamic random access memory (RAM) (DRAM), such as double data rate (DDR) synchronous DRAM (SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, and rambus DRAM (RDRAM). In some example embodiments, the memory device may include non-volatile memory, such as flash memory, magnetic RAM (MRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), and resistive RAM (ReRAM).

[0033] The DUT 14 may include an interface (I / F) circuit 14_1 to receive test signals from the test apparatus 11 and store the received test signals in a memory cell array (not shown). Furthermore, the DUT 14 can read the data stored in the memory cell array and provide test results to the test apparatus 11 via the I / F circuit (PAM) 14_1 based on the read data.

[0034] According to some example embodiments, DUT 14 may include a storage device that interfaces with a modulated signal based on an N-level pulse amplitude modulation (hereinafter referred to as PAM-N, where N is a natural number equal to or greater than 3) method. As indicated herein, the PAM-N method performed by a DUT including DUT 14 can be interchangeably referred to as PAM-N operation. For example, the I / F circuit (PAM) 14_1 of DUT 14 can perform interface communication by using one of the PAM-4, PAM-6, PAM-8, or PAM-16 methods. The PAM-N method can be a modulation method for transmitting multiple bits within a unit interval. In some example embodiments, the unit interval may correspond to the symbol period of a signal used to transmit a symbol. For example, when data is modulated using the PAM-N method, a symbol may include multiple bits. In the following description, example embodiments will be based on the PAM-4 method, which includes 2 bits for each symbol among various PAM-N methods, and for ease of description, PAM-4, PAM-6, PAM-8, and PAM-16 signals will be collectively referred to as PAM signals. Therefore, it will be understood that test apparatus 11 can be configured to test DUT 14 of an interface communication that is performing (and / or configured to perform) Pulse Amplitude Modulation (PAM) operation.

[0035] In some example embodiments, the test apparatus 11 may include an I / F circuit (NRZ) 11_2 that interfaces with a signal modulated based on a 2-level PAM (hereinafter referred to as NRZ) method. The NRZ method may be a modulation method for transmitting one bit during a unit interval, and when a signal is modulated by the NRZ method, a symbol may include one bit.

[0036] According to some example embodiments, testing of the DUT 14 employing a PAM-4 interface can be performed using a test apparatus 11 that does not support the PAM-4 interface. In other words, testing of the PAM-4-based DUT 14 can be performed using the NRZ-based test apparatus 11 without replacing the major components of the expensive PAM-4 modulation method.

[0037] According to some example embodiments, the test board 12 may include a superposition line that superimposes the voltages of 2-level voltage signals (hereinafter referred to as NRZ signals) transmitted from the test device 11 as test signals via two or more channels. For example, since the test device 11 transmits test signals via multiple channels, the wiring circuit area 13 may include one or more superposition lines (e.g., a first superposition line 13_1 and a second superposition line 13_2), and both the first superposition line 13_1 and the second superposition line 13_2 can provide the DUT 14 with a PAM signal having a voltage level that satisfies the level of the PAM-4 interface by superimposing the voltages of at least two NRZ signals. For example, the voltage level of the PAM signal may have any one of four levels corresponding to logic states "00", "01", "10" and / or "11". For example, the test board 12 may be configured to receive a first NRZ signal having a voltage level according to the logic state of the first bit of a plurality of bits from the test device 11 via a first channel CH1, and a second NRZ signal having a voltage level according to the logic state of the second bit of a plurality of bits from the test device 11 via a second channel CH2, and the test board 12 may include a superposition line (e.g., a first superposition line 13_1) configured to provide a pulse amplitude modulation (PAM) signal as a test signal to the device under test (DUT) 14, the PAM signal being generated based on voltage superposition of the first NRZ signal and the second NRZ signal to satisfy PAM operation.

[0038] According to some example embodiments, both the first overlay line 13_1 and the second overlay line 13_2 can receive NRZ signals via multiple channels. Including Figure 1A and Figure 1BIn some example embodiments of the example implementation, the following example is shown: a first overlay line 13_1 can receive NRZ signals via first to Nth channels CH1 to CHN (N is any natural number greater than 1, such as any natural number equal to or greater than 3), and a second overlay line 13_2 can receive NRZ signals via (N+1) to (N+M)th channels CH(N+1) to CH(N+M) (M is any natural number greater than 1, such as any natural number equal to or greater than 3). The first overlay line 13_1 can voltage overlay N NRZ signals to establish a PAM signal, which is a test signal with a voltage level satisfying the PAM-N method, and can provide the PAM signal to DUT 14 via any DUT channel (e.g., the first DUT channel DCH1). In addition, the second superposition line 13_2 can superimpose the voltages of M NRZ signals to establish a PAM signal, which is a test signal with a voltage level that satisfies the PAM-N method, and can provide the PAM signal to DUT 14 via another DUT channel (e.g., the second DUT channel DCH2).

[0039] As an example of a test operation, test logic 11_1 can generate multiple bits of data as a test pattern, and each bit can have a logic state based on its value. I / F circuit (NRZ) 11_2 can generate and output an NRZ signal based on the logic states of the multiple bits. The NRZ signal can be converted into a PAM signal via a first superposition line 13_1 and a second superposition line 13_2, and the PAM signal can be provided to DUT 14. As an example of the PAM-4 method, a PAM signal provided to DUT 14 can include 2 bits, the logic state of which can be determined by the demodulation process of the PAM signal in DUT 14, and the 2-bit data determined according to each PAM signal can be stored in the memory cell array in DUT 14.

[0040] However, test results from DUT 14 can be provided to test apparatus 11 via wiring circuit area 13. For example, when DUT 14 generates PAM signals based on the PAM-4 method, the PAM signals transmitted via each channel of DUT 14 may include data with 2 bits. Additionally, PAM signals can be provided jointly (in parallel) to at least two channels via wiring circuit area 13 and can be provided to the I / F circuit (NRZ) 11_2 of test apparatus 11. Test apparatus 11 can determine the logic state based on the NRZ interface for the received PAM signals, and as an example, determination operations can be performed on multiple channels to which the same PAM signal has been transmitted, based on different criteria. For example, the same PAM signal can be received via first to Nth channels CH1 to CHN, and a determination operation for the PAM signal can be performed in response to each of the first to Nth channels CH1 to CHN. Because different determination criteria are applied to the first to Nth channels CH1 to CHN, the determination results in at least two of the first to Nth channels CH1 to CHN may be different. In other words, the logical state of the 2-bit data of the PAM signal can be determined based on a combination of the results determined in the first to Nth channels CH1 to CHN.

[0041] According to the example embodiments described above, the PAM-based DUT 14 can be tested using a test apparatus 11 based on an existing NRZ interface (e.g., a test apparatus with NRZ I / F circuitry instead of PAM I / F circuitry), without using a separate apparatus (such as an ASIC or FPGA) for interface conversion between the NRZ interface of the test apparatus 11 and the PAM interface of the DUT 14. Therefore, it is not necessary to include a separate test apparatus supporting the PAM interface (e.g., a test apparatus specifically including PAM I / F circuitry), and the PAM-based DUT can be tested without the expense of adding separate, expensive components for conversion between different interfaces.

[0042] For example, a test apparatus 11 having an NRZ interface circuit (e.g., an I / F circuit (NRZ) 11_2) but not a PAM interface circuit can be configured to test a DUT 14 having a PAM interface circuit (e.g., an I / F circuit (PAM-4) 14_1) based on at least including and / or implementing the above-described logic generation / determination device, the first driver, and the second driver. The logic generation / determination device is configured to generate a plurality of bits corresponding to a test mode. The first driver is configured to generate a first non-return-to-zero (NRZ) signal based on the logic state of the first bit among the plurality of bits and output the generated first NRZ signal via a first channel. The second driver is configured to generate a second NRZ signal based on the logic state of the second bit among the plurality of bits and output the generated second NRZ signal via a second channel. The first NRZ signal has a first high level or a first low level based on the logic state of the first bit, and the second NRZ signal has a second high level or a second low level based on the logic state of the second bit, wherein the first high level and the second high level are different.

[0043] By providing such a test apparatus configured to test a device under test (DUT) performing pulse amplitude modulation (PAM) operation, the costs associated with developing the test apparatus (including manufacturing costs) and replacing key components related to signal generation in existing test apparatuses can be reduced, thereby improving the practicality and cost-effectiveness of manufacturing the test apparatus and the DUT (based on reducing the costs associated with testing such an apparatus during its manufacturing process). Furthermore, the costs associated with manufacturing the storage device and / or electronic device 888 as described herein can be reduced based on providing such a test apparatus (e.g., based on the reduced costs associated with testing, where the testing is provided by a test apparatus associated with manufacturing the storage device and / or electronic device 888).

[0044] In some example embodiments, a test apparatus 11 having NRZ interface circuitry (e.g., I / F circuitry (NRZ) 11_2) and excluding PAM interface circuitry is configured to test a DUT 14 having PAM interface circuitry (e.g., I / F circuitry (PAM-4) 14_1), thereby allowing the first and second NRZ signals to be voltage-superimposed via superimposed lines formed on the test board 12 and provided to the DUT 14 as test signals, further reducing the aforementioned costs associated with the test apparatus, the DUT, the manufactured storage device, and / or the manufactured electronic device.

[0045] In some example embodiments, the test board 12 is configured to receive a first NRZ signal having a voltage level according to the logic state of the first bit of a plurality of bits from the test device 11 via a first channel CH1, and a second NRZ signal having a voltage level according to the logic state of the second bit of a plurality of bits from the test device 11 via a second channel CH2. Furthermore, a superposition line (e.g., a first superposition line 13_1) further included in the test board 12 is configured to provide a pulse amplitude modulation (PAM) signal as a test signal to the device under test (DUT) 14. This PAM signal is generated based on the voltage superposition of the first and second NRZ signals to satisfy PAM operation. The above configuration of the test board 12 and the further included superposition line can further enable the test device 11, which has NRZ interface circuitry (e.g., I / F circuitry (NRZ) 11_2) but does not include PAM interface circuitry, to be configured to test a DUT that has PAM interface circuitry (e.g., I / F circuitry (PAM-4) 14_1) but may not include NRZ interface circuitry. 14. Conduct testing to reduce the aforementioned costs associated with the test equipment, DUT, manufactured storage device and / or manufactured electronic device.

[0046] Still refer to Figure 1A and Figure 1B In some example embodiments, the test apparatus 11 may be configured to determine the logic state and / or voltage level of a test result based on signals (e.g., PAM signals) received from the DUT 14 described herein. The received signals (e.g., PAM signals) may be received after the test apparatus 11 and / or the test board 12 provide a PAM signal to the DUT 14 based on a first NRZ signal and a second NRZ signal (e.g., voltage superimposed on them to generate and / or provide a PAM signal), and / or the received signals (e.g., PAM signals) may be received in response to the test apparatus 11 and / or the test board 12 providing a PAM signal to the DUT 14 based on the first NRZ signal and the second NRZ signal. Based on the determined logic state and / or voltage level of the test result, the test apparatus 11 and / or the test board 12 may determine whether the DUT has passed or failed the test. Figure 1BAs shown, the test system 10 (e.g., test apparatus 11 and / or test board 12) may include a communication interface 11_3, such as a wired or wireless communication interface or transceiver. The test apparatus 11 and / or test board 12 may generate a pass / fail signal based on a determination that the DUT has passed or failed the test (this can be based on a logical state determining the test result). For example, a DUT can be determined to have passed the test based on a logical state of "11" for the test result. In another example, a DUT can be determined to have failed the test based on a logical state of "00" for the test result. The test apparatus 11 and / or test board 12 may be configured to generate a pass / fail signal indicating whether the DUT has passed or failed the test, and may send this pass / fail signal to an external device via interface 11_3. In some example embodiments, interface 11_3 may be included in the circuitry of the test apparatus 11 (e.g., the test control circuitry of the test apparatus according to some example embodiments).

[0047] Reference Figure 1B The test system 10 can be communicatively coupled to a manufacturing system 99, which is configured to manufacture (e.g., mass-produce) electronic devices 888 based on one or more input storage devices associated with the DUT 14. Such input storage devices include the DUT 14 and / or storage devices 777 that may be associated with the DUT 14 (e.g., the DUT 14 may be selected from a batch of storage devices including storage devices 777 to serve as a representative of the storage devices 777 for testing by the test system 10). The electronic device 888 can be a storage device such as the DUT 14 and / or the storage devices 777 associated with the DUT 14, and / or an electronic device that includes storage devices such as the DUT 14 and / or the storage devices 777 associated with the DUT 14 as components thereof. Manufacturing system 99 may include control device 99_1, actuator device 99_2, and manufacturing apparatus 99_3 (which may be one or more manufacturing apparatuses) configured to manufacture electronic device 888 based on the use of one or more storage devices as input. Actuator device 99_2 may be a motorized manipulator, arm, deflector arm, door, etc., configured to selectively manipulate, guide, and / or transfer one or more storage devices to the input area of ​​manufacturing apparatus 99_3, or to selectively manipulate, guide, and / or transfer one or more storage devices from manufacturing apparatus 99_3 to a waste area (e.g., from the manufacturing process) so that they are not included in the manufactured electronic device 888.

[0048] In some example embodiments where the manufactured electronic device 888 is storage device 777 and / or DUT 14, manufacturing device 99_3 and actuator device 99_2 may be the same device, and the manufacture of electronic device 888 may include selectively directing / forwarding certain storage devices (e.g., 777 and / or 14) to a finished product area, or transferring / discarding certain storage devices (e.g., 777 and / or 14) to a separate (e.g., discard) area. In some example embodiments where the manufactured electronic device 888 includes storage device 777 and / or DUT 14 as its components, manufacturing device 99_3 and actuator device 99_2 may be different devices, and manufacturing device 99_3 may be used to assemble electronic device 888, which includes one or more storage devices (e.g., device 14 and / or 777) associated with DUT 14 as one or more of its components. In some example embodiments, actuator device 99_2 may be part of manufacturing apparatus 99_3, such that commands transmitted to control actuator device 99_2 may be transmitted to manufacturing apparatus 99_3.

[0049] Still refer to Figure 1B In some example embodiments, the control device 99_1 may receive a pass / fail signal generated at the test system 10, indicating whether the DUT 14 has passed or failed the test. In response to processing the pass / fail signal, the control device 99_1 may selectively include one or more storage devices in the storage devices input to the manufacturing apparatus 99_3, or selectively exclude one or more storage devices from the storage devices input to the manufacturing apparatus 99_3, to manufacture one or more electronic devices 888.

[0050] In some example embodiments, the control device 99_1 may command the actuator device 99_2 and / or the manufacturing device 99_3 to selectively include the DUT 14 itself as an input to the manufacturing device 99_3 so as to be included in the manufactured electronic device 888, or to prevent the DUT 14 from being input to the manufacturing device 99_3 (e.g., transferred, discarded, etc.) and thus prevent it from being included in the manufactured electronic device 888.

[0051] In some example embodiments, DUT 14 may be selected from storage device 777 (which may be a specific batch of manufactured storage devices) and may be tested at test system 10 as a representative of storage device 777. Therefore, it will be understood that storage device 777 may be associated with DUT 14 (e.g., based on a DUT 14 selected from a batch of storage devices that also include storage device 777). Control device 99_1 may, in response to DUT 14 being determined to pass the test, command actuator device 99_2 and / or manufacturing device 99_3 to selectively include a specific storage device 777 (which may include DUT 14, or may not include DUT 14) as input to manufacturing device 99_3 in the manufactured electronic device 888, or, in response to DUT 14 being determined to fail the test, selectively exclude that specific storage device from being included as input to manufacturing device 99_3 in the manufactured electronic device 888.

[0052] Therefore, the control device 99_1 can cause the manufacturing system 99 to manufacture one or more electronic devices 888, such that, based on the determined logic state and / or voltage level of the test results received from the DUT 14 (e.g., at the test device 11), one or more specific storage devices associated with the DUT 14 (which may include storage device 777 and may include or may not include the DUT 14) are selectively included or excluded from one or more manufactured electronic devices 888.

[0053] like Figure 1A As shown, the test system 10 may or may not be communicatively coupled to the manufacturing system 99, which is configured to manufacture (e.g., mass-produce) electronic devices 888 based on one or more input storage devices associated with the DUT 14. Such devices include the DUT 14 and / or storage devices 777 that may be associated with the DUT 14. In some example embodiments, the aforementioned pass / fail signals generated at the test system 10, indicating whether the DUT 14 has passed or failed the test, can be used to selectively allocate one or more storage devices (e.g., in response to a pass signal), selectively redirect one or more storage devices to be repaired (e.g., in response to a failure signal), selectively redirect one or more storage devices to be set / discarded (e.g., in response to a failure signal), etc. One or more storage devices may be distributed as finished products and / or as components of other products. One or more storage devices may include the DUT 14 and / or storage devices that may be associated with the DUT 14 (e.g., Figure 1B(Storage device 777 shown). Selective allocation and / or redirection can be controlled by a control device, which can be implemented by one or more instances of processing circuitry as described herein, and can be communicatively coupled to at least the test system, such that the control device is configured to receive and process pass / fail signals generated at the test system 10. Such a control device can be internal or external to one or more devices of the test system 10.

[0054] Figure 2 and Figure 3 This is a block diagram of a test system 100 illustrating an implementation example of the test apparatus 110. Figure 2 and Figure 3 In this context, DUT 130 can be installed inside interface board 120 (or test board), but for ease of illustration, DUT 130 is shown outside interface board 120.

[0055] Reference Figure 2 The test system 100 may include a test apparatus 110 and an interface board 120, and the DUT 130 may be mounted on the test system 100 for performing tests. The test apparatus 110 may be configured to test the DUT 130 performing (and / or configured to perform) pulse amplitude modulation (PAM) operation of the interface communication. The test apparatus 110 may include test control circuitry 111, logic generation / determination device 112, transmit (Tx) / receive (Rx) circuitry 113, and power supply 114, and the interface board 120 may include overlay lines according to the above example embodiment. Figure 2 For ease of explanation, the superimposed lines can be simply shown as electrical wiring. Furthermore, from the perspective of controlling electrical signals using pins (not shown) connected to the test device 110 across multiple channels, the Tx / Rx circuit 113 can be referred to as a pin circuit.

[0056] Figure 2 At least some components of the test apparatus 110 shown can be provided Figure 1A and Figure 1B The test logic 11_1 shown, and / or by Figure 1A and Figure 1B The test logic 11_1 shown is implemented. For example, Figure 2At least a portion of the components of the test apparatus 110 shown can constitute test logic 11_1, and the logic generation / determination device 112 can be provided (e.g., included and / or implemented in) the test logic 11_1. Furthermore, the Tx / Rx circuit 113 can be a component included in the I / F circuit 14_1 in the above example embodiment. The test control circuit 111 can control all operations of the test apparatus 110, and the logic generation / determination device 112 can generate data with logic states corresponding to the test mode. For example, the logic generation / determination device 112 can be configured to generate multiple bits corresponding to the test mode. Furthermore, the logic generation / determination device 112 can perform a logic determination operation on the test results received via the Tx / Rx circuit 113, and based on this performance, can determine the logic states of the bits included in the test results.

[0057] The Tx / Rx circuit 113 may include: circuitry that converts data having a logic 0 or logic 1 value and outputs it as a physical electrical signal (e.g., logic high voltage and logic low voltage) applied to the DUT 130; and circuitry (e.g., a comparator) that compares the level of the physical electrical signal with at least one reference voltage to determine the logic state of the electrical signal provided by the DUT 130. As an example, the test apparatus 110 may include multiple pins for transmitting and receiving test signals and test results via multiple channels, and the Tx / Rx circuit 113 may include one or more drivers and one or more comparators corresponding to each pin.

[0058] For example, the test signal transmitted from the test apparatus 110 via two channels (e.g., the first channel CH1 and the second channel CH2) can be a voltage superimposed via the interface board 120 (e.g., a voltage superimposed via superimposed lines formed on the interface board 120) and provided as a test signal to the DUT 130. The superimposed lines of the interface board 120 can include: a first conductor CL1 connected to the first channel CH1, a second conductor CL2 connected to the second channel CH2, and a third conductor CL3 electrically connected to both the first conductor CL1 and the second conductor CL2 (e.g., electrically connected to both the first conductor CL1 and the second conductor CL2). The first conductor CL1 and the second conductor CL2 can be referred to as dual transmission lines that transmit different signals respectively. To ensure the high-speed transmission characteristics of the test signal, the first conductor CL1 and the second conductor CL2 can be arranged to have the same or substantially the same length.

[0059] However, a third conductor CL3 can be provided via any channel of DUT 130, and the test signal transmitted via the third conductor CL3 can have a voltage level that satisfies the PAM-4 method as described in the example embodiment above. The third conductor CL3 can be configured to transmit a PAM signal generated based on the voltage superposition of a first NRZ signal and a second NRZ signal received via the first channel CH1 and the second channel CH2, respectively. The third conductor CL3 can be connected to DUT 130 via a DUT channel (e.g., the first DUT channel DCH1) and can provide the PAM signal to DUT 130 via the DUT channel. Furthermore, power supply 114 can provide power to DUT 130 for test operations, and, as an example, power can be provided to DUT 130 via interface board 120.

[0060] In some example embodiments, such as Figure 3 As shown, the transmit (Tx) / receive (Rx) circuit 113 may include: a first driver Tx_1 and a first comparator Rx_1 connected to the first channel CH1 (collectively referred to as the first Tx / Rx circuit 113_1), and a second driver Tx_2 and a second comparator Rx_2 connected to the second channel CH2 (collectively referred to as the second Tx / Rx circuit 113_2). Based on the bit values ​​of data from the logic generation / determination device 112, the first driver Tx_1 may output a first signal having a level corresponding to one of two voltage levels (e.g., the first bit). Furthermore, the second driver Tx_2 may output a second signal having a level corresponding to the second bit of the two voltage levels. Additionally, according to some example embodiments, the voltage level of the first signal output by the first driver Tx_1 may be different from the voltage level of the second signal output by the second driver Tx_2, such that the superimposed signal satisfies the PAM method. For example, the first driver Tx_1 can generate a first non-return-to-zero (NRZ) signal based on the logic state of the first bit among multiple bits, and output the generated first NRZ signal through the first channel CH1. The second driver Tx_2 can generate a second NRZ signal based on the logic state of the second bit among multiple bits, and output the generated second NRZ signal through the second channel CH2.

[0061] Furthermore, the third signal generated according to the PAM method and provided as a test result can be transmitted to the first wire CL1 and the second wire CL2 via the third wire CL3, and the third signal can be jointly provided to the first channel CH1 and the second channel CH2 via the first wire CL1 and the second wire CL2 respectively. Each of the first comparator Rx_1 and the second comparator Rx_2 can perform a determination operation on the common third signal based on different conditions. The logic state of the third signal with 2 bits of data from DUT 130 can be determined by combining the first comparator Rx_1 and the second comparator Rx_2.

[0062] Figure 4 This is a block diagram illustrating an implementation example of a test system 200 according to some exemplary embodiments of the concept proposed in this invention. Figure 4 The image shows an example of an interface board 221, which includes overlay lines, provided separately on a test board 220.

[0063] The test system 200 may include a test device 210 and a test board 220, and the test device 210 may include test logic 211 and I / F circuitry (NRZ) 212. Furthermore, the test board 220 may include a slot (not shown) on which the DUT is mounted together with the interface board 221, and... Figure 4 The diagram shows a DUT 222 mounted on a slot. Furthermore, according to the example embodiment described above, the DUT 222 may include an I / F circuit (PAM-4) 222_1 that interfaces for performing (e.g., configured to perform) a PAM-4 method.

[0064] According to the above example embodiments, NRZ signals transmitted via two channels can be voltage superimposed in interface board 221, thus providing DUT 222 with a PAM signal that satisfies the PAM method. For example, two NRZ signals transmitted via first channel CH1 and second channel CH2 can be superimposed to generate a PAM signal, and similarly to some example embodiments, two NRZ signals transmitted via third channel CH3 and fourth channel CH4 can be voltage superimposed to generate a PAM signal.

[0065] According to some example embodiments, interface board 221 can be installed in test board 220, and different interface boards 221 can be installed depending on the interface type of the DUT 222 to be tested. Figure 4In some example embodiments of the example implementation, an example is shown where the interface board 221 with the superimposed lines described in the example embodiments above is installed when the DUT 222 performs interface communication using the PAM method. However, when the DUT 222 performs interface communication using the NRZ method, an interface board 221 with wiring arranged therein can be installed, allowing the NRZ signal to be transmitted in parallel via multiple channels without voltage superposition. Furthermore, the test apparatus 210 can set the output operation of the test signal (e.g., the voltage level of the NRZ signal) differently for some example embodiments of the PAM method test DUT 222 and some example embodiments of the NRZ method test DUT 222 by using control operations of the internal test mode. Additionally, the determination operation of the data logic state can be set differently based on the test results. The test apparatus 210 can determine whether the DUT 222 passes the test and can generate a pass / fail signal indicating whether the DUT 222 passes the test based on the logic state of the data determined according to the test results.

[0066] In the following example embodiments, the terms test board and interface board may be used interchangeably because the test system can be implemented in various ways. However, the scope of the example embodiments is not limited by these terms.

[0067] Figure 5A and Figure 5B This is a diagram illustrating the logic states of signals transmitted via a first channel CH1, a second channel CH2, and a first DUT channel DCH1 according to some example embodiments. According to the above example embodiments, the first channel CH1 and the second channel CH2 can transmit a first NRZ signal and a second NRZ signal, and the first DUT channel DCH1 can transmit a superimposed signal to the DUT. As described above, the first driver of the Tx / Rx circuit 113 can generate a first NRZ signal based on the logic state of the first bit among a plurality of bits generated by the logic generation / determination device 112, and outputs the generated first NRZ signal via the first channel CH1. The second driver of the Tx / Rx circuit 113 can generate a second NRZ signal based on the logic state of the second bit among a plurality of bits generated by the logic generation / determination device 112, and outputs the generated second NRZ signal via the second channel CH2.

[0068] Reference Figure 5A and Figure 5B It can generate test patterns including multiple bits, and can generate a first NRZ signal and a second NRZ signal in parallel, in units of two bits, for multiple bits. The high level of logic state "1" of the first NRZ signal and the high level of logic state "1" of the second NRZ signal can be set to be different from each other, as shown in the following example embodiment. Figure 5A and Figure 5BExample: A high level v1 corresponding to a logic state "1" of the first NRZ signal can correspond to approximately 1.2V, and a high level v2 corresponding to a logic state "1" of the second NRZ signal can correspond to approximately 0.6V. Therefore, the first NRZ signal can have a first high level (e.g., v1) or a first low level depending on the logic state of the first bit (from which the first driver can generate the first NRZ signal), and the second NRZ signal can have a second high level (e.g., v2) or a second low level depending on the logic state of the second bit (from which the second driver can generate the second NRZ signal), wherein the first high level can be different from the second high level (e.g., different in magnitude) (e.g., v1 can be greater than v2, at least as...). Figure 5A (As shown). In Figure 5A In this example, both the first low level and the second low level are 0V, but the example embodiment is not limited to this, and in some example embodiments, the first low level and the second low level may be different from each other (e.g., they may have different magnitudes).

[0069] According to the above example embodiment, since the first NRZ signal and the second NRZ signal are output via the first channel CH1 and the second channel CH2, a superimposed signal including 2 bits of information can be transmitted via the first DUT channel DCH1. The level of the superimposed signal can correspond to the average of the high level v1 of the first NRZ signal and the high level v2 of the second NRZ signal. Figure 5B As shown, when the logic states of the first NRZ signal and the second NRZ signal are "0", a superimposed signal corresponding to logic state "00" can be transmitted. Furthermore, similar to these example embodiments, when the logic state of the first NRZ signal is "0" and the logic state of the second NRZ signal is "1", a superimposed signal corresponding to logic state "01" can be transmitted. Additionally, when the logic state of the first NRZ signal is "1" and the logic state of the second NRZ signal is "0", a superimposed signal corresponding to logic state "10" can be transmitted. Moreover, when the logic states of the first NRZ signal and the second NRZ signal are "1", a superimposed signal corresponding to logic state "11" can be transmitted. Furthermore, as... Figure 5B As shown, the voltage levels of the superimposed signals corresponding to the logic states “00”, “01”, “10” and “11” can be different from each other, and example embodiments with voltage levels of approximately 0V, approximately 0.3V, approximately 0.6V and approximately 0.9V corresponding to the logic states are shown as examples.

[0070] Figure 6 and Figure 7 This is a flowchart of the operation method of a test system according to some example embodiments. Figure 6 This illustrates an operational example of a sample embodiment of the test apparatus providing test signals to the DUT. Figure 7An operational example of a sample embodiment of how test results from a DUT are provided to a test apparatus is shown.

[0071] Figures 6 to 7 The illustrated operating method can be performed by any example embodiment of the testing system and / or manufacturing system (including any embodiment of the test board and / or testing apparatus and / or manufacturing system control apparatus). In some example embodiments, Figure 6 and / or Figure 7 The operations shown can be omitted from the operating methods of the test system, and / or can be used in conjunction with... Figures 6 to 7 The different execution orders shown. In some example embodiments, Figures 6 to 7 At least some of the operations of the method shown can be performed sequentially (e.g., during execution). Figure 6 Execute the method after Figure 7 The methods) and / or at least partially parallelized (e.g., at least partially parallelized in a given test system and / or manufacturing system). Figure 6 and Figure 7 (Methods).

[0072] Including Figure 6 and Figure 7 In some example embodiments of the illustrated embodiments, the test system may include a test apparatus that does not support (e.g., does not include) a PAM-4 interface (e.g., a PAM-4 interface circuit), and a DUT including a PAM-4 interface circuit as the test object, which can transmit various signals between the test apparatus and the DUT via a test board (or interface board). In the following, it is assumed that the test apparatus outputs a first NRZ signal via a first channel and a second NRZ signal via a second channel, and a DUT channel (e.g., a first DUT channel) corresponding to the first and second channels is arranged, through which the DUT receives test signals.

[0073] The testing device can generate a first NRZ signal to be output via a first channel based on the logic state of the first bit data among multiple bits corresponding to the test mode, and generate a second NRZ signal to be output via a second channel based on the logic state of the second bit data among multiple bits corresponding to the test mode. The first and second NRZ signals can be voltage-superimposed on the interface board. The superimposed signal can have a waveform satisfying the PAM-4 method, therefore the levels of the first and second NRZ signals can be correlated with each other. Therefore, the first and second NRZ signals can be voltage-superimposed via superimposed lines formed on the test board and provided as a test signal to the DUT, wherein the test signal can have a voltage level satisfying the PAM-4 method (e.g., PAM-4 operation). For example, the second NRZ signal can be generated based on the level of the first NRZ signal (S11).

[0074] Since the NRZ signal includes only one bit of information, each of the first and second NRZ signals can have two voltage levels depending on the logic state. For example, the first NRZ signal can have a first high level or a first low level depending on the logic state of the first bit, and the second NRZ signal can have a second high level or a second low level depending on the logic state of the second bit. The first high level can be different from the second high level, and the first low level can be different from the second low level. For example, when setting the levels of the first and second NRZ signals, the second high level can be decreased while the first high level is increased. Similarly, in these example embodiments, the second low level can be set to decrease when the first low level is increased.

[0075] The testing device can output a first NRZ signal via a first channel (S12), output a second NRZ signal via a second channel (S13), and generate a PAM signal satisfying the PAM method by voltage superimposing the first and second NRZ signals on each other via the superposition line of the interface board (S14). It will be understood that operation S14 may include generating a PAM signal satisfying the PAM method by voltage superimposing the first and second NRZ signals. The PAM signal can be provided to the DUT via a first DUT channel, for example, as a test signal (S15). The DUT can determine the logic state with 2 bits of data based on the PAM signal by using a PAM-based processing operation (e.g., demodulation operation) on the PAM signal.

[0076] In some example embodiments, reference is made to Figure 7 The test apparatus can receive PAM signals according to the PAM method from the DUT, and as an example, it can receive PAM signals jointly via the first channel and the second channel (S21). For example, PAM signals from the DUT including information with at least 2 bits can be transmitted as test results to the overlay line of the test board, and test results can be provided to the test apparatus in parallel via the first channel CH1 and the second channel CH2.

[0077] For example, the PAM signal may include a signal having any one of four voltage levels, and the logic state of the PAM signal may be determined by a comparator arranged in each of the first and second channels. As an example, a determination operation (S22) may be performed on the PAM signal received via the first channel according to a first condition, and a determination operation (S23) may be performed on the PAM signal received via the second channel according to a second condition.

[0078] Because different determination conditions are applied to the same PAM signal, various combinations of determination results can be generated. For example, the test apparatus can perform a logic state determination operation based on the NRZ interface, and correspondingly, two determination results (e.g., logic low and logic high) can occur in each of the first and second channels. For example, a first comparison can be performed between a PAM signal receiving from the DUT via the first channel as a test result, including information with at least 2 bits, and a first reference voltage, and a second comparison can be performed between a PAM signal receiving via a second channel in parallel with the first channel and a second reference voltage. The level of the first reference voltage may be different from the level of the second reference voltage. The logic state of the PAM signal can be determined by combining the determination results of the first channel and the second channel (S24), for example, a logic state with 2 bits of data can be determined based on the level of the PAM signal. For example, the logic state of the test result based on a combination of the first comparison result of the first comparison and the second comparison result of the second comparison can be determined.

[0079] Based on the processing of the logic state determined in S24, it can be selectively determined whether the DUT that received the PAM signal from it in S21 has passed the test (S25). This selective determination in S25 may include generating a pass / fail signal indicating whether the DUT has passed the test based on the determined logic state. For example, in response to determining that the logic state with 2 bits of data corresponds to "00", it can be determined in S25 that the DUT has failed the test and a pass / fail signal indicating that the DUT has failed the test can be generated. In another example, in response to determining that the logic state with 2 bits of data corresponds to "11", it can be determined in S25 that the DUT has passed the test and a pass / fail signal indicating that the DUT has passed the test can be generated.

[0080] One or more storage devices may be selectively included or excluded from one or more inputs in the manufacturing process for manufacturing one or more electronic devices (S26). For example, the pass / fail signal generated in S25 may be transmitted to a control device (e.g., control device 99_1) that can process the pass / fail signal to determine whether the DUT has failed the test.

[0081] In response to determining that the DUT has passed the test, the control device may generate one or more control signals to selectively include (e.g., transfer, guide, etc.) one or more specific storage devices (e.g., storage device 777 and / or the DUT itself) associated with the DUT as part of the input to the manufacturing system 99 (e.g., the input to the manufacturing device 99_3), such that the specific storage device is or is included in one or more manufactured electronic devices 888 manufactured by the manufacturing device 99_3. The one or more storage devices selectively included as input may include: the DUT from which it receives the PAM signal in S21, and / or may be individual storage devices (e.g., a batch of storage devices from which DUTs are selected for testing).

[0082] In response to determining that the DUT has failed the test, the control device may generate one or more control signals to selectively exclude (e.g., transfer, discard, etc.) one or more specific storage devices (e.g., storage device 777 and / or the DUT itself) associated with the DUT from becoming part of the input of the manufacturing system 99 (e.g., the input of the manufacturing device 99_3), such that the specific storage device is excluded from or not included in one or more manufactured electronic devices 888. The excluded device may be selectively transferred (e.g., via actuator device 99_2 and / or manufacturing device 99_3) to a discard area for disposal, repair, etc. The selectively excluded one or more storage devices may include: the DUT from which the PAM signal is received in S21, and / or may be individual storage devices (e.g., a batch of storage devices from which DUTs are selected for testing).

[0083] One or more electronic devices (e.g., electronic device 888) may be manufactured based on the selective inclusion of input storage devices (S27), which may include or exclude storage device 777 and / or DUT based on the results of S26. As a result, testing of the DUT may selectively affect which storage devices are included in the manufactured electronic device 888. To reiterate, one or more methods according to some example embodiments may include manufacturing one or more electronic devices (e.g., electronic device 888) such that one or more specific storage devices associated with the DUT (e.g., storage device 777 and / or the DUT itself) are selectively included or excluded in one or more manufactured electronic devices based on the logical state of the determined test results.

[0084] Figure 8This is a table illustrating examples of voltage levels of signals output by a test apparatus according to some example embodiments. According to the above example embodiments, the test apparatus can output a first NRZ signal via a first channel CH1 and a second NRZ signal via a second channel CH2, and according to the above example embodiments, the first NRZ signal and the second NRZ signal can be voltage-superimposed on the interface board. Furthermore, the length of the first wire connected to the first channel CH1 can be the same as or substantially the same as the length of the second wire connected to the second channel CH2, and the superimposed signal corresponding to the average level of the first NRZ signal and the second NRZ signal can be provided to the DUT via a third wire.

[0085] According to some example embodiments, the voltage level of the first NRZ signal may differ from the voltage level of the second NRZ signal. As an implementation example, the test apparatus may include a first driver and a second driver. The first driver is used to generate the first NRZ signal based on the logic state of the first bit in the bits generated by the generation / determination device, and the second driver is used to generate the second NRZ signal based on the logic state of the second bit in the bits generated by the generation / determination device. To adjust the levels of the first and second NRZ signals, a method for adjusting the levels of the power supply voltages supplied to the first and second drivers may be applied. In some example embodiments, as another implementation example, the example embodiment may be implemented by providing the same power supply voltage to the first and second drivers, and each of the first and second drivers drives the signal using different driving capabilities from each other.

[0086] The first and second NRZ signals can be configured such that the voltage level of the superimposed signal matches the four voltage levels required in the PAM-4 method when their levels are voltage superimposed. For example, assuming the power supply voltage of the driver set in the PAM-4 interface circuit is VDDQ, the values ​​of the four voltage levels required by the PAM-4 method can be 0, 1 / 3*VDDQ, 2 / 3*VDDQ, and VDDQ. In some example embodiments, when the first and second NRZ signals are voltage superimposed, the level of the superimposed voltage of the first and second NRZ signals can be set to have the aforementioned four voltage levels. Furthermore, the aforementioned power supply voltage VDDQ can have voltage levels according to various specifications of the semiconductor device as the DUT, and as an example, when the DUT includes a memory device with a memory cell array, it can have a voltage level of approximately 1.2V or a similar value.

[0087] exist Figure 8The example illustrates two examples applicable to the exemplary embodiments, and the levels can be set such that the sum of the high levels of the first NRZ signal and the high levels of the second NRZ signal is 2*VDDQ. As an example, in the first case (Case 1), the first NRZ signal may have a value of 4 / 3*VDDQ or 0 depending on the logical state of the data, and the second NRZ signal may have a value of 2 / 3*VDDQ or 0 depending on the logical state of the data. In some exemplary embodiments, the level of the first NRZ signal may differ from the level of the second NRZ signal depending on the value of the 2 bits of data to be transmitted. For example, when the test device transmits data "11", the first NRZ signal may have a level of 4 / 3*VDDQ depending on any bit of the data "11" (e.g., the most significant bit (MSB)), and the second NRZ signal may have a level of 2 / 3*VDDQ depending on the other bit (e.g., the least significant bit (LSB)). Furthermore, similar to these exemplary embodiments, when the test device transmits data "10", the first NRZ signal may have a level of 4 / 3*VDDQ and the second NRZ signal may have a level of 0. In addition, when the test device transmits data "01", the first NRZ signal can have a level of 0 and the second NRZ signal can have a level of 2 / 3*VDDQ. When the test device transmits data "00", the first NRZ signal and the second NRZ signal can have a level of 0.

[0088] However, Case 2 illustrates an example where the logic high and logic low levels of the first and second NRZ signals are set to be different from each other. For example, the first NRZ signal may have a value of 4 / 3*VDDQ or 2 / 3*VDDQ depending on the logic state of the data, while the second NRZ signal may have a value of 2 / 3*VDDQ or -2 / 3*VDDQ depending on the logic state of the data. Even in Case 2, when the first and second NRZ signals are voltage superimposed, the superimposed signal can have four levels: 0, 1 / 3*VDDQ, 2 / 3*VDDQ, and VDDQ.

[0089] Therefore, it will be understood that in some example embodiments, the first NRZ signal and the second NRZ signal are voltage superimposed via superposition lines formed on the test board and provided to the DUT as a test signal, and the test signal has a voltage level that satisfies PAM-4 operation. The test signal may have any one of the following levels based on the PAM-4 method: power supply voltage (VDDQ), 2 / 3*VDDQ, 1 / 3*VDDQ, or 0V. The sum of the first high level and the second high level may be 2*VDDQ.

[0090] However, the levels of the first NRZ signal and the second NRZ signal according to the example embodiment are not limited to... Figure 8The values ​​shown can be varied within the constraints of the voltage superposition level meeting the voltage level required by the PAM-4 method.

[0091] Figure 9 , Figure 10A and Figure 10B This is a diagram illustrating an example of how a test apparatus determines the logical state of data based on test results, according to some example embodiments.

[0092] Figure 9 An example implementation of the comparator set up in the test apparatus is shown, and... Figure 9 The diagram illustrates an example of determining three or more states of a signal in each channel when two or more comparators are arranged corresponding to each channel. Additionally, each comparator can compare a test result received via the corresponding channel with a specific reference voltage and output the comparison result. Furthermore, in some example embodiments, a logic high state, a logic low state, and a high resistance (Hi-Z) state can be determined based on the comparison results of the two comparators corresponding to each channel.

[0093] The data read from the DUT can be modulated using the PAM-4 method and can be provided as the test result Res_T to the first channel CH1 and the second channel CH2 via the interface board. Furthermore, the first comparator COM1 and the second comparator COM2 can be arranged corresponding to the first channel CH1. The first comparator COM1 outputs the comparison result of the test result Res_T with the first high reference voltage VrefH1, and the second comparator COM2 outputs the comparison result of the test result Res_T with the first low reference voltage VrefL1. Furthermore, the third comparator COM3 and the fourth comparator COM4 can be arranged corresponding to the second channel CH2. The third comparator COM3 outputs the comparison result of the test result Res_T with the second high reference voltage VrefH2, and the fourth comparator COM4 outputs the comparison result of the test result Res_T with the second low reference voltage VrefL2.

[0094] According to some example embodiments, the level of the first high reference voltage VrefH1 can be different from the level of the second high reference voltage VrefH2. Furthermore, the level of the first low reference voltage VrefL1 can be different from the level of the second low reference voltage VrefL2. Therefore, even if the same test result Res_T is received, different determination results can be generated in the first channel CH1 and the second channel CH2, and the logic state of the 2-bit test result Res_T can be determined by combining these determination results.

[0095] The testing device can further determine whether the DUT from which data is read (e.g., receiving PAM signals) passes the test based on the processing of the determined logical state of the test result Res_T, and can generate a pass / fail signal indicating whether the DUT passes the test based on the determined logical state of the test result Res_T. The pass / fail signal can be transmitted to a control device (e.g., control device 99_1), which can cause one or more storage devices to be selectively included in the manufacturing process (as input to manufacturing device 99_3), or excluded from the manufacturing process (e.g., transferred, discarded, etc.) (e.g., not as input to manufacturing device 99_3).

[0096] The following will refer to Figure 10A and Figure 10B The description refers to the determination of operations based on some example embodiments. Including... Figure 10A and Figure 10B In some example embodiments, two feasible examples are shown. In the first case, Case 1, the following example is shown: the level of the first high reference voltage VrefH1 is 5 / 6 * VDDQ, the level of the first low reference voltage VrefL1 and the second high reference voltage VrefH2 is 3 / 6 * VDDQ, and the level of the second low reference voltage VrefL2 is 1 / 6 * VDDQ. In the second case, Case 2, the following example is shown: the level of the first high reference voltage VrefH1 is 5 / 6 * VDDQ, the level of the second high reference voltage VrefH2 and the second low reference voltage VrefL2 is 3 / 6 * VDDQ, and the level of the first low reference voltage VrefL1 is 1 / 6 * VDDQ.

[0097] Reference Figure 10BIn Case 1, the four voltage levels of the test result Res_T can be determined based on the results of the determination of the first channel CH1 and the second channel CH2, and a 2-bit logic state can be determined using these results. For example, when the results of the determination of the first channel CH1 and the second channel CH2 are logic high (H), the level of the test result Res_T can be determined to correspond to VDDQ, and the logic state of the test result Res_T can be "11". Additionally, when the results of the determination of the first channel CH1 correspond to Hi-Z and the results of the determination of the second channel CH2 correspond to logic high (H), the level of the test result Res_T can be determined to correspond to 2 / 3*VDDQ, and the logic state of the test result Res_T is "10". Furthermore, when the results of the determination of the first channel CH1 correspond to logic low (L) and the results of the determination of the second channel CH2 correspond to Hi-Z, the level of the test result Res_T can be determined to correspond to 1 / 3*VDDQ, and the logic state of the test result Res_T is "01". In addition, when the determination result of the first channel CH1 and the second channel CH2 is logic low L, it can be determined that the level of the test result Res_T corresponds to 0, and the logic state of the test result Res_T can be "00".

[0098] Similar to Case 1, in Case 2, based on the conditions set in Case 2, when the determination result of the first channel CH1 corresponds to Hi-Z and the determination result of the second channel CH2 corresponds to logic low L, the level of the test result Res_T can be determined to correspond to 1 / 3*VDDQ.

[0099] Therefore, in some example embodiments, the test apparatus according to some or any example embodiments may include a first comparator COM1 and a second comparator COM2, which are configured to receive, in parallel, a PAM signal including at least 2 bits of information from the DUT via a first channel CH1 as a test result Res_T. The test apparatus may also include a third comparator COM3 and a fourth comparator COM4, ​​which are configured to receive the PAM signal in parallel via a second channel CH2. The first comparator COM1 may be configured to compare the PAM signal with a first high reference voltage VrefH1, the second comparator COM2 may be configured to compare the PAM signal with a first low reference voltage VrefL1, the third comparator COM3 may be configured to compare the PAM signal with a second high reference voltage VrefH2, and the fourth comparator COM4 may be configured to compare the PAM signal with the second low reference voltage VrefL2. The level of the first high reference voltage VrefH1 may be different from the level of the second high reference voltage VrefH2. In some example embodiments, the level of the first low reference voltage VrefL1 may be different from the level of the second low reference voltage VrefL2. In some example embodiments, the logic generation / determination device of the test apparatus (e.g., logic generation / determination device 112) may determine the logic state of the test result Res_T based on the comparison results of the first, second, third, and fourth (e.g., first to fourth) comparators COM1 to COM4. In some example embodiments, any one of the logic high, logic low, or high resistance (Hi-Z) states of the PAM signal may be determined based on the combination of the comparison results of the first comparator COM1 and the second comparator COM2, and any one of the logic high, logic low, or Hi-Z states of the PAM signal may be determined based on the combination of the comparison results of the third comparator COM3 and the fourth comparator COM4, ​​and the combination of the comparison results of the first comparator COM1 and the second comparator COM2 may be different from the combination of the comparison results of the third comparator COM3 and the fourth comparator COM4.

[0100] Figure 11 , Figure 12A and Figure 12B This is a diagram illustrating an example of a test apparatus determining a logic state according to some example embodiments. Figure 11 , Figure 12A and Figure 12B In this example, since one comparator is arranged for each channel, an example of applying the example embodiment is shown when only logic high or logic low can be determined in each channel.

[0101] Reference Figure 11 The data read from the DUT can be modulated according to the PAM-4 method and provided as the test result Res_T to the first channel CH1 and the second channel CH2 via the interface board. The test result Res_T can also be provided to the first comparator COM1 corresponding to the first channel CH1 and the second comparator COM2 corresponding to the second channel CH2. The first comparator COM1 outputs the comparison result of the test result Res_T with the first reference voltage Vref1, and the second comparator COM2 outputs the comparison result of the test result Res_T with the second reference voltage Vref2. Therefore, both the first comparator COM1 and the second comparator COM2 can output a logic high (H) or logic low (L) comparison result based on the level of the input test result Res_T.

[0102] According to some example embodiments, the level of the first reference voltage Vref1 may be different from the level of the second reference voltage Vref2. Furthermore, to determine the four voltage levels according to the PAM-4 waveform, two read operations can be performed on the same data from the DUT, and the level of the test result Res_T can be determined based on the combination of the comparison results in the first read operation and the comparison results in the second read operation. Moreover, at least one of the aforementioned first reference voltage Vref1 or second reference voltage Vref2 may have a varying level in both the first and second read operations. Figure 11 The diagram shows a reference voltage generator Vref Gen for generating a first reference voltage Vref1 and a second reference voltage Vref2, and also shows an example of test logic controlling the levels of the first reference voltage Vref1 in a first read operation and the second reference voltage Vref2 in a second read operation.

[0103] Reference Figure 12A and Figure 12B The following example illustrates how, based on the results of the first and second read operations, the four voltage levels of the test result Res_T are logically determined. For example, as... Figure 12A As shown, assuming that in the first read operation, the levels of the first reference voltage Vref1 and the second reference voltage Vref2 are 3 / 6*VDDQ, while in the second read operation, the level of the first reference voltage Vref1 is 5 / 6*VDDQ and the level of the second reference voltage Vref2 is 1 / 6*VDDQ, it can be based on the following... Figure 12B The combination of the results shown determines the level of the test result Res_T.

[0104] For example, when the determination results of the first channel CH1 and the second channel CH2 are both logic high (H) in the first and second read operations, the level of the test result Res_T can be determined to correspond to VDDQ and the logic state of the test result Res_T is "11". Additionally, when the determination results of the first channel CH1 and the second channel CH2 are logic high (H) in the first read operation, and the determination results of the first channel CH1 and the second channel CH2 are logic low (L) in the second read operation, the level of the test result Res_T can be determined to correspond to 2 / 3 * VDDQ, and the logic state of the test result Res_T is "10". Furthermore, when the determination results of the first channel CH1 and the second channel CH2 are logic low (L) in the first read operation, and the determination results of the first channel CH1 and the second channel CH2 are logic high (H) in the second read operation, the level of the test result Res_T can be determined to correspond to 1 / 3 * VDDQ, and the logic state of the test result Res_T is "01". In addition, when the determination results of the first channel CH1 and the second channel CH2 are both logic low L in the first read operation and the second read operation, it can be determined that the level of the test result Res_T corresponds to 0, and the logic state of the test result Res_T is "00".

[0105] According to the above example embodiment, the four voltage levels of the test result Res_T according to the PAM-4 method can be determined based on two reference voltages (e.g., Vref1 and Vref2). Therefore, since the number of circuit elements (e.g., comparators) arranged corresponding to each channel of the test device is reduced, the implementation area and power consumption of the test device can be reduced. In addition, the manufacturing cost of the test device can be reduced.

[0106] Therefore, in some example embodiments, the test apparatus according to some or any example embodiments may include a first comparator COM1, which is configured to receive a PAM signal including at least 2 bits of information from the DUT via a first channel CH1 and compare the PAM signal with a first reference voltage Vref. The test apparatus according to some or any example embodiments may also include a second comparator COM2, which is configured to receive the PAM signal in parallel with the first comparator COM1 via a second channel CH2 and compare the PAM signal with a second reference voltage Vref2. The test result Res_T is continuously provided to the first comparator COM1 and the second comparator COM2 when the same data from the DUT is read in a first read operation and a second read operation. The level of at least one of the first reference voltage Vref1 or the second reference voltage Vref2 may be changed (e.g., varied) during the first read operation and the second read operation. In some example embodiments, in one of the first read operation or the second read operation, the level of the first reference voltage Vref1 and the level of the second reference voltage Vref2 can be set to be the same, while in the other of the first read operation or the second read operation, the level of the first reference voltage Vref1 can be set to be different from the level of the second reference voltage Vref2. In some example embodiments, the logic generation / determination device of the test apparatus (e.g., logic generation / determination device 112) can determine the logic state of the test result Res_T based on the comparison result of the first comparator COM1 and the comparison result of the second comparator COM2 combined in the first read operation, and the comparison result of the first comparator COM1 and the comparison result of the second comparator COM2 combined in the second read operation.

[0107] Therefore, based on a test apparatus that includes at least the first comparator COM1 and the second comparator COM2 configured to operate as described above, the number of circuit elements in the test apparatus can be reduced, thereby reducing the implementation area and power consumption of the test apparatus, and further reducing the manufacturing cost of the test apparatus.

[0108] The testing apparatus can also determine whether the DUT from which data is read (e.g., receiving a PAM signal) passes the test by processing the logic state of the determined test result Res_T, and can generate a pass / fail signal indicating whether the DUT has passed the test based on the logic state of the determined test result Res_T. For example, in response to determining that the level of the test result Res_T corresponds to 0 and the logic state of the test result Res_T is "00", the testing apparatus can determine that the DUT has failed the test and can generate a pass / fail signal indicating that the DUT has failed the test. In another example, in response to determining that the level of the test result Res_T corresponds to VDDQ and the logic state of the test result Res_T is "11", the testing apparatus can determine that the DUT has passed the test and can generate a pass / fail signal indicating that the DUT has passed the test. The pass / fail signal can be transmitted to a control device (e.g., control device 99_1), which can cause one or more storage devices to be selectively included in the manufacturing process (as input to manufacturing device 99_3) or excluded from the manufacturing process (e.g., transferred, discarded, etc.) (e.g., not as input to manufacturing device 99_3).

[0109] Figure 13 This is a block diagram illustrating an example of communication between a test apparatus 310 and a storage device 320, which is a DUT, according to some example embodiments. Figure 13 As shown, the test system 300 may include a test device 310, and a storage device 320, serving as a DUT, may be mounted on a test board. According to an example embodiment, the test system 300 may further include a test board comprising one or more overlay lines, but in… Figure 13 The details related to it are omitted in the text.

[0110] The storage device 320 may include an I / F circuit 321, a control logic circuit 322, and a memory cell array 323. The I / F circuit 321 may communicate with the test device 310 via first to eighth pins P11 to P18. As an example, the storage device 320 may receive a chip enable signal nCE via the first pin P11, and when the chip enable signal nCE is enabled, it may transmit and receive various signals via the second to eighth pins P12 to P18.

[0111] Furthermore, the storage device 320 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE via pins P12 to P14. Additionally, the storage device 320 can transmit and receive input / output signals DQ via pin P17, and as an example, can receive commands / addresses / data or send data to the test device 310 via pin P17. For example, pin P17 may include multiple pins, and the input / output signals DQ can be transmitted via multiple signal lines.

[0112] As an example, storage device 320 can obtain command CMD during the enable phase of command latch enable signal CLE based on the toggle timing of write enable signal nWE. Furthermore, storage device 320 can obtain address ADDR during the enable phase of address latch enable signal ALE based on the toggle timing of write enable signal nWE.

[0113] The storage device 320 can receive a read enable signal nRE via pin 5 P15, receive a data strobe signal DQS via pin 6 P16, or send the data strobe signal DQS to the test device 310. During the data output operation of the storage device 320, data DATA can be sent to the test device 310 based on the switching timing of the data strobe signal DQS. Furthermore, during the data reception operation of the storage device 320, data DATA can be obtained from the test device 310 based on the switching timing of the data strobe signal DQS. Additionally, the storage device 320 can send a ready / busy output signal nR / B to the test device 310 via pin 8 P18. For example, when the storage device 320 is in a busy state (i.e., when internal operations of the storage device 320 are being performed), the storage device 320 can send the ready / busy output signal nR / B to the test device 310.

[0114] In some example embodiments, control logic circuitry 322 can control all operations of storage device 320. Control logic circuitry 322 can generate control signals for controlling other components of storage device 320 based on commands and / or addresses CMD / ADDR obtained from I / F circuitry 321. For example, control logic circuitry 322 can store data DATA in storage cell array 323, or can generate various control signals for reading data DATA from storage cell array 323. Storage cell array 323 can store data DATA obtained from I / F circuitry 321 under the control of control logic circuitry 322. Storage cell array 323 can output the stored data DATA to I / F circuitry 321 under the control of control logic circuitry 322.

[0115] In some example embodiments, the test device 310 may include an I / F circuit 311 and communicate with the storage device 320 via first to eighth pins P21 to P28. The first to eighth pins P21 to P28 of the test device 310 may correspond to the first to eighth pins P11 to P18 of the storage device 320, and since detailed descriptions of its communication operation are provided with reference to the description given regarding the storage device 320, they are omitted here.

[0116] According to some example embodiments, referring to the I / F circuit 311 of the test apparatus 310, the pins for which the superposition line is applied can be applied to at least some of the first to eighth pins P21 to P28 described above. As an example, when the superposition line of the example embodiment is applied to the seventh pin P27 for transmitting command / address / data, the signals transmitted via the multiple pins included in the seventh pin P27 can be voltage superimposed via the superposition line. For example, NRZ signals can be transmitted from two of the multiple pins included in the seventh pin P27, and the NRZ signals from the two pins can be voltage superimposed and provided to the storage device 320 as a PAM signal satisfying the PAM-4 method. Furthermore, according to some example embodiments, the test apparatus 310 can output NRZ signals related to command / address / data, and the storage device 320 can receive PAM signals related to command / address / data. Therefore, in some example embodiments, the test apparatus 310 may perform tests on the DUT (e.g., storage device 320) based on transmitting commands, addresses and data to the DUT, and the first and second bits (whose logical states may be used to generate the first NRZ signal and the second NRZ signal described herein) may be any one of commands, addresses or data.

[0117] Figure 14A , Figure 14B , Figure 15A , Figure 15B and Figure 15C This is a diagram illustrating an operational example of a test system based on some example embodiments. Figure 14A , Figure 14B , Figure 15A , Figure 15B and Figure 15C The PAM-8 method can be shown among various PAM-N interface methods.

[0118] Reference Figure 14A Since NRZ signals are output via channels CH1 to CH3, and the voltages of the three NRZ signals are superimposed via the superposition line, the level of the superimposed signal can correspond to the average value (v1+v2+v3) / 3 of the high-level first to third NRZ signals. Furthermore, the voltage levels of the first to third NRZ signals can be set such that the superimposed signal satisfies the PAM method.

[0119] In some example embodiments, for example, as referenced Figures 6 to 7 The described operation method of the test system, in addition to including outputting a first NRZ signal based on the logic state of the first bit among a plurality of bits corresponding to the test mode via a first channel and a second NRZ signal based on the logic state of the second bit among a plurality of bits corresponding to the test mode via a second channel, may further include: outputting a third NRZ signal based on the logic state of the third bit among a plurality of bits via a third channel, wherein the third NRZ signal may have a third high level or a third low level depending on the logic state of the third bit. A PAM signal may be generated based on voltage superposition of the first to third NRZ signals, and the PAM signal may be provided to the DUT as a test signal (S14-S15). When voltage superposition of the first to third NRZ signals, the test signal may have any one of N voltage levels, where N may be an integer equal to or greater than 5. According to the implementation example, in the PAM-8 method, the superimposed signal can include 3 bits of information, and the superimposed signal can have the following values ​​as 8 levels: 0, 1 / 7*VDDQ, 2 / 7*VDDQ, 3 / 7*VDDQ, 4 / 7*VDDQ, 5 / 7*VDDQ, 6 / 7*VDDQ, and VDDQ. Furthermore, as... Figure 14B As shown, to ensure that the first to third NRZ signals have the aforementioned voltage levels when the voltages are superimposed, the first NRZ signal transmitted via the first channel CH1 can have a value of 12 / 7*VDDQ or 0 according to the logic state, the second NRZ signal transmitted via the second channel CH2 can have a value of 6 / 7*VDDQ or 0 according to the logic state, and the third NRZ signal can have a value of 3 / 7*VDDQ or 0 according to the logic state. However, the example embodiment is not limited to this. Figure 14A and Figure 14B The example shown can be used to apply the PAM-6, PAM-8, and PAM-16 methods by setting various other voltage levels.

[0120] exist Figure 15A , Figure 15B and Figure 15C The image shows an example of a testing setup processing test results corresponding to PAM-8 signals. Figure 15AThe following example is shown: a test result Res_T, including 3 bits of information, is provided jointly via the first to third channels CH1 to CH3, and comparators arranged corresponding to the first to third channels CH1 to CH3 receive the test result Res_T. The comparator of the first channel CH1 can compare the test result Res_T with a first reference voltage Vref1, the comparator of the second channel CH2 can compare the test result Res_T with a second reference voltage Vref2, and the comparator of the third channel CH3 can compare the test result Res_T with a third reference voltage Vref3.

[0121] exist Figure 15B The example shown illustrates the following: Three read operations are performed on the same data from the DUT, and a test result Res_T can be provided in each read operation. Furthermore, the levels of the first to third reference voltages Vref1 to Vref3 can vary. For example, in a comparison operation using the test result Res_T read in the first read operation, the levels of the first to third reference voltages Vref1 to Vref3 can be 7 / 14 * VDDQ. Additionally, in a comparison operation using the test result Res_T read in the second read operation, the level of the first reference voltage Vref1 can be 13 / 14 * VDDQ, the level of the second reference voltage Vref2 can be 11 / 14 * VDDQ, and the level of the third reference voltage Vref3 can be 9 / 14 * VDDQ. In addition, in the comparison operation of the test result Res_T read in the third read operation, the level of the first reference voltage Vref1 can be 5 / 14*VDDQ, the level of the second reference voltage Vref2 can be 3 / 14*VDDQ, and the level of the third reference voltage Vref3 can be 1 / 14*VDDQ.

[0122] By combining the results of the three comparison operations described above, the level of the test result Res_T can be determined. As an example, in... Figure 15C The following example is shown: based on what has already been used Figure 15B The logic state of the 3-bit test result Res_T is determined by the combination of logic states determined by the first to third reference voltages Vref1 to Vref3. For example, when the comparison results of the comparators of the first to third channels CH1 to CH3 in the first to third read operations are all logic high (H), the logic state of the test result Res_T can correspond to "111", and when the comparison results are all logic low (L), the logic state of the test result Res_T can correspond to "000". Furthermore, other logic states of the test result Res_T can be determined based on other combinations of comparison results of the comparators of the first to third channels CH1 to CH3 in the first to third read operations.

[0123] The testing apparatus can also determine whether the DUT from which data is read (e.g., receiving PAM signals) passes the test based on the logical state of the determined test result Res_T, and can generate a pass / fail signal indicating whether the DUT has passed the test based on the logical state of the determined test result Res_T. For example, in response to determining that the logical state of the test result Res_T corresponds to "000", the testing apparatus can determine that the DUT has failed the test and can generate a pass / fail signal indicating that the DUT has failed the test. In another example, in response to determining that the logical state of the test result Res_T corresponds to "111", the testing apparatus can determine that the DUT has passed the test and can generate a pass / fail signal indicating that the DUT has passed the test. The pass / fail signal can be transmitted to a control device (e.g., control device 99_1), which can cause one or more storage devices to be selectively included in the manufacturing process (as input to manufacturing device 99_3) or excluded from the manufacturing process (e.g., transferred, discarded, etc.) (e.g., not as input to manufacturing device 99_3).

[0124] However, the example embodiments are not limited to Figure 15A , Figure 15B and Figure 15C The example shown illustrates this. The first to third reference voltages Vref1 to Vref3 can be set to different levels in each read operation. Furthermore, based on other combinations of comparison results, the logic state of the test result Res_T can be determined. Additionally, according to the example embodiment described above, two or more comparators can be arranged to determine at least three states in each of the first to third channels CH1 to CH3, and the example embodiment for the PAM-8 method can set the reference voltage for each channel differently (e.g., high reference voltage and low reference voltage).

[0125] Figure 16 This is a block diagram of an electronic device according to some example embodiments. The electronic device may include and / or implement any electronic device and / or circuitry included in any of the example embodiments, including… Figure 1B The one or more manufactured electronic devices shown 888 Figure 1B The control device 99_1 shown Figure 1B Manufacturing apparatus 99_3 shown Figure 1B The actuator device 99_2 shown is an example.

[0126] Reference Figure 16Electronic device 1100 may include a processor 1120, a memory 1130, and an interface 1140 electrically coupled together via a bus 1110. Electronic device 1100 may include one or more manipulator / actuator devices 1150 that can be coupled to the bus 1110. Interface 1140 may be a communication interface (e.g., a wired or wireless communication transceiver). One or more manipulator / actuator devices 1150 may include actuators of actuator device 99_2 and / or manufacturing means 99_3 configured to selectively include or exclude one or more storage devices as inputs to manufacturing one or more electronic devices 888. One or more manipulator / actuator devices 1150 may include manufacturing means configured to manufacture one or more electronic devices 888.

[0127] The memory 1130, which may be a non-transitory computer-readable medium, may store instruction programs and / or other information. The memory 1130 may be a non-volatile memory such as flash memory, phase-change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM), or a volatile memory such as static RAM (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM). The processor 1120 may execute the stored instruction programs to perform one or more functions. For example, in the case where electronic device 1100 is included in and / or implements control device 99_1, processor 1120 may be configured to process pass / fail signals received from test system 10 to selectively include or exclude one or more storage devices as inputs to manufacturing device 99_3. Processor 1120 may be configured to generate outputs (e.g., commands to control actuator device 99_2 and / or manufacturing device 99_3) based on such processing.

[0128] Processor 1120 may include processing circuitry, such as hardware including logic circuitry, hardware / software combinations such as processors executing software, or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processor 1120 may be configured to generate output based on such processing (e.g., an image to be displayed on a display interface).

[0129] One or more of the processor 1120, memory 1130, interface 1140, and / or manipulator / actuator device 1150 may be included in, or implement one or more instances of the processing circuitry, such as hardware including logic circuitry, hardware / software combinations such as processors executing software, or combinations thereof. In some example embodiments, the one or more instances of the processing circuitry may include, but are not limited to, a central processing unit (CPU), application processor (AP), arithmetic logic unit (ALU), graphics processing unit (GPU), digital signal processor, microcomputer, field-programmable gate array (FPGA), system-on-a-chip (SoC), programmable logic unit, microprocessor, or application-specific integrated circuit (ASIC), etc. In some example embodiments, any memory, storage device, memory unit, etc., as described herein may include a non-transitory computer-readable storage device that stores instruction programs, such as a solid-state drive (SSD), and the one or more instances of the processing circuitry may be configured to execute instruction programs to perform some or all or any of the functions of the processor 1120, memory 1130, interface 1140, (one or more) manipulator / actuator devices 1150, etc., according to any example embodiment described herein.

[0130] In some exemplary embodiments, some or all of the systems, apparatuses, and / or elements thereof described herein with reference to any of the accompanying drawings (including, but not limited to, any part of a test system, test apparatus, test board, device under test, storage device, electronic device, etc., according to any exemplary embodiment) may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry, hardware / software combinations such as processors executing software, or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), an application processor (AP), a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a solid-state drive (SSD)) storing instructions and a processor (e.g., a CPU) configured to execute the instructions to perform the functionality of any element of the system, apparatus, and / or its components described herein, including but not limited to the functionality of any part of a test system, test apparatus, test board, device under test, storage device, electronic device, etc., according to any example embodiment. It will be further understood that the processing circuitry may be configured to perform any method as described herein based on a non-transitory computer-readable storage device (e.g., a solid-state drive (SSD)) and a processor (e.g., a CPU) storing instructions, wherein the processor (e.g., the CPU) is configured to execute the instructions to perform any or all of the operations (including but not limited to) any method according to any example embodiment. Figures 6 to 7 (Any and all operations of any and all methods shown).

[0131] While the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A test apparatus configured to test a device under test (DUT) performing interface communication that performs pulse amplitude modulation (PAM) operation, wherein the PAM operation is referred to as PAM, and the DUT is referred to as DUT, the test apparatus comprising: A logic generation / determination device configured to generate a plurality of bits corresponding to a test mode; A first driver is configured to generate a first NRZ signal based on the logic state of the first bit among the plurality of bits and output the generated first NRZ signal via a first channel, wherein the NRZ signal is non-return-to-zero. as well as A second driver is configured to generate a second NRZ signal based on the logic state of a second bit among the plurality of bits and output the generated second NRZ signal via a second channel. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. Wherein, the first high level is different from the second high level. The first NRZ signal and the second NRZ signal are voltage-superimposed via superposition lines formed on the test board and provided to the DUT as a test signal, wherein the test signal has a voltage level that satisfies PAM-4 operation. The superimposed lines include: The first wire is connected to the first channel. The second wire, which is connected to the second channel, and A third conductor is electrically connected to both the first and second conductors, the third conductor is configured to transmit the test signal, and the third conductor is connected to the DUT via a DUT channel.

2. The testing apparatus according to claim 1, wherein, The first low level is different from the second low level.

3. The testing apparatus according to claim 1, wherein, The test signal has a power supply voltage VDDQ based on PAM-4 operation, 2 / 3 VDDQ, 1 / 3 Any level, either VDDQ or 0V, and The sum of the first high level and the second high level is 2. VDDQ.

4. The testing apparatus according to claim 1, further comprising: A first comparator is configured to receive a PAM signal containing at least 2 bits of information from the DUT via the first channel and compare the PAM signal with a first reference voltage. as well as A second comparator, configured to receive the PAM signal in parallel with the first comparator via the second channel, and compare the PAM signal with a second reference voltage. Specifically, when performing a first read operation and a second read operation on the same data from the DUT, the test results are continuously provided to the first comparator and the second comparator, and In the first read operation and the second read operation, the level of at least one of the first reference voltage or the second reference voltage is changed.

5. The testing apparatus according to claim 4, wherein, In either the first read operation or the second read operation, the levels of the first reference voltage and the second reference voltage are set to be the same, and In either the first read operation or the second read operation, the level of the first reference voltage is set to a level different from that of the second reference voltage.

6. The testing apparatus according to claim 5, wherein, The logic generation / determination device is configured to determine the logic state of the test result based on the following operations: Combine the comparison results of the first comparator and the second comparator in the first read operation, and The comparison results of the first comparator and the second comparator in the second read operation are combined.

7. The testing apparatus according to claim 1, further comprising: A first comparator and a second comparator are configured to receive, in parallel from the DUT, a PAM signal including at least 2 bits of information as a test result via the first channel; as well as A third comparator and a fourth comparator are configured to receive the PAM signal in parallel via the second channel. In this configuration, the first comparator is configured to compare the PAM signal with a first high reference voltage, the second comparator is configured to compare the PAM signal with a first low reference voltage, the third comparator is configured to compare the PAM signal with a second high reference voltage, and the fourth comparator is configured to compare the PAM signal with a second low reference voltage. The level of the first high reference voltage is different from the level of the second high reference voltage.

8. A testing system, comprising: A test board configured to communicate with a test device, the test device including an NRZ interface circuit, where NRZ stands for Non-Return-to-Zero. The test board is configured as follows: A first NRZ signal having a voltage level according to the logic state of the first bit among a plurality of bits is received from the test apparatus via a first channel, and A second NRZ signal having a voltage level according to the logic state of the second bit among the plurality of bits is received from the test device via the second channel. The test board includes a superposition line configured to provide a pulse amplitude modulation signal as a test signal to the device under test (DUT). The pulse amplitude modulation is PAM, and the PAM signal is generated based on the voltage superposition of the first NRZ signal and the second NRZ signal to satisfy the PAM operation.

9. The testing system according to claim 8, wherein, The superimposed lines include: The first wire is connected to the first channel. The second wire, which is connected to the second channel, and A third conductor, electrically connected to both the first and second conductors, is configured to transmit the PAM signal. The third conductor is connected to the DUT via a DUT channel.

10. The testing system according to claim 8, wherein, The first NRZ signal has a first high level or a first low level depending on the logic state of the first bit. The second NRZ signal has a second high level or a second low level according to the logic state of the second bit, and The first high level is different from the second high level.

11. The testing system according to claim 10, wherein, The first low level is different from the second low level.

12. The testing system according to claim 10, wherein, The test signal has a power supply voltage VDDQ based on PAM-4 operation, 2 / 3 VDDQ, 1 / 3 Any level, either VDDQ or 0V, and The sum of the first high level and the second high level is 2. VDDQ.

13. The testing system according to claim 8, wherein, A PAM signal containing at least 2 bits of information from the DUT is transmitted to the overlay line as a test result, and The test results are provided to the test device in parallel via the first channel and the second channel.

14. The testing system according to claim 13, wherein, The testing apparatus includes: A first comparator is configured to compare the test result received via the first channel with a first reference voltage; A second comparator, configured to compare the test result received via the second channel with a second reference voltage; and A logic generation / determination apparatus configured to determine the logic state of the test result based on a combination of the comparison results of the first comparator and the second comparator. The level of the first reference voltage is different from the level of the second reference voltage.

15. The testing system according to claim 14, wherein, The logic generation / determination device is configured to generate a test pattern including the plurality of bits used to generate the test signal.

16. A method of operating a test system, the test system being configured to test a device under test (DUT) performing interface communication that performs pulse amplitude modulation (PAM), the PAM being used for PUT operations, the method comprising: The first NRZ signal is output via the first channel according to the logic state of the first bit among multiple bits corresponding to the test mode, wherein the NRZ does not return to zero; A second NRZ signal is output via the second channel based on the logic state of the second bit among the plurality of bits; as well as The first PAM signal, which satisfies the PAM operation and is generated by voltage superposition of the first NRZ signal and the second NRZ signal via a superposition line, is provided as a test signal to the DUT. The first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit. Wherein, the first high level is different from the second high level. The superimposed lines include: The first wire is connected to the first channel. The second wire, which is connected to the second channel, and A third conductor is electrically connected to both the first and second conductors, the third conductor is configured to transmit the test signal, and the third conductor is connected to the DUT via a DUT channel.

17. The operating method according to claim 16, further comprising: A first comparison is made between a second PAM signal, which includes at least 2 bits of information and is received from the DUT via the first channel as a test result, and a first reference voltage. The second PAM signal received via the second channel, which is parallel to the first channel, is compared with the second reference voltage in a second comparison. as well as The logical state of the test result is determined based on the combination of the first comparison result of the first comparison and the second comparison result of the second comparison. The level of the first reference voltage is different from the level of the second reference voltage.

18. The operating method according to claim 16, further comprising: A third NRZ signal, based on the logic state of the third bit among the plurality of bits, is output via the third channel. The third NRZ signal has a third high level or a third low level depending on the logic state of the third bit, and When the first NRZ signal, the second NRZ signal, and the third NRZ signal are voltage superimposed to generate the first PAM signal, the test signal has any one of N voltage levels, where N is an integer equal to or greater than 5. The superimposed line further includes a fourth conductor, which is connected to the third channel and the third conductor.

19. The operating method according to claim 17, further comprising: Based on the determined logical state of the test results, one or more electronic devices are manufactured such that one or more storage devices associated with the DUT are selectively included or excluded from the manufactured one or more electronic devices.

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