Method and computer system for simulating an electric machine

Abstract

The invention relates to a method for real-time simulation of a circuit, said circuit being modeled in a graph model comprising at least two blocks connected by signals, said graph model comprising at least two matrix operations, said matrix operations generating one multi-dimensional output signal from at least one multi-dimensional input signal. The matrix operations are implemented in two separate blocks, namely a matrix routing block and a matrix calculation block, wherein the matrix routing block is arranged to provide the matrix calculation block with the respective at least one input signal and to store the calculated output signal, and the matrix calculation block is arranged to apply an operation on the currently received input signal to calculate the output signal. The first and the second matrix operation comprise two separate matrix routing blocks, but one common matrix calculation block, each matrix routing block alternatingly providing the matrix calculation block with an input signal and receiving an output signal. A bitstream is generated from the graph model and the bitstream is executed on a programmable logic module.

Description

Technical Field

[0001] This invention relates to a computer implementation method, computer system, and computer-readable storage medium for real-time simulation of circuits, particularly motors. Background Technology

[0002] Modern products, such as controllers, are often developed using computer-aided simulation of dynamic systems. For example, a controller's controlled system, or controlled object, can be simulated to test components, such as controllers, in hardware-in-the-loop simulation before the entire product is completed. This is done using a dedicated real-time computer, which ensures a response within a predetermined maximum timeframe. System dynamics are typically limited, so a maximum latency, for example, in the millisecond range, is appropriate, and a real-time computer with a conventional processor can be used.

[0003] However, for circuits such as electric motors or inverters used to control them, the maximum permissible latency for real-time simulation may be in the microsecond range. In this case, a real-time computer with programmable logic modules, particularly a field-programmable gate array (FPGA), is preferred. It can also be specified that slower regulation of control or higher-level processes is performed by a computing node with a processor that exchanges data with the programmable logic modules. The FPGA is configured by reading a bitstream that directly affects the connections of the individual logic elements, thus defining the designed circuit. A method for simulating dynamic systems is known from DE102019107817A1, which simulates small electronic circuits with a fixed, predetermined configuration and, particularly, with very short latency. Since the characteristics of an electric motor, such as the number of stator poles, can vary considerably, and different discretization methods (or solvers) are used depending on the application, it is recommended not to use a fixed configuration, but rather to create a bitstream based on a model for the specific motor. However, according to the prior art, this is associated with poor resource utilization and relatively long latency. Summary of the Invention

[0004] Against this backdrop, the objective of this invention is to provide a method and apparatus for simulating circuits—particularly motors—that further improves upon existing techniques. In particular, efficient use of FPGA resources is desirable.

[0005] This task is accomplished by a method for real-time simulation of circuits, especially motors, that has the features of the present invention, and by a computer system that has the features of the present invention.

[0006] According to the present invention, a method for real-time simulation of circuits, particularly motors, is proposed, wherein the circuit is modeled in a graphical model comprising at least two blocks connected by signals, wherein the graphical model includes at least two matrix operations that generate a multidimensional output signal from at least one multidimensional input signal. The method is executed on a computer system comprising an operating computer and a real-time computer connected to the operating computer, wherein the operating computer executes a graphical modeling environment and the real-time computer has at least one programmable logic module. Matrix operations are implemented in two separate blocks, namely a matrix routing block and a matrix computation block, wherein the matrix routing block is configured to provide at least one corresponding input signal to the matrix computation block and store the calculated output signal, and wherein the matrix computation block is configured to apply operations to the currently received input signal to calculate the output signal. The first matrix operation and the second matrix operation comprise two separate matrix routing blocks but include a common matrix computation block, wherein the matrix routing block of the first matrix operation and the matrix block of the second matrix operation alternately provide input signals to the matrix computation block and receive output signals. A bitstream is generated by at least the portion of the graphical model including the matrix operations and is executed on the programmable logic module.

[0007] In one embodiment of the invention, a method for real-time simulation of circuits, particularly motors, is proposed, wherein the characteristics of the circuit are modeled in a graphical model comprising at least two blocks connected by signals, wherein the graphical model includes at least two matrix operations that generate a multidimensional output signal from one or more multidimensional input signals. The method is executed on a computer system comprising an operating computer and a real-time computer connected to the operating computer, wherein the operating computer executes a graphical modeling environment and the real-time computer has at least one programmable logic module. Matrix operations are implemented in two separate blocks, namely a matrix routing block and a matrix computation block, wherein the first and second matrix operations comprise two separate matrix routing blocks but include a common matrix computation block, wherein the first and second matrix routing blocks are configured to provide one or more input signals to the matrix computation block and store the calculated output signal, wherein the matrix computation block is configured to receive different input signals in successive cycles and apply operations to these different input signals, wherein the resulting output signal is not stored in the matrix computation block and is generated as a bitstream by at least the portion of the graphical model including the matrix operations and executed on the programmable logic module.

[0008] The method according to the invention advantageously makes better use of FPGA hardware resources and reduces or optimizes computational latency, thereby maximizing the sampling rate.

[0009] Furthermore, computational accuracy can be improved: the data type of the input signal and / or the data type of the output signal and / or the data type of the matrix elements are preferably floating-point types, for example, especially double-precision floating-point types. The method according to the invention can be used independently of the data type and is not limited to fixed-point types, which are problematic in terms of accuracy and scaling.

[0010] Ideally, the matrix computation block should be configured to apply operations row-by-row in parallel to each element of at least one input signal. To achieve a good trade-off between resource requirements and latency, it can be specified that the input signals are processed column-by-column. Accordingly, both column-by-column and row-by-row computation are possible.

[0011] In one embodiment of the invention, the number of elements to be processed in parallel before generating the bitstream can be adapted according to parameters, particularly specifications received from the user or the characteristics of the programmable logic module. For example, if the parameter exceeds a threshold, the entire line of input can be processed in parallel; if the parameter is below the threshold, the line can be divided into multiple blocks, and only the elements of one block can be processed in parallel. By adapting the number of values ​​for parallel processing, unused or available surfaces or existing logic elements on the programmable logic module can be used in the best possible way.

[0012] The matrix computation block is preferably configured to process square matrices, wherein the size of the square matrix is ​​selected such that it can include the input signals of the first matrix operation and the second matrix operation, the size of the square matrix being selected specifically according to the corresponding maximum dimension of the input signals, wherein computation on the square matrix stops once all elements of the output signal of the currently active matrix operation have been computed. This enables a high degree of parallelization and thus low latency without excessively consuming available space on the programmable logic module.

[0013] Preferably, the matrix computation block does not buffer the output signals generated by applying operations to the input signals. This avoids excessive consumption of memory resources in the programmable logic module.

[0014] Preferably, the matrix routing blocks of the first and second matrix operations receive and forward trigger signals to determine the active matrix routing block, while the matrix computation block remains active. The matrix routing block receiving the trigger signal is active and sends its input signals to the matrix computation block, which then performs the required matrix computation. Upon receiving the result, the currently active matrix routing block forwards the destination trigger signal, allowing the next matrix routing block to become active. Particularly preferably, the matrix routing block provides the at least one input signal to the connected matrix computation block based on the received trigger signal and forwards the trigger signal based on the storage of the generated output signal.

[0015] Preferably, two or more matrix routing blocks can be connected to a matrix computation block, and the matrix computation block is configured to continuously execute matrix operations of all connected matrix routing blocks, such that all matrix operations belonging to the connected matrix routing blocks are executed once in each time step of the simulation. It can also be specified that a scheduler or scheduler is used to control the processing of matrix operations according to an externally predetermined order or superior rules.

[0016] Preferably, the graphical model includes more than one matrix computation block, wherein at least two first matrix routing blocks are connected to one first matrix computation block and at least two second matrix routing blocks are connected to one second matrix computation block. Specifically, the first matrix computation blocks sequentially execute the computation of their first matrix routing blocks in each time step, while the second matrix computation blocks sequentially execute the computation of their second matrix routing blocks in each time step. Alternatively, a scheduler or scheduler may be specified for each. By using multiple instances of matrix computation blocks, more computations can be executed in parallel (provided the programmable logic module has the necessary resources). The size of the matrix computation blocks can be selected based on the corresponding input signals, wherein if the input signals have different dimensions, the first matrix computation blocks have different sizes than the second matrix computation blocks.

[0017] Preferably, the matrix computation block supports various matrix operations, such as addition of two matrices, matrix-matrix multiplication, or matrix-vector multiplication, wherein the active matrix operation is selected according to a control signal. In one embodiment, it may also be specified that a predetermined mathematical function is applied to each element of the input matrix. For example, the reciprocal 1 / x or trigonometric functions such as sinx, cosx, or tanx can be calculated. Advantageously, the type and number of supported computational operations or functions are predetermined in the model or selected according to parameters. In particular, the functionality provided by the matrix computation block can be selected based on the available facets or movable logic elements of the programmable logic module used.

[0018] Preferably, the matrix routing block is configured to adapt input signals, particularly to rename input signals or move elements to the desired region of the matrix computation block, and to output control signals for selecting active matrix operations to the matrix computation block.

[0019] Furthermore, the present invention relates to a computer system comprising an operating computer and a working computer having a human-machine interface, wherein the working computer includes a processor and a programmable logic module and is configured to execute the method according to the present invention.

[0020] Furthermore, the present invention relates to a computer-readable storage medium having instructions provided thereon, which, when executed by a computer system including a processor and a programmable logic module, cause the computer system to be configured to perform the method according to the present invention. Attached Figure Description

[0021] The invention will now be explained in more detail with reference to the accompanying drawings. Components of the same type are labeled with the same reference numerals. The illustrated embodiments are highly schematic; that is, distances and dimensions are not drawn to scale, and unless otherwise stated, there are no deducible geometric relationships between them. In the figures:

[0022] Figure 1 This is a preferred embodiment for operating a computer.

[0023] Figure 2 This is a preferred embodiment of a real-time computer.

[0024] Figure 3 This is a schematic diagram of the components of a hybrid vehicle.

[0025] Figure 4 This is a simulation diagram of a hybrid vehicle.

[0026] Figure 5 It is a schematic diagram of a graphical model with multiple matrix operations.

[0027] Figure 6 This is an example of matrix operations using matrix routing blocks and matrix computation blocks, and

[0028] Figure 7 Is execution Figure 4 A schematic diagram illustrating the load of matrix computation blocks in matrix operations. Detailed Implementation

[0029] Figure 1 A preferred embodiment of an operating computer (PC) is illustrated. The operating computer has a processor (CPU), which may in particular be implemented as a multi-core processor, working memory (RAM), and a bus controller (BC). The operating computer PC is preferably designed for direct manual operation by the user, wherein a display (DIS) is connected via a graphics card (GPU), and a keyboard (KEY) and mouse (MOU) are connected via a peripheral interface (HMI). In principle, the operating computer PC may also have a touch interface. The operating computer also includes non-volatile data storage (HDD), which may in particular be designed as a hard disk and / or solid-state drive (SSD), and includes an interface (NET), particularly a network interface.

[0030] The NET interface allows connection to other computers, particularly real-time computers (ES). In principle, one or more arbitrary interfaces, especially wired interfaces, can exist on the operating computer (PC), and each interface can be used to connect to other computers. The destination can use a network interface conforming to the Ethernet standard, wherein at least the physical layer is designed to conform to the standard; one or more higher protocol layers can also be implemented in a proprietary manner or adapted to the real-time computer. The NET interface can also be implemented wirelessly, particularly as a WLAN interface or according to standards such as Bluetooth. It can also be a mobile radio connection, such as LTE, where the exchanged data is preferably encrypted. Advantageously, at least one interface of the operating computer is designed as a standard Ethernet interface, allowing other computers to easily connect to the operating computer (PC).

[0031] An operating computer (PC) can have a secure data container (SEC), which simplifies the use of licensed applications on the operating computer and also allows the operating computer to function as a license server for real-time computing. The secure data container (SEC) can be implemented, for example, in the form of a dongle, specifically a dongle connected to a peripheral interface. Alternatively, the secure data container (SEC) can be specified as a component permanently integrated into the operating computer or stored as a file on a non-volatile data storage device (HDD).

[0032] Preferred embodiments of real-time computer ES are in Figure 2 The real-time computer is illustrated in the diagram. It includes a computing node CN, which is connected to an operating computer PC via a network interface NET. In principle, this connection is only required during the configuration of the real-time computer ES, and preferably it is continuous. The computing node CN has at least one processor CPU, particularly a multi-core processor or multiple processors, working memory RAM, and non-volatile memory NVM, on which the operating system and / or bootloader are preferably stored. At least one logic board FPGA and a device interface DEV are connected to the computing node via a high-speed bus SBC or a corresponding controller. The logic board FPGA includes programmable logic modules that can be configured according to the present invention. It can also be specified that the real-time computer ES has multiple logic boards FPGA or multiple programmable logic modules on a single logic board. Multiple modules, such as a fault simulation circuit FIU that applies defined electrical faults to connected devices, or an interface card IOC that provides one or more analog or digital I / O channels, can be connected via the device interface DEV.

[0033] Figure 3 A schematic diagram of the components of a hybrid vehicle or at least sometimes a motor vehicle driven by an electric motor is shown.

[0034] The electric motor is controlled by a controller ECU, which includes a regulator and a power stage. The controller is connected to the motor and provides it with, for example, three-phase voltage. The motor may also have a greater number of coils, which require a correspondingly greater number of phase voltages or phase currents. The motor is mechanically connected to a transmission, which in particular can drive one or more wheels. However, the electric motor is also used in a range of other vehicle applications that can also be simulated. The vehicle has a range of sensors, such as wheel speed sensors. At least one output signal or one or more sensor signals are provided to the vehicle controller. The electric motor may also have a range of sensors, such as position sensors indicating the position of the rotor relative to the stator; this position signal is also provided to the controller.

[0035] The controller includes an application regulator that receives sensor signals from the vehicle and position signals from the electric motor, and thereby determines setpoints for electrical parameters, particularly current, on each phase of the electric motor according to a regulation algorithm. A current regulator controls the semiconductor switches of the power stage or inverter based on these setpoints or by comparison with current signals from current sensors (e.g., shunt resistors) located in the power stage.

[0036] The three dashed lines illustrate the different levels of the simulation on which the motor can be started. At the signal level, where the regulator operates, only electrical signals or values ​​exist. The inverter operates at the power level, where considerable voltage and current, or electrical power, may occur. The motor converts this electrical power into mechanical force. A suitable test bench is required to test the entire system consisting of the controller and motor at the mechanical level. Where possible, the regulation algorithm can also be tested at the signal level via software simulation.

[0037] exist Figure 4 The image shows a simulation of a hybrid vehicle, or at least sometimes a motor vehicle driven by an electric motor.

[0038] The simulation system shown has an electronic load that can handle or manipulate voltage and current at the power level. Therefore, the controller can be tested as a real component without the presence of the entire vehicle or any hazards associated with driving tests. The vehicle or mechanical components are simulated based on a simulation model on a computing node CN or a real-time computer ES processor CPU. The sensor signals required by the controller are generated through sensor simulation, which is executed by the processor and / or programmable logic module FPGA.

[0039] To ensure low latency, the electronic load is controlled by a programmable logic module (FPGA), whose configuration is created based on a module library. The module library preferably includes matrix routing blocks and matrix computation blocks for executing the method according to the invention.

[0040] Figure 5 A schematic diagram of a graphical model with multiple matrix operations is shown.

[0041] The model shown includes four matrix operation blocks B1, B2, B3, and B4, which are interconnected via signals. Each matrix operation block has two input signals and outputs one output signal. Module B1 receives two matrix signals A and B and calculates their product A x B. Module B2 receives the output signal from B1 and another matrix signal C and calculates the sum (A x B) + C. Module B3 receives the output signal from B2 and another matrix signal D and calculates the product (A x B) + C) x D. Block B4 receives the output signals from B1 and B3 and outputs the sum (((A x B) + C) x D) + (A x B) as the output signal.

[0042] Because time processing introduces a certain delay, and subsequent calculations must wait for the results of the previous calculation stage, it is appropriate for the subsequent operations to be triggered by an external pulse. For this purpose, the matrix operation block has a trigger input, Trig. After the calculation is completed, the trigger pulse used to activate the calculation is forwarded to the next component through the trigger output, New.

[0043] If each matrix operation block is implemented as a single block (monolithische Blöcke) as usual, this leads to low hardware utilization because matrix calculations are only activated for a very short time ("working time") and then wait for the next pulse ("idle time") after completing the calculation. However, the next trigger pulse is only received after a complete chain of matrix operation blocks has been completed. This results in low utilization of executed matrix calculations or poor working-idle ratios. Matrix operation blocks occupy a large portion of the programmable logic module.

[0044] Figure 6 An embodiment of matrix operations using the matrix routing block and matrix computation block according to the present invention is shown.

[0045] A matrix routing block (GRU) and a matrix computation block (GCU) replace the single matrix operation block. The matrix routing block (GRU) receives input signals A and B and outputs an output signal Out. Furthermore, the matrix routing block (GRU) has a trigger input terminal (Trig) and a trigger output terminal (New). The matrix routing block (GRU) provides a "gateway / routing" function and forwards the corresponding data to the associated matrix computation block (GCU), which performs the corresponding calculation. After the calculation is completed, the result is again stored in the matrix routing block (GRU), which also forwards the trigger signal.

[0046] Multiple matrix routing blocks can be connected to a single matrix computation block (GCU). Since subsequent computations are performed using the same GCU, the logic elements on the programmable logic module can be utilized much more effectively. Only the computation block (GCU) requires dedicated hardware resources for computation, and it can support more complex computations applicable to matrices in addition to different basic operation types. Depending on the destination, the matrix routing block (GRU) selects the current computation operation of the matrix computation block via configuration signals or configuration words, thus allowing for tailored control.

[0047] Figure 7 The execution was shown Figure 4 A schematic diagram of the usage load (Auslastung) of the matrix computation block GCU for matrix operations.

[0048] This section specifies which matrix operations or blocks (B1, B2, B3, B4) are being executed by the matrix computation block (GCU). The matrix computation block is used under heavy load; only the transitions between different matrix operations, indicated by dashed lines, may cause short delays.

[0049] If more computational performance is required, matrix computation blocks (GCUs) can be added or multiple GCU blocks can be used, which are connected to a portion of each matrix routing block (GRU) and thus enable parallel processing.

[0050] In one embodiment of the invention, the matrix routing block and the matrix computation block can be implemented in a module library for a technical computing environment such as MATLAB / Simulink. Advantageously, the matrix routing block has a user interface in which the matrix computation block can be selected, and input signals are provided to the matrix computation block for computation. The desired computational operation, such as matrix multiplication or addition, can also be selected in the user interface, or a predetermined function can be applied element-wise to the elements of the input matrix. The matrix computation block can be designed as a general-purpose computation block supporting a predefined range of computations, wherein connected matrix routing blocks select the desired computation from the predefined range via signals or instructions. It can also be specified that the matrix computation block has a user interface in which the degree of parallelism of the computation can be selected.

[0051] Specifically, entire rows of a matrix can be processed in parallel, or blocks can be divided for parallel processing, which can be set by the user, for example, via a slider. The module library can contain matrix computation blocks of various sizes, making it easy to select the appropriate block. The allocation between matrix routing blocks and matrix computation blocks can be based on computation number and / or block identifier or name. For example, the bitstream of a programmable logic module can be generated from the created model using the Xilinx system generator.

[0052] The following advantages can be derived from the calculation method described:

[0053] • The order of matrix operations can be easily understood based on the signal paths between matrix routing blocks, keeping the model readable or easy to read.

[0054] • The path from the matrix routing block GRU to each matrix computation block GCU is implemented transparently to the user.

[0055] • Make better use of dedicated hardware resources for computing, such as DSP slices.

[0056] Because fewer computational blocks are used, each block can utilize more dedicated hardware resources for computation, thus offering several advantages:

[0057] • Matrix calculations can be set up in parallel as much as possible to minimize latency.

[0058] • Matrix computation can be performed with higher bit widths (e.g., double precision instead of single precision), resulting in more accurate simulations.

Claims

1. A method for real-time circuit simulation, wherein, The circuit is modeled in a graphical model comprising at least two blocks connected by signals. The graphical model includes at least two matrix operations that generate a multidimensional output signal from at least one multidimensional input signal. The method is executed on a computer system comprising an operational computer and a real-time computer connected to the operational computer. The operational computer executes a graphical modeling environment, and the real-time computer has at least one programmable logic module. The matrix operations are implemented in two separate blocks: a matrix routing block and a matrix computation block. The matrix routing block is configured to provide at least one corresponding input signal to the matrix computation block and store the calculated output signal. The matrix computation block is configured to apply operations to the currently received input signal to calculate the output signal. The first and second matrix operations comprise two separate matrix routing blocks but include a common matrix computation block. The matrix routing blocks of the first and second matrix operations alternately provide input signals to the matrix computation block and receive output signals. A bitstream is generated by at least the portion of the graphical model including the matrix operations and is executed on the programmable logic module.

2. The method according to claim 1, wherein, The matrix computation block is configured to apply operations row-by-row in parallel to each element of at least one input signal.

3. The method according to claim 1, wherein, A matrix computation block is configured to process a square matrix, wherein the size of the square matrix is ​​selected such that the square matrix can include the input signals of a first matrix operation and a second matrix operation, wherein computation on the square matrix stops once all elements of the output signal of the currently active matrix operation have been computed.

4. The method according to any one of claims 1 to 3, wherein, The matrix computation block does not buffer the output signals generated by applying operations to the input signals.

5. The method according to any one of claims 1 to 3, wherein, The matrix routing block of the first matrix operation and the matrix routing block of the second matrix operation receive and forward trigger signals to determine the active matrix routing block, while the matrix computation block is always in an active state.

6. The method according to claim 5, wherein, The matrix routing block provides the at least one input signal to the connected matrix computation block based on the receipt of the trigger signal and forwards the trigger signal based on the storage of the generated output signal.

7. The method according to any one of claims 1 to 3, wherein, It is possible to connect two or more matrix routing blocks to a matrix computation block, and the matrix computation block is configured to continuously execute matrix operations of all connected matrix routing blocks, such that all matrix operations belonging to the connected matrix routing blocks are executed once in each time step of the simulation.

8. The method according to any one of claims 1 to 3, wherein, The graphical model includes one or more matrix computation blocks, wherein at least two first matrix routing blocks are connected to one first matrix computation block and at least two second matrix routing blocks are connected to one second matrix computation block.

9. The method according to any one of claims 1 to 3, wherein, At least one element of a multidimensional input signal and / or at least one element of a multidimensional output signal has floating-point numbers as data types.

10. The method according to any one of claims 1 to 3, wherein, The matrix computation block supports different matrix operations and selects the active matrix operation based on the control signal.

11. The method according to any one of claims 1 to 3, wherein, The matrix routing block is configured to adapt to input signals or move elements to the desired region of the matrix computation block, and to output control signals for selecting active matrix operations to the matrix computation block.

12. The method according to any one of claims 1 to 3, wherein, The circuit is a motor.

13. The method according to claim 3, wherein, The size of the square matrix is ​​selected based on the corresponding maximum dimension of the input signal.

14. The method according to claim 9, wherein, The floating-point number is a double-precision number.

15. The method according to claim 10, wherein, The matrix computation block supports addition of two matrices, multiplication of matrices, or multiplication of a matrix with a vector.

16. The method according to claim 11, wherein, The matrix routing block is set to rename the input signal.

17. A computer system, said computer system comprising an operating computer with a human-computer interface and a real-time computer, wherein, The real-time computer includes a processor and a programmable logic module, and the computer system is configured to perform the method according to any one of claims 1 to 16.

18. A computer-readable storage medium having instructions provided thereon that, when executed by a computer system including a processor and a programmable logic module, cause the computer system to be configured to perform the method according to any one of claims 1 to 16.

Images