Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. In one embodiment, a device includes a p-type transistor including a first channel region, a first gate dielectric layer on the first channel region, a tungsten-containing work function adjustment layer on the first gate dielectric layer, and a first fill layer on the tungsten-containing work function adjustment layer, and an n-type transistor including a second channel region, a second gate dielectric layer on the second channel region, a tungsten-free work function adjustment layer on the second gate dielectric layer, and a second fill layer on the tungsten-free work function adjustment layer.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a first nanostructure; a second nanostructure; a gate dielectric layer surrounding the first nanostructure and the second nanostructure; a tungsten-free work function adjustment layer surrounding the gate dielectric layer; a tungsten-containing work function adjustment layer surrounding the tungsten-free work function adjustment layer, wherein a region between the first nanostructure and the second nanostructure is completely filled by corresponding portions of the tungsten-containing work function adjustment layer, the tungsten-free work function adjustment layer, and the gate dielectric layer; and a filling layer located on the tungsten-containing work function adjustment layer.

[0005] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a p-type transistor including: a first channel region; a first gate dielectric layer located on the first channel region; a tungsten-containing work function adjustment layer located on the first gate dielectric layer; and a first fill layer located on the tungsten-containing work function adjustment layer; and an n-type transistor including: a second channel region; a second gate dielectric layer located on the second channel region; a tungsten-free work function adjustment layer located on the second gate dielectric layer; and a second fill layer located on the tungsten-free work function adjustment layer.

[0006] According to another embodiment of this disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a gate dielectric layer having a first portion surrounding a first nanostructure; depositing a first tungsten-free work function material on the first portion of the gate dielectric layer; depositing a tungsten-containing work function material on the first tungsten-free work function material, the resistivity of the tungsten-containing work function material being lower than that of the first tungsten-free work function material; and depositing a filler layer on the tungsten-containing work function material. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 Examples of nanostructured field-effect transistors (nanoFETs) are shown in a three-dimensional view according to some embodiments.

[0009] Figure 2-20B This is a view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010] Figures 21A-21B This is a view of a nanoFET according to some embodiments.

[0011] Figures 22A-22B This is a view of a nanoFET according to some embodiments.

[0012] Figures 23A-23B This is a view of a nanoFET according to some embodiments. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "below," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0015] According to various embodiments, the gate structure for a p-type device includes a work function adjustment layer formed of a tungsten-containing work function material (WFM). For example, the tungsten-containing WFM can be pure tungsten (e.g., fluorine-free tungsten), tungsten nitride, tungsten carbide, tungsten carbonitride, etc., which can be deposited by one of several deposition processes. Tungsten is suitable for adjusting the work function of p-type devices. Advantageously, the resistance of a p-type device having a work function adjustment layer formed of a tungsten-containing WFM can be lower than that of a p-type device having a work function adjustment layer formed of a WFM containing other metals (e.g., tantalum). Device performance can therefore be improved.

[0016] Embodiments have been described in a specific context, including dies for nanoFETs. However, various embodiments may be applied to dies that replace or are combined with nanoFETs to include other types of transistors (e.g., FinFETs, planar transistors, etc.).

[0017] Figure 1 Examples of nanoFETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments are shown. Figure 1 This is a 3D view, in which some features of the nanoFET have been omitted for ease of explanation. A nanoFET can be a nanosheet field-effect transistor (NSFET), a nanowire field-effect transistor (NWFET), a gate all-around field-effect transistor (GAAFET), etc.

[0018] The nanoFET includes nanostructures 66 (e.g., nanosheets, nanowires, etc.) situated above fins 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 66 serve as channel regions for the nanoFET. Nanostructures 66 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 70, such as shallow trench isolation (STI) regions, are disposed between adjacent fins 62 and may protrude beyond the isolation regions 70. Although the STI regions 70 are described / shown as separated from the substrate 50, as used herein, the term "substrate" may refer only to the semiconductor substrate or to a combination of the semiconductor substrate and the isolation regions. Furthermore, although the bottom portion of the fin 62 is shown as a single continuous material with the substrate 50, the bottom portion of the fin 62 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fin 62 refers to the portion extending between adjacent isolation regions 70.

[0019] Gate dielectric 122 is located above the top surface of fin 62 and along the top, sidewalls, and bottom surface of nanostructure 66. Gate electrode 124 is located above gate dielectric 122. Epitaxial source / drain regions 98 are disposed on fin 62, on opposite sides of gate dielectric 122 and gate electrode 124. Epitaxial source / drain regions 98 can be shared between the various fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, for example by coalescing the epitaxial source / drain regions 98 using epitaxial growth, or by coupling the epitaxial source / drain regions 98 to the same source / drain contacts.

[0020] Figure 1 Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 124 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 98 of the nano-FinFET. Cross section B-B' is along the longitudinal axis of the fin 62 and in a direction, for example, the current flow direction between the epitaxial source / drain regions 98 of the nano-FET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 98 of the nano-FET. For clarity, the following figures refer to these reference cross sections.

[0021] Some embodiments discussed herein are discussed in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Moreover, some embodiments contemplate aspects used in planar devices such as planar FETs or fin field-effect transistors (FinFETs). For example, a FinFET may include fins on a substrate, where these fins serve as the channel region of the FinFET. Similarly, a planar FET may include a substrate, where a portion of the substrate serves as the channel region of the planar FET.

[0022] Figure 2-20B This is a view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 It is a 3D view, showing the relationship with Figure 1 A similar 3D view. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A as well as Figure 20A It shows Figure 1 The reference cross section A-A' is shown. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B as well as Figure 20B It shows Figure 1 The reference cross section B-B' is shown. Figure 9C and Figure 9D It shows Figure 1 The reference cross section C-C' shown is illustrated.

[0023] exist Figure 2The diagram provides a substrate 50 for forming a nano-FET. The substrate 50 can be a semiconductor substrate (e.g., a bulk semiconductor), a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type impurities) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. For example, the insulating layer can be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; combinations thereof, etc.

[0024] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanoFET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0025] The substrate 50 may be lightly doped with p-type or n-type impurities. Anti-punch-through (APT) implantation may be performed on the upper portion of the substrate 50 to form an APT region. During APT implantation, impurities may be implanted into the substrate 50. The impurities may have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region may extend below the source / drain regions in the nano-FET. The APT region can be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region may be approximately 10. 18 cm -3 To about 10 19 cm -3 Within the range.

[0026] A multilayer stack 52 is formed on a substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, while the second semiconductor layers 56 are formed of a second semiconductor material. The semiconductor materials can each be selected from candidate semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers of each of the first semiconductor layers 54 and the second semiconductor layers 56. It should be understood that the multilayer stack 52 can include any number of first semiconductor layers 54 and second semiconductor layers 56.

[0027] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layer 54 is removed and the second semiconductor layer 56 is patterned to form channel regions for a nanoFET in both the n-type region 50N and the p-type region 50P. The first semiconductor layer 54 is a sacrificial layer (or dummy layer) that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity for etching the second semiconductor layer 56, such as silicon germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0028] In another embodiment (not shown separately), the first semiconductor layer 54 will be patterned to form a channel region for a nanoFET in one region (e.g., p-type region 50P), and the second semiconductor layer 56 will be patterned to form a channel region for a nanoFET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si). x Ge 1-x The second semiconductor material of the second semiconductor layer 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, etc. The etching of the first semiconductor material and the second semiconductor material relative to each other can have high etch selectivity, thereby allowing the first semiconductor layer 54 to be removed without removing the second semiconductor layer 56 in the n-type region 50N, and the second semiconductor layer 56 to be removed without removing the first semiconductor layer 54 in the p-type region 50P.

[0029] Each layer of the multilayer stack 52 can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Each layer can have a small thickness, for example, in the range of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layer 56) are formed to be thinner than other layers (e.g., the first semiconductor layer 54). For example, in an embodiment where the first semiconductor layer 54 is a sacrificial layer (or dummy layer) and the second semiconductor layer 56 is patterned to form a channel region for a nanoFET in both the n-type region 50N and the p-type region 50P, the first semiconductor layer 54 can have a first thickness, and the second semiconductor layer 56 can have a second thickness, wherein the second thickness is about 30% to about 60% smaller than the first thickness. Forming the second semiconductor layer 56 to a smaller thickness allows the channel region to be formed at a higher density.

[0030] exist Figure 3 In this process, trenches are patterned in substrate 50 and multilayer stack 52 to form fins 62, a first nanostructure 64, and a second nanostructure 66. Fin 62 is a semiconductor strip patterned in substrate 50. The first nanostructure 64 and the second nanostructure 66 respectively comprise the remainders of the first semiconductor layer 54 and the second semiconductor layer 56. The trenches can be patterned using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0031] The fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fins 62 and nanostructures 64, 66. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern the fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on the nanostructures 64, 66.

[0032] Fins 62 and nanostructures 64, 66 may each have a width ranging from about 8 nm to about 40 nm. In the illustrated embodiment, fins 62 and nanostructures 64, 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, fins 62 and nanostructures 64, 66 in one region (e.g., n-type region 50N) are wider or narrower than fins 62 and nanostructures 64, 66 in another region (e.g., p-type region 50P).

[0033] exist Figure 4 In this embodiment, STI regions 70 are formed on the substrate 50 and between adjacent fins 62. The STI regions 70 are disposed around at least a portion of the fins 62 such that at least a portion of the nanostructures 64, 66 protrudes between adjacent STI regions 70. In the illustrated embodiment, the top surface of the STI region 70 is coplanar with the top surface of the fin 62 (within process variations). In some embodiments, the top surface of the STI region 70 is higher or lower than the top surface of the fin 62. The STI regions 70 separate features of adjacent devices.

[0034] The STI regions 70 can be formed by any suitable method. For example, an insulating material can be formed on the substrate 50 and nanostructures 64, 66, and between adjacent fins 62. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof, which can be formed by a chemical vapor deposition (CVD) process (e.g., high-density plasma CVD (HDP-CVD), flowable chemical vapor deposition (FCVD), or a combination thereof). Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66. Although each of the STI regions 70 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 62, and nanostructures 64, 66. Subsequently, a filler material such as that described previously can be formed on the liner.

[0035] Then, a removal process is applied to the insulating material to remove excess insulating material on top of the nanostructures 64, 66. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back processes, or combinations thereof, may be utilized. In embodiments where the mask remains on the nanostructures 64, 66, the planarization process may expose or remove the mask. After the planarization process, the insulating material and the top surface of the mask (if present) or nanostructures 64, 66 are coplanar (within process variations). Therefore, the top surface of the mask (if present) or nanostructures 64, 66 is exposed through the insulating material. In the illustrated embodiment, no mask remains on the nanostructures 64, 66. The insulating material is then recessed to form the STI region 70. The insulating material is recessed such that at least a portion of the nanostructures 64, 66 protrudes between adjacent portions of the insulating material. Furthermore, the top surface of the STI region 70 may have a flat surface, a convex surface, a concave surface (e.g., a recess), or a combination thereof, as shown. The top surface of STI region 70 can be formed into a flat, convex, and / or concave shape through appropriate etching. Any acceptable etching process can be used to recess the insulating material, such as a material-selective etching process (e.g., selectively etching the insulating material of STI region 70 at a faster rate than the materials of fins 62 and nanostructures 64, 66). For example, dilute hydrofluoric acid (dHF) can be used to perform oxide removal.

[0036] The previously described process is merely one example of how the fins 62 and nanostructures 64, 66 can be formed. In some embodiments, masking and epitaxial growth processes can be used to form the fins 62 and / or nanostructures 64, 66. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 62 and / or nanostructures 64, 66. The epitaxial structure can include the alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxial growth material can be doped in situ during growth, which can avoid prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0037] Furthermore, suitable wells (not shown separately) can be formed in nanostructures 64, 66, fins 62, and / or substrate 50. The wells can have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and p-type region 50P. In some embodiments, a p-type well is formed in n-type region 50N, and an n-type well is formed in p-type region 50P. In some embodiments, either a p-type well or an n-type well is formed in both n-type region 50N and p-type region 50P.

[0038] In embodiments with different well types, masks such as photoresists (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fins 62, nanostructures 64, 66, and STI region 70 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration ranging from about 10. 13 cm -3 To about 10 14 cm -3 After injection, the photoresist can be removed, for example, by any acceptable ashing process.

[0039] After or before implantation of the p-type region 50P, a mask, such as a photoresist (not shown separately), is formed over the fins 62, nanostructures 64, 66, and STI region 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region, with a concentration ranging from about 10. 13 cm -3 To about 10 14 cm -3 After injection, the photoresist can be removed, for example, by any acceptable ashing process.

[0040] Following implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where epitaxial structures of fins 62 and / or nanostructures 64, 66 are epitaxially grown, the grown material can be doped in situ during growth, which can eliminate implantation, but in-situ and implantation doping can be used together.

[0041] exist Figure 5 In this process, a dummy dielectric layer 72 is formed on fins 62 and nanostructures 64 and 66. The dummy dielectric layer 72 can be formed of a dielectric material such as silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown using acceptable techniques. A dummy gate layer 74 is formed on the dummy dielectric layer 72, and a mask layer 76 is formed on the dummy gate layer 74. The dummy gate layer 74 can be deposited on the dummy dielectric layer 72 and then planarized (e.g., by CMP). The mask layer 76 can be deposited on the dummy gate layer 74. The dummy gate layer 74 can be formed of conductive or non-conductive materials, such as amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metals, metal nitrides, metal silicides, metal oxides, etc., which can be deposited by physical vapor deposition (PVD), CVD, etc. The dummy gate layer 74 can be formed from one or more materials with high etch selectivity for etching insulating materials (e.g., STI region 70 and / or dummy dielectric layer 72). The mask layer 76 can be formed from a dielectric material such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the fins 62, nanostructures 64, 66, and STI region 70, such that the dummy dielectric layer 72 is over the STI region 70 and extends between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and nanostructures 64, 66.

[0042] exist Figure 6In this process, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 is then transferred to dummy gate layer 74 using any acceptable etching technique to form dummy gate 84. The pattern of mask 86 may optionally be further transferred to dummy dielectric layer 72 using any acceptable etching technique to form dummy dielectric 82. Dummy gate 84 covers portions of nanostructures 64, 66 that will be exposed in subsequent processing to form channel regions. Specifically, dummy gate 84 extends along portions of nanostructures 66 that will be patterned to form channel regions 68. The pattern of mask 86 may be used to physically separate adjacent dummy gates 84. Dummy gate 84 may also have a length direction substantially perpendicular to the length direction of fin 62 (within process variations). Mask 86 may optionally be removed after patterning, for example, by any acceptable etching technique.

[0043] Figure 7A-20B Various additional steps in manufacturing the embodiment device are shown. Figure 7A-13B and Figure 18A-20B Features in either the n-type region 50N or the p-type region 50P are shown. For example, the structure shown can be applied to both the n-type region 50N and the p-type region 50P. Differences in the structure of the n-type region 50N and the p-type region 50P, if any, are described in the text accompanying each figure. Figure 14A-16B Features in the p-type region 50P are shown. Figures 17A-17B The characteristics of the n-type region 50N are shown.

[0044] exist Figure 7A and Figure 7B In this embodiment, gate spacers 90 are formed on nanostructures 64, 66, on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 90 can be formed by conformally depositing one or more dielectric materials and subsequently etching (one or more) of the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by conformal deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), etc. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, each gate spacer 90 comprises multiple layers, such as a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are made of silicon carbonitride (e.g., SiO2). x N y C 1-x-yThe first spacer layer 90A is formed from silicon carbonitride, which is similar to or different from the second spacer layer 90B. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to pattern one or more dielectric materials. The etching can be anisotropic. The one or more dielectric materials have portions remaining on the sidewalls of the dummy gate 84 during etching (thus forming the gate spacer 90). As will be described in more detail later, the one or more dielectric materials may also have portions remaining on the sidewalls of the fins 62 and / or nanostructures 64, 66 during etching (thus forming the fin spacer 92, see [link to relevant documentation]). Figure 9C and Figure 9D After etching, the fin spacer 92 and / or the gate spacer 90 may have straight sidewalls (as shown) or may have curved sidewalls (not shown separately).

[0045] Furthermore, implantation can be performed to form lightly doped source / drain (LDD) regions (not shown separately). In embodiments with different device types, similar to the implantation previously described for traps, a mask such as a photoresist (not shown separately) can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist (not shown separately) can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fins 62 and / or nanostructures 64, 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. During implantation, the channel region 68 remains covered by the dummy gate 84, ensuring that the channel region 68 remains substantially free of impurities implanted to form the LDD region. The impurity concentration of the LDD region can be approximately 10. 15 cm -3 To about 10 19 cm -3 Within this range, annealing can be used to repair injection damage and reactivate the injected impurities.

[0046] Note that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or more spacers can be used, different step sequences can be used, additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0047] exist Figure 8A and Figure 8B In the illustrated embodiments, source / drain recesses 94 are formed in nanostructures 64, 66. In the illustrated embodiments, the source / drain recesses 94 extend through nanostructures 64, 66 and into fin 62. The source / drain recesses 94 may also extend into substrate 50. In various embodiments, the source / drain recesses 94 may extend to the top surface of substrate 50 without etching substrate 50; fin 62 may be etched such that the bottom surface of the source / drain recesses 94 is disposed below the top surface of STI region 70, etc. The source / drain recesses 94 can be formed by etching nanostructures 64, 66 using anisotropic etching processes (e.g., RIE, NBE, etc.). During the etching process used to form the source / drain recesses 94, gate spacer 90 and dummy gate 84 jointly cover portions of fin 62 and / or nanostructures 64, 66. Each of nanostructures 64, 66 can be etched using a single etching process, or multiple etching processes can be used to etch nanostructures 64, 66. After the source / drain recess 94 reaches the desired depth, a timed etching process can be used to stop etching the source / drain recess 94.

[0048] Optionally, internal spacers 96 are formed on the sidewalls of the remainder of the first nanostructure 64, such as those exposed by the source / drain recesses 94. As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recesses 94, and the first nanostructure 64 will subsequently be replaced by a corresponding gate structure. The internal spacers 96 act as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 96 can be used to substantially prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for the subsequent removal of the first nanostructure 64).

[0049] As an example of forming the internal spacer 96, the source / drain recess 94 can extend laterally. Specifically, the portion of the sidewall of the first nanostructure 64 exposed by the source / drain recess 94 can be recessed. Although the sidewall of the first nanostructure 64 is shown as straight, the sidewall can be concave or convex. The sidewall can be recessed by any acceptable etching process, such as an etching process selective for the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate than the material of the second nanostructure 66). The etching can be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In another embodiment, the etching process can be a dry etching using a fluorine-based gas such as hydrogen fluoride (HF). In some embodiments, the same etching process can be performed continuously to both form the source / drain recess 94 and recess the sidewall of the first nanostructure 64. The internal spacer 96 can then be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material can be silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k-value less than about 3.5. The insulating material can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.). The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. Although the outer wall of the internal spacer 96 is shown flush with the sidewall of the gate spacer 90, the outer wall of the internal spacer 96 may extend beyond or be recessed from the sidewall of the gate spacer 90. In other words, the internal spacer 96 may partially fill, completely fill, or overfill the sidewall recess. Furthermore, although the sidewall of the internal spacer 96 is shown as straight, the sidewall of the internal spacer 96 may be concave or convex.

[0050] exist Figure 9A and Figure 9B In this process, an epitaxial source / drain region 98 is formed in the source / drain recess 94. The epitaxial source / drain region 98 is formed in the source / drain recess 94 such that each dummy gate 84 (and corresponding channel region 68) is disposed between each adjacent pair of epitaxial source / drain regions 98. In some embodiments, gate spacers 90 and internal spacers 96 are used to separate the epitaxial source / drain regions 98 from the dummy gate 84 and the first nanostructure 64 by appropriate lateral distances, respectively, so that the epitaxial source / drain regions 98 do not short-circuit with the gate of the subsequently formed nanoFET. The material of the epitaxial source / drain regions 98 can be selected to apply stress in the corresponding channel region 68, thereby improving performance.

[0051] The epitaxial source / drain region 98 in the n-type region 50N can be formed by masking the p-type region 50P. Then, the epitaxial source / drain region 98 in the n-type region 50N is epitaxially grown in the source / drain recess 94 in the n-type region 50N. The epitaxial source / drain region 98 can include any acceptable material suitable for an n-type device. For example, the epitaxial source / drain region 98 in the n-type region 50N can include a material on which tensile strain is applied to the channel region 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 98 in the n-type region 50N can be referred to as the "n-type source / drain region". The epitaxial source / drain region 98 in the n-type region 50N can have surfaces protruding from the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have small facets.

[0052] The epitaxial source / drain region 98 in the p-type region 50P can be formed by masking the n-type region 50N. Then, the epitaxial source / drain region 98 in the p-type region 50P is epitaxially grown in the source / drain recess 94 in the p-type region 50P. The epitaxial source / drain region 98 can include any acceptable material suitable for a p-type device. For example, the epitaxial source / drain region 98 in the p-type region 50P can include a material on which compressive strain is applied to the channel region 68, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 98 in the p-type region 50P can be referred to as the "p-type source / drain region". The epitaxial source / drain region 98 in the p-type region 50P can have surfaces protruding from the corresponding surfaces of the fins 62 and nanostructures 64, 66, and can have small facets.

[0053] Epitaxial source / drain regions 98, nanostructures 64, 66, and / or fins 62 can be implanted with impurities to form source / drain regions, similar to the previously described process for forming LDD regions, followed by annealing. The impurity concentration of the source / drain regions can be approximately 10. 19 cm -3 To about 10 21 cm -3 Within the range. The n-type and / or p-type impurities used for the source / drain regions can be any impurities previously discussed. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0054] As a result of the epitaxial process used to form the epitaxial source / drain regions 98, the upper surface of the epitaxial source / drain regions has facets that extend laterally outward beyond the sidewalls of the fins 62 and nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 98 to merge, such as... Figure 9CAs shown. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 98 remain separated, as... Figure 9D As shown. In the illustrated embodiment, the spacer etching used to form the gate spacer 90 is adjusted to also form fin spacers 92 on the sidewalls of the fins 62 and / or nanostructures 64, 66. The fin spacers 92 are formed to cover portions of the sidewalls of the fins 62 and / or nanostructures 64, 66 extending above the STI region 70, thereby preventing epitaxial growth. In another embodiment, the spacer etching used to form the gate spacer 90 is adjusted so that no fin spacers are formed, thereby allowing the epitaxial source / drain region 98 to extend to the surface of the STI region 70.

[0055] The epitaxial source / drain region 98 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 98 may each include a liner layer 98A, a main layer 98B, and a finishing layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the epitaxial source / drain region 98. Each of the liner layer 98A, the main layer 98B, and the finishing layer 98C may be formed of different semiconductor materials and may be doped to different impurity concentrations. In some embodiments, the liner layer 98A may have a lower impurity concentration than the main layer 98B, and the finishing layer 98C may have a higher impurity concentration than the liner layer 98A and a lower impurity concentration than the main layer 98B. In an embodiment where the epitaxial source / drain region 98 includes three semiconductor material layers, a liner layer 98A can be grown in the source / drain recess 94, a main layer 98B can be grown on the liner layer 98A, and a finishing layer 98C can be grown on the main layer 98B.

[0056] exist Figures 10A-10B In this configuration, a first interlayer dielectric (ILD) 104 is deposited over the epitaxial source / drain region 98, gate spacer 90, mask 86 (if present), or dummy gate 84. The first ILD 104 can be formed of a dielectric material, which can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), FCVD, etc. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used.

[0057] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain region 98, the gate spacer 90, and the mask 86 (if present) or the dummy gate 84. The CESL 102 may be formed of a dielectric material such as silicon nitride, silicon oxide, or silicon oxynitride, which has high etch selectivity relative to the etching of the first ILD 104. The CESL 102 may be formed by any suitable method such as CVD, ALD, etc.

[0058] exist Figure 11A-11B In this process, a removal process is performed to make the top surface of the first ILD 104 flush with the top surface of the mask 86 (if present) or the dummy gate 84. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84, as well as portions of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the gate spacer 90, the first ILD 104, CESL 102, and the top surfaces of the mask 86 (if present) or the dummy gate 84 are coplanar (within process variations). Therefore, the top surface of the mask 86 (if present) or the dummy gate 84 is exposed through the first ILD 104. In the illustrated embodiment, the mask 86 is retained, and the planarization process makes the top surface of the first ILD 104 flush with the top surface of the mask 86.

[0059] exist Figure 12A-12B In the etching process, the mask 86 (if present) and the dummy gate 84 are removed to form the recess 106. A portion of the dummy dielectric 82 within the recess 106 is also removed. In some embodiments, the dummy gate 84 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 84 at a rate faster than the first ILD 104 or the gate spacer 90. During removal, the dummy dielectric 82 may be used as an etch stop layer while the dummy gate 84 is etched. The dummy dielectric 82 is then removed. Each recess 106 exposes and / or covers a portion of the channel region 68. A portion of the second nanostructure 66 serving as the channel region 68 is disposed between adjacent pairs of epitaxial source / drain regions 98.

[0060] The remaining portion of the first nanostructure 64 is then removed to enlarge the recess 106, thereby forming an opening 108 in the region 50I between the second nanostructures 66. The remaining portion of the first nanostructure 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructure 64 at a rate faster than the material of the second nanostructure 66. The etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon-germanium and the second nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the second nanostructure 66. Figure 14A-16B As shown more clearly in (described in more detail later), the remainder of the second nanostructure 66 may have rounded corners.

[0061] exist Figures 13A-13B In the recess 106, a gate dielectric layer 112 is formed. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers used to replace the gate and each surrounds all (e.g., four) sides of the second nanostructure 66.

[0062] A gate dielectric layer 112 is disposed on the sidewalls and / or top surface of the fin 62; on the top surface, sidewalls, and bottom surface of the second nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric layer 112 may also be formed on the top surface of the first ILD 104 and the gate spacer 90. The gate dielectric layer 112 may comprise oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric layer 112 may comprise a dielectric material having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in Figures 13A-13B A single-layer gate dielectric layer 112 is shown, but as will be described in more detail later, the gate dielectric layer 112 may include any number of interface layers and any number of main layers.

[0063] The gate electrode layer 114 may include a metal-containing material, such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, or multiple layers thereof. Although in Figures 13A-13B The diagram shows a single gate electrode layer 114, but as will be described in more detail later, the gate electrode layer 114 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0064] The formation of the gate dielectric layer 112 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 112 in each region is formed of the same material, and the formation of the gate electrode layer 114 can occur simultaneously, such that the gate electrode layer 114 in each region is formed of the same material. In some embodiments, the gate dielectric layer 112 in each region can be formed by different processes, such that the gate dielectric layer 112 can be made of different materials and / or have different numbers of layers, and / or the gate electrode layer 114 in each region can be formed by different processes, such that the gate electrode layer 114 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions. In the following description, at least a portion of the gate electrode layer 114 in the n-type region 50N and the gate electrode layer 114 in the p-type region 50P are formed, respectively.

[0065] Figure 14A-16B The process of forming a gate dielectric layer 112 and a gate electrode layer 114 for replacing the gate is shown in the recess 106 in the p-type region 50P. Figure 14A , Figure 15A and Figure 16A It shows Figure 13A Features in region 50A. Figure 14B , Figure 15B and Figure 16B It shows Figure 13B Features in region 50B. The gate electrode layer 114 in the p-type region 50P includes one or more work function adjustment layers formed of a tungsten-containing material. Tungsten is suitable for adjusting the work function of the device in the p-type region 50P. Advantageously, forming one or more work function adjustment layers of tungsten-containing material can allow the gate electrode layer 114 in the p-type region 50P to have a lower resistance than a gate electrode layer having a work function adjustment layer formed of a material containing other metals (e.g., tantalum). Device performance can therefore be improved. The n-type region 50N can be masked at least while forming a portion of the gate electrode layer 114 in the p-type region 50P.

[0066] exist Figures 14A-14B In this configuration, a gate dielectric layer 112 is formed in the recess 106. The gate dielectric layer 112 may also be deposited on the top surface of the first ILD 104 and the gate spacer 90 (see [reference]). Figure 13BThe gate dielectric layer 112 can be formed using methods such as molecular beam deposition (MBD), ALD, PECVD, etc. The gate dielectric layer 112 surrounds all (e.g., four) sides of the second nanostructure 66. The gate dielectric layer 112 fills portions of regions 50I between the second nanostructures 66 in the p-type region 50P (e.g., portions of openings 108 in the p-type region 50P). In the illustrated embodiment, the gate dielectric layer 112 is multilayered, including an interface layer 112A (or more generally, a first gate dielectric sublayer) and an overlying high-k dielectric layer 112B (or more generally, a second gate dielectric sublayer). The interface layer 112A can be formed of silicon oxide, and the high-k dielectric layer 112B can be formed of hafnium oxide. The gate dielectric layer 112 can include any acceptable number and combination of sublayers.

[0067] exist Figures 15A-15B Optionally, a first work function adjustment layer 114A is formed on the gate dielectric layer 112 around the second nanostructure 66 in the p-type region 50P. As will be described in more detail later, in some embodiments, the first work function adjustment layer 114A is omitted. Then, a second work function adjustment layer 114B is formed on the first work function adjustment layer 114A (if present) or the gate dielectric layer 112 around the second nanostructure 66 in the p-type region 50P.

[0068] The first work function adjustment layer 114A (if present) is formed of a p-type work function material (PWFM). This PWFM, considering the application of the device to be formed, can be used to adjust the work function of the device to a desired amount and can be deposited using any acceptable deposition process. Specifically, the first work function adjustment layer 114A is formed of tungsten-free PWFM such as titanium nitride (TiN), tantalum nitride (TaN), or combinations thereof, which can be deposited by ALD, CVD, PVD, etc. The first work function adjustment layer 114A may also be referred to as a "tungsten-free work function adjustment layer." The first work function adjustment layer 114A may be included or omitted based on the desired work function of the resulting device. The thickness of the first work function adjustment layer 114A can range from about 5 Å to about 60 Å. In the illustrated embodiment, the first work function adjustment layer 114A is a single continuous layer of tungsten-free PWFM. In other embodiments, the first work function adjustment layer 114A is a multilayer of tungsten-free PWFM. The first work function adjustment layer 114A fills a portion of the region 50I between the second nanostructures 66 in the p-type region 50P (e.g., a portion of the opening 108 in the p-type region 50P).

[0069] The second work function adjustment layer 114B is formed of a p-type work function material (PWFM) with low resistivity and can be deposited using any acceptable deposition process. Specifically, the second work function adjustment layer 114B is formed of tungsten-containing PWFM such as pure tungsten (e.g., fluorine-free tungsten), tungsten nitride, tungsten carbide, tungsten carbonitride, etc., which can be deposited by ALD, CVD, PVD, etc. The second work function adjustment layer 114B can also be referred to as a "tungsten-containing work function adjustment layer". The thickness of the second work function adjustment layer 114B can be in the range of about 5 Å to about 60 Å. In the illustrated embodiment, the second work function adjustment layer 114B is a single continuous layer of tungsten-containing PWFM. In other embodiments (hereinafter referred to as...) Figures 22A-23B (As described below), the second work function adjustment layer 114B is a multilayer containing tungsten PWFM. The material of the second work function adjustment layer 114B can also be used to adjust the work function of the device to the desired amount (in a similar manner to the first work function adjustment layer 114A), but can have a lower resistivity than the material of the first work function adjustment layer 114A. Device performance can be improved by using PWFM with low resistivity.

[0070] In some embodiments, the second work function adjustment layer 114B is formed of fluorine-free tungsten, which is deposited using an ALD process. Specifically, the second work function adjustment layer 114B can be formed by placing a substrate 50 in a deposition chamber and cyclically distributing different source precursors into the deposition chamber. The source precursors include one or more tungsten source precursors and one or more precursors that react with the tungsten source precursors to form fluorine-free tungsten. Fluorine-free tungsten is fluorine-free tungsten and is deposited using fluorine-free tungsten source precursors, such as fluorine-free tungsten source precursors. Depositing tungsten using fluorine-free tungsten source precursors avoids the generation of undesirable corrosive fluoride byproducts during the deposition process, which can improve manufacturing yield.

[0071] The first pulse of the ALD cycle is performed by dispensing a first precursor into the deposition chamber. The first precursor is a fluorine-free tungsten source precursor. Acceptable fluorine-free tungsten source precursors include tungsten chloride (V) (WCl5), etc. The first precursor can be maintained in the deposition chamber for a duration ranging from about 0.2 seconds to about 5 seconds. The first precursor is then removed from the deposition chamber, for example by any acceptable vacuum process and / or by allowing an inert gas to flow into the deposition chamber.

[0072] The second pulse of the ALD cycle is performed by dispensing a second precursor into the deposition chamber. The second precursor is any acceptable precursor that reacts with the first precursor (e.g., a fluorine-free tungsten source precursor) to deposit fluorine-free tungsten. For example, when the first precursor is tungsten chloride (V), the second precursor could be hydrogen (H2), etc. The second precursor can be maintained in the deposition chamber for a duration ranging from about 0.2 seconds to about 5 seconds. The second precursor is then removed from the deposition chamber, for example, by any acceptable vacuum process and / or by introducing an inert gas into the deposition chamber.

[0073] Each ALD cycle results in the deposition of an atomic layer (sometimes called a monolayer) of fluorine-free tungsten. For example, when the first precursor is tungsten chloride (V) and the second precursor is hydrogen, they can be repeatedly reacted according to equations (1) and (2) to form gaseous byproducts (removed from the deposition chamber) and fluorine-free tungsten.

[0074] (1) (2)

[0075] The ALD cycle is repeated until fluorine-free tungsten is deposited to the desired thickness (previously described). For example, the ALD cycle can be repeated from about 1 to about 500 times. Furthermore, the ALD process can be performed at temperatures ranging from about 300 °C to about 500 °C and pressures ranging from about 0.5 Torr to about 50 Torr, for example, by maintaining the deposition chamber at such temperatures and pressures. Performing the ALD process with parameters within these ranges allows fluorine-free tungsten to be formed to the desired thickness (previously described) and quality. Performing the ALD process with parameters outside these ranges may not result in fluorine-free tungsten being formed to the desired thickness or quality.

[0076] In some embodiments, the second work function adjustment layer 114B is formed of tungsten nitride deposited by ALD. Tungsten nitride can be formed by an ALD process similar to that previously described for forming fluorine-free tungsten, except that different precursors can be used. For example, the first precursor can be a tungsten source precursor (which may be fluorine-free or may contain fluorine), and the second precursor can be a nitrogen source precursor that reacts with the first precursor (e.g., a tungsten source precursor) to deposit tungsten nitride. Acceptable tungsten source precursors for depositing tungsten nitride include bis(tert-butylimino)-bis(dimethylamino)tungsten (… t BuN)2(Me2N)2W, etc. Acceptable nitrogen source precursors for depositing tungsten nitride include ammonia (NH3), etc.

[0077] The ALD cycle is repeated until tungsten nitride is deposited to the desired thickness (previously described). For example, the ALD cycle can be repeated from about 1 to about 500 times. Furthermore, the ALD process can be performed at temperatures ranging from about 200 °C to about 450 °C and pressures ranging from about 0.1 Torr to about 60 Torr, for example, by maintaining the deposition chamber at such temperatures and pressures. Performing the ALD process with parameters within these ranges allows tungsten nitride to be formed to the desired thickness (previously described) and quality. Performing the ALD process with parameters outside these ranges may fail to form tungsten nitride to the desired thickness or quality.

[0078] The second work function adjustment layer 114B fills the remaining portion of region 50I between the second nanostructures 66 in the p-type region 50P (e.g., the remaining portion of opening 108 in the p-type region 50P). Specifically, the second work function adjustment layer 114B is deposited on the first work function adjustment layer 114A (if present) or the gate dielectric layer 112 until it is thick enough to fuse together. In embodiments where the first work function adjustment layer 114A is present, its thickness may be less than the thickness of the second work function adjustment layer 114B, which avoids fusion of the first work function adjustment layer 114A and promotes fusion of the second work function adjustment layer 114B. Interface 118 can be formed by contact between adjacent portions of the second work function adjustment layer 114B (e.g., those portions around the second nanostructures 66 in the p-type region 50P). Therefore, the opening 108 in the p-type region 50P is completely filled by the corresponding portions of the gate dielectric layer 112, the first work function adjustment layer 114A (if present), and the second work function adjustment layer 114B. Specifically, the corresponding portions of the gate dielectric layer 112 surround the corresponding second nanostructure 66 in the p-type region 50P, the corresponding portions of the first work function adjustment layer 114A surround the corresponding portions of the gate dielectric layer 112, and the corresponding portions of the second work function adjustment layer 114B surround the corresponding portions of the first work function adjustment layer 114A, thereby completely filling the region between the corresponding second nanostructures 66. When the second work function adjustment layer 114B is a single continuous layer of tungsten-free PWFM, the tungsten-free PWFM extends continuously between the corresponding portions of the first work function adjustment layer 114A (if present) or the corresponding portions of the dielectric layer 112. As described above, the first work function adjustment layer 114A is a tungsten-free layer. In the p-type region, no tungsten-containing layer is provided between the second work function adjustment layer 114B and the second nanostructure 66.

[0079] exist Figures 16A-16BIn this process, a filler layer 114E is deposited on a second work function adjustment layer 114B. Optionally, a binder layer 114D is formed between the filler layer 114E and the second work function adjustment layer 114B. After formation, the gate electrode layer 114 in the p-type region 50P includes a first work function adjustment layer 114A, a second work function adjustment layer 114B, a binder layer 114D, and a filler layer 114E.

[0080] The adhesive layer 114D comprises any acceptable material to promote adhesion and prevent diffusion. For example, the adhesive layer 114D can be formed of a metal or a metal nitride such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, etc., which can be deposited by ALD, CVD, PVD, etc.

[0081] The filler layer 114E comprises any acceptable low-resistivity material. For example, the filler layer 114E can be formed of metals such as tungsten, aluminum, cobalt, ruthenium, or combinations thereof, which can be deposited by ALD, CVD, PVD, etc. The filler layer 114E fills the remaining portion of the recess 106.

[0082] Figures 17A-17B The gate dielectric layer 112 and gate electrode layer 114 for replacing the gate are shown in the recess 106 formed in the n-type region 50N. Figure 17A It shows Figure 13A Features in region 50A. Figure 17B It shows Figure 13B Features in region 50B. In some embodiments, gate dielectric layers 112 in both n-type region 50N and p-type region 50P can be formed simultaneously. Furthermore, at least a portion of the gate electrode layer 114 in n-type region 50N can be formed before or after the formation of the gate electrode layer 114 in p-type region 50P, and at least a portion of the gate electrode layer 114 in n-type region 50N can be formed while masking p-type region 50P. Thus, the gate electrode layer 114 in n-type region 50N can include a different material than the gate electrode layer 114 in p-type region 50P. For example, the gate electrode layer 114 in n-type region 50N can include a third work function adjustment layer 114C, a binder layer 114D, and a filler layer 114E. As will be described in more detail later, the third work function adjustment layer 114C has a different material composition than the first work function adjustment layer 114A and the second work function adjustment layer 114B. The adhesive layer 114D in the n-type region 50N may have (or may not have) the same material composition as the adhesive layer 114D in the p-type region 50P (and be deposited therewith). The filler layer 114E in the n-type region 50N may have (or may not have) the same material composition as the filler layer 114E in the p-type region 50P (and be deposited therewith).

[0083] The third work function adjustment layer 114C is formed of an n-type work function material (NWFM). Considering the application of the device to be formed, this n-type work function material (NWFM) can be used to adjust the work function of the device to a desired amount and can be deposited using any acceptable deposition process. Specifically, the third work function adjustment layer 114C is formed of a tungsten-free NWFM such as titanium aluminide, titanium aluminum carbide, aluminum tantalum, tantalum carbide, or combinations thereof, which can be deposited by ALD, PEALD, PVD, CVD, PECVD, etc. The material of the third work function adjustment layer 114C is different from the materials of the first work function adjustment layer 114A and the second work function adjustment layer 114B. In some embodiments, the first work function adjustment layer 114A may be formed of titanium nitride, the second work function adjustment layer 114B may be formed of fluorine-free tungsten or tungsten nitride, and the third work function adjustment layer 114C may be formed of titanium aluminide.

[0084] The material of the third work function adjustment layer 114C can also have a low resistivity (in a similar manner to the second work function adjustment layer 114B). The material of the third work function adjustment layer 114C can have a lower resistivity than the material of the first work function adjustment layer 114A. Device performance can be improved by using an NWFM with low resistivity. The material of the third work function adjustment layer 114C can have a higher or lower resistivity than the material of the second work function adjustment layer 114B. In some embodiments, the resistivity of the material of the third work function adjustment layer 114C is lower than that of the material of the first work function adjustment layer 114A and higher than that of the material of the second work function adjustment layer 114B.

[0085] The third work function adjustment layer 114C fills the remaining portion of region 50I between the second nanostructures 66 in the n-type region 50N (e.g., the remaining portion of opening 108 in the n-type region 50N). Specifically, the third work function adjustment layer 114C is deposited on the gate dielectric layer 112 until it is thick enough to be joined together. Interface 120 can be formed by contact between adjacent portions of the third work function adjustment layer 114C (e.g., those portions surrounding the second nanostructures 66 in the n-type region 50N). The corresponding portions of the gate dielectric layer 112 surround the corresponding second nanostructures 66 in the n-type region 50N, and the corresponding portions of the third work function adjustment layer 114C surround the corresponding portions of the gate dielectric layer 112, thereby completely filling the region between the corresponding second nanostructures 66.

[0086] exist Figures 18A-18BIn this process, a removal process is performed to remove excess material from the gate dielectric layer 112 and the gate electrode layer 114, which lies above the top surfaces of the first ILD 104 and the gate spacer 90, thereby forming the gate dielectric 122 and the gate electrode 124. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof may be utilized. The gate dielectric layer 112 has a portion remaining in the recess 106 during planarization (thus forming the gate dielectric 122). The gate electrode layer 114 has a portion remaining in the recess 106 during planarization (thus forming the gate electrode 124). The top surfaces of the following items are flush (within process variations): gate spacer 90; CESL 102; first ILD 104; gate dielectric 122 (e.g., interface layer 112A and high-k dielectric layer 112B, see...). Figure 14A-17B ); and gate electrode 124 (e.g., work function adjustment layers 114A, 114B, 114C, adhesive layer 114D (if present) and filler layer 114E, see Figure 14A-17B The gate dielectric 122 and gate electrode 124 form the replacement gate of the obtained nanoFET. Each pair of gate dielectric 122 and gate electrode 124 may be collectively referred to as a "gate structure". Each gate structure extends along the top surface, sidewalls and bottom surface of the channel region 68 of the second nanostructure 66.

[0087] exist Figures 19A-19B In this configuration, the second ILD 134 is deposited over the gate spacer 90, CESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 134 is formed from a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method such as CVD, PECVD, etc.

[0088] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacer 90, ESL 102, the first ILD 104, the gate dielectric 122, and the gate electrode 124. The ESL 132 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has high etch selectivity relative to the etching of the second ILD 134.

[0089] exist Figures 20A-20BIn this configuration, gate contact 142 and source / drain contact 144 are formed to contact gate electrode 124 and epitaxial source / drain region 98, respectively. Gate contact 142 is physically and electrically coupled to gate electrode 124. Source / drain contact 144 is physically and electrically coupled to epitaxial source / drain region 98.

[0090] As an example of forming the gate contact 142 and the source / drain contact 144, an opening for the gate contact 142 is formed through the second ILD 134 and ESL 132, and an opening for the source / drain contact 144 is formed through the second ILD 134, ESL 132, the first ILD 104, and CESL 102. These openings can be formed using acceptable photolithography and etching techniques. A liner (not shown separately), such as a diffusion barrier layer or adhesion layer, and a conductive material are formed within the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 134. The remaining liner and conductive material form the gate contact 142 and the source / drain contact 144 within the openings. The gate contact 142 and the source / drain contact 144 can be formed using different processes or using the same process. Although each of the gate contact 142 and the source / drain contact 144 is shown to have the same cross-section, it should be understood that each of the gate contact 142 and the source / drain contact 144 can be formed to have different cross-sections, which can prevent short circuits in the contacts.

[0091] Optionally, a metal-semiconductor alloy region 146 is formed at the interface between the epitaxial source / drain region 98 and the source / drain contact 144. The metal-semiconductor alloy region 146 may be a silicide region formed of metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanium region formed of metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanium region formed of both metal silicides and metal germanides. The metal-semiconductor alloy region 146 can be formed before one or more materials of the source / drain contact 144 by depositing metal in the opening for the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the epitaxial source / drain region 98 to form a low-resistance metal-semiconductor alloy (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof). The metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process such as wet cleaning can be performed to remove any residual metal from the openings of the source / drain contact 144, for example, from the surface of the metal-semiconductor alloy region 146. Then, one or more materials of the source / drain contact 144 can be formed on the metal-semiconductor alloy region 146.

[0092] Figures 21A-21B This is a view of a nanoFET according to some other embodiments. Except for omitting the first work function adjustment layer 114A, this embodiment is similar to that of... Figures 16A-16B The described embodiment. Therefore, the opening 108 in the p-type region 50P is completely filled by the corresponding portions of the gate dielectric layer 112 and the second work function adjustment layer 114B. In the illustrated embodiment, the second work function adjustment layer 114B is a single continuous layer of tungsten-containing PWFM, such that the tungsten-containing PWFM extends continuously between the corresponding portions of the dielectric layer 112.

[0093] Figures 22A-23B This is a view of a nano-FET according to some other embodiments. These embodiments are similar to those for [other embodiments], except that the second work function adjustment layer 114B is a multilayer tungsten-containing PWFM. Figures 21A-21B The described embodiments. Although Figures 22A-23B An embodiment in which the first work function adjustment layer 114A is omitted is shown; however, it should be understood that in other embodiments, the first work function adjustment layer 114A is included. In some embodiments, the second work function adjustment layer 114B is a bilayer tungsten-containing PWFM, including a first work function adjustment sublayer 114B1 and a second work function adjustment sublayer 114B2 on the first work function adjustment sublayer 114B1, such as... Figures 22A-22BAs shown. In some embodiments, the second work function adjustment layer 114B is a three-layer tungsten-containing PWFM, which is similar to a two-layer structure, but further includes a third work function adjustment sublayer 114B3 on top of the second work function adjustment sublayer 114B2, as shown. Figures 23A-23B As shown. Each sublayer is a single continuous layer of different tungsten-containing PWFM. The tungsten-containing material of the first work function adjusting sublayer 114B1 may be the same as (or different from) the tungsten-containing material of the third work function adjusting sublayer 114B3. In some embodiments, the first work function adjusting sublayer 114B1 is fluorine-free tungsten, the second work function adjusting sublayer 114B2 is tungsten nitride, and the third work function adjusting sublayer 114B3 (if present) is fluorine-free tungsten. In some embodiments, the first work function adjusting sublayer 114B1 is tungsten nitride, the second work function adjusting sublayer 114B2 is fluorine-free tungsten, and the third work function adjusting sublayer 114B3 (if present) is tungsten nitride.

[0094] When the second work function adjustment layer 114B is a multilayer tungsten-containing PWFM, sublayers of tungsten-containing PWFM are deposited such that the lower sublayers of the second work function adjustment layer 114B (e.g., the first work function adjustment sublayer 114B1) merge and bond together. For example, the lower sublayer of the second work function adjustment layer 114B may have a greater thickness than each of the upper sublayer(s) of the second work function adjustment layer 114B (e.g., the third work function adjustment sublayer 114B3 (if present) and the second work function adjustment sublayer 114B2), which can avoid merging of the upper sublayer(s) and promote merging of the lower sublayer.

[0095] Some embodiments are intended to use other tungsten-containing PWFMs. For example, although some of the foregoing embodiments use tungsten nitride for tungsten-containing PWFMs, tungsten carbides may also be used. In some embodiments, tungsten carbide and / or tungsten carbonitride may be used instead of tungsten nitride (or tungsten carbide and / or tungsten carbonitride may be used in addition to tungsten nitride).

[0096] The embodiments offer advantages. Tungsten is suitable for adjusting the work function of the device in the p-type region 50P. Forming a second work function adjustment layer 114B from a tungsten-containing PWFM allows for adjustment of the threshold voltage of the resulting device. Furthermore, the tungsten-containing PWFM has low resistivity. Forming a second work function adjustment layer 114B from a tungsten-containing PWFM allows the gate electrode 124 in the p-type region 50P to have, for example, a lower resistance than the gate electrode of the work function adjustment layer, which is formed from a PWFM containing other metals (e.g., tantalum). Therefore, device performance can be improved.

[0097] In one embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric layer surrounding the first and second nanostructures; a tungsten-free work function adjustment layer surrounding the gate dielectric layer; a tungsten-containing work function adjustment layer surrounding the tungsten-free work function adjustment layer, wherein a region between the first and second nanostructures is completely filled by corresponding portions of the tungsten-containing work function adjustment layer, the tungsten-free work function adjustment layer, and the gate dielectric layer; and a filling layer located on the tungsten-containing work function adjustment layer. In some embodiments of the device, the resistivity of the first material of the tungsten-containing work function adjustment layer is lower than the resistivity of the second material of the tungsten-free work function adjustment layer. In some embodiments of the device, the tungsten-containing work function adjustment layer comprises fluorine-free tungsten. In some embodiments of the device, the tungsten-containing work function adjustment layer comprises tungsten nitride, tungsten carbide, or tungsten carbonitride. In some embodiments of the device, the tungsten-containing work function adjustment layer is a single continuous layer of tungsten-containing material. In some embodiments of the device, the tungsten-containing work function adjustment layer includes: a first layer of a first tungsten-containing material surrounding a tungsten-free work function adjustment layer; and a second layer of a second tungsten-containing material surrounding the first tungsten-containing material, wherein the second tungsten-containing material is different from the first tungsten-containing material. In some embodiments of the device, the tungsten-containing work function adjustment layer further includes: a third layer of the first tungsten-containing material surrounding the second tungsten-containing material.

[0098] In one embodiment, a device includes: a p-type transistor comprising: a first channel region; a first gate dielectric layer located on the first channel region; a tungsten-containing work function adjustment layer located on the first gate dielectric layer; and a first fill layer located on the tungsten-containing work function adjustment layer; and an n-type transistor comprising: a second channel region; a second gate dielectric layer located on the second channel region; a tungsten-free work function adjustment layer located on the second gate dielectric layer; and a second fill layer located on the tungsten-free work function adjustment layer. In some embodiments of the device, no tungsten-containing layer is disposed between the first channel region and the tungsten-containing work function adjustment layer. In some embodiments of the device, the tungsten-containing work function adjustment layer comprises fluorine-free tungsten or tungsten nitride, and the tungsten-free work function adjustment layer comprises titanium aluminide.

[0099] In one embodiment, a method includes: forming a gate dielectric layer having a first portion surrounding a first nanostructure; depositing a first tungsten-free work function material on the first portion of the gate dielectric layer; depositing a tungsten-containing work function material on the first tungsten-free work function material, the resistivity of the tungsten-containing work function material being lower than that of the first tungsten-free work function material; and depositing a filler layer on the tungsten-containing work function material. In some embodiments of the method, depositing the tungsten-containing work function material includes: depositing fluorine-free tungsten by an ALD process performed using tungsten chloride (V) and hydrogen, the ALD process being performed at a temperature in the range of 300 °C to 500 °C, and at a pressure in the range of 0.5 Torr to 50 Torr. In some embodiments of the method, depositing a tungsten-containing work function material includes: depositing tungsten nitride via an ALD process, the ALD process being performed using bis(tert-butylimino)-bis(dimethylamino)tungsten and ammonia, the ALD process being performed at a temperature ranging from 200 °C to 450 °C, and at a pressure ranging from 0.1 Torr to 60 Torr. In some embodiments of the method, depositing a tungsten-containing work function material includes: depositing a single continuous layer of the tungsten-containing work function material. In some embodiments of the method, depositing a tungsten-containing work function material includes: depositing multiple layers of the tungsten-containing work function material. In some embodiments of the method, the gate dielectric layer has a second portion surrounding a second nanostructure, and the method further includes: depositing a second tungsten-free work function material on the second portion of the gate dielectric layer, the second tungsten-free work function material being different from the first tungsten-free work function material; and depositing a filler layer on the second tungsten-free work function material. In some embodiments, the method further includes: growing p-type source / drain regions on a substrate, with a first nanostructure disposed between the p-type source / drain regions; and growing n-type source / drain regions on a substrate, with a second nanostructure disposed between the n-type source / drain regions. In some embodiments of the method, the resistivity of the second tungsten-free work function material is lower than the resistivity of the first tungsten-free work function material and higher than the resistivity of the tungsten-containing work function material. In some embodiments of the method, the first tungsten-free work function material comprises titanium nitride, the tungsten-containing work function material comprises fluorine-free tungsten or tungsten nitride, and the second tungsten-free work function material comprises titanium aluminide. In some embodiments of the method, the first tungsten-free work function material is deposited to a first thickness, and the tungsten-containing work function material is deposited to a second thickness, the second thickness being greater than the first thickness.

[0100] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0101] Example 1 is a semiconductor device comprising: a first nanostructure; a second nanostructure; a gate dielectric layer surrounding the first nanostructure and the second nanostructure; a tungsten-free work function adjustment layer surrounding the gate dielectric layer; a tungsten-containing work function adjustment layer surrounding the tungsten-free work function adjustment layer, wherein a region between the first nanostructure and the second nanostructure is completely filled by corresponding portions of the tungsten-containing work function adjustment layer, the tungsten-free work function adjustment layer, and the gate dielectric layer; and a filling layer located on the tungsten-containing work function adjustment layer.

[0102] Example 2 is the semiconductor device described in Example 1, wherein the resistivity of the first material containing the tungsten work function adjustment layer is lower than the resistivity of the second material without the tungsten work function adjustment layer.

[0103] Example 3 is the semiconductor device described in Example 1, wherein the tungsten-containing work function adjustment layer comprises fluorine-free tungsten.

[0104] Example 4 is the semiconductor device described in Example 1, wherein the tungsten-containing work function adjustment layer comprises tungsten nitride, tungsten carbide, or tungsten carbonitride.

[0105] Example 5 is the semiconductor device described in Example 1, wherein the tungsten work function adjustment layer is a single continuous layer of tungsten-containing material.

[0106] Example 6 is the semiconductor device described in Example 1, wherein the tungsten-containing work function adjustment layer comprises: a first layer of a first tungsten-containing material surrounding the tungsten-free work function adjustment layer; and a second layer of a second tungsten-containing material surrounding the first layer of the first tungsten-containing material, the second tungsten-containing material being different from the first tungsten-containing material.

[0107] Example 7 is the semiconductor device described in Example 6, wherein the tungsten-containing work function adjustment layer further includes: a third layer of the first tungsten-containing material surrounding a second layer of the second tungsten-containing material.

[0108] Example 8 is a semiconductor device comprising: a p-type transistor including: a first channel region; a first gate dielectric layer located on the first channel region; a tungsten-containing work function adjustment layer located on the first gate dielectric layer; and a first fill layer located on the tungsten-containing work function adjustment layer; and an n-type transistor including: a second channel region; a second gate dielectric layer located on the second channel region; a tungsten-free work function adjustment layer located on the second gate dielectric layer; and a second fill layer located on the tungsten-free work function adjustment layer.

[0109] Example 9 is the semiconductor device described in Example 8, wherein no tungsten-containing layer is disposed between the first channel region and the tungsten-containing work function adjustment layer.

[0110] Example 10 is the semiconductor device described in Example 8, wherein the tungsten work function adjustment layer comprises fluorine-free tungsten or tungsten nitride, and the tungsten-free work function adjustment layer comprises titanium aluminide.

[0111] Example 11 is a method for manufacturing a semiconductor device, comprising: forming a gate dielectric layer having a first portion surrounding a first nanostructure; depositing a first tungsten-free work function material on the first portion of the gate dielectric layer; depositing a tungsten-containing work function material on the first tungsten-free work function material, the resistivity of the tungsten-containing work function material being lower than that of the first tungsten-free work function material; and depositing a filler layer on the tungsten-containing work function material.

[0112] Example 12 is the method described in Example 11, wherein depositing the tungsten-containing work function material comprises: depositing fluorine-free tungsten by an ALD process, the ALD process being performed using tungsten chloride (V) and hydrogen, the ALD process being performed at a temperature in the range of 300 °C to 500 °C, and the ALD process being performed at a pressure in the range of 0.5 Torr to 50 Torr.

[0113] Example 13 is the method described in Example 11, wherein depositing the tungsten-containing work function material comprises: depositing tungsten nitride by an ALD process, the ALD process being performed using bis(tert-butylimino)-bis(dimethylamino)tungsten and ammonia, the ALD process being performed at a temperature in the range of 200 °C to 450 °C, and the ALD process being performed at a pressure in the range of 0.1 Torr to 60 Torr.

[0114] Example 14 is the method described in Example 11, wherein depositing the tungsten work function material comprises: depositing a single continuous layer of the tungsten work function material.

[0115] Example 15 is the method described in Example 11, wherein depositing the tungsten work function material includes: depositing a multilayer of the tungsten work function material.

[0116] Example 16 is the method of Example 11, wherein the gate dielectric layer has a second portion surrounding the second nanostructure, and the method further includes: depositing a second tungsten-free work function material on the second portion of the gate dielectric layer, the second tungsten-free work function material being different from the first tungsten-free work function material; and depositing the filler layer on the second tungsten-free work function material.

[0117] Example 17 is the method of Example 16, further comprising: growing p-type source / drain regions on a substrate, wherein the first nanostructure is disposed between the p-type source / drain regions; and growing n-type source / drain regions on the substrate, wherein the second nanostructure is disposed between the n-type source / drain regions.

[0118] Example 18 is the method described in Example 16, wherein the resistivity of the second tungsten-free work function material is lower than the resistivity of the first tungsten-free work function material and higher than the resistivity of the tungsten-containing work function material.

[0119] Example 19 is the method described in Example 16, wherein the first tungsten-free work function material comprises titanium nitride, the tungsten-containing work function material comprises fluorine-free tungsten or tungsten nitride, and the second tungsten-free work function material comprises titanium aluminide.

[0120] Example 20 is the method described in Example 11, wherein the first tungsten-free work function material is deposited to a first thickness, and the tungsten-containing work function material is deposited to a second thickness, the second thickness being greater than the first thickness.

Claims

1. A semiconductor device, comprising: First nanostructure; Second nanostructure; A gate dielectric layer surrounds the first nanostructure and the second nanostructure; A tungsten-free work function adjustment layer surrounds the gate dielectric layer; A tungsten-containing work function adjustment layer surrounds the tungsten-free work function adjustment layer. The region between the first nanostructure and the second nanostructure is completely filled by corresponding portions of the tungsten-containing work function adjustment layer, the tungsten-free work function adjustment layer, and the gate dielectric layer. The resistivity of the first material of the tungsten-containing work function adjustment layer is lower than the resistivity of the second material of the tungsten-free work function adjustment layer. A filling layer is located on the tungsten-containing work function adjustment layer.

2. The semiconductor device of claim 1, wherein, The tungsten-containing work function adjustment layer includes fluorine-free tungsten.

3. The semiconductor device of claim 1, wherein, The tungsten-containing work function adjustment layer includes tungsten nitride, tungsten carbide, or tungsten carbonitride.

4. The semiconductor device of claim 1, wherein, The tungsten-containing work function adjustment layer is a single continuous layer of tungsten-containing material.

5. The semiconductor device of claim 1, wherein, The tungsten-containing work function adjustment layer includes: A first layer of a first tungsten-containing material, surrounding the tungsten-free work function adjustment layer; and A second layer of a second tungsten-containing material surrounds a first layer of a first tungsten-containing material, and the second tungsten-containing material is different from the first tungsten-containing material.

6. The semiconductor device of claim 5, wherein, The tungsten-containing work function adjustment layer also includes: The third layer of the first tungsten-containing material surrounds the second layer of the second tungsten-containing material.

7. A semiconductor device, comprising: p-type transistor, the p-type transistor comprising: First trench area; A first gate dielectric layer is located on the first channel region; A tungsten work function adjustment layer is located on the first gate dielectric layer; and A first filling layer, which is located on the tungsten-containing work function adjustment layer; and An n-type transistor, comprising: Second trench area; A second gate dielectric layer is located on the second channel region; A tungsten-free work function adjustment layer is located on the second gate dielectric layer; and The second filling layer is located on the tungsten-free work function adjustment layer. The resistivity of the first material in the tungsten-containing work function adjustment layer is lower than that of the second material in the tungsten-free work function adjustment layer.

8. The semiconductor device of claim 7, wherein, No tungsten-containing layer is provided between the first channel region and the tungsten-containing work function adjustment layer.

9. The semiconductor device of claim 7, wherein, The tungsten-containing work function adjustment layer includes fluorine-free tungsten or tungsten nitride, and the tungsten-free work function adjustment layer includes titanium aluminide.

10. A method for manufacturing a semiconductor device, comprising: A gate dielectric layer having a first portion surrounding the first nanostructure is formed; A first tungsten-free work function material is deposited on the first portion of the gate dielectric layer; A tungsten-containing work function material is deposited on the first tungsten-free work function material, wherein the resistivity of the tungsten-containing work function material is lower than that of the first tungsten-free work function material; and A filling layer is deposited on the tungsten-containing work function material.

11. The method of claim 10, wherein, The tungsten-containing work function material to be deposited includes: Fluorine-free tungsten is deposited using an ALD process, which is performed with tungsten chloride (V) and hydrogen, at a temperature ranging from 300 °C to 500 °C, and at a pressure ranging from 0.5 Torr to 50 Torr.

12. The method of claim 10, wherein, The tungsten-containing work function material to be deposited includes: Tungsten nitride is deposited by an ALD process, wherein the ALD process is performed using bis(tert-butylimino)-bis(dimethylamino)tungsten and ammonia, the ALD process is performed at a temperature ranging from 200 °C to 450 °C, and the ALD process is performed at a pressure ranging from 0.1 Torr to 60 Torr.

13. The method of claim 10, wherein, The tungsten-containing work function material to be deposited includes: Deposit a single continuous layer of the tungsten work function material.

14. The method of claim 10, wherein, The tungsten-containing work function material to be deposited includes: Multilayer deposition of tungsten work function-containing materials.

15. The method of claim 10, wherein, The gate dielectric layer has a second portion surrounding the second nanostructure, and the method further includes: A second tungsten-free work function material is deposited on the second portion of the gate dielectric layer, the second tungsten-free work function material being different from the first tungsten-free work function material; and The filling layer is deposited on the second tungsten-free work function material.

16. The method of claim 15, further comprising: A p-type source / drain region is grown on a substrate, and the first nanostructure is disposed between the p-type source / drain regions; as well as An n-type source / drain region is grown on the substrate, and the second nanostructure is disposed between the n-type source / drain regions.

17. The method according to claim 15, wherein, The resistivity of the second tungsten-free work function material is lower than that of the first tungsten-free work function material, but higher than that of the tungsten-containing work function material.

18. The method according to claim 15, wherein, The first tungsten-free work function material includes titanium nitride, the tungsten-containing work function material includes fluorine-free tungsten or tungsten nitride, and the second tungsten-free work function material includes titanium aluminide.

19. The method according to claim 10, wherein, The first tungsten-free work function material is deposited to a first thickness, and the tungsten-containing work function material is deposited to a second thickness, the second thickness being greater than the first thickness.

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