Transistor with elevated extension region and semiconductor fin

Abstract

This application relates to transistors with elevated extension regions and semiconductor fins. The invention provides apparatus and methods of forming similar transistors, the apparatus having a transistor connected between a voltage node and a load node, where the transistor includes: a dielectric material with a semiconductor material overlying the dielectric material, the semiconductor material including a fin and having a first conductivity type; a conductor overlying the dielectric material; first and second extension region bases formed in the semiconductor material and having a second conductivity type; first and second extension region risers formed overlying the respective first and second extension region bases and having the second conductivity type; and first and second source / drain regions formed in the respective first and second extension region risers and having the second conductivity type at a higher level of conductivity than their respective extension region risers.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuits, and more specifically, in one or more embodiments, to transistors having raised extension regions and semiconductor fins, as well as devices containing such transistors and methods of forming such transistors. Background Technology

[0002] Integrated circuit devices span a wide range of electronic devices. One specific type includes memory devices, often simply referred to as memory. Memory devices are typically provided as internal components, semiconductors, or integrated circuit devices in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0003] Flash memory has evolved into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. By programming (often referred to as writing) the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the use of non-volatile memory continues to expand.

[0004] NAND flash memory is a common type of flash memory device, so named because of the logical form of its basic memory cell configuration. Typically, the memory cell array for NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns in the array comprise strings of memory cells (often called NAND strings) connected in series between a pair of select gates (e.g., source select transistors and drain select transistors). Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0005] In memory devices, access to memory cells (e.g., programming memory cells) typically utilizes high voltage levels, potentially exceeding 20V, passed to the control gates of those memory cells. Gate-leveling of such voltage levels often relies on transistors with high breakdown voltages, such as field-effect transistors (FETs). One technique for creating transistors with high breakdown voltages utilizes a lightly doped region between the transistor's source / drain regions and the control gate. This region is often referred to as the extended region. Such transistors typically require a relatively high surface area on the substrate on which the integrated circuit device is fabricated. Summary of the Invention

[0006] In one aspect, this disclosure relates to an apparatus comprising: a voltage node; a load node; and a transistor connected between the voltage node and the load node, the transistor comprising: a semiconductor overlying a substrate, wherein the semiconductor includes a plurality of fins overlying the substrate, and wherein the semiconductor has a first conductivity type; a plurality of plugs of a first dielectric, wherein each of the plurality of plugs of the first dielectric is formed between a pair of fins of the plurality of fins of the semiconductor; a second dielectric overlying the semiconductor; a conductor overlying the second dielectric; a first extension region substrate formed in the semiconductor and extending beyond a first edge of the conductor, wherein the first extension region substrate has a second conductivity type different from the first conductivity type; and a second extension region substrate formed in the semiconductor. The second extension region extends beyond a second edge of the conductor opposite to a first edge of the conductor, wherein the second extension region substrate has a second conductivity type; a first extension region vertical plate is formed over the first extension region substrate and has a second conductivity type; a second extension region vertical plate is formed over the second extension region substrate and has a second conductivity type; a first source / drain region is formed in the first extension region vertical plate and connected to a voltage node, wherein the first source / drain region has a second conductivity type and has a conductivity level greater than that of the first extension region vertical plate; and a second source / drain region is formed in the second extension region vertical plate and connected to a load node, wherein the second source / drain region has a second conductivity type and has a conductivity level greater than that of the second extension region vertical plate.

[0007] In another aspect, this disclosure relates to a memory comprising: an array of memory cells; a plurality of access lines, each of the plurality of access lines generally connected to a control gate of a corresponding plurality of memory cells in the array of memory cells; and a driver circuit system comprising a plurality of transistors, wherein each of the plurality of transistors has a first source / drain region connected to a corresponding access line of the plurality of access lines; wherein a particular transistor of the plurality of transistors comprises: a semiconductor overlying a substrate, wherein the semiconductor comprises a plurality of fins overlying the substrate, and wherein the semiconductor has a first conductivity type; a plurality of plugs of a first dielectric, wherein each of the plurality of plugs of the first dielectric is formed between a pair of fins of the plurality of fins of the semiconductor; a second dielectric overlying the semiconductor; a conductor overlying the second dielectric; and a first extension region substrate formed in the semiconductor and extending beyond the conductor. An edge, wherein a first extension region substrate has a second conductivity type different from a first conductivity type; a second extension region substrate formed in a semiconductor and extending beyond a conductor to a second edge opposite to the first edge of the conductor, wherein the second extension region substrate has a second conductivity type; a first extension region vertical plate formed over the first extension region substrate and having a second conductivity type; a second extension region vertical plate formed over the second extension region substrate and having a second conductivity type; a first source / drain region formed in the first extension region vertical plate and connected to a voltage node, wherein the first source / drain region has a second conductivity type and has a conductivity level greater than that of the first extension region vertical plate; and a second source / drain region formed in the second extension region vertical plate and connected to a load node, wherein the second source / drain region has a second conductivity type and has a conductivity level greater than that of the second extension region vertical plate.

[0008] In other aspects, this disclosure relates to a method of forming a transistor, comprising: forming a semiconductor having a first conductivity type; patterning the semiconductor to define a plurality of fins of the semiconductor; forming a plurality of plugs of a first dielectric, wherein each of the plurality of plugs of the first dielectric is located between a pair of fins of the semiconductor in the plurality of fins of the semiconductor; forming a second dielectric overlying the semiconductor; forming a conductor overlying the second dielectric; patterning the conductor to define a gate stack of the transistor; and forming a first extension region substrate and a second extension region substrate in the semiconductor, wherein the first extension region substrate and the second extension region substrate each have a first conductivity type. A second conductivity type of different type; forming a first extension region vertical plate covering a first extension region substrate, wherein the first extension region vertical plate has a second conductivity type; forming a second extension region vertical plate covering a second extension region substrate, wherein the second extension region vertical plate has a second conductivity type; forming a first source / drain region in the first extension region vertical plate, wherein the first source / drain region has a second conductivity type and has a conductivity level greater than that of the first extension region vertical plate; and forming a second source / drain region in the second extension region vertical plate, wherein the second source / drain region has a second conductivity type and has a conductivity level greater than that of the second extension region vertical plate. Attached Figure Description

[0009] Figure 1 A simplified block diagram of a memory that communicates with a processor as part of an electronic system according to an embodiment.

[0010] Figures 2A to 2C For reference only Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0011] Figure 3A For reference only Figure 1 A schematic diagram of a portion of the memory cell array and string driver in a memory device of the described type.

[0012] Figure 3B For reference only Figure 1 A schematic diagram of a portion of an instance of a string driver in a memory of the described type.

[0013] Figure 3C For reference only Figure 1 A schematic diagram of a portion of another instance of a string driver in a memory of the described type.

[0014] Figure 4A This is a planar diagram of a transistor related to the technology.

[0015] Figure 4B for Figure 4A A cross-sectional view of a transistor.

[0016] Figure 5A This is a plan view of a transistor according to an embodiment.

[0017] Figure 5B for Figure 5A A cross-sectional view of a transistor.

[0018] Figure 6A This is a plan view of a transistor according to an embodiment.

[0019] Figures 6B to 6E for Figure 6A A cross-sectional view of a transistor.

[0020] Figures 7A to 7M For various manufacturing states according to the embodiments Figure 5B A cross-sectional view of a transistor.

[0021] Figures 8A to 8B This is a cross-sectional view of a transistor according to other embodiments.

[0022] Figures 9A to 9B This is a perspective view of a semiconductor with fins according to an embodiment.

[0023] Figure 10 This is a flowchart of a method for forming a transistor according to an embodiment.

[0024] Figure 11 A conceptual depiction of the connection of a portion of a string driver connected to access lines of a plurality of memory cell blocks, according to an embodiment. Detailed Implementation

[0025] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and specific embodiments are illustrated by way of description. In the drawings, like reference numerals describe generally similar components throughout several views. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0026] As used herein, the term "semiconductor" may refer to, for example, a material layer, a wafer, or a substrate, and includes any basic semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a basic semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the basic semiconductor structure using prior process steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0027] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0028] This paper recognizes that even when values ​​are expected to be equal, the variability and precision of industrial processing and operation can still cause differences from their expected values. These variability and precision will typically depend on the technology utilized in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then those values ​​are considered equal regardless of their resulting values.

[0029] Figure 1 This is a simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100, which is part of a third device in the form of an electronic system and communicates with a second device in the form of a processor 130, according to an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, etc. The processor 130 (e.g., a controller external to the memory device 100) may be a memory controller or other external host device.

[0030] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in a logical row are commonly connected to the same access line (collectively referred to as a word line), while memory cells in a logical column are typically selectively connected to the same data line (collectively referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0031] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data into and from memory device 100, as well as the output of data and status information. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0032] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and can generate status information for external processor 130; that is, control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to addresses.

[0033] Control logic 116 may also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, such as data guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 for output to external processor 130; then, new data can be transferred from data register 120 back to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form part of said page buffer). The page buffer may further include sensing devices ( Figure 1 (Not shown in the diagram) The data state of the memory cells can be sensed, for example, by sensing the state of the data lines of the memory cells connected to the memory cell array 104. The status register 122 can communicate with the I / O control circuitry 112 and the control logic 116 to latch status information for output to the processor 130.

[0034] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received further via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134, and outputs data to the processor 130 via the I / O bus 134.

[0035] For example, commands can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134, and then written to command register 124. Addresses can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134, and then written to address register 114. Data can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and then written to cache register 118. The data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0036] Those skilled in the art should understand that additional circuitry and signals can be provided, and that simplification has been achieved. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality can exceed that of a single block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0037] Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0038] Figure 2A For reference only Figure 1 A schematic diagram of a memory cell array 200A (e.g., a NAND memory array) that is part of a memory cell array 104 in a memory of the described type. The memory array 200A includes access lines (e.g., word lines) 2020 to 2020. N And data lines (e.g., bit lines) 2040 to 204 M Access line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have, for example, p-type conductivity to form a p-well, or n-type conductivity to form an n-well.

[0039] The memory array 200A can be arranged in rows (each corresponding to an access line 202) and columns (each corresponding to a data line 204). Each column may include a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may include memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended to store data, and further include other memory cells not intended to store data, such as dummy memory cells. For the sake of fully understanding the operational advantages, dummy memory cells are generally not accessible to the user of the memory and are typically incorporated into a string of serially connected memory cells instead.

[0040] The memory cells 208 in each NAND string 206 may be connected in series to the select gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., it may be a source-select transistor, collectively referred to as the select-gate source) and select-gate 212 (e.g., a field-effect transistor) (e.g., select-gate 2120 to 212). M Between one of them (for example, it could be a drain-select transistor, collectively referred to as the select gate drain)). Select gate 2100 to 210M They can be commonly connected to select line 214, such as source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as a drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0041] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0042] The drain of each select gate 212 can be connected to the data line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0043] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally flat structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and the plane containing the data line 204, the plane being substantially parallel to the plane containing the common source 216.

[0044] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that determines the data state of the memory cell (e.g., through changes in a threshold voltage), and a control gate 236, such as Figure 2A As shown in the diagram. The data storage structure 234 may include both conductive and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 may additionally have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases formed) the access line 202.

[0045] Columns of memory cells 208 may be NAND strings 206 or multiple NAND strings 206 selectively connected to a given data line 204. Rows of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 may (but do not necessarily) include all memory cells 208 commonly connected to a given access line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 typically include all other memory cells 208 commonly connected to a given access line 202. For example, commonly connected to access line 202 N Furthermore, memory cells 208 selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while being commonly connected to access line 202. N Furthermore, memory cells 208 selectively connected to odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.) can be another physical page of memory cell 208 (e.g., an odd-numbered memory cell). Although in Figure 2A Data lines 2043 to 2045 are not explicitly depicted in the diagram, but it is evident from the illustration that data lines 204 of the memory cell array 200A can extend from data line 2040 to data line 2045. M Memory cells 208 that are commonly connected to a given access line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given access line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (in some embodiments, it may still be an entire row) that is read during a single read operation or programmed during a single programming operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may include those memory cells configured to be erased together, such as those connected to access lines 2020 to 202. NAll memory cells (e.g., all NAND strings 206 sharing common access line 202). Unless explicitly distinguished, a reference to a page of a memory cell herein refers to the memory cell of the logical page of the memory cell.

[0046] Although it was discussed in conjunction with NAND flash memory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0047] Figure 2B For reference only Figure 1 Another schematic diagram of a memory cell array 200B, for example, which is part of a memory cell array 104, in a memory of the type described. Figure 2B Elements with the same number in the text correspond to elements about Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may include semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to data lines 2040 to 2046 via a select transistor 212 (e.g., which may be a drain select transistor, collectively referred to as select gate drain). M And selectively connected to a common source 216 via a selection transistor 210 (e.g., which may be a source selection transistor, collectively referred to as a select gate source). Multiple NAND strings 206 can be selectively connected to the same data line 204. A subset of NAND strings 206 can be connected via select lines 2150 to 215... K Bias selectively activates specific select transistors 212, each located between the NAND string 206 and the data line 204, to connect to their respective data lines 204. Select transistors 210 can be activated by biasing select line 214. Each access line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells commonly connected to each other via specific access lines 202 can be collectively referred to as a hierarchy.

[0048] A three-dimensional NAND memory array 200B may be formed above a peripheral circuit system 226. The peripheral circuit system 226 may represent various circuit systems used for accessing the memory array 200B. The peripheral circuit system 226 may include complementary circuit elements. For example, the peripheral circuit system 226 may include both n-channel transistors and p-channel transistors formed on the same semiconductor substrate, a process collectively referred to as CMOS or complementary metal-oxide-semiconductor. Although CMOS typically no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0049] Figure 2C For reference only Figure 1 Other schematic diagrams of the type of memory described, for example, of a memory cell array 200C that is part of a memory cell array 104. Figure 2C Elements with the same number in the text correspond to elements such as those related to... Figure 2A The provided description. The memory cell array 200C may include, for example: Figure 2A The memory cell array 200A depicts a series-connected string of memory cells (e.g., a NAND string) 206, access lines (e.g., word lines) 202, data lines (e.g., bit lines) 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and source 216. For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C. Figure 2C The diagram depicts the NAND string 206 being grouped into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a grouping of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may include those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The source 216 of memory cell block 2500 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250 L They can typically be selectively connected to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 can be connected to memory cell blocks 2500 to 2500 respectively. L Access lines 202 and select lines 214 and 215 of any other memory cell block are not directly connected.

[0050] Data cable 2040 to 204 MIt can be connected (e.g., selectively connected) to a buffer portion 240 that may be part of a data buffer for memory. Buffer portion 240 may correspond to a memory plane (e.g., memory cell blocks 2500 to 250). L The buffer portion 240 may include sensing circuitry for sensing the data value indicated on the corresponding data line 204. Figure 2C (Not shown in the text).

[0051] Although Figure 2C Each memory cell block 250 is depicted as having only one select line 215, but the memory cell block 250 may include those NAND strings 206 that are typically associated with more than one select line 215. For example, the select lines 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C may further include those with... Figure 2B Selection line 2151 to 215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 typically associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to the buffer section 240 in response to its respective select line 215.

[0052] Figure 3A For reference only Figure 1 A schematic diagram of a memory cell array and a portion of a string driver in a memory device of the type described, depicting a many-to-one relationship between local access lines (e.g., local word lines) 202 and global access lines (e.g., global word lines) 302.

[0053] like Figure 3A As depicted, multiple storage blocks 250 may have local access lines 202 that are typically selectively connected to multiple global access lines 302. Although Figure 3A Depicting only storage blocks 2500 and 250 L (Block 0 and Block L), but additional memory block 250 may have access lines 202 that are typically connected to global access lines 302 in a similar manner. Similarly, although Figure 3A Only four access lines 202 are depicted, but memory block 250 may include fewer or more access lines 202.

[0054] To facilitate memory access operations of a specific memory block 250 that is commonly coupled to a given set of global access lines 302, each memory block 250 may have a corresponding set of block select transistors 354 in a one-to-one relationship with its access lines 202. The control gates of the set of block select transistors 354 for a given memory block 250 may have control gates that are commonly coupled to the corresponding block select lines 356. For example, for memory block 2500, access lines 202 00 Transistor 354 can be selected via block. 00 Selectively connected to global access line 3020, access line 202 10 Transistor 354 can be selected via block. 10 Selectively connected to global access line 3021, access line 202 20 Transistor 354 can be selected via block. 20 Selectively connected to global access line 3022, and access line 202 30 Transistor 354 can be selected via block. 30 Selectively connected to global access line 3023, while block select transistor 354 00 Up to 354 30 In response to a control signal received on block select line 3560, the block select transistor 354 of memory cell block 250 can be collectively referred to as a serial driver, or simply as a driver circuit system.

[0055] Figure 3B For reference only Figure 1 A schematic diagram of a portion of an instance of a string driver in a memory of the described type. Figure 3B A portion of the string driver describes a transistor (e.g., block select transistor 354). YX ), which responds to control signal nodes (e.g., block select line 356) X ), and connected to a voltage node configured to supply voltage level (e.g., global access line 302). Y ) and load nodes configured to receive voltage levels (e.g., local access line 202) YX Between ), for example, block select transistor 354. YX This can represent a block select transistor 354 with a control gate. 10 The control gate is connected to the block select line 3560 and to the global access line 3021 and local access line 202 of the memory cell block 2500. 10 Between. Block select transistor 354 YX It can be a high-voltage n-type FET or an nFET.

[0056] Figure 3C For reference only Figure 1A schematic diagram of a portion of another instance of a string driver in a memory of the described type. Figure 3C A portion of the string driver depicts two transistors, such as block select transistor 354. YX Block select transistor 354 Y(X+1) Block select transistor 354 YX In response to control signal nodes (e.g., block select line 356) X And connected to a voltage node configured to supply voltage level (e.g., global access line 302). Y ) and load nodes configured to receive voltage levels (e.g., local access line 202) YX Between ), for example, block select transistor 354. YX This can represent a block select transistor 354 with a control gate. 10 The control gate is connected to the block select line 3560 and to the global access line 3021 and local access line 202 of the memory cell block 2500. 10 between.

[0057] Block select transistor 354 Y(X+1) In response to control signal nodes (e.g., block select line 356) X+1 And connected to a voltage node configured to supply voltage level (e.g., global access line 302). Y ) and load nodes configured to receive voltage levels (e.g., local access line 202) Y(X+1) Between ), for example, block select transistor 354. Y(X+1) This can represent a block select transistor 354 with a control gate. 1L The control gate is connected to the block select line 356. L And connected to memory cell block 250 L Global access line 3021 and local access line 202 1L Between. Block select transistor 354 YX and 354 Y(X+1) Each can be a high-voltage n-type FET or an nFET.

[0058] Figure 4A This is a planar diagram of a transistor related to the technology. Figure 4A Transistors can be made of, for example Figure 3C The diagram depicted in the image is shown. Figure 4A In this configuration, transistors are formed in the active region 460 of the semiconductor. Each transistor may be formed between, for example, a first contact 478 for connection to a voltage node and a second contact 480 for connection to a load node. Such transistors are responsive to a control signal received on a conductor 464, which may be connected to (and may form) the control gate of one or more transistors.

[0059] Each active region 460 may have a width 461. Distance 463 may represent the width of conductor 464, distance 465 may represent the distance between an edge (e.g., the nearest edge) of conductor 464 and an end (e.g., the nearest end) of active region 460, distance 467 may represent the distance between adjacent edges of conductor 464, and distance 469 may represent the distance between adjacent ends of active region 460. Active region 460 may have a length 471 equal to the sum of distances 463, 465, and 467 between its ends.

[0060] Figure 4B For intercepting along line 4B-4B′ Figure 4A A cross-sectional view of a transistor. Figure 4B The description can correspond to Figure 3C transistor 354 YX and 354 Y(X+1) Two transistors 454, for example 454 X and 454 X+1 Transistor 454 is formed as a superimposed semiconductor 462 (e.g., on it). Semiconductor 462 may contain monocrystalline silicon or other semiconductor materials. Semiconductor 462 may have a conductivity type, for example, p-type conductivity. An isolation region 476 may be formed in semiconductor 462 to define... Figure 4A The active region is 460.

[0061] Figure 4B Each gate stack of transistor 454 may include a dielectric 466 formed as a cover semiconductor 462 (e.g., on it), and a conductor 464 formed as a cover corresponding gate dielectric 466 (e.g., on it). The dielectric 466 may typically be formed of one or more dielectric materials, while the conductor 464 may typically be formed of one or more conductive materials. The dielectric 466 may correspond to the gate dielectric of its corresponding transistor 454, while the conductor 464 may correspond to the control gate of the corresponding transistor 454.

[0062] A first extension region 468 may be formed in semiconductor 462, located between the gate stacks of transistor 454. The first extension region 468 may have a different (e.g., relative) conductivity type than semiconductor 462. Continuing the example, the first extension region 468 may have n-type conductivity. The conductivity level of the first extension region 468 may be referred to as light doping, for example, having n-conductivity. To generate n-type conductivity in a p-type substrate, the dopant material may include ions of arsenic (As), antimony (Sb), phosphorus (P), or another n-type impurity. Alternatively, to generate p-type conductivity in an n-type substrate, the dopant material may include ions of boron (B) or another p-type impurity.

[0063] A first source / drain region (e.g., a source) 470 may be formed in the first extension region 468. The first source / drain region 470 may have the same conductivity type as the first extension region 468 but at a higher conductivity level. For example, the first source / drain region 470 may have n+ conductivity. The difference in conductivity level may correspond to different amounts of impurities, such as dopant material, implanted in the semiconductor 462. The impurity content of the first source / drain region 470 may be an order of magnitude or greater than the impurity content of the first extension region 468. As an example, n- conductivity may represent an impurity content of 1E16 to 1E19 ions per cubic centimeter, while n+ conductivity may represent an impurity content of greater than or equal to 1E20 ions per cubic centimeter.

[0064] The first contact 478 may be formed to connect to the first source / drain region 470. The first contact 478 may typically be formed of one or more conductive materials. The first contact 478 may be configured to receive a voltage level to be provided to the first source / drain region 470. For example, the first contact 478 may be configured to connect to... Figure 3A Global access line 302.

[0065] A second extension region 472 may be formed in semiconductor 462, adjacent to each gate stack of transistor 454. The second extension region 472 may have a different (e.g., opposite) conductivity type than semiconductor 462. Continuing the example, the second extension region 472 may have n-type conductivity. The conductivity level of the second extension region 472 may be referred to as light doping, for example, having n-conductivity.

[0066] A second source / drain region (e.g., a drain) 474 may be formed in each second extension region 472. The second source / drain region 474 may have the same conductivity type as the second extension region 472 but at a higher conductivity level. For example, the second source / drain region 474 may have n+ conductivity. The difference in conductivity level may correspond to different amounts of impurities, such as dopant material, implanted in the semiconductor 462. The impurity content of the second source / drain region 474 may be an order of magnitude or greater than the impurity content of the second extension region 472.

[0067] The second contact 480 may be formed to connect to each of the second source / drain regions 474. The second contact 480 may typically be formed of one or more conductive materials. Each second contact 480 may be configured to provide a voltage level at its second source / drain region 474 to a load. For example, the second contact 480 may be configured to connect to... Figure 3A Local access line 202.

[0068] Figure 5A This is a plan view of a transistor according to an embodiment. Figure 5A Transistors can be made of, for example Figure 3C The diagram depicted in the image is shown. Figure 5A In this process, transistors can be formed in the active region 560 of the semiconductor. Each transistor can be formed between, for example, a first contact 578 for connection to a voltage node and a second contact 580 for connection to a load node. Such transistors are responsive to a control signal received on a conductor 564, which can be connected to (and may form) the control gates of one or more transistors.

[0069] Each active region 560 may have a width 561. A distance 563 may represent the width of a conductor 564, a distance 565 may represent the distance between an edge (e.g., the nearest edge) of a conductor 564 and an end (e.g., the nearest end) of an active region 560, a distance 567 may represent the distance between adjacent edges of a conductor 564, and a distance 569 may represent the distance between adjacent ends of an active region 560. An active region 560 may have a length 571 equal to the sum of each of the distances 563, 565, and 567 between its ends. For some embodiments, Figure 5A The distances 563 and 569 can be roughly equal to... Figure 4A The distances are 463 and 469.

[0070] Figure 5B For the section taken along line 5B-5B′ Figure 5A A cross-sectional view of a transistor. Figure 5B The description can correspond to Figure 3C transistor 354 YX and 354 Y(X+1) Two transistors 554, for example 554 X and 554 X+1 Transistor 554 may be formed as a superimposed semiconductor 562 (e.g., on which a substrate 586 is superimposed). Semiconductor 562 may contain monocrystalline silicon or other semiconductor materials. Semiconductor 562 may have a conductivity type, for example, p-type conductivity. An isolation region 576 may be formed in semiconductor 562 to define... Figure 5A The active region 560. The substrate 586 may further contain a semiconductor material. In some embodiments where the substrate 586 contains a semiconductor material, the semiconductor 562 and the substrate 586 may each be formed from a single column of semiconductor material. In such embodiments, the substrate 586 may have the same or different (e.g., opposite) conductivity type as the semiconductor 562. For example, in embodiments where the substrate 586 has a different conductivity type, the substrate 586 may represent a deep n-well, and the semiconductor 562 may represent a p-well contained within the n-well. In some embodiments, an isolation region 576 may extend into the substrate 586. In other embodiments, the substrate 586 may contain a dielectric material.

[0071] Figure 5B Each transistor 554's gate stack may include a dielectric 566 formed as a cover semiconductor 562 (e.g., on it), and a conductor 564 formed as a cover corresponding dielectric 566 (e.g., on it). The dielectric 566 may typically be formed of one or more dielectric materials, while the conductor 564 may typically be formed of one or more conductive materials. The dielectric 566 may correspond to the gate dielectric of its corresponding transistor 554, while the conductor 564 may correspond to the control gate of the corresponding transistor 554.

[0072] A first extension region substrate 568 may be formed in semiconductor 562, located between the gate stacks of transistor 554. The first extension region substrate 568 may have a different (e.g., relative) conductivity type than semiconductor 562. Continuing the example, the first extension region substrate 568 may have n-type conductivity. The conductivity level of the first extension region substrate 568 may be referred to as light doping, for example, having n-conductivity. To generate n-type conductivity in a p-type semiconductor, the dopant material may include ions of arsenic (As), antimony (Sb), phosphorus (P), or another n-type impurity. Alternatively, to generate p-type conductivity in an n-type semiconductor, the dopant material may include ions of boron (B) or another p-type impurity.

[0073] A first extension region vertical plate 582 may be formed over the first extension region substrate 568. The first extension region vertical plate 582 may have the same conductivity type and a similar (e.g., the same) conductivity level as the first extension region substrate 568. The first extension region vertical plate 582 may have a similar (e.g., the same) construction material as the first extension region substrate 568. For example, if the semiconductor 562 is monocrystalline silicon, then the first extension region vertical plate 582 may be conductive-doped monocrystalline silicon. Alternatively, the first extension region vertical plate 582 may be made of a different semiconductor material than the semiconductor 562.

[0074] A first source / drain region (e.g., a source) 570 may be formed in the first extension region vertical plate 582. The first source / drain region 570 may have the same conductivity type as the first extension region vertical plate 582 but at a higher conductivity level. For example, the first source / drain region 570 may have n+ conductivity. Differences in conductivity levels may correspond to different amounts of impurities, such as dopant, implanted in the semiconductor material of the first extension region vertical plate 582. The impurity content of the first source / drain region 570 may be an order of magnitude or greater than the impurity content of the first extension region vertical plate 582. As an example, n- conductivity may represent an impurity content of 1E16 to 1E19 ions per cubic centimeter, while n+ conductivity may represent an impurity content greater than or equal to 1E20 ions per cubic centimeter.

[0075] The first contact 578 may be formed to connect to the first source / drain region 570. The first contact 578 may typically be formed of one or more conductive materials. The first contact 578 may be configured to receive a voltage level to be provided to the first source / drain region 570. For example, the first contact 578 may be configured to connect to... Figure 3A Global access line 302.

[0076] A second extension region substrate 572 may be formed in semiconductor 562, adjacent to each gate stack of transistor 554. The second extension region substrate 572 may have a different (e.g., relative) conductivity type than semiconductor 562. Continuing the example, the second extension region substrate 572 may have n-type conductivity. The conductivity level of the second extension region substrate 572 may be referred to as light doping, for example, having n-conductivity.

[0077] A second extension region vertical plate 584 may be formed over the second extension region substrate 572. The second extension region vertical plate 584 may have the same conductivity type and a similar (e.g., the same) conductivity level as the second extension region substrate 572. The second extension region vertical plate 584 may have a similar (e.g., the same) construction material as the second extension region substrate 572. For example, if the semiconductor 562 is monocrystalline silicon, then the second extension region vertical plate 584 may be conductive-doped monocrystalline silicon. Alternatively, the second extension region vertical plate 584 may be made of a different semiconductor material than the semiconductor 562.

[0078] A second source / drain region (e.g., drain) 574 may be formed in each of the second extension region vertical plates 584. The second source / drain region 574 may have the same conductivity type as the second extension region vertical plate 584, but at a higher conductivity level. For example, the second source / drain region 574 may have n+ conductivity. Differences in conductivity levels may correspond to different amounts of impurities, such as dopant, implanted into the semiconductor 562. The impurity content of the second source / drain region 574 may be an order of magnitude or greater than the impurity content of the second extension region vertical plate 584.

[0079] The second contact 580 may be formed to connect to each of the second source / drain regions 574. The second contact 580 may typically be formed of one or more conductive materials. Each second contact 580 may be configured to provide a voltage level at its second source / drain region 574 to a load. For example, the second contact 580 may be configured to connect to... Figure 3A Local access line 202.

[0080] Compared to Figure 4BThe structure, using the first extension region vertical plate 582 and / or the second extension region vertical plate 584, can reduce the lateral spacing (e.g., in the direction of the transistor's length) between the first contact 578 and the isolation region 576. For example, using... Figure 5B The first extension area vertical plate 582 can reduce the lateral spacing between the first contact 578 and the conductor 564 of the transistor 554. Compared to Figure 4B The extension region between the first source / drain region 470 and the channel of transistor 554, using the first extension region stand 582, can further provide the same or increased length of the extension region between the first source / drain region 570 and the channel of transistor 554. Similarly, using Figure 5B The second extension region vertical plate 584 can reduce the lateral spacing between the second contact 580 and the conductor 564 of the transistor 554. Compared to Figure 4B The extension region between the second source / drain region 474 and the channel of transistor 454, using a second extension region stand 584, can further provide the same or increased length of the extension region between the second source / drain region 574 and the channel of transistor 554. Furthermore, using... Figure 5B The second extension plate 584 can reduce the lateral spacing between the second contact 580 and the adjacent isolation region 576, because it may not be necessary to laterally separate the second source / drain region 574 from the adjacent isolation region 576 in the manner depicted between the second source / drain region 474 and the adjacent isolation region 476.

[0081] Various embodiments may further incorporate fins into the channel of transistor 554. These embodiments enable... Figure 5A The width of the active region 560 is 561 relative to Figure 4A The width 461 of the active region 460 (e.g., in the direction of the transistor width) is reduced. Figure 6A This is a plan view of transistor 554A according to an embodiment. Figure 6B For along Figure 6A A cross-sectional view of transistor 554A taken from line 6B-6B′. Figure 6C For along Figure 6A A cross-sectional view of transistor 554A taken from line 6C-6C′. Figure 6D For along Figure 6A The cross-sectional view of transistor 554A taken from line 6D-6D′, and Figure 6E For along Figure 6A A cross-sectional view of transistor 554A taken from line 6E-6E′. Figures 6A to 6E The same numbered elements correspond to, as about Figures 5A to 5B The description provided.

[0082] Figure 6AA first contact 578 and a second contact 580 are depicted covering an active region 560 including a semiconductor 562. A conductor 564 may cover the semiconductor 562 and a dielectric plug 588. The dielectric plug 588 may be formed between portions of the semiconductor 562 to define fins between the dielectric plugs 588. For clarity, Figure 6A The dielectric material formed outside the boundary of the active region 560 is not depicted.

[0083] Figure 6B The image depicts a portion of the semiconductor 562 between the fins defining the dielectric plug 588. In some embodiments, the fins of the semiconductor 562 may have an aspect ratio (e.g., height to width) in the range of 2 to 4. In some embodiments, the fins of the semiconductor 562 may have a height of 500 nm ± 300 nm. The dielectric plug 588 may have a height less than the height of the fins of the semiconductor 562. In some embodiments, the dielectric plug 588 may have a height of 100 nm ± 30 nm. The dielectric plug 588 may have a height sufficient to reduce the formation of parasitic transistors between the conductor and the substrate 586. In some embodiments, the height of the fins of the semiconductor 562 may be in the range of 5 to 15 times the height of the dielectric plug 588.

[0084] Dielectric material (e.g., gate dielectric) 566 may be formed as a portion (e.g., on) the fins of semiconductor 562, such as a portion of the upper surface and sidewalls of the fins of semiconductor 562. For example, dielectric material 566 may be formed on a portion of the fins of semiconductor 562 extending beyond the dielectric plug 588 (e.g., above) of it. Conductor (e.g., control gate) 564 may be formed extending between and covering the fins of semiconductor 562. Conductor 564 may extend to the surface (e.g., upper surface) of dielectric plug 588. When dielectric material 566 is formed as a portion covering the upper surface and sidewalls of the fins of semiconductor 562, the effective operable width of transistor 554A can be increased by reducing the physical width of transistor 554A, such as reducing the width 561 of active region 560. Although Figure 6B The example depicts four fins of the semiconductor 562, but more or fewer fins can be used.

[0085] Figure 6C A dielectric 566 is depicted in a portion of a first extended region substrate 568 of an optionally overlaid semiconductor 562. An example of a dielectric plug 588 may be formed as a sidewall of the semiconductor 562 adjacent to the overlaid substrate 586. Figure 6C The fins depicting semiconductor 562 may not extend the full width of the active region, for example... Figure 6C The portion of semiconductor 562 depicted in the diagram is bridging. Figure 6B The gap between the fins of semiconductor 562 depicted in the figure.

[0086] Figure 6D A dielectric 566 is depicted optionally covering the upper surface and sidewalls of the first extension region substrate 568 and the second extension region substrate 572, as well as the sidewalls of portions of the semiconductor 562. An example of a dielectric plug 588 may be formed between portions of the semiconductor 562 and covering the substrate 586. A conductor 564 may be formed covering the dielectric plug 588. A first extension region vertical plate 582 may be formed covering the first extension region substrate 568, and a first source / drain region 570 may be formed in the first extension region vertical plate 582. A second extension region vertical plate 584 may be formed covering the second extension region substrate 572, and a second source / drain region 574 may be formed in the second extension region vertical plate 584. Figure 6D In the embodiments depicted, the semiconductor fins do not extend the full length of the active region. However, other embodiments may pattern the semiconductor 562 to define fins that extend the full length of the active region.

[0087] Figure 6E A dielectric 566 is depicted covering the upper surfaces of the semiconductor 562 and optionally the first extension region substrate 568 and the second extension region substrate 572. A conductor 564 may be formed covering the gate dielectric 566. A first extension region vertical plate 582 may be formed covering the first extension region substrate 568, and a first source / drain region 570 may be formed in the first extension region vertical plate 582. A second extension region vertical plate 584 may be formed covering the second extension region substrate 572, and a second source / drain region 574 may be formed in the second extension region vertical plate 584. A first contact 578 may be formed to connect to the first source / drain region 570. A second contact 580 may be formed to connect to the second source / drain region 574. Figure 6E Further depiction shows that the distance (e.g., lateral distance) 696 between the first extension region vertical plate 582 and the conductor 564 can differ from the distance (e.g., lateral distance) 698 between the second extension region vertical plate 584 and the conductor 564. For example, if it is desired that the extension regions between the source and drain sides of transistor 554A have different lengths, for example, due to a desired voltage drop across transistor 554A, then having different distances 696 and 698 can help obtain extension regions of different lengths while maintaining the same height of the extension region vertical plates 582 and 584. For example, distance 696 can be greater than distance 698. This difference between distances 696 and 698 can also be used in transistor configurations according to other embodiments, such as... Figure 5B As depicted in the text.

[0088] Figures 7A to 7M For various manufacturing states according to the embodiments Figure 5B A cross-sectional view of a transistor. Figures 7A to 7M The same numbered elements correspond to, as about Figures 5A to 5B The description provided.

[0089] exist Figure 7A In this embodiment, semiconductor 562 may be formed as an overlying substrate 586, for example, on which it is disposed. Semiconductor 562 may comprise silicon, such as monocrystalline silicon or other semiconductor materials. Semiconductor 562 may have a conductivity type, for example, p-type conductivity. Substrate 586 may further contain semiconductor material. In other embodiments, substrate 586 may contain dielectric material. In some embodiments where substrate 586 contains semiconductor material, semiconductor 562 and substrate 586 may represent two portions of a single example of semiconductor material. In some embodiments, isolation region 576 may extend into substrate 586.

[0090] exist Figure 7B and 7C In this process, semiconductor 562 can be patterned to define the width 561 of the active region and to define the fins of semiconductor 562. Figure 7B Patternable after the patterned semiconductor 562 Figure 7A The view, and Figure 7C It can depict the section intercepted along line 7C-7C′ Figure 7B A cross-sectional view. Patterning may include removing portions of semiconductor 562 using photolithography or other methods for selective material removal. The fins of semiconductor 562 may extend orthogonally to the width 561 of the active region. For some embodiments, Figure 7C The cross-section can be extended to less than Figure 7B The length of the active region is 571. For example, the formation of the fins of semiconductor 562 can form closed trenches, such as container-shaped recesses, between the fins of semiconductor 562. For other embodiments, Figure 7C The cross-section can be extended Figure 7B The active region has a total length of 571. For example, the formation of the fins of semiconductor 562 may form open trenches between the fins of semiconductor 562, for example, where no portion of semiconductor 562 bridges the gap between two fins of semiconductor 562.

[0091] exist Figure 7D and 7E In this process, the dielectric material plug 588 may be formed as an exposed portion (e.g., on) the overlying substrate 586. Figure 7D Corresponding to Figure 7B The structure described in the text, and Figure 7E Corresponding to Figure 7C The structure is described herein. The dielectric plug 588 may contain one or more dielectric materials. For example, the dielectric plug 588 may contain oxides (e.g., silicon dioxide), be composed of oxides or substantially composed of oxides, and / or may contain, be composed of or substantially composed of: high-k dielectric materials, such as aluminum oxide (Al₂O₃). x ), Hafnium oxide (HfO) x), Hafnium aluminum oxide (HfAlO) x ), hafnium silicon oxide (HfSiO) x ), Lanthanum oxide (LaO) x ), tantalum oxide (TaO) x Zirconium oxide (ZrO) x ), Zirconia aluminum (ZrAlO) x The dielectric plug 588 can be formed by blanket deposition of dielectric material, followed by etching back to achieve the desired height of the dielectric plug 588.

[0092] exist Figure 7F In this configuration, a portion of isolation region 576 may be formed adjacent to semiconductor 562. Isolation region 576 may represent a shallow trench isolation structure as well known in the related art. For example, isolation region 576 may be formed by filling a trench (not shown) adjacent to the active region with one or more dielectric materials.

[0093] exist Figure 7G In the middle, dielectric 566 can be formed as the overlay. Figure 7F The structure (e.g., on which), for example, a semiconductor 562 and an isolation region 576 are overlaid. Dielectric 566 may be formed of one or more dielectric materials. For example, dielectric 566 may comprise oxides (e.g., silicon dioxide), consist of oxides or are substantially composed of oxides, and / or may comprise, consist of, or be substantially composed of high-k dielectric materials, such as aluminum oxide (Al₂O₃). x ), Hafnium oxide (HfO) x ), Hafnium aluminum oxide (HfAlO) x ), hafnium silicon oxide (HfSiO) x ), Lanthanum oxide (LaO) x ), tantalum oxide (TaO) x Zirconium oxide (ZrO) x ), Zirconia aluminum (ZrAlO) x Dielectric 566 may contain the same or different dielectric material as the dielectric plug 588.

[0094] Conductor 564 may be formed as an overlying dielectric 566 (e.g., thereon). Conductor 564 may be formed of one or more conductive materials. Conductor 564 may comprise, consist of, or be substantially composed of conductive doped polysilicon, and / or may comprise, consist of, or be substantially composed of: a metal, such as a refractory metal; or a metal-containing material, such as a refractory metal silicide or a metal nitride, such as a refractory metal nitride; and any other conductive material.

[0095] A patterned mask 790 can be formed to overlay (e.g., on) a conductor 564 to expose areas of the conductor 564 and dielectric 566 for removal. Mask 790 may represent a mask formed using a photolithography process. Photolithography is commonly used in integrated circuit manufacturing to define desired patterns. In a photolithography process, a photoresist layer can be formed on the surface of a processing device. The photoresist layer may contain a photosensitive polymer that becomes easily removable upon exposure to light or other electromagnetic radiation. To define the pattern, the photoresist layer may be selectively exposed to radiation and subsequently developed to expose portions of the underlying layer. In a positive resist system, the photoresist layer exposed to radiation is photodissolved, and the photomask is designed to prevent those portions of the photoresist layer to be retained after development from being exposed to radiation. In a negative resist system, the photopolymerizes the photoresist layer exposed to radiation, and the photomask is designed to prevent those portions of the photoresist layer to be removed by development from being exposed to radiation.

[0096] exist Figure 7H In this process, exposed areas of conductor 564 and dielectric 566 can be removed anisotropically, for example. For instance, a reactive ion etching process can be used to remove portions of conductor 564 and dielectric 566 not covered by the patterned mask 790. The mask 790 can then be removed, for example, by ashing or otherwise removing the photoresist material. The remaining portion of conductor 564 may represent the control gate of a future transistor.

[0097] exist Figure 7IIn this process, a first extension region substrate 568 and a second extension region substrate 572 may be formed. The first extension region substrate 568 may extend beyond one edge of each conductor 564, while each second extension region substrate 572 may extend beyond the opposite edge of its corresponding conductor 564. The second extension region substrate 572 may further extend into a corresponding isolation region 576. Forming these extension region substrates 568 and 572 may include portions of the conductive doped semiconductor 562 not covered by the conductors 564. For example, the first extension region substrate 568 and the second extension region substrate 572 may be formed by implanting a corresponding dopant material into the semiconductor 562. As is well known in the art, such implantation may typically involve accelerating ions directed toward the surface of the semiconductor 562. To produce n-type conductivity, the dopant material may include ions of arsenic (As), antimony (Sb), phosphorus (P), or another n-type impurity. To produce p-type conductivity, the dopant material may include ions of boron (B) or another p-type impurity. Other methods for forming conductive regions in a semiconductor are known. While the implanted dopant material can self-align with the gate stack, it is further desirable for the extension regions 568 and 572 to extend beneath the conductor 564. The channel region will be the area beneath the dielectric 566 between the first extension region substrate 568 and the corresponding second extension region substrate 572. In some embodiments, the fins of the semiconductor 562 may extend the full length of the channel region. In other embodiments, the fins of the semiconductor 562 may extend beyond the full length of the channel region.

[0098] exist Figure 7J In the middle, dielectric 792 can be formed as the overlay. Figure 7I The structure of dielectric 792. Dielectric 792 may contain one or more dielectric materials. Figure 7K In this process, a void 794 may be formed in the dielectric 792 to define the region for forming the extension region vertical plate. For example, a portion of the dielectric 792 may be anisotropically removed to define the void 794. Figure 7L In this process, for example, a first extension region vertical plate 582 and a second extension region vertical plate 584 may be formed simultaneously. The top surfaces of the first extension region vertical plate 582 and the second extension region vertical plate 584 may be located above the top surface of the conductor 564. The first extension region vertical plate 582 and the second extension region vertical plate 584 may be formed of a material having similar properties to their corresponding first extension region substrate 568 and second extension region substrate 572. As an example, in the case where the semiconductor 562 contains monocrystalline silicon, amorphous or polycrystalline silicon (collectively referred to as polycrystalline silicon) may be formed in the void 794 using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and subsequently crystallized to simulate the properties of the underlying extension region substrate. This can be achieved by solid-state epitaxy. For example, solid-state epitaxy may include low-temperature annealing (e.g., 700°C for 30 minutes).

[0099] Alternatively, selective epitaxial growth of single-crystal silicon can be used to form vertical plates. Silicon epitaxial formation is a CVD process. This process replicates the structure of the silicon material formed thereon. For example, if the substrate structure is single-crystal silicon, then epitaxial growth can maintain the same single-crystal structure. A silicon precursor is transferred to and adsorbed onto the exposed silicon structure. Common silicon precursors used to produce epitaxial silicon include silicon tetrachloride (SiCl4), trichlorosilane (SiHCl3), dichlorosilane (SiH2Cl2), and silane (SiH4). As another alternative, epitaxial growth of high-bandgap semiconductors can also be used. A high-bandgap semiconductor can be defined as a semiconductor with a bandgap of 1.7 eV or higher. Some high-bandgap semiconductors, such as gallium phosphide (GaP), can be epitaxially grown on silicon to form a single lattice containing the high-bandgap semiconductor.

[0100] Regardless of the formation method, conductive doping of the first extension region vertical plate 582 and the second extension region vertical plate 584 can be performed together or after formation. The conductive doping of the extension region vertical plates 582 and 584 can use dopant of the same type (e.g., n-type or p-type) but at a higher level as the extension region substrates 568 and 572. For both the extension region vertical plates and the extension region substrate, the dopant can further be of the same material.

[0101] exist Figure 7M In the first source / drain region 570 and the second source / drain region 574, respectively, the first extension region vertical plate 582 and the second extension region vertical plate 584 may be formed. The bottom surfaces of the first source / drain region 570 and the second source / drain region 574 may be above the top surface of the conductor 564. The formation of the source / drain regions 570 and 574 may include using dopant of the same type (e.g., n-type or p-type) but at a higher level to conductively dope the extension region vertical plates 582 and 584. For both the extension region vertical plates 582 and 584 and the source / drain regions 570 and 574, the dopant may further be of the same material. Contacts 578 and 580 ( Figure 7M (Not shown in the image) can then be formed to contact the source / drain regions 570 and 574, respectively. Although Figures 7A to 7M The description corresponds to the formation of, for example Figure 3C The diagram depicted in Figure 5B The method for the 554 transistor, but refer to Figures 7A to 7M The description will readily reveal the formation corresponding to Figure 3B The schematic diagram shows the transistor 554.

[0102] Although Figures 7A to 7MNot depicted, but the first set of fins of semiconductor 562 may be formed as one extending from the first extension region substrate 568 to the second extension region substrate 572, and the second set of fins of semiconductor 562 may be formed as the other extending from the first extension region substrate 568 to the second extension region substrate 572. Each set of fins of semiconductor 562 may not extend through the first extension region substrate 568 to contact each other, for example, with... Figure 6D Similar examples exist. The formation of such fins in semiconductor 562 can create closed trenches within the semiconductor 562. Alternatively, Figures 7A to 7M Examples may include a single set of fins for semiconductor 562 for the two transistors depicted. The formation of such fins in semiconductor 562 may involve forming open trenches within semiconductor 562.

[0103] Figures 8A to 8B This is a cross-sectional view of transistor 554 according to other embodiments. Figures 8A to 8B The same numbered elements correspond to, as about Figures 5A to 5B The description provided.

[0104] Similar to Figure 5B and 7M Implementation examples, Figure 8A The embodiments may schematically correspond to Figure 3C The circuit. However, instead of having a shared first extension region base 568, a shared first extension region vertical plate 582, and a shared first contact 578, Figure 8A Embodiments may utilize a shared first extension region substrate 568, but utilize two first extension region vertical plates 582, two first source / drain regions 570, and two first contacts 578, for example, one group per transistor 554. The first contacts 578 can be used to connect to transistor 554. X and 554 X+1 The conductors 899 of each first contact 578 are electrically connected to each other (e.g., short-circuited). The conductors 899 may be formed of one or more conductive materials and may be connected to voltage nodes, such as global access lines 302.

[0105] Similar to Figure 5B and 7M Implementation examples, Figure 8B The embodiments may schematically correspond to Figure 3C The circuit. However, instead of having a shared first extension region base 568, a shared first extension region vertical plate 582, and a shared first contact 578, Figure 8B Embodiments may utilize a shared first extension region substrate 568, two first extension region vertical plates 582, two first source / drain regions 570, and two first contacts 578, for example, one set per transistor 554. The first contacts 578 may be used to connect to transistor 554. X and 554X+1 The conductors 899 of each first contact 578 are electrically connected to each other (e.g., short-circuited). The conductors 899 may be formed of one or more conductive materials and may be connected to voltage nodes, such as global access lines 302. The two first extension region substrates 568 may be separated by isolation regions 576, for example, they may be electrically isolated from each other, but they are connected through their corresponding first extension region uprights 582, their corresponding first source / drain regions 570, their corresponding first contacts 578, and the conductors 899.

[0106] Figure 9A An example of a closed trench 901 formed in a semiconductor 562 to define a fin 905 is depicted. The closed trench 901 may extend to a surface (e.g., the upper surface) of a substrate 586. A portion 907 of the semiconductor 562 may bridge the gap defined by the closed trench 901 between two fins 905 in the semiconductor 562. Although not illustrated in the figures, the semiconductor 562 may include portions at both ends of each closed trench 901 bridging the gap between each pair of fins 905 in the semiconductor 562. Figure 9A The structure depicted defines an active region 560 for forming two transistors, for example. Figure 5B transistor 554 X and 554 X+1 Alternatively, Figure 9A The structure depicted defines a continuous portion of the active region 560 extending by a distance 565 plus a distance 563 plus half a distance 567, for use in forming a transistor, for example. Figure 5B transistor 554 X Or 554 X+1 In this type of embodiment, the active region 560 may include... Figure 9A The structures depicted and their mirror images, wherein the fins 901 of each structure extend in the direction of length 571 of the active region 560.

[0107] Figure 9B An example of an open trench 903 formed in semiconductor 562 to define fin 905 is depicted. The open trench 903 may extend to the surface of substrate 586 (e.g., the upper surface). Figure 9B The structure depicted defines an active region 560 for forming two transistors, for example. Figure 5B transistor 554 X and 554 X+1 .

[0108] Figure 10This is a flowchart of a method for forming a transistor according to an embodiment. At 1011, a semiconductor may be formed and patterned to define fins. For example, a semiconductor 562 may be formed and patterned to define fins 901 or 903. The semiconductor may have a first conductivity type. At 1013, a first dielectric plug may be formed between the fins of the semiconductor. For example, a dielectric plug 588 may be formed.

[0109] At 1011, a second dielectric material covering the semiconductor can be formed. For example, dielectric 566 can be formed. At 1017, a conductor covering the second dielectric material can be formed. For example, conductor 564 can be formed. At 1019, the conductor can be patterned to define the gate stack of the transistor. In some embodiments, the second dielectric material can be patterned simultaneously with the conductor.

[0110] At location 1021, a first extension region substrate and a second extension region substrate may be formed in the semiconductor. For example, a first extension region substrate 568 and a second extension region substrate 572 may be formed. The first extension region substrate and the second extension region substrate may have a second conductivity type different from the first conductivity type. The first extension region substrate and the second extension region substrate may further have a first conductivity level.

[0111] At position 1023, a first extension region vertical plate and a second extension region vertical plate may be formed. For example, a first extension region vertical plate 582 and a second extension region vertical plate 584 may be formed. The first extension region vertical plate may be formed to cover a first extension region substrate, and the second extension region vertical plate may be formed to cover a second extension region substrate. The first extension region vertical plate and the second extension region vertical plate may have a second conductivity type. The first extension region vertical plate and the second extension region vertical plate may further have a first conductivity level.

[0112] At position 1025, a first source / drain region and a second source / drain region may be formed. For example, a first source / drain region 570 and a second source / drain region 574 may be formed. The first source / drain region may be formed in a first extension region vertical plate, and the second source / drain region may be formed in a second extension region vertical plate. The first source / drain region and the second source / drain region may have a second conductivity type. The first source / drain region and the second source / drain region may further have a conductivity level greater than the first conductivity level.

[0113] Figure 11 The diagram conceptually depicts a portion of a string driver circuitry system connected to access lines of multiple memory cell blocks according to an embodiment. For example, a first string driver 11300 may have corresponding conductors 5640 and respectively connected to first contacts 578 (e.g., first contact 578). X 578 X+1 and 578 X+2) and corresponding second contact 580 (e.g., second contact 580) X0 580 (X+1)0 and 580 (X+2)0 The transistors between (not in) Figure 11 (as listed above), and the second string driver 11301 may have corresponding conductors 5641 and respectively connected to the first contact 578 (e.g., the first contact 578). X 578 X+1 and 578 X+2 ) and corresponding second contact 580 (e.g., second contact 580) X1 580 (X+1)1 and 580 (X+2)1 The transistors between (not in) Figure 11 (Listed in the text). The transistors of the string drivers 11300 and 11301 may correspond, for example, to... Figure 5A and 5B The transistor 554 is depicted in the document.

[0114] The second contact 580 of the first string driver 11300 X0 580 (X+1)0 and 580 (X+2)0 Access lines 202 that can be connected to memory cell block 2500 respectively X0 202 (X+1)0 and 202 (X+2)0 Access Line 202 X0 202 (X+1)0 and 202 (X+2)0 This may represent only a portion of the access lines of memory cell block 2500. For example, memory cell block 2500 may include, for example... Figure 2A The N+1 access lines 202 depicted herein, and the access lines 202 of the memory cell block 2500 X0 202 (X+1)0 and 202 (X+2)0 They can correspond to respectively Figure 2A Access line 202 X 202 X+1 and 202 X+2 .

[0115] The second contact 580 of the second string driver 11301 X1 580 (X+1)1 and 580 (X+2)1 Access lines 202 that can be connected to memory cell block 2501 respectively X1 202 (X+1)1 and 202 (X+2)1 Access Line 202 X1 202 (X+1)1 and 202(X+2)1 This may represent only a portion of the access lines of memory cell block 2501. For example, memory cell block 2501 may include, for example... Figure 2A The N+1 access lines 202 depicted herein, and the access lines 202 of memory cell block 2501 X1 202 (X+1)1 and 202 (X+2)1 They can correspond to respectively Figure 2A Access line 202 X 202 X+1 and 202 X+2 .

[0116] Serial drivers 11300 and 11301 can be Figure 2C It is part of the peripheral circuitry 226. For example, the serial driver 11300 may be configured as an access line 202 in the memory cell block 2500. X0 202 (X+1)0 and 202 (X+2)0 Below (e.g., at least partially below). Similarly, the string driver 11301 may be configured as an access line 202 of the memory cell block 2501. X1 202 (X+1)1 and 202 (X+2)1 Below (for example, at least partially below).

[0117] Memory cell blocks 2500 and 2501 may include more than one sub-block of memory cells. For example, memory cell blocks 2500 and 2501 may have corresponding... Figure 2B The architecture of the memory cell array 200B, wherein the memory cell array 200B will have K+1 sub-blocks, wherein each sub-block includes elements responsive to select lines 2150 to 215... K The memory cells are selectively connected to the corresponding data lines 204 via a select line 215. The spacing between these sub-blocks of memory cells can extend in the direction of the data lines 204. Spacing refers to the distance between repeating elements in a structure with translational symmetry. For example, the spacing between sub-blocks can represent the distance between an edge of the NAND string of memory cell 206 in the memory cell sub-block corresponding to select line 2150 and the corresponding edge of the adjacent NAND string of memory cell 206 in the memory cell sub-block corresponding to select line 2151.

[0118] Similarly, string drivers 11300 and 11301 may have spacing in the same linear direction as the memory cell sub-blocks. (Reference) Figure 5AThe spacing between string drivers 11300 and 11301 may correspond to half a distance 567 plus distance 563 plus distance 565 plus half a distance 569. In some embodiments, the spacing between string drivers 11300 and 11301 may be less than three times the spacing between the memory cell sub-blocks of memory cell blocks 2500 and 2501, respectively. In other embodiments, the spacing between string drivers 11300 and 11301 may be less than 2.5 times the spacing between the memory cell sub-blocks of memory cell blocks 2500 and 2501, respectively.

[0119] in conclusion

[0120] While specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement contemplated to achieve the same purpose may replace the specific embodiments shown. Many modifications to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. An integrated circuit device comprising: Voltage node; Load nodes; and A transistor connected between the voltage node and the load node, the transistor comprising: A semiconductor having a substrate on which it is covered, wherein the semiconductor comprises a plurality of fins covering the substrate, and wherein the semiconductor has a first conductivity type; A plurality of plugs of a first dielectric, wherein each of the plurality of plugs of the first dielectric is formed between a pair of fins in the plurality of fins of the semiconductor; A second dielectric material, on which the semiconductor is coated; A conductor, on which the second dielectric is coated; A first extension region substrate is formed in the semiconductor and extends beyond a first edge of the conductor, wherein the first extension region substrate has a second conductivity type different from the first conductivity type; A second extension region substrate is formed in the semiconductor and extends beyond a second edge of the conductor opposite to the first edge of the conductor, wherein the second extension region substrate has the second conductivity type; The first extension region vertical plate is formed to cover the first extension region substrate and has the second conductivity type; The second extension region vertical plate is formed to cover the second extension region substrate and has the second conductivity type; A first source / drain region is formed in the first extension region vertical plate and connected to the voltage node, wherein the first source / drain region has a second conductivity type and a conductivity level greater than that of the first extension region vertical plate. as well as A second source / drain region is formed in the second extension region vertical plate and connected to the load node, wherein the second source / drain region has the second conductivity type and has a conductivity level greater than that of the second extension region vertical plate.

2. The integrated circuit device of claim 1, wherein each of the plurality of fins has an aspect ratio in the range of 2 to 4.

3. The integrated circuit device of claim 1, wherein the height of the fins among the plurality of fins is in the range of 5 to 15 times the height of the plugs among the plurality of plugs of the first dielectric.

4. The integrated circuit device of claim 1, wherein the second dielectric comprises a plurality of examples of the second dielectric, and wherein each example of the second dielectric is formed on the upper surface and sidewall of a corresponding fin in the plurality of fins of the semiconductor material.

5. The integrated circuit device of claim 1, wherein a portion of the semiconductor bridges the gap between the pair of fins of the plurality of fins of the semiconductor at one end of a pair of fins.

6. The integrated circuit device of claim 5, wherein the portion of the semiconductor is a first portion of the semiconductor, and wherein the second portion of the semiconductor bridges the gap between the pair of fins of the plurality of fins of the semiconductor at different ends opposite to one end of the pair of fins of the plurality of fins of the semiconductor.

7. The integrated circuit device of claim 1, wherein the semiconductor defines an active region of the transistor, wherein the active region of the transistor has a length extending in a direction from an edge of the second extension region substrate to an opposite edge of the second extension region substrate, and wherein each of the plurality of fins extends by a distance less than the length of the active region of the transistor.

8. The integrated circuit device of claim 1, wherein the semiconductor comprises a first semiconductor material, wherein the first extension region substrate comprises the first semiconductor material and a dopant, and wherein the first extension region vertical plate comprises a second semiconductor material and the dopant.

9. The integrated circuit device of claim 8, wherein the second semiconductor material is different from the first semiconductor material.

10. The integrated circuit device of claim 1, wherein the top surface of the first extension region vertical plate and the top surface of the second extension region vertical plate are located above the top surface of the conductor.

11. The integrated circuit device of claim 1, wherein the transistor is a first transistor, the load node is a first load node, the conductor is a first conductor and the second dielectric is a first example of the second dielectric, and wherein the integrated circuit device further comprises: The second load node; and A second transistor, connected between the voltage node and the second load node, the second transistor comprising: A second example of the second dielectric is that the semiconductor is covered thereon; The second conductor, which is covered with the second dielectric material, is the second example. A third extension region substrate is formed in the semiconductor and extends beyond the first edge of the second conductor, wherein the third extension region substrate has the second conductivity type; The third extension region vertical plate is formed to cover the third extension region substrate and has the second conductivity type; as well as A third source / drain region is formed in the third extension region vertical plate and connected to the second load node, wherein the third source / drain region has the second conductivity type and has a conductivity level greater than that of the third extension region vertical plate. The first extension region substrate extends between the first edge of the first conductor and the second edge of the second conductor opposite to the first edge of the second conductor.

12. The integrated circuit device of claim 11, further comprising: A fourth extension region vertical plate, formed to cover the first extension region substrate and having the second conductivity type, wherein the fourth extension region vertical plate is located between the first extension region vertical plate and the second edge of the second conductor; and A fourth source / drain region is formed in the fourth extension region vertical plate and connected to the voltage node, wherein the fourth source / drain region has the second conductivity type and has a conductivity level greater than that of the fourth extension region vertical plate.

13. The integrated circuit device of claim 1, wherein the transistor is a first transistor, the load node is a first load node, the conductor is a first conductor and the second dielectric is a first example of the second dielectric, and wherein the integrated circuit device further comprises: The second load node; and A second transistor, connected between the voltage node and the second load node, the second transistor comprising: A second example of the second dielectric is that the semiconductor is covered thereon; The second conductor, which is covered with the second dielectric material, is the second example. A third extension region substrate is formed in the semiconductor and extends beyond the first edge of the second conductor, wherein the third extension region substrate has the second conductivity type; A fourth extension region substrate is formed in the semiconductor and extends beyond the second edge of the second conductor opposite to the first edge of the second conductor, wherein the fourth extension region substrate has the second conductivity type; The third extension region vertical plate is formed to cover the third extension region substrate and has the second conductivity type; A fourth extension region vertical plate is formed to cover the fourth extension region substrate and has the second conductivity type; A third source / drain region is formed in the third extension region vertical plate and connected to the voltage node, wherein the third source / drain region has the second conductivity type and has a conductivity level greater than that of the third extension region vertical plate. as well as A fourth source / drain region is formed in the fourth extension region vertical plate and connected to the second load node, wherein the fourth source / drain region has the second conductivity type and has a conductivity level greater than that of the fourth extension region vertical plate.

14. The integrated circuit device of claim 13, further comprising: Third conductor; A first contact element is connected to the third conductor and the third source / drain region; and The second contact is connected to the third conductor and the fourth source / drain region.

15. A memory comprising: Memory cell array; Multiple access lines, each of which is typically connected to the control gate of a corresponding plurality of memory cells in the memory cell array; as well as A driver circuit system comprising a plurality of transistors, wherein each of the plurality of transistors has a respective first source / drain region connected to a respective access line in the plurality of access lines; A specific transistor among the plurality of transistors includes: A semiconductor having a substrate on which it is covered, wherein the semiconductor comprises a plurality of fins covering the substrate, and wherein the semiconductor has a first conductivity type; A plurality of plugs of a first dielectric, wherein each of the plurality of plugs of the first dielectric is formed between a pair of fins in the plurality of fins of the semiconductor; A second dielectric material, on which the semiconductor is coated; A conductor, on which the second dielectric is coated; A first extension region substrate is formed in the semiconductor and extends beyond a first edge of the conductor, wherein the first extension region substrate has a second conductivity type different from the first conductivity type; A second extension region substrate is formed in the semiconductor and extends beyond a second edge of the conductor opposite to the first edge of the conductor, wherein the second extension region substrate has the second conductivity type; The first extension region vertical plate is formed to cover the first extension region substrate and has the second conductivity type; The second extension region vertical plate is formed to cover the second extension region substrate and has the second conductivity type; The corresponding first source / drain region of the specific transistor is formed in the first extension region vertical plate, wherein the corresponding first source / drain region of the specific transistor has a second conductivity type and a conductivity level greater than that of the first extension region vertical plate. as well as A second source / drain region is formed in the second extension region vertical plate and connected to a voltage node, wherein the second source / drain region has the second conductivity type and has a conductivity level greater than that of the second extension region vertical plate.

16. The memory of claim 15, wherein the semiconductor comprises a first semiconductor material, and wherein the substrate comprises the first semiconductor material.

17. The memory of claim 15, wherein the memory cell array is a three-dimensional NAND memory array, and wherein the three-dimensional NAND memory array is formed above the driver circuitry.

18. The memory of claim 17, wherein the three-dimensional NAND memory array comprises memory cell blocks, the memory cell blocks comprising: A first memory cell sub-block of a plurality of memory cell sub-blocks, comprising a first plurality of serially connected strings of memory cells selectively connected to corresponding data lines of a plurality of data lines in response to a first select line; as well as The second memory cell sub-block of the plurality of memory cell sub-blocks includes a second plurality of serially connected memory cell strings that are selectively connected to corresponding data lines of the plurality of data lines in response to a second selection line. The spacing of the driver circuit system in the direction of the data lines in the plurality of data lines is less than three times the spacing of the memory cell sub-blocks in the plurality of memory cell sub-blocks in the direction of the data lines in the plurality of data lines.

19. The memory of claim 15, wherein each of the plurality of transistors comprises: A corresponding example of the semiconductor is covered by the substrate, wherein each corresponding example of the semiconductor includes a corresponding plurality of fins covered by the substrate, and wherein each corresponding example of the semiconductor has the first conductivity type; The first dielectric material has a plurality of corresponding plugs, wherein each of the plurality of corresponding plugs of the first dielectric material is formed between a pair of fins in a plurality of corresponding fins of a semiconductor of a corresponding example thereof. A corresponding example of the second dielectric, which is covered by a corresponding example of the semiconductor; The corresponding conductor, which is covered with the corresponding example of the second dielectric; A corresponding first extension region substrate, which is formed in the corresponding example of the semiconductor and extends beyond the first edge of its corresponding conductor, wherein each corresponding first extension region substrate has the second conductivity type; A corresponding second extension region substrate, which is formed in the corresponding example of the semiconductor and extends beyond the second edge of its corresponding conductor opposite to the first edge of its corresponding conductor, wherein each corresponding second extension region substrate has the second conductivity type; The corresponding first extension region vertical plate is formed to cover its corresponding first extension region substrate and has the second conductivity type; The corresponding second extension region vertical plate is formed to cover its corresponding second extension region substrate and has the second conductivity type; The respective first source / drain region of each of the plurality of transistors is formed in its respective first extension region vertical plate, wherein each respective first source / drain region has the second conductivity type and has a conductivity level greater than that of its respective first extension region vertical plate; and A corresponding second source / drain region is formed in its corresponding second extension region vertical plate and connected to the corresponding voltage node, wherein each corresponding second source / drain region has the second conductivity type and has a conductivity level greater than that of its corresponding second extension region vertical plate.

20. The memory of claim 19, wherein the respective conductors of each of the plurality of transistors are commonly connected.

21. The memory of claim 15, wherein the first extension region substrate of the particular transistor further extends below the conductor, and wherein the second extension region substrate of the particular transistor further extends below the conductor.

22. The memory of claim 15, wherein the first extension region pedestal and the first extension region substrate of the particular transistor each comprise the same semiconductor material.

23. The memory of claim 15, wherein the first extension region prism and the first extension region substrate of the particular transistor each have a single lattice.

24. The memory of claim 15, wherein the plurality of access lines are a plurality of local access lines, wherein the second source / drain region of the particular transistor is connected to a global access line serving as the voltage node, wherein the global access line is selectively connected to a local access line among the plurality of local access lines and selectively connected to local access lines among different plurality of local access lines of the memory.

25. The memory of claim 15, wherein the second extension region substrate of the particular transistor extends from the second edge of the conductor to the edge of an isolation region adjacent to the semiconductor.

26. The memory of claim 15, wherein the conductivity level of the respective first source / drain region of the particular transistor is at least an order of magnitude greater than the conductivity level of the first extension region pedestal of the particular transistor.

27. The memory of claim 26, wherein the conductivity level of the first extension region pedestal of the particular transistor is the same as the conductivity level of the first extension region substrate of the particular transistor.

28. The memory of claim 15, wherein the driver circuitry is a first driver circuitry, the plurality of access lines are a first plurality of access lines, the plurality of transistors are a first plurality of transistors, the second dielectric of a particular transistor among the first plurality of transistors is a first example of the second dielectric, and the conductor of the particular transistor among the first plurality of transistors is a first conductor, the memory further comprising: The second plurality of access lines, each of the second plurality of access lines being connected together to the control gate of a corresponding plurality of memory cells in the memory cell array; as well as A second driver circuit system includes a second plurality of transistors, wherein each of the second plurality of transistors has a corresponding first source / drain region connected to a corresponding access line in the second plurality of access lines. The specific transistor in the second plurality of transistors includes: A second example of the second dielectric is that the semiconductor is covered thereon; The second conductor, which is covered with the second dielectric material, is the second example. A third extension region substrate is formed in the semiconductor and extends beyond the first edge of the second conductor, wherein the third extension region substrate has the second conductivity type; A third extension region vertical plate, which is formed to cover the third extension region substrate and has the second conductivity type; and The corresponding first source / drain region of the specific transistor in the second plurality of transistors is formed in the third extension region vertical plate, wherein the corresponding first source / drain region of the specific transistor in the second plurality of transistors has the second conductivity type and has a conductivity level greater than that of the third extension region vertical plate; The second source / drain region of the specific transistor in the second plurality of transistors is the second source / drain region of the specific transistor in the first plurality of transistors.

29. A method of forming a transistor, comprising: Forming a semiconductor having a first conductivity type; The semiconductor is patterned to define a plurality of fins on the semiconductor; A plurality of plugs forming a first dielectric, wherein each of the plurality of plugs of the first dielectric is located between a pair of fins of the semiconductor in the plurality of fins of the semiconductor; A second dielectric material is formed over the semiconductor; A conductor covered by the second dielectric is formed; The conductors are patterned to define the gate stack of the transistors; A first extension region substrate and a second extension region substrate are formed in the semiconductor, wherein the first extension region substrate and the second extension region substrate each have a second conductivity type different from the first conductivity type; A first extension region vertical plate is formed over the first extension region substrate, wherein the first extension region vertical plate has the second conductivity type; A second extension region vertical plate is formed over the second extension region substrate, wherein the second extension region vertical plate has the second conductivity type; A first source / drain region is formed in the first extension region vertical plate, wherein the first source / drain region has a second conductivity type and a conductivity level greater than that of the first extension region vertical plate; as well as A second source / drain region is formed in the second extension region vertical plate, wherein the second source / drain region has the second conductivity type and has a conductivity level greater than that of the second extension region vertical plate.

30. The method of claim 29, wherein the plurality of fins that pattern the semiconductor to define the semiconductor include forming a plurality of trenches in the semiconductor.

31. The method of claim 30, wherein forming the plurality of trenches in the semiconductor comprises forming a plurality of closed trenches in the semiconductor.

32. The method of claim 29, wherein the semiconductor comprises a first semiconductor material, and wherein forming the first extension region vertical plate covering the first extension region substrate and forming the second extension region vertical plate covering the second extension region substrate comprises: A third dielectric is formed covering the first extended region substrate, the conductor, and the second extended region substrate; A first void is formed in the third dielectric material covering the first extended region substrate, and a second void is formed in the third dielectric material covering the second extended region substrate; and A second semiconductor material is formed in the first gap and the second gap.

33. The method of claim 32, wherein forming the second semiconductor material comprises forming a first structure of the second semiconductor material selected from a group consisting of polycrystalline and amorphous forms, and converting the second semiconductor material into a single lattice.

34. The method of claim 32, wherein forming the second semiconductor material comprises epitaxially growing the second semiconductor material to have the same crystal structure as the first semiconductor material.

35. The method of claim 34, wherein the first semiconductor material and the second semiconductor material are different semiconductor materials.

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