InGaN-based red light emitting diode chip and preparation method thereof

Abstract

The present disclosure provides an InGaN-based red light emitting diode chip and a preparation method thereof, belonging to the field of optoelectronic manufacturing technology. The InGaN-based red light emitting diode chip includes a substrate, a light emitting structure and a flat layer stacked in sequence; the flat layer includes a silicon nitride layer and a plurality of composite layers stacked in sequence, the silicon nitride layer is located on the surface of the light emitting structure away from the substrate, and the composite layer includes a first silicon oxide layer and a second silicon oxide layer stacked alternately, and the deposition temperature of the first silicon oxide layer is higher than the deposition temperature of the second silicon oxide layer. The embodiments of the present disclosure can improve the problem of cracks generated by the flat layer under the influence of cold and heat, enhance the performance of the chip in blocking water vapor, and improve the durability of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to an InGaN-based red light emitting diode chip and a preparation method thereof. Background Art

[0002] Micro Light Emitting Diode (Micro LED) refers to an ultra-small light-emitting diode with a side length of 10μm to 100μm. Micro LEDs are small in size and can be arranged more densely to greatly improve resolution. They also have self-luminous properties and have the characteristics of high brightness, high contrast, high responsiveness and power saving.

[0003] In the related art, an InGaN-based red light emitting diode chip generally includes a substrate, a light emitting structure, a buffer layer, a passivation layer and two solder joint blocks. The light emitting structure and the planar layer are sequentially stacked on the surface of the substrate. The planar layer has two via holes exposing two electrodes in the light emitting structure. The two solder joint blocks are respectively located in the two via holes and are electrically connected to the two electrodes in the light emitting structure through the two via holes.

[0004] However, the flat layer is prone to cracks under the influence of heat and cold, which affects the chip's ability to block moisture and reduces the chip's durability. Summary of the invention

[0005] The disclosed embodiment provides an InGaN-based red light emitting diode chip and a method for manufacturing the same, which can improve the problem of cracks in the flat layer under the influence of heat and cold, enhance the chip's ability to block water vapor, and improve the chip's durability. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode chip, wherein the InGaN-based red light-emitting diode chip includes a substrate, a light-emitting structure and a flat layer stacked in sequence; the flat layer includes a silicon nitride layer and a plurality of composite layers stacked in sequence, the silicon nitride layer is located on a surface of the light-emitting structure away from the substrate, the composite layer includes a first silicon oxide layer and a second silicon oxide layer stacked alternately, and the deposition temperature of the first silicon oxide layer is higher than the deposition temperature of the second silicon oxide layer.

[0007] Optionally, the surface of the first silicon oxide layer away from the silicon nitride layer includes a first laser irradiated area that has been irradiated with laser and a first non-irradiated area that has not been irradiated with laser, and the surface of the second silicon oxide layer away from the silicon nitride layer includes a second laser irradiated area that has been irradiated with laser and a second non-irradiated area that has not been irradiated with laser; the orthographic projection of the first laser irradiated area on the substrate coincides with the orthographic projection of the second non-irradiated area on the substrate, and the orthographic projection of the second laser irradiated area on the substrate coincides with the orthographic projection of the first non-irradiated area on the substrate.

[0008] Optionally, the first laser irradiation area and the first non-irradiation area are both rectangular, and the first laser irradiation area and the first non-irradiation area are alternately arranged along an edge of the first silicon oxide layer away from the surface of the silicon nitride layer.

[0009] Optionally, the silicon nitride layer has a thickness of 80 angstroms to 200 angstroms, and in each of the composite layers, the first silicon oxide layer has a thickness of 4000 angstroms to 6000 angstroms, and the second silicon oxide layer has a thickness of 4000 angstroms to 6000 angstroms.

[0010] Optionally, the InGaN-based red light emitting diode chip further includes: a passivation layer, a first solder point block and a second solder point block; the passivation layer is located on the light emitting structure, and the passivation layer has a first through hole and a second through hole, the first through hole exposes the first electrode of the light emitting structure, and the second through hole exposes the second electrode of the light emitting structure; the first solder point block is located in the first through hole and extends to the first electrode through the first through hole, and the second solder point block is located in the second through hole and extends to the second electrode through the second through hole.

[0011] On the other hand, the present disclosure also provides a preparation method, the preparation method comprising:

[0012] providing a substrate;

[0013] A light-emitting structure and a planar layer are sequentially formed on the substrate, wherein the planar layer comprises a silicon nitride layer and a plurality of composite layers stacked in sequence, wherein the silicon nitride layer is located on a surface of the light-emitting structure away from the substrate, and the composite layer comprises a first silicon oxide layer and a second silicon oxide layer stacked alternately, wherein a deposition temperature of the first silicon oxide layer is higher than a deposition temperature of the second silicon oxide layer.

[0014] Optionally, the deposition temperature of the first silicon oxide layer is greater than 250°C, and the deposition temperature of the second silicon oxide layer is 200°C to 250°C.

[0015] Optionally, a deposition temperature of the silicon nitride layer is the same as a deposition temperature of the first silicon oxide layer.

[0016] Optionally, when forming the composite layer, the method includes: after depositing the first silicon oxide layer, laser irradiating a first laser irradiation area of ​​the surface of the first silicon oxide layer away from the silicon nitride layer; after depositing the second silicon oxide layer, laser irradiating a second laser irradiation area of ​​the surface of the second silicon oxide layer away from the silicon nitride layer, the surface of the first silicon oxide layer away from the silicon nitride layer also includes a first non-irradiation area that has not been laser irradiated, and the surface of the second silicon oxide layer away from the silicon nitride layer also includes a second non-irradiation area that has not been laser irradiated; the orthographic projection of the first laser irradiation area on the substrate coincides with the orthographic projection of the second non-irradiation area on the substrate, and the orthographic projection of the second laser irradiation area on the substrate coincides with the orthographic projection of the first non-irradiation area on the substrate.

[0017] Optionally, the first laser irradiation area and the first non-irradiation area are both rectangular, and the first laser irradiation area and the first non-irradiation area are alternately arranged along an edge of the first silicon oxide layer away from the surface of the silicon nitride layer.

[0018] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0019] The InGaN-based red light emitting diode chip provided by the embodiment of the present disclosure includes a substrate, a light emitting structure and a flat layer stacked in sequence. Among them, the flat layer includes a silicon nitride layer and a plurality of composite layers stacked in sequence, the silicon nitride layer is located on the surface of the light emitting structure away from the substrate, and the silicon nitride layer is used to improve the adhesion so that the flat layer can connect the light emitting structure more closely together; the composite layer includes a first silicon oxide layer and a second silicon oxide layer stacked alternately, and the deposition temperature of the first silicon oxide layer is higher than the deposition temperature of the second silicon oxide layer. A lower deposition temperature can reduce the proportion of chemical bonds, thereby alleviating the accumulation of stress in the silicon oxide layer, while a higher deposition temperature can form a silicon oxide layer with better compactness. In this way, the first silicon oxide layer with good compactness and the second silicon oxide layer with relieved stress are alternately formed, which can not only improve the problem of stress concentration in the flat layer, but also ensure the compactness of the flat layer. The performance of the flat layer in coping with temperature rise and fall is greatly improved, the problem of cracks generated under the influence of hot and cold on the flat layer is improved, the performance of the chip in blocking water vapor is enhanced, and the durability of the chip is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1It is a schematic structural diagram of an InGaN-based red light emitting diode chip provided by an embodiment of the present disclosure;

[0022] Figure 2 is a hierarchical schematic diagram of a flat layer provided by an embodiment of the present disclosure;

[0023] Figure 3 is a top view of an InGaN-based red light emitting diode chip provided by an embodiment of the present disclosure;

[0024] Figure 4 is a schematic diagram of a first silicon oxide layer provided by an embodiment of the present disclosure;

[0025] Figure 5 is a schematic diagram of a second silicon oxide layer provided in an embodiment of the present disclosure;

[0026] Figure 6 It is a flow chart of a method for preparing an InGaN-based red light emitting diode chip provided by an embodiment of the present disclosure;

[0027] Figure 7 It is a schematic diagram of a preparation process of an InGaN-based red light emitting diode chip provided in an embodiment of the present disclosure;

[0028] Figure 8 It is a schematic diagram of the preparation process of an InGaN-based red light emitting diode chip provided in an embodiment of the present disclosure.

[0029] The descriptions of the marks in the figure are as follows:

[0030] 10. substrate; 11. GaAs substrate;

[0031] 20. Light emitting structure; 21. First semiconductor layer; 22. Multi-quantum well layer; 23. Second semiconductor layer; 25. First electrode; 26. Second electrode; 27. First solder joint block; 28. Second solder joint block;

[0032] 30, flat layer; 310, silicon nitride layer; 320, composite layer; 321, first silicon oxide layer; 322, second silicon oxide layer; 330, first laser irradiation area; 331, first non-irradiation area; 340, second laser irradiation area; 341, second non-irradiation area;

[0033] 40. Groove; 41. First through hole; 42. Second through hole; 43. Passivation layer. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0035] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] Figure 1 FIG. 1 is a schematic diagram of the structure of an InGaN-based red light emitting diode chip provided by an embodiment of the present disclosure. Figure 1 As shown, the InGaN-based red light emitting diode chip includes a substrate 10, a light emitting structure 20 and a planar layer 30 which are stacked in sequence.

[0037] Figure 2 FIG. 1 is a schematic diagram of the hierarchical structure of a flat layer 30 provided in an embodiment of the present disclosure. Figure 2 As shown, the planarization layer 30 includes a silicon nitride layer 310 and a plurality of composite layers 320 stacked in sequence, the silicon nitride layer 310 is located on the surface of the light emitting structure 20 away from the substrate 10, the composite layer 320 includes a first silicon oxide layer 321 and a second silicon oxide layer 322 stacked alternately, and the deposition temperature of the first silicon oxide layer 321 is higher than the deposition temperature of the second silicon oxide layer 322.

[0038] The InGaN-based red light emitting diode chip provided by the embodiment of the present disclosure includes a substrate 10, a light emitting structure 20 and a flat layer 30 stacked in sequence. Among them, the flat layer 30 includes a silicon nitride layer 310 and a plurality of composite layers 320 stacked in sequence, the silicon nitride layer 310 is located on the surface of the light emitting structure 20 away from the substrate 10, and the silicon nitride layer 310 is used to improve the adhesion, so that the flat layer 30 can be more closely connected to the light emitting structure 20; the composite layer 320 includes a first silicon oxide layer 321 and a second silicon oxide layer 322 alternately stacked, and the deposition temperature of the first silicon oxide layer 321 is higher than the deposition temperature of the second silicon oxide layer 322. A lower deposition temperature can reduce the proportion of chemical bonds, thereby relieving the accumulation of stress in the silicon oxide layer, while a higher deposition temperature can form a silicon oxide layer with better compactness. In this way, the first silicon oxide layer 321 with good compactness and the second silicon oxide layer 322 with relieved stress are alternately formed, which can not only improve the problem of stress concentration in the flat layer 30, but also ensure the compactness of the flat layer 30. The performance of the flat layer 30 in coping with temperature rise and fall is greatly improved, the problem of cracks in the flat layer 30 under the influence of heat and cold is improved, the performance of the chip in blocking water vapor is enhanced, and the durability of the chip is improved.

[0039] Alternatively, if Figure 1 As shown, the light emitting structure 20 includes: a first semiconductor layer 21 , a multi-quantum well layer 22 , a second semiconductor layer 23 , a first electrode 25 and a second electrode 26 .

[0040] like Figure 1 As shown, the first semiconductor layer 21, the multi-quantum well layer 22 and the second semiconductor layer 23 are stacked in sequence on the substrate 10, the second electrode 26 is located on the surface of the second semiconductor layer 23, the surface of the second semiconductor layer 23 has a groove exposing the first semiconductor layer 21, and the first electrode 25 is located on the surface of the first semiconductor layer 21 and on the bottom of the groove.

[0041] A first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 are sequentially stacked on a substrate 10, wherein a second electrode 26 is arranged on the surface of the second semiconductor layer 23, and the surface of the second semiconductor layer 23 has a groove exposing the first semiconductor layer 21, that is, part of the second semiconductor layer 23 and the multi-quantum well layer 22 are removed through the groove, so that the first electrode 25 is directly arranged on the surface of the first semiconductor layer 21 through the groove, so that the overall thickness of the epitaxial structure is thinned.

[0042] like Figure 1 As shown, the InGaN-based red light emitting diode chip further includes: a passivation layer 43, a first solder joint block 27 and a second solder joint block 28. The passivation layer 43 is located on the light emitting structure 20, wherein the passivation layer 43 at least covers the surfaces of the first semiconductor layer 21, the first electrode 25, the groove, the second semiconductor layer 23 and the second electrode 26.

[0043] like Figure 1 As shown, the passivation layer 43 has a first through hole 41 and a second through hole 42, the first through hole 41 exposes the first electrode 25 of the light-emitting structure 20, and the second through hole 42 exposes the second electrode 26 of the light-emitting structure 20; the first solder joint block 27 is located in the first through hole 41 and extends to the first electrode 25 through the first through hole 41, and the second solder joint block 28 is located in the second through hole 42 and extends to the second electrode 26 through the second through hole 42.

[0044] By covering the first solder joint block 27 on the first through hole 41 and connecting the light to the first electrode 25, the electrical connection of the first electrode 25 is facilitated; the second solder joint block 28 covers the second through hole 42 and connects to the second electrode 26, which facilitates the electrical connection of the second electrode 26.

[0045] Figure 3 FIG. 1 is a top view of an InGaN-based red light emitting diode chip provided by an embodiment of the present disclosure. Figure 3 As shown, the first soldering point block 27 and the second soldering point block 28 are both rectangular blocks, which increase the area and facilitate conduction. In addition, on the surface of the passivation layer 43, the first soldering point block 27 and the second soldering point block 28 are distributed at intervals.

[0046] Optionally, the substrate 10 is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light emitting diode has good light emitting effect and stability.

[0047] Optionally, the first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0048] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers, wherein the multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0049] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0050] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0051] Optionally, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0052] Optionally, the passivation layer 43 may be a SiO2 layer, and the thickness of the SiO2 layer may be 5000 angstroms to 8000 angstroms. In addition to the passivation function, the SiO2 layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the passivation layer 43 to the substrate 10, thereby improving the light extraction effect.

[0053] Figure 4 is a schematic diagram of a first silicon oxide layer 321 provided by the present disclosure, Figure 5 FIG. 3 is a schematic diagram of a second silicon oxide layer 322 provided in an embodiment of the present disclosure. Figure 4 , 5 As shown, the surface of the first silicon oxide layer 321 away from the silicon nitride layer 310 includes a first laser irradiated area 330 that has been irradiated with laser and a first non-irradiated area 331 that has not been irradiated with laser, and the surface of the second silicon oxide layer 322 away from the silicon nitride layer 310 includes a second laser irradiated area 340 that has been irradiated with laser and a second non-irradiated area 341 that has not been irradiated with laser.

[0054] The orthographic projection of the first laser irradiation area 330 on the substrate 10 coincides with the orthographic projection of the second non-irradiation area 341 on the substrate 10 , and the orthographic projection of the second laser irradiation area 340 on the substrate 10 coincides with the orthographic projection of the first non-irradiation area 331 on the substrate 10 .

[0055] The first laser irradiation area 330 disposed on the first silicon oxide layer 321 is used for laser irradiation, so that a small amount of chemical bonds on the first laser irradiation area 330 of the first silicon oxide layer 321 can be broken by laser irradiation, thereby reducing the stress on the first silicon oxide layer 321. The second laser irradiation area 340 disposed on the second silicon oxide layer 322 is used for laser irradiation, so that a small amount of chemical bonds on the second laser irradiation area 340 of the second silicon oxide layer 322 can be broken by laser irradiation, thereby reducing the stress on the second silicon oxide layer 322.

[0056] Among them, the first laser irradiation area 330 is opposite to the second non-irradiation area 341, and the second laser irradiation area 340 is opposite to the first non-irradiation area 331. That is, the first laser irradiation area 330 and the second laser irradiation area 340 are complementary, and the first laser irradiation area 330 and the second laser irradiation area 340 are combined to cover the entire silicon nitride layer 310. By setting the first laser irradiation area 330 of the first silicon oxide layer 321 and the second laser irradiation area 340 of the second silicon oxide layer 322 as complementary patterns, the areas where the chemical bonds are broken on the composite layer 320 will not overlap, which effectively reduces the stress and does not significantly affect the mechanical strength of the film layer.

[0057] For example, Figure 4As shown, the first laser irradiation area 330 and the first non-irradiation area 331 are both rectangular, and the first laser irradiation area 330 and the first non-irradiation area 331 are alternately arranged along the edge of the first silicon oxide layer 321 away from the surface of the silicon nitride layer 310 .

[0058] For example, Figure 5 As shown, the second laser irradiation area 340 and the second non-irradiation area 341 are both rectangular, and the second laser irradiation area 340 and the second non-irradiation area 341 are alternately arranged along the edge of the second silicon oxide layer 322 away from the surface of the silicon nitride layer 310 .

[0059] By arranging the first laser irradiation area 330 and the second laser irradiation area 340 in a checkerboard shape, and making the pattern corresponding to the first laser irradiation area 330 and the pattern corresponding to the second laser irradiation area 340 complementary patterns, the areas where the chemical bonds are broken on the first silicon oxide layer 321 and the second silicon oxide layer 322 will not overlap, which effectively reduces the stress without significantly affecting the mechanical strength of the film layer.

[0060] Optionally, the thickness of the silicon nitride layer 310 is 80 angstroms to 200 angstroms, and in each composite layer 320 , the thickness of the first silicon oxide layer 321 is 4000 angstroms to 6000 angstroms, and the thickness of the second silicon oxide layer 322 is 4000 angstroms to 6000 angstroms.

[0061] For example, the thickness of silicon oxide may be 100 angstroms. In each composite layer 320 , the thickness of the first silicon oxide layer 321 is 5000 angstroms, and the thickness of the second silicon oxide layer 322 is 5000 angstroms.

[0062] As an example, the planarization layer 30 may include a silicon nitride layer 310 and five composite layers 320. The thickness of the silicon nitride layer 310 is 100 angstroms, and the deposition temperature of the silicon nitride is greater than 250°C, for example, the deposition temperature of the silicon nitride is 300°C. In each composite layer 320, the thickness of the first silicon oxide layer 321 is 5000 angstroms, and the deposition temperature of the first silicon oxide layer 321 is greater than 250°C, for example, the deposition temperature of the first silicon oxide layer 321 is 300°C; the thickness of the second silicon oxide layer 322 is 5000 angstroms, and the deposition temperature of the second silicon oxide layer 322 is 200°C to 250°C, for example, the deposition temperature of the second silicon oxide layer 322 is 200°C.

[0063] Figure 6 This is a flow chart of a method for preparing an InGaN-based red light emitting diode chip provided in an embodiment of the present disclosure. Figure 1 The InGaN-based red light emitting diode chip shown in FIG. Figure 6 As shown, the preparation method comprises:

[0064] S11: providing a substrate 10.

[0065] S12 : forming the light emitting structure 20 and the planarization layer 30 on the substrate 10 in sequence.

[0066] Among them, the planarization layer 30 includes a silicon nitride layer 310 and a plurality of composite layers 320 stacked in sequence, the silicon nitride layer 310 is located on the surface of the light-emitting structure 20 away from the substrate 10, and the composite layer 320 includes a first silicon oxide layer 321 and a second silicon oxide layer 322 stacked alternately, and the deposition temperature of the first silicon oxide layer 321 is higher than the deposition temperature of the second silicon oxide layer 322.

[0067] The InGaN-based red light-emitting diode chip prepared by this preparation method includes a substrate 10, a light-emitting structure 20 and a flat layer 30 stacked in sequence. Among them, the flat layer 30 includes a silicon nitride layer 310 and a plurality of composite layers 320 stacked in sequence, the silicon nitride layer 310 is located on the surface of the light-emitting structure 20 away from the substrate 10, and the silicon nitride layer 310 is used to improve the adhesion, so that the flat layer 30 can be more closely connected to the light-emitting structure 20; the composite layer 320 includes a first silicon oxide layer 321 and a second silicon oxide layer 322 alternately stacked, and the deposition temperature of the first silicon oxide layer 321 is higher than the deposition temperature of the second silicon oxide layer 322. A lower deposition temperature can reduce the proportion of chemical bonds, thereby relieving the accumulation of stress in the silicon oxide layer, while a higher deposition temperature can form a silicon oxide layer with better density. In this way, the first silicon oxide layer 321 with good density and the second silicon oxide layer 322 with relieved stress are alternately formed, which can not only improve the problem of stress concentration in the flat layer 30, but also ensure the density of the flat layer 30. The performance of the flat layer 30 in coping with temperature rise and fall is greatly improved, the problem of cracks in the flat layer 30 under the influence of heat and cold is improved, the performance of the chip in blocking water vapor is enhanced, and the durability of the chip is improved.

[0068] Optionally, the substrate 10 is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light emitting diode has good light emitting effect and stability.

[0069] In step S11, the sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0070] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0071] The light emitting structure 20 grown in step S12 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 sequentially stacked on the substrate 10 .

[0072] like Figure 7 As shown, the process of growing the light emitting structure 20 may include: first, growing a second semiconductor layer 23 on the GaAs substrate 11 .

[0073] Exemplarily, the second semiconductor layer 23 is a magnesium-doped p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0074] like Figure 7 As shown, after the second semiconductor layer 23 is grown, the multi-quantum well layer 22 is grown on the second semiconductor layer 23 .

[0075] The multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0076] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0077] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0078] like Figure 7 As shown, after the multi-quantum well layer 22 is grown, the first semiconductor layer 21 is grown on the multi-quantum well layer 22 .

[0079] The first semiconductor layer 21 is a silicon-doped n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0080] In step S12 , a GaAs layer and an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .

[0081] After growing the first semiconductor layer 21 , a GaP window layer may be further grown, wherein the thickness of the GaP window layer is 2 μm to 5 μm.

[0082] Exemplarily, the thickness of the GaP window layer is 3 μm.

[0083] After the light emitting structure 20 is formed in step S12 , the method further includes: bonding the substrate 10 and the light emitting structure 20 to form a bonding layer.

[0084] Specifically, the process may include coating liquid silicon oxide on the surface of the first semiconductor layer 21 of the light emitting structure 20, and curing the liquid silicon oxide to form a bonding layer at a curing temperature of 250° C. to 350° C. Furthermore, after the light emitting structure 20 is bonded to the substrate 10, the GaAs substrate 11 is removed.

[0085] Exemplarily, the bonding temperature may be 300°C.

[0086] In the embodiment of the present disclosure, after the bonding is completed, a complete light emitting structure 20 can be formed.

[0087] First, a groove exposing the first semiconductor layer 21 is etched on the surface of the second semiconductor layer 23 .

[0088] like Figure 8 As shown, it may specifically include: removing a part of the second semiconductor layer by dry etching, and etching until the first semiconductor layer 21 is exposed. The etching depth is 1 μm to 2 μm, for example, etching 1.5 μm.

[0089] After etching the grooves, a first electrode 25 may be formed on the first semiconductor layer 21 , and a second electrode 26 may be formed on the second semiconductor layer 23 .

[0090] The forming of the first electrode 25 and the second electrode 26 may include: processing the first electrode 25 and the second electrode 26 respectively by negative resist stripping.

[0091] like Figure 8 As shown, the second electrode 26 is located on the surface of the second semiconductor layer 23, and the first electrode 25 is located on the bottom surface of the groove.

[0092] The first electrode 25 is mainly composed of gold beryllium, and the second electrode 26 is evaporated with gold germanium as the base material. When evaporating the gold germanium alloy, the evaporation power must be guaranteed to avoid the evaporation time exceeding 5 seconds to prevent the deviation of the alloy composition, and annealing is performed.

[0093] In step S12 , manufacturing the planar layer 30 may include: sequentially forming a silicon nitride layer 310 and a plurality of composite layers 320 on the surface of the light emitting structure 20 .

[0094] Each composite layer 320 includes first silicon oxide layers 321 and second silicon oxide layers 322 that are alternately stacked, and a deposition temperature of the first silicon oxide layer 321 is higher than a deposition temperature of the second silicon oxide layer 322 .

[0095] Optionally, the deposition temperature of the first silicon oxide layer 321 is greater than 250°C, and the deposition temperature of the second silicon oxide layer 322 is 200°C to 250°C.

[0096] Exemplarily, the deposition temperature of the first silicon oxide layer 321 is 300° C., and the deposition temperature of the second silicon oxide layer 322 is 200° C.

[0097] The deposition temperature of the silicon nitride layer 310 is the same as the deposition temperature of the first silicon oxide. For example, the deposition temperature of the silicon nitride layer 310 is 300° C. to form a silicon nitride layer with good quality.

[0098] The surface of the first silicon oxide layer 321 away from the silicon nitride layer 310 includes a first laser irradiated area 330 that has been irradiated with laser and a first non-irradiated area 331 that has not been irradiated with laser, and the surface of the second silicon oxide layer 322 away from the silicon nitride layer 310 includes a second laser irradiated area 340 that has been irradiated with laser and a second non-irradiated area 341 that has not been irradiated with laser. The orthographic projection of the first laser irradiated area 330 on the substrate 10 coincides with the orthographic projection of the second non-irradiated area 341 on the substrate 10, and the orthographic projection of the second laser irradiated area 340 on the substrate 10 coincides with the orthographic projection of the first non-irradiated area 331 on the substrate 10.

[0099] Optionally, when forming the composite layer 320 , the process includes: after depositing the first silicon oxide layer 321 , performing laser irradiation on the first laser irradiation area 330 ; and after depositing the second silicon oxide layer 322 , performing laser irradiation on the second laser irradiation area 340 .

[0100] By means of laser irradiation, a small amount of chemical bonds on the first laser irradiation area 330 of the first silicon oxide layer 321 can be broken, thereby reducing the stress on the first silicon oxide layer 321. By means of laser irradiation, a small amount of chemical bonds on the second laser irradiation area 340 of the second silicon oxide layer 322 can be broken, thereby reducing the stress on the second silicon oxide layer 322.

[0101] For example, Figure 4 , 5 As shown, the first laser irradiation area 330 and the first non-irradiation area 331 are both rectangular, and the first laser irradiation area 330 and the first non-irradiation area 331 are alternately arranged along the edge of the first silicon oxide layer 321 away from the surface of the silicon nitride layer 310. The second laser irradiation area 340 and the second non-irradiation area 341 are both rectangular, and the second laser irradiation area 340 and the second non-irradiation area 341 are alternately arranged along the edge of the second silicon oxide layer 322 away from the surface of the silicon nitride layer 310.

[0102] By setting the first laser irradiation area 330 of the first silicon oxide layer 321 and the second laser irradiation area 340 of the second silicon oxide layer 322 as complementary patterns, the areas where the chemical bonds are broken on the composite layer 320 will not overlap, which effectively reduces stress without significantly affecting the mechanical strength of the film layer.

[0103] Optionally, when performing laser irradiation, the focus of the laser is located at the center of the first laser irradiation area 330 when performing laser irradiation on the first laser irradiation area 330 ; and the focus of the laser is located at the center of the second laser irradiation area 340 when performing laser irradiation on the second laser irradiation area 340 .

[0104] Controlling the focus of the laser to irradiate the center of the first laser irradiation area 330 can ensure the laser irradiation effect of the first laser irradiation area 330 and ensure that the broken chemical bonds are located in the first laser irradiation area 330. Controlling the focus of the laser to irradiate the center of the second laser irradiation area 340 can ensure the laser irradiation effect of the second laser irradiation area 340 and ensure that the broken chemical bonds are located in the second laser irradiation area 340.

[0105] After the planarization layer 30 is formed, Figure 1 As shown, the preparation method may further include: forming a first through hole 41 and a second through hole 42 on the surface of the flat layer 30 away from the substrate 10. Forming a first soldering point block 27 on the surface of the flat layer 30 by photolithography, so that the first soldering point block 27 is connected to the first electrode 25 through the first through hole 41; then, forming a second soldering point block 28 on the surface of the flat layer 30 by photolithography, so that the second soldering point block 28 is connected to the second electrode 26 through the second through hole 42.

[0106] like Figure 1 As shown, after the first soldering point block 27 and the second soldering point block 28 are formed, a passivation layer 43 may be formed on the surface of the planar layer 30 , and the passivation layer 43 extends from the surface of the planar layer 30 to the substrate 10 .

[0107] For example, in the embodiment of the present disclosure, the passivation layer 43 may be a silicon oxide film layer, and the thickness of the silicon oxide film layer is 2000 angstroms.

[0108] It should be noted that after the passivation layer 43 is grown on the surface of the planar layer 30 , a through hole exposing the solder joint block can be etched on the surface of the passivation layer 43 using a photolithography technique to facilitate electrical connection.

[0109] After forming the passivation layer 43 , the sapphire substrate 10 is thinned, and the final thickness after thinning is 80 μm.

[0110] Finally, the sapphire can be cut and cracked by stealth cutting, which can effectively reduce the loss of brightness. Then, the InGaN-based red light emitting diode chip is obtained by testing.

[0111] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. An InGaN-based red light emitting diode chip, characterized in that: The InGaN-based red light emitting diode chip comprises a substrate (10), a light emitting structure (20) and a flat layer (30) which are stacked in sequence; The flat layer (30) comprises a silicon nitride layer (310) and a plurality of composite layers (320) stacked in sequence, the silicon nitride layer (310) being located on a surface of the light emitting structure (20) away from the substrate (10), the composite layer (320) comprising a first silicon oxide layer (321) and a second silicon oxide layer (322) stacked alternately, the deposition temperature of the first silicon oxide layer (321) being higher than the deposition temperature of the second silicon oxide layer (322); The surface of the first silicon oxide layer (321) away from the silicon nitride layer (310) includes a first laser irradiated area (330) that has been irradiated with laser and a first non-irradiated area (331) that has not been irradiated with laser, and the surface of the second silicon oxide layer (322) away from the silicon nitride layer (310) includes a second laser irradiated area (340) that has been irradiated with laser and a second non-irradiated area (341) that has not been irradiated with laser; The orthographic projection of the first laser irradiation area (330) on the substrate (10) coincides with the orthographic projection of the second non-irradiation area (341) on the substrate (10), and the orthographic projection of the second laser irradiation area (340) on the substrate (10) coincides with the orthographic projection of the first non-irradiation area (331) on the substrate (10).

2. The InGaN-based red light emitting diode chip according to claim 1, characterized in that: The first laser irradiation area (330) and the first non-irradiation area (331) are both rectangular, and the first laser irradiation area (330) and the first non-irradiation area (331) are alternately arranged along the edge of the first silicon oxide layer (321) away from the surface of the silicon nitride layer (310).

3. The InGaN-based red light emitting diode chip according to claim 1 or 2, characterized in that: The thickness of the silicon nitride layer (310) is 80 angstroms to 200 angstroms. In each of the composite layers (320), the thickness of the first silicon oxide layer (321) is 4000 angstroms to 6000 angstroms, and the thickness of the second silicon oxide layer (322) is 4000 angstroms to 6000 angstroms.

4. The InGaN-based red light emitting diode chip according to claim 1 or 2, characterized in that: The InGaN-based red light emitting diode chip further comprises: a passivation layer, a first soldering point block (27) and a second soldering point block (28); The passivation layer is located on the light emitting structure (20), and has a first through hole (41) and a second through hole (42) on the passivation layer, wherein the first through hole (41) exposes the first electrode (25) of the light emitting structure (20), and the second through hole (42) exposes the second electrode (26) of the light emitting structure (20); The first soldering point block (27) is located in the first through hole (41) and extends to the first electrode (25) through the first through hole (41), and the second soldering point block (28) is located in the second through hole (42) and extends to the second electrode (26) through the second through hole (42).

5. A method for preparing an InGaN-based red light emitting diode chip, characterized in that: The preparation method comprises: providing a substrate; A light-emitting structure and a planar layer are sequentially formed on the substrate, wherein the planar layer comprises a silicon nitride layer and a plurality of composite layers stacked in sequence, wherein the silicon nitride layer is located on a surface of the light-emitting structure away from the substrate, wherein the composite layer comprises a first silicon oxide layer and a second silicon oxide layer stacked alternately, wherein the deposition temperature of the first silicon oxide layer is higher than the deposition temperature of the second silicon oxide layer, and when forming the composite layer, the steps include: after depositing the first silicon oxide layer, laser irradiating a first laser irradiation area on a surface of the first silicon oxide layer away from the silicon nitride layer; after depositing the second silicon oxide layer, laser irradiating a second laser irradiation area on a surface of the second silicon oxide layer away from the silicon nitride layer, wherein the surface of the first silicon oxide layer away from the silicon nitride layer further comprises a first non-irradiation area which has not been subjected to laser irradiation, and the surface of the second silicon oxide layer away from the silicon nitride layer further comprises a second non-irradiation area which has not been subjected to laser irradiation; the orthographic projection of the first laser irradiation area on the substrate coincides with the orthographic projection of the second non-irradiation area on the substrate, and the orthographic projection of the second laser irradiation area on the substrate coincides with the orthographic projection of the first non-irradiation area on the substrate.

6. The preparation method according to claim 5, characterized in that: The deposition temperature of the first silicon oxide layer is greater than 250°C, and the deposition temperature of the second silicon oxide layer is between 200°C and 250°C.

7. The preparation method according to claim 6, characterized in that: The deposition temperature of the silicon nitride layer is the same as the deposition temperature of the first silicon oxide layer.

8. The preparation method according to claim 5, characterized in that: The first laser irradiation area and the first non-irradiation area are both rectangular, and the first laser irradiation area and the first non-irradiation area are alternately arranged along an edge of the first silicon oxide layer away from the surface of the silicon nitride layer.

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