Data processing apparatus and method

Abstract

Apparatus and methods for data processing are disclosed. An apparatus includes a first instruction execution circuit, a second instruction execution circuit, and a decoupled access buffer. Instructions in an in-order instruction sequence are issued for execution to one of the first instruction execution circuit and the second instruction execution circuit depending on whether the instructions have a first type of tag or a second type of tag. Instructions having the first type of tag are access-related instructions that determine at least one characteristic of a load operation to retrieve a data value from a memory address. Instruction execution of instructions having the first type of tag by the first instruction execution circuit is prioritized over instruction execution of instructions having the second type of tag by the second instruction execution circuit. Data values retrieved from memory are stored in the decoupled access buffer as a result of execution of the first type of instructions. Once a data value needed for execution of a pending second type of instruction is in the decoupled access buffer, the second instruction execution circuit retrieves the data value from the decoupled access buffer and executes the pending instruction.

Description

Background Technology

[0001] This invention relates to a data processing apparatus.

[0002] There are constant driving forces for improving the performance of contemporary and future data processing devices such as CPUs. However, opportunities to do so are limited and improvements are slow, resulting in new generations of CPUs typically achieving only small performance improvements relative to their predecessors. Specific challenges in processor design involve scaling instruction windows and, consequently, scaling look-ahead execution depth. While larger instruction windows generally increase look-ahead execution depth and thus allow for higher levels of instruction-level parallelism, the complexity associated with building devices that support increasingly larger instruction windows is significant. Furthermore, stagnation due to cache misses (and other memory access latency challenges) degrades overall performance and exacerbates the instruction window problem, as some parts of the instruction flow may fail to progress but still consume resources and reduce effective look-ahead execution depth. Summary of the Invention

[0003] At least some examples disclosed herein provide a data processing apparatus comprising: a publishing circuit for publishing instructions for out-of-order execution relative to an ordered sequence of instructions; a first instruction execution circuit and a second instruction execution circuit; and a decoupled access buffer, wherein the publishing circuit, in response to a type flag associated with an instruction, publishes an instruction for execution to the first instruction execution circuit when the instruction has a first type flag, and publishes an instruction for execution to the second instruction execution circuit when the instruction has a second type flag; wherein the instructions with the first type flag and the instructions with the second type flag originate from the ordered sequence; wherein when the instruction is an access-related instruction, the instruction has the first type flag, the access-related instruction being determined for execution according to memory... The instruction has at least one feature of loading an address-retrieval data value, wherein when the instruction is not an access-related instruction, the instruction has a second type flag; wherein the data processing device is arranged to prioritize the execution of an instruction with a first type flag by a first instruction execution circuit over the execution of an instruction with a second type flag by a second instruction execution circuit; and wherein the first instruction execution circuit is arranged to store a data value retrieved from memory as the result of the execution of the instruction with the first type flag in a decoupled access buffer, and the second instruction execution circuit, in response to the data value required to execute a pending instruction with a second type flag stored in the decoupled access buffer, retrieves the data value from the decoupled access buffer and executes the pending instruction.

[0004] At least some examples disclosed herein provide a data processing method comprising: issuing instructions for out-of-order execution relative to an ordered sequence of instructions; issuing instructions for execution to a first instruction execution circuit when the instructions have a first type flag, and issuing instructions for execution to a second instruction execution circuit when the instructions have a second type flag, wherein the instructions with the first type flag and the instructions with the second type flag originate from the ordered sequence, wherein when the instructions are access-related instructions, the instructions have the first type flag, the access-related instructions determining at least one feature of a load operation for retrieving a data value based on a memory address. Furthermore, when the instruction is not an access-related instruction, the instruction has a second type flag; the execution of the instruction with the first type flag performed by the first instruction execution circuit takes precedence over the execution of the instruction with the second type flag performed by the second instruction execution circuit; the data value retrieved from memory is stored in the decoupled access buffer as the result of the execution of the instruction with the first type flag performed by the first instruction execution circuit; in response to the data value required to execute the pending instruction with the second type flag stored in the decoupled access buffer, the data value is retrieved from the decoupled access buffer for the second instruction execution circuit and the pending instruction is executed in the second instruction execution circuit.

[0005] At least some examples disclosed herein provide a data processing apparatus comprising: means for issuing instructions for out-of-order execution relative to an ordered sequence of instructions; a first means for instruction execution and a second means for instruction execution; a decoupled access buffer; means for issuing instructions for execution to the first means for instruction execution when an instruction has a first type tag, in response to a type tag associated with an instruction; and means for issuing instructions for execution to the second means for instruction execution when an instruction has a second type tag, wherein the instructions with the first type tag and the instructions with the second type tag originate from the ordered sequence, wherein when the instruction is an access-related instruction, the instruction has the first type tag, the access-related instruction determining at least one feature of a load operation for retrieving a data value based on a memory address. The instruction has a second type flag when it is not an access-related instruction; means for performing the following operations: prioritizing the execution of an instruction with a first type flag performed by a first means for instruction execution over the execution of an instruction with a second type flag performed by a second means for instruction execution; means for performing the following operations: storing a data value retrieved from memory as the result of the execution of an instruction with a first type flag performed by the first means for instruction execution in a decoupled access buffer; means for retrieving the data value from the decoupled access buffer for the second means for instruction execution in response to the data value required for executing a pending instruction with a second type flag stored in the decoupled access buffer; and means for executing the pending instruction in the second means for instruction execution. Attached Figure Description

[0006] The invention will be further described by way of example only, with reference to embodiments of the invention shown in the accompanying drawings, and in conjunction with the following description: Figure 1A This illustrates an instruction sequence, including both access and execution instructions received by a prior art processor, in a scenario where a cache miss for an access instruction causes the pipeline to stall due to some subsequent execution instructions. Figure 1B The same sequence of instructions received by the processor is shown according to some implementations, wherein the execution of priority access instructions and the deferral of execution instructions allow for greater instruction execution progress; Figure 2 The data processing apparatus in some embodiments is illustrated schematically; Figure 3 The sequence of steps taken in a processor according to some exemplary embodiments is illustrated; Figure 4 The data processing apparatus in some embodiments is illustrated schematically; Figure 5The data processing apparatus in some embodiments is illustrated schematically; Figure 6 The collision detection circuitry provided in some embodiments is illustrated schematically; and Figure 7 The sequence of steps taken by a collision detection circuit according to some exemplary implementation methods is shown.

[0007] Figure 8A and Figure 8B A data dependency graph of an exemplary instruction sequence is shown, in which Figure 8A It is a "access" data dependency graph, and Figure 8B It is an "execution" data dependency graph; Figure 9 A data processing apparatus according to some embodiments is schematically shown; Figure 10 It is a flowchart illustrating the sequence of steps taken according to some implementation schemes; Figure 11 It is a flowchart illustrating the sequence of steps taken according to some implementation schemes; Figure 12 A data processing apparatus according to some embodiments is schematically shown; Figure 13A An example of the contents of a traversal table according to some implementation schemes is shown; Figure 13B An exemplary content of the final writer table according to some implementation schemes is shown; Figure 14A and Figure 14B An instruction tag storage device according to some embodiments and some exemplary content are schematically shown; Figure 15A and Figure 15B The instruction cache hierarchy associated with the micro-operations cache is illustrated schematically according to some implementation schemes; Figure 16 An apparatus according to some exemplary specific implementations is illustrated schematically; Figure 17 The illustrations show some exemplary specific implementations. Figure 16 The device also shows an example of effective operation; Figure 18 An apparatus according to some exemplary specific implementations is illustrated schematically; Figure 19 The illustrations show effective examples of experimental proximity checks and address proximity checks according to some exemplary specific implementations; Figure 20The contents of a pending load buffer at different stages are illustrated schematically in a valid example of a few exemplary specific implementations; Figure 21 This is a flowchart illustrating a method for performing data processing operations according to some exemplary specific implementations; Figure 22 The diagram schematically illustrates a sequence of instructions including a first instruction according to some embodiments, the first instruction defining each instruction in a set of subsequent instructions as either an execution instruction or an access instruction; Figure 23 The decoding circuitry in some implementation schemes is illustrated schematically; Figure 24 The data processing apparatus including a micro-operation cache is illustrated schematically in some embodiments; Figure 25 The diagram schematically illustrates a data processing apparatus including a register set in some embodiments; Figures 26A to 26C Three versions of the instructions according to the present technology are illustrated schematically in some exemplary embodiments; Figure 27 The decoding circuitry in some implementation schemes is illustrated schematically; Figure 28 This is a flowchart illustrating a series of steps taken by the decoding circuit according to some implementation schemes; Figure 29 This is a flowchart illustrating a series of steps taken by the decoding circuit according to some implementation schemes; and Figure 30 The illustration schematically shows a specific implementation of a simulator that can be used in some implementation schemes. Detailed Implementation

[0008] In at least one example of this document, there exists a data processing apparatus comprising: a publishing circuit for publishing instructions for out-of-order execution relative to an ordered sequence of instructions; a first instruction execution circuit and a second instruction execution circuit; and a decoupled access buffer, wherein the publishing circuit, in response to a type flag associated with an instruction, publishes an instruction for execution to the first instruction execution circuit when the instruction has a first type flag, and publishes an instruction for execution to the second instruction execution circuit when the instruction has a second type flag; wherein the instructions with the first type flag and the instructions with the second type flag originate from the ordered sequence; wherein when the instruction is an access-related instruction, the instruction has a first type flag, the access-related instruction being determined for execution according to memory... The instruction has at least one feature of loading an address-retrieval data value, wherein when the instruction is not an access-related instruction, the instruction has a second type flag; wherein the data processing device is arranged to prioritize the execution of an instruction with a first type flag by a first instruction execution circuit over the execution of an instruction with a second type flag by a second instruction execution circuit; and wherein the first instruction execution circuit is arranged to store a data value retrieved from memory as the result of the execution of the instruction with the first type flag in a decoupled access buffer, and the second instruction execution circuit, in response to the data value required to execute a pending instruction with a second type flag stored in the decoupled access buffer, retrieves the data value from the decoupled access buffer and executes the pending instruction.

[0009] Therefore, this technology proposes a configuration of a data processing apparatus based on a decoupled access / execution method. The apparatus receives a single instruction stream and internally divides the program into two streams, processed by a first instruction execution circuit and a second instruction execution circuit, respectively. The first instruction execution circuit is also referred to herein as an "access" component, and the second instruction execution circuit is also referred to herein as an "execution" component. These components operate largely independently of each other, and specifically, the apparatus is arranged such that the operation of the access instruction execution circuit takes precedence over the operation of the execution instruction execution circuit. That is, in cases where the apparatus supports out-of-order execution of instructions received in a single instruction stream, the corresponding operations of the access instruction execution circuit and the execution instruction execution circuit are intentionally configured to allow access instructions processed by the access instruction execution circuit to be executed before other execution instructions processed by the execution instruction execution circuit. In practice, one configuration of the apparatus could be to allow such access instructions to be executed as early as possible relative to execution instructions.

[0010] This technique associates a first-type ("access") flag with an instruction when it is "access-related," meaning that the instruction defines at least one characteristic of the load operation. Therefore, it should be noted that not only is the load instruction itself an access instruction, but any other instruction that defines at least one characteristic of the load operation is also an access instruction. For example, if the load instruction defines the memory address at which a load should occur, as defined by a value held in a specified register, then a previous instruction that stores that value in the specified register is also an access instruction. Furthermore, for example, if a previous instruction that stores that value in the specified register does so by modifying the contents of another register, then an earlier instruction that provides that value in that other register is also an access instruction, and so on. This approach recognizes that, in order to perform the memory access specified by the load instruction, all those previous instructions must have already been executed. Therefore, in order to prioritize the execution of the load instruction, those other previous instructions themselves must also be prioritized. According to this technique, an instruction whose characteristics are not determined is an "execution" instruction. In fact, according to one method of marking instructions according to this technique, an instruction can be simply identified as an "execution" instruction by the fact that it is not marked as an "access" instruction.

[0011] This approach particularly recognizes the fact that latency associated with memory access can have a significant impact on the timescale of instruction execution and processing within a device. However, it should be noted that the technique proposed in out-of-order processors further reduces the impact of memory access latency than conventional techniques. For example, with a sufficiently large instruction window, load instructions can be executed well in an out-of-order processor before the values ​​actually needed to be read from memory via these load instructions. If these loads (which are dispatched early) result in cache misses, then the latency of memory access is effectively “hidden” because the processor can execute other instructions between dispatching the load and subsequently executing instructions based on the result of that load. Therefore, this reordering mechanism has certain benefits if the processor can overlap memory accesses with instruction execution. However, if there are instructions that depend on data that has not yet been “loaded” using critical resources (but have not made progress), the effective look-ahead execution depth can be significantly smaller than the actual instruction window.

[0012] However, this technique also supports further advance execution of load and load-related instructions by prioritizing the execution of access instruction sequences within a dedicated set of execution circuits for executing that type of instruction, and by separating these instructions into a separate set of execution circuits to defer the execution of the instruction sequences. These two sets of instruction execution circuits operate substantially independently of each other, and therefore, at least in this respect, there may be no constraint on how these instruction execution circuits execute the corresponding instructions. Thus, two instruction strings (access and execution) originating from a single stream of programming instructions can be executed out of order, not just relative to each other.

[0013] However, these two sets of instruction execution circuits are associated by providing a decoupled access buffer. The access instruction execution circuit stores data values ​​retrieved from memory into this decoupled access buffer, and the execution instruction execution circuit can read the data values ​​needed to execute one of its own pending instructions from this decoupled access buffer. This internal buffer between the access and execution units is managed by hardware and is transparent to the software. Therefore, it should be noted that this technique does not require software involvement (and specifically, the movement of data values ​​between the access and execution units does not require explicit coordination by software). For example, there is no need for software-visible queues and source code transformations via compilers or programmers, making the transfer between the access and execution parts explicit.

[0014] Decoupled access buffers can also be advantageously located closer to where their contents are needed (e.g., instruction execution circuitry), thus reducing latency not only by bringing data closer to the CPU but also increasing the bandwidth of that data access. Access to this internal buffer can have higher bandwidth (in terms of the number of different items that can be accessed in a loop) compared to reading from the L1 data cache. This is because the internal DAB buffer can be provided as a smaller structure than a regular cache, and therefore the internal DAB buffer can have more access ports without becoming overly complex.

[0015] It should also be noted that while there is some overlap between the benefits of this technique and those achieved through "prefetching," this is not limited to the prefetching techniques disclosed herein. Typically, prefetching can be used to reduce cache misses by placing specific data into the cache before it is needed. Therefore, a prefetcher can be employed that observes memory access patterns and uses past accesses to predict future accesses. However, various issues can limit the benefits achievable through prefetching. For example, the prefetcher requires an initial training period to lock onto patterns. The next question is how much to prefetch. If too little prefetching is performed, cache misses will still occur frequently. If too much prefetching is performed, this can lead to cache pollution problems (i.e., prefetched data evicts data that is still needed). Furthermore, it can be difficult to determine when the prefetcher should operate under a specific identified memory access pattern.

[0016] Because the "early" operation of the processor's access unit is entirely defined by a single stream of programming instructions, this technique does indeed also bring data closer to the processor's functional unit (or a higher level in the memory hierarchy). However, unlike prefetching, it may generate more useful traffic because the operation is more closely aligned with the operation the processor is actually performing. Therefore, it is considered that executing the (entire) single stream of programming instructions requires all the data that needs to be placed in the decoupled access buffer via the access operation. Thus, the problems caused by an overactive prefetcher putting "useless" prefetched data into the cache (leading to the eviction of more useful data) are irrelevant here. Over-prefetching can also cause significant problems in multiprocessor systems because excessive bandwidth consumed by one or more processors can make it more difficult for other processors in the system to make positive progress without appropriate fairness strategies.

[0017] In fact, this technique can even support improved prefetching because it allows more accesses to be seen together in a merged “batch,” thus enabling the prefetcher (if it exists in the system) to be trained more promptly.

[0018] According to this technology, instructions can be labeled in various ways. For example, in some embodiments, the data processing apparatus further includes an instruction dependency determination circuit that associates a first-type label with the instruction being determined when the instruction being determined is a load instruction, and performs a dependency chain determination process to attempt to find a dependency chain including the instruction being determined, wherein when a dependency chain leading to the load instruction is found, the first-type label is associated with the instruction being determined. Therefore, providing an instruction dependency determination circuit gives the data processing apparatus the ability to identify the "first-type" (access) instruction itself based on the identification of the dependency chain leading to the load instruction. Any instruction forming part of such a dependency chain is an access instruction. Therefore, by using its instruction dependency determination circuit, the data processing apparatus can label the instructions of the received instruction stream itself, meaning that it is not necessary to receive a received instruction stream that has already been labeled.

[0019] Instruction dependency determination circuitry can take various forms, but in some implementations, the data processing apparatus further includes register renaming circuitry that includes a rename table for storing temporary associations between schema registers specified in an instruction and physical registers for holding temporary copies of data values. The instruction dependency determination circuitry is arranged to perform a dependency chain determination process using the contents of this rename table. The rename table (also used in out-of-order processors to store associations between schema registers and physical registers) provides various aspects of instruction dependency identification (e.g., because once an instruction has been renamed, other instructions interacting with the same schema register (in the program) must be identified and directed to the physical register whose schema register has been renamed). Therefore, instruction dependency determination circuitry can advantageously be associated with register renaming circuitry, and especially with the rename table maintained by register renaming circuitry.

[0020] The instruction dependency determination circuit can also use various other information available in the data processing apparatus to perform the dependency chain determination process. For example, in some embodiments, the data processing apparatus further includes: a decoding circuit for receiving an ordered sequence of instructions and performing decoding operations, wherein at least some of the decoding operations result in the instructions being divided into more than one micro-operation definition, wherein these micro-operation definitions are received by a issuing circuit; and a micro-operation cache for receiving and temporarily storing the micro-operation definitions issued by the issuing circuit, thereby eliminating the need for decoding due to the recurrence of instructions that derive the micro-operation definitions, wherein the instruction dependency determination circuit is arranged to perform the dependency chain determination process using the contents of the micro-operation cache. The contents of the micro-operation cache represent a useful body of instruction-related information within which various associations and dependencies between instructions can be quickly identified (e.g., by referencing the matching target and source registers of micro-operation pairs), and therefore, when the instruction dependency determination circuit is arranged to perform the dependency chain determination process using the contents of the micro-operation cache, an efficient configuration of the instruction dependency determination circuit can be provided.

[0021] However, other exemplary embodiments are possible in which an external agent provides the data processing device with information about which instructions in a received instruction stream are of "first type" and which are of "second type" (access or execution). This information can be provided in various ways, but in some embodiments, the data processing device further includes decoding circuitry for receiving an ordered sequence of instructions and performing a decoding operation. In response to an instruction type classification instruction in the ordered sequence, the decoding circuitry associates one of a first type tag and a second type tag with each instruction in the subset of the ordered sequence, based on a tag type definition specified in the instruction type classification instruction for that subset. Therefore, the present technology also proposes an instruction type classification instruction that enables a programmer to define whether each instruction in a particular set of instructions (e.g., a limited number of instructions following it) has a first type or a second type, and in response, the decoding circuitry then applies a first type tag or a second type tag to each instruction in that set.

[0022] In some implementations, while execution of a first type of instruction by the first execution circuit is in progress, the second instruction execution circuit can enter an inactive state in which no second type of instruction execution occurs. Given the fact that the execution of access instructions takes precedence over the execution of execution instructions, there may even be operational periods during which the execution circuit may make almost no positive progress before some results of the access instruction execution are available (i.e., already stored in the decoupled access buffer). Therefore, although execution of the first type of instruction by the first execution circuit continues, entering an inactive state by the second instruction execution circuit can achieve power savings during certain operational periods of the data processing device.

[0023] In some embodiments where the second instruction execution circuit depends on the result of the first type of instruction execution performed by the first execution circuit, as described above, the second instruction execution circuit exits the inactive state and continues to perform the second type of instruction execution in response to an activation signal from the first instruction execution circuit.

[0024] The triggering event for reactivating the second instruction execution circuit can take various forms, but in some implementations, the first instruction execution circuit issues an activation signal to the second instruction execution circuit in response to the occupancy of the decoupling access buffer. This can be, for example, a binary triggering event, where the second instruction execution circuit enters its inactive state when the decoupling access buffer is completely exhausted, and returns to the active state when the decoupling access buffer has been refreshed.

[0025] However, in some implementations, the first instruction execution circuit issues an activation signal to the second instruction execution circuit in response to the decoupling access buffer occupancy exceeding a threshold occupancy. Therefore, this threshold occupancy can be effectively and flexibly limited according to specific system performance requirements.

[0026] The second instruction execution circuit can be configured differently to allow it to receive instructions from an ordered sequence of instructions (identified as having a second type of tag), and may also not execute those instructions for a certain interval (while other first type of instructions continue to proceed in the first type of instruction execution circuit). In some embodiments, the second instruction execution circuit includes an execution cache for storing instructions issued to the second instruction execution circuit by the issuing circuit before instruction execution begins. Thus, these “independent” instructions (i.e., those that terminate outside all dependent chains of loading in the program’s data flow graph) can be stored in the execution cache until the data required for their continuation is fetched from memory. These instructions can, for example, be effectively kept in a compact “passive” form (i.e., not fully unpacked / expanded) until they need to continue further, thereby limiting the required storage capacity.

[0027] The second instruction execution circuit can take many forms and can be provided in virtually any form that executes the types of instructions received by the second instruction execution circuit. However, in some embodiments, the second instruction execution circuit includes a reserved station circuit for supporting register renaming operations for out-of-order instruction execution, wherein the reserved station circuit is arranged to receive data values ​​from a decoupled access buffer. Thus, the reserved station circuit represents a useful component of the second instruction execution circuit providing the connection from the decoupled access buffer, and existing mechanisms of the reserved station circuit (e.g., for reordering instructions based on dependencies) can be effectively utilized when data values ​​are introduced from the decoupled access buffer.

[0028] This technology also recognizes that, in certain circumstances, operational aspects of the second instruction execution circuitry related to memory operations may require careful handling. For example, in some embodiments, the second instruction execution circuitry includes a memory cell that temporarily holds an entry containing a data value to be stored into memory, and the means are arranged to identify entries in a decoupled access buffer, wherein the load address of the entry whose data value is loaded by an executed load instruction matches the memory address of the entry in the memory cell for the memory instruction being executed; and are arranged to determine that a conflict condition is true when the memory instruction precedes the load instruction in an ordered sequence of instructions. For example, the memory buffer may temporarily hold write data that will not leave the memory buffer until the memory is “committed.” This technology recognizes that, particularly where the execution of the load instruction by the second instruction execution circuitry can occur at a considerably “early” time, there is a possibility that a newer memory instruction may overtake an older load instruction at the same address (and therefore a possibility of a read-before-write error). Therefore, identifying such conflict conditions allows for remedial measures to be taken before such data hazards occur.

[0029] In some implementations, the apparatus, in response to a conflict condition, refreshes the load instructions and any subsequent instructions from the ordered instruction sequence in the first and second instruction execution circuits. Thus, the load instructions and all subsequent instructions can be refreshed. However, in some implementations, the apparatus, in response to a conflict condition, refreshes the load instructions and any subsequent instructions that directly or indirectly depend on the ordered instruction sequence in the first and second instruction execution circuits. These techniques ensure that data hazards are avoided and that the processed data is not contaminated. Furthermore, some implementations will achieve more selective refreshing, and some will achieve more complete refreshing. In some implementations, for example, the apparatus, in response to a conflict condition, refreshes the load instructions and any instructions in the first and second instruction execution circuits determined to depend on the load. In other words, it does not distinguish between new and old / ordered instructions; this is a more sluggish approach (potentially refreshing more instructions), but simpler to implement. In contrast, in other implementations, partial refreshing can be implemented, refreshing only those instructions determined to be potentially affected by data hazards, which causes less interference with ongoing processing, although it requires more detailed tracking of relevant instructions.

[0030] As described above, the tags can be provided differently, but in some embodiments, a first type of tag includes a first predefined flag associated with an instruction, and a second type of tag includes a second predefined flag associated with an instruction. In some embodiments, a first type of tag includes a first predefined flag associated with an instruction, and a second type of tag includes a second predefined flag associated with an instruction.

[0031] In at least one example of this document, there is a data processing method comprising: issuing instructions for out-of-order execution relative to an ordered sequence of instructions; issuing instructions for execution to a first instruction execution circuit when the instructions have a first type flag, and issuing instructions for execution to a second instruction execution circuit when the instructions have a second type flag, wherein the instructions with the first type flag and the instructions with the second type flag originate from the ordered sequence, wherein when the instructions are access-related instructions, the instructions have the first type flag, the access-related instructions determining at least one feature of a load operation for retrieving a data value based on a memory address. Furthermore, when the instruction is not an access-related instruction, the instruction has a second type flag; the execution of the instruction with the first type flag performed by the first instruction execution circuit takes precedence over the execution of the instruction with the second type flag performed by the second instruction execution circuit; the data value retrieved from memory is stored in the decoupled access buffer as the result of the execution of the instruction with the first type flag performed by the first instruction execution circuit; in response to the data value required to execute the pending instruction with the second type flag stored in the decoupled access buffer, the data value is retrieved from the decoupled access buffer for the second instruction execution circuit and the pending instruction is executed in the second instruction execution circuit.

[0032] In at least one example of this document, there exists a data processing apparatus comprising: means for issuing instructions for out-of-order execution relative to an ordered sequence of instructions; a first means for instruction execution and a second means for instruction execution; a decoupled access buffer; means for issuing instructions for execution to the first means for instruction execution when an instruction has a first type tag, in response to a type tag associated with an instruction; and means for issuing instructions for execution to the second means for instruction execution when an instruction has a second type tag, wherein the instructions with the first type tag and the instructions with the second type tag originate from the ordered sequence, wherein when the instruction is an access-related instruction, the instruction has the first type tag, the access-related instruction determining at least one feature of a load operation for retrieving a data value based on a memory address. The instruction has a second type flag when it is not an access-related instruction; means for performing the following operations: prioritizing the execution of an instruction with a first type flag performed by a first means for instruction execution over the execution of an instruction with a second type flag performed by a second means for instruction execution; means for performing the following operations: storing a data value retrieved from memory as the result of the execution of an instruction with a first type flag performed by the first means for instruction execution in a decoupled access buffer; means for retrieving the data value from the decoupled access buffer for the second means for instruction execution in response to the data value required for executing a pending instruction with a second type flag stored in the decoupled access buffer; and means for executing the pending instruction in the second means for instruction execution.

[0033] Some specific implementation schemes will now be described with reference to the accompanying drawings.

[0034] Figure 1A The diagram illustrates a scenario that provides context in which the inventive technique is particularly relevant. The figure (on the left) shows a sequence of instructions comprising both access (A1, A2, etc.) and execution (E1, E2, etc.) instructions, received by a prior art processor in a single, interwoven stream as shown. Assume that access instruction A3 is a "load" instruction that provides the information required by execution instruction E1. If access instruction A3 triggers a cache miss, the sequence of execution instructions starting with E1 will be stalled until the memory system delivers the requested data. This has the additional disadvantage that the entire pipeline is subsequently filled with stalled execution instructions, limiting its look-ahead execution depth and ultimately forcing it to stall.

[0035] Figure 1BThis illustrates the applicability of the technique to the same context in which the processor receives the same sequence of instructions, including both access (A1, A2, etc.) and execution (E1, E2, etc.) instructions, according to the technique. Here, the pipeline shown belongs to the processor's "access" pipeline, and it can be seen that by prioritizing access instructions (processed in the access pipeline shown) and deferring execution instructions (E1-E3, which can be processed by the processor's "execution" pipeline (not shown)), the complete processor is able to execute more instructions during the time it spends waiting for data with access instruction E1. In fact, if the program's access section can detect another potentially long-latency event (e.g., a cache miss) while executing A6, the cost of the "miss" can be compensated, for example, by initiating a data access before the point at which the event would normally occur. It should be noted that the execution instructions are placed in a temporary storage area or cache ("E cache" in the figure) designed to remain passive for several loops until the data arrives.

[0036] Figure 2 A data processing apparatus according to some embodiments is schematically illustrated. A single set of "front-end" circuitry for retrieving and decoding an ordered sequence of instructions to be executed by the data processing apparatus is provided, the set including an acquisition circuit 101 and a decoding circuit 102. The decoded instructions are passed to a release circuit 103. According to the present technology, the release circuit 103 is arranged to identify a marker associated with at least some of the instructions in the received ordered sequence of instructions. Specifically, the release circuit 103, in response to the identification of an "access" marker associated with an instruction, releases the instruction to an access execution circuit 104 for execution. Conversely, instructions without an "access" marker are directed to an "execution" execution circuit 105 for execution. While there may be two explicit types of markers in some examples, in the illustrated example there is actually only an access marker. Therefore, instructions with this marker are directed to the access execution circuit 104, and conversely, any instructions without an access marker are directed to the execution circuit 105. The access marker is associated with all access-related instructions that determine at least one feature for a load operation to retrieve a data value based on a specified memory address. Figure 8A and Figure 8B The associated description illustrates the definition of access instructions according to this technology, wherein it can be seen that the access dependency graph includes all instructions leading to the terminal node representing the load instruction.

[0037] The access execution circuitry includes an execution section 106, which may be arranged, for example, in a pipelined manner. It should be understood that... Figure 2The schematic diagram is at a relatively high level of abstraction to provide an overview of the general principles of the construction of the data processing apparatus 100. However, it is particularly important to note that the loading unit 107, within the access execution circuit 104, delegates its loading operations, defined by the loading instructions executed by the execution section 106. This loading operation first accesses the L1 cache 108, which also forms part of the access execution circuit 104, and (if an access miss occurs) may further propagate the access to the L2 cache 109 (and possibly further to the memory system). Data values ​​returned from the memory system and / or cache hierarchy enter the L1 cache 108, and data values ​​returned from the cache subsystem are placed in the decoupled access buffer 110, which forms part of the access execution circuit 104. These values ​​may also be provided to the register 111, which the execution section 106 accesses as part of its data processing operations.

[0038] Instructions without an "access" flag are issued by the issue circuit 103 to the execution circuit 105. The received instructions are temporarily held in the instruction cache 112, allowing these instructions to be delayed while prioritizing the parallel execution of access instructions, which is then performed in the access execution circuit 104. The decoupled access buffer 110 is arranged to send certain signals about its contents to the execution circuit 104. Therefore, when a data item retrieved from memory via a load operation is available in the decoupled access buffer 110, this fact can be signaled to the execution section 113 of the execution circuit 105, which can then utilize the value when executing a specific instruction. The execution section 113 can also utilize the value held in register 111, and conversely, due to its own data processing operations, cause certain updates to the contents of register 111. In cases where the data processing of the execution circuit 105 depends on the processing performed by the access execution circuit 104, Figure 2 Another feature of the exemplary embodiment shown is a low-power state control circuit 114 that provides execution circuitry 105. When the decoupling access buffer 110 is depleted (becomes empty), the low-power state control circuit receives a notification from the decoupling access buffer 110, and in response, the low-power state control 114 causes execution circuitry 105 to enter an inactive low-power (or low-frequency operation) state. Conversely, when the decoupling access buffer 110 has content again, the low-power state control 114 can cause execution circuitry 105 to become active again (i.e., fully powered or operating at a higher frequency than before) and begin further instruction execution. While the execution circuitry 105 can be woken up in this way once any content is present in the decoupling access buffer 110, Figure 2In the example, the decoupled access buffer 110 signals the low-power status control 114 when its contents meet a predetermined threshold content (i.e., minimum content), thereby improving the power-saving advantages of operating the execution circuit 105 in this manner, and waking up the execution circuit to continue instruction execution only when a sufficient amount of data value is available in the decoupled access buffer 110. The specific level of this threshold can be set as a specific implementation detail according to system requirements.

[0039] Figure 3 This is a flowchart illustrating the sequence of steps taken according to a method based on some implementation schemes. Specifically, Figure 3 This diagram illustrates how instructions within a received instruction sequence are processed according to the present technique. The process begins at step 150, where the next instruction in the received instruction sequence is considered. At step 151, it is determined whether the instruction has a first type (“access”) marker. If it does, the process continues to step 152, where the instruction is issued to the access execution circuitry. Then, at step 153, the execution of the instruction is prioritized in out-of-order instruction execution performed by the access execution circuitry. Then, at step 154, when one or more data values ​​retrieved from the memory system are returned, the values ​​or such values ​​are stored in a decoupled access buffer. However, if at step 151, it is found that the instruction does not have a first type marker, the process continues to step 155, where the instruction is issued to the execution execution circuitry. Then, at step 156, as part of out-of-order instruction execution performed by the execution execution circuitry, the instruction is delayed (e.g., the instruction is held in an instruction cache or buffer). At step 155, execution of the instruction is initiated once the required data value for the instruction is available in the decoupled access buffer. For example, the presence of the required data value for the instruction in the decoupled access buffer can be used to trigger the execution of the instruction while the instruction is held in the instruction execution circuit. It should be noted that the dashed path from step 154 ​​to step 157 indicates that step 157 depends on actions generated by other paths, but this is not a true step in the illustrated procedural flow.

[0040] Figure 4An exemplary data processing apparatus 200 according to some embodiments is schematically illustrated. A single set of front-end circuitry 201 includes an instruction cache 202, a fetch circuit 203, a decode circuit 204, and a splitter 205. Thus, the received ordered sequence of instructions arrives at the splitter 205, which is then arranged to direct the instructions to either the access circuit 210 or the execution circuit 220 depending on whether the instruction has an associated “access” flag. When an instruction is passed to the access circuit 210, the first stage of this access circuit is shown as a micro-operation cache 211, a renaming circuit 212, a release queue 213, and a register fetch stage 214. These pipelined components are arranged in a manner familiar to those skilled in the art and not described in detail herein. Furthermore, depending on the nature of the instruction, corresponding signals are passed from the register fetch stage 214 to the integer ALU unit 216, the load unit 218, and / or the branch resolution (BR) unit 220. Therefore, it should be understood that the access circuit 210 is capable of executing various types of instructions (note that it is not limited to load instructions), and indeed as... Figure 2 The specific execution units 216 and 218 shown are merely examples, and other execution units may be provided. The result of branch resolution (as determined in BR unit 220) is passed back to fetch unit 203 and micro-operations cache 211. It should also be noted that data processing apparatus 200 is further provided with branch prediction unit 230, which interacts with the contents of micro-operations cache 211 and indicates to fetch unit 203 when it predicts that a branch will be taken and the corresponding jump in the fetched instruction should be implemented.

[0041] Integer ALU unit 216 performs its data processing operations relative to the values ​​held in the registers of access section 210, which may have been retrieved from the cache / memory system. The loading unit 218 performs the retrieval of these values ​​from memory (through a load operation). Figure 4 The interaction between these loading units and L1 cache 231 is illustrated, which forms part of a cache hierarchy including L2 cache 232. Additional cache levels leading to a memory system (not shown) may also be provided. Values ​​returned from the cache / memory system are stored in a decoupled access (DA) buffer 234. Referring to the aforementioned data processing operations of integer ALU unit 216, these results are also fed into access result cache 236, which the integer ALU unit 216 has access to as part of performing its data processing operations. Modifications performed on these values ​​are passed to commit queue 238 before being applied to register 240 of data processing device 200.

[0042] Instructions received in an ordered instruction sequence and without access markers are passed from splitter 205 to execution circuit 220. Specifically, these instructions are first received in X-scheduling cache 250, where they are held to delay execution relative to access instructions prioritized in access circuit 210. Execution instructions can be held in X-scheduling cache 250 in a compact pre-execution form (i.e., not fully unpacked and expanded as they will eventually be executed) to allow for compact provisioning of cache 250. Execution circuit 220 includes a reservation station 252 that enables the execution circuit to manage its own out-of-order instruction execution and, in particular, to continuously track instruction dependencies and operand availability. Execution circuit 220 also includes two integer ALU units 253 and two floating-point units (FPUs) 254, as well as two memory units 255. When executing its instructions, execution circuit 220 is therefore arranged such that it receives the values ​​required by ALU 253 and FPU 254 from reserved station 252 and transmits the results of data processing performed by these units back to reserved station 252. Execution circuit 220 also includes branch resolution (BR) unit 258, which, like BR unit 220 of access circuit 210, sends a signal notification to acquisition circuit 203 of front-end circuit 201.

[0043] Reserved station 252 passes the resulting value to the commit queue 238 of access circuit 210 to update the register value. The data value to be written to memory is passed from reserved station 252 to memory cell 255. The memory transaction initiated by memory cell 255 is temporarily buffered in memory buffer 256 of access circuit 210. This allows for buffering of write data until memory is "committed". This also provides a sliver of opportunity to identify cases where the address of a memory transaction matches the address of a load that has already brought the value to decoupled access buffer 234. Identifying updates that could lead to data hazards (i.e., conflicts between newer loads and older memory) allows for remedial actions, and will be referred to below. Figure 5 This feature will be discussed in more detail.

[0044] Figure 5 A data processing apparatus 300 is schematically illustrated in some exemplary embodiments. The data processing apparatus 300 includes a front-end circuit 301, which itself includes an acquisition circuit 302, a decoding circuit 303, and a publishing circuit 304. In the manner discussed above, the publishing circuit 304 identifies certain instructions (which have associated "access" tags) and publishes these instructions to the access circuit 305, while publishing other instructions to the execution circuit 306. Figure 5 based on Figure 4An example is provided, but not all components are shown, merely for the sake of clarity in this example. Instructions received by access circuitry 305 enter its execution pipeline 307, which performs various data processing operations, some of which involve interaction with register 308, and some of which cause load unit 309 to initiate a load transaction with the cache / memory system. Figure 5 The diagram shows only L1 cache 310. Data values ​​returned from the cache / memory hierarchy are passed to decoupled access buffer 311, and thereafter, some of these values ​​can cause updates to the values ​​held in register 308 (e.g., via various stages such as the commit queue—see...). Figure 4 ). Figure 5 The specific focus of the discussion is the provision of the conflict detection unit 312, which is described in more detail below. The execution circuitry 306 includes an execution cache 313, a reservation station 314, an ALU / FPU unit 315, and a storage unit 316. The execution circuitry 306 operates in a manner substantially similar to that described above for... Figure 4 The execution circuit 220 is described in the same manner and will not be repeated here for the sake of brevity. The conflict detection unit 312 also interacts with the storage unit 316 and is specifically arranged to identify situations that can lead to data hazards, namely, conflicts between newer load instructions prioritized in the execution performed by the access circuit 305 and older store instructions executed by the execution circuit 306. Data hazards can occur when these corresponding load and store operations involve the same memory address, i.e., in program order, the store should be performed before the load, but this order has been disrupted by the priority of load operations according to this technology. Furthermore, in cases where the store and load are already performed in separate, largely independent execution units (i.e., execution circuit 306 and access circuit 305), mechanisms that would typically prevent such data hazards within a separate out-of-order processing unit may be insufficient.

[0045] The following is for reference. Figure 6 and Figure 7 The specific manner in which the collision detection unit 312 operates is described in more detail. However, when such a data hazard is identified, the collision detection unit is arranged to signal this data hazard to various parts of the data processing apparatus 300, including the access execution pipeline 307 and the execution cache 313 / reservation station 314, because it will be necessary to refresh various instructions from the corresponding pipelines and re-execute some instructions. In some embodiments, the data processing apparatus 300 is arranged such that only the load instructions and any subsequent instructions are refreshed, but simpler embodiments assume that, due to the simplicity of implementation, a complete refresh of the corresponding pipeline is triggered when such a data hazard condition is identified.

[0046] Figure 6 The operation of the conflict detection circuit 312 relative to the contents of the memory cell 316 and the decoupled access buffer 311 is illustrated schematically. The memory cell 316 holds entries about storage transactions that are still "in flight," i.e., not yet committed. Various related information can be associated with each entry, although relevant to this discussion (e.g., ...). Figure 6 As shown in the example), but this information includes the value to be stored, the address where the value will be stored, and the instruction identifier (which is provided here by the Reorder Buffer (ROB) ID). The decoupled access buffer 311 also includes various information related to the entries it holds, in Figure 6 In the example, this information is shown as the address of the retrieved value, the value itself, and the instruction identifier associated with the load operation, which is in Figure 6 The example also uses the ROB ID. As is known to those skilled in the art, out-of-order execution pipelines, such as those... Figure 4 The out-of-order execution pipeline provided by the example access circuit 210 and execution circuit 220 utilizes such reordering buffers and ROB IDs to maintain the program's knowledge of the order in which it executes instructions, so that even though they perform out-of-order execution, the effects of the instructions can be correctly ordered when the results are submitted. Conflict detection circuit 312 is arranged to monitor the corresponding contents of memory cell 316 and decoupled access buffer 311 and identify instances of address matching between entries. This can be performed, for example, by a cyclical check of entries in one of them (e.g., DAB 311)—in turn, obtaining the address of each entry and checking for a matching entry in the other (e.g., memory cell 316). When a pair of address matches is found, the corresponding order of the instructions is determined by referring to the ROB ID, and when a data hazard (“conflict”) is thus identified, the conflict detection circuit causes a flush. This flush can be a full pipeline flush or a partial pipeline flush.

[0047] Figure 7The sequence of steps that can be operated according to the conflict detection circuit 312 is illustrated. At step 400, the next entry in the decoupled access buffer is checked. At step 401, it is then determined whether an entry with the same address exists within the execution memory cell. If not, the flow returns to step 400 to check the next entry in the decoupled access buffer. However, if a matching address exists, the flow continues to step 402, where it is determined whether the memory cell entry (in program order) was loaded before the value was brought into the decoupled access buffer (DAB). If this is not the case, the flow returns to step 400 to check the next entry in the decoupled access buffer. However, if this is the case, a conflict condition has been identified, and at step 403, the load instruction itself is compressed and any subsequent instructions in the access and execution circuitry are refreshed to avoid the erroneous side effect of the load and store operations being reversed. In other embodiments, the execution portion of the pipeline is refreshed such that only instructions that directly or indirectly depend on the compressed load instruction are also compressed, while the rest of the pipeline remains unchanged. Then, the process returns to step 400.

[0048] The following are exemplary sequences of instructions that the data processing device can receive and execute: I1:[E]SUBx10, x11, x10 I2:[A]ADDx1, x2, x3 I3:[A]SUBx4, x1, x2 I4:[E]CLZx13, x2 I5:[A]LSLx4, x4, #1 I6:[E]MADDx14, x10, x11, x13 I7:[A]ADDx8, x3, x9 I8:[E]CMPx14, #39 I9:[A]EORx5, x4, x6, LSR #5 I10:[A]LDRd0, [x5, x8, LSL #3] I11:[E]FMSUBd1, d2, d0, d3 I12:[E]FCSELd2, d1, d5, GT I13:[E]STRd2, [x12], #4 Given the instruction sequence shown above, and assuming that Loaded Instructions (LDRs) are defined as "instructions of a predetermined type," the labeling of instructions depends on the analysis of data dependencies between instructions. These dependencies are... Figure 8A and Figure 8B This is illustrated graphically. Here, any instruction that provides a value to the source operand of a load instruction is considered an "access" instruction, and any instruction that provides a value to the source operand of an "access" instruction is itself considered an access instruction. Instructions not labeled as access instructions are considered execution instructions because they are found not to be part of the access data dependency graph. Therefore, as... Figure 8A As shown, instructions I10, I7, I9, I5, I3, and I2 in the access data dependency graph are given the access marker "A". The remaining instructions (which do not directly or indirectly cause "loading") are marked as execution (E), including I13, I12, I11, I8, I6, I14, and I1. This technology relates to identifying such data dependency graphs for sequences of instructions received by a data processing device, and specifically, as will be described in more detail below with reference to the figures below, this technology provides an apparatus and method that allows a data processing device to carefully construct such access data dependency graphs and mark their constituent instructions with "access" markers (this is executed online, i.e., executed on the spot as the data processing device receives and executes the instructions).

[0049] Figure 9A data processing apparatus according to some embodiments is schematically illustrated. As shown schematically, the data processing apparatus 500 includes an acquire / decode stage 501 that acquires and decodes instructions in a sequence of instructions to be executed by the data processing apparatus. These decoded instructions are stored in an instruction store 502, from which a remapper circuit 503 accesses these decoded instructions and performs any required remapping of the instruction-specified registers. Depending on the remapper stage, instructions are passed to either a release circuit 504 or a release circuit 505. The release circuit 505 releases instructions for execution by an execution circuit 506, while the release circuit 507 releases instructions for execution by an execution circuit 507. These parallel pipelines are also aggregated in a final commit stage 508. A register writer store 510 accessed by the remapper circuit 503 is also provided, where entries are created by the remapper circuit 503. Entries 511 in the register writer store 510 include instruction indicators and register indicators. Specifically, for each instruction encountered by the remapper circuit 503, the remapper circuit creates an entry in the register writer storage device 510 that indicates the instruction and its destination register (i.e., the register whose contents are written by the instruction). It should be noted that, for out-of-order processors, the registers mentioned in entry 511 of the register rewriter storage device 510 are physical registers (in this case, the remapper 503 is a renaming phase arranged to manage the mapping between the schema registers mentioned in the instruction and the physical registers of the data processing device). Conversely, for ordered processors, the registers mentioned in entry 511 of the register rewriter storage device 510 can be schema registers (i.e., as mentioned in the instruction). It should be noted that some instructions may have more than one destination register, and therefore multiple entries 511 may be created in the register rewriter storage device 510 in response to a single instruction.

[0050] Figure 9 The data processing apparatus 500 also includes an instruction tagging queue 512, an instruction tagging circuit 513, and an instruction tag storage device 514. The instruction tag storage device 514 is provided in association with an instruction storage area 502, such that instructions in the instruction storage area 502 can be associated (or not associated) with tags stored in the instruction tag storage device 514. In practice, in some embodiments, the instruction storage area 502 and the instruction tag storage device 514 can be combined into a single storage unit, where tags are stored directly associated with instructions. However, in other embodiments, the instruction storage area 502 is absent, and the instruction tag storage device 514 operates by receiving tags generated by the instruction tagger 513 and providing these tags directly to the front end of the processor (described below). Figure 15B(This type of implementation is illustrated schematically.) The instruction labeling circuit 513 operates by acquiring the identifier of the next instruction queued in the instruction labeling queue 512 and writing it into the instruction label storage device 514 to indicate that the instruction is "labeled". For example, when it is necessary to classify instructions as "access" or "execute" as described above, the label of the instruction indicates that the instruction is a defined "access" instruction (while unlabeled instructions are interpreted as "execute" instructions).

[0051] In addition to storing tags in instruction tag storage 514, instruction tagger 513 also determines whether an instruction has any producer instructions. Producer instructions are those instructions that generate at least one source operand of an instruction. Therefore, based on the specified source register for the current instruction, instruction tagger 513 refers to register writer storage 510 to determine whether any entries indicating that register or these registers are stored therein. When this is the case, the corresponding instruction identifier from the entry in register writer storage 510 is added to instruction tagging queue 512. Thus, a data dependency chain or data dependency graph leading to an instruction of a predetermined type (in this exemplary embodiment, a load instruction) can be identified, and each instruction in that data dependency chain or data dependency graph can be tagged. Note also the path from remapper 503 to instruction tagging queue 512. This is used to initiate the process by inserting the load instruction identifier of any encountered load instructions into the instruction tagging queue. Therefore, instruction tagger 513 receives instruction identifiers from instruction tag queue 12, which are written into the queue through previous iterations (where instruction tagger 513 identifies producer instructions in register writer storage device 510 and causes the producer instructions or those producer instructions to be added to the instruction tag queue), or are inserted into the instruction tag queue by remapper 503 when a load instruction is encountered.

[0052] Figure 10 This is a flowchart illustrating the sequence of steps taken according to a method based on some implementation schemes, which specifically describes... Figure 9In this example, the operation of components such as remapper 503 in the data processing apparatus 500 is illustrated. The process can be considered to begin at step 550, where the component encounters the next instruction in the sequence of instructions being executed by the data processing apparatus. At step 550, it is determined whether the instruction is written to the destination register. If not, the process loops itself to consider the next instruction in the sequence. However, if it is, the process continues to step 551, where an entry associated with the destination register and the instruction is created in the register write storage. Next, at step 552, it is determined whether the instruction has a predetermined type. For example, this could be a determination of whether the instruction is a load instruction. If not, the process returns to step 550. If it is, the process continues to step 553, where the instruction (i.e., its identifier) ​​is added to the instruction tagging queue. Then, the process returns to step 550.

[0053] Figure 11 This is a flowchart illustrating a sequence of steps taken according to some implementation schemes, specifically those steps performed to label instructions, such as those that can be... Figure 9 The steps performed by the instruction tagging circuit 513 of the data processing device 500 are as follows. The process can be considered to begin at step 600, in which the next instruction is received from the instruction tagging queue. Then, at step 601, an entry is created in the instruction tag storage device, thereby "tagging" the instruction, where the association between the instruction and its tag forms the entry in the instruction tag storage device. Then, at step 602, it is determined whether the instruction has one or more producer instructions, i.e., whether at least one source operand of the instruction is given by the contents of a register that has been written to by another instruction. (Refer to the above...) Figure 9 This can be performed, for example, via reference register writer storage device 510 and the entries stored therein. If an instruction does not have any producer instructions, or if a producer is not available in instruction storage area 502, or if a producer instruction has already been previously tagged, the process returns to step 600 to process the next instruction in the instruction tagging queue. However, when one or more producer instructions are identified, the instructions in these producer instructions are added to the instruction tagging queue at step 603, and then the process returns to step 600.

[0054] Figure 12A data processing apparatus 700 according to some embodiments is schematically shown. The fetch circuit 701 and decode circuit 702 operate to retrieve the sequence of instructions to be executed from memory and decode them. This can be further subdivided into micro-operation cache 703, which fills the micro-operations with the decoded instructions. The next pipeline stage is a renaming circuit 704. The data processing apparatus 700 is arranged to perform out-of-order instruction execution, and therefore performs renaming of the physical register architecture to support this operation. Thereafter, depending on whether the given instruction is marked "A" (i.e., access instruction) or "E" (i.e., execute instruction), the given instruction is passed to one of the two execution pipelines shown. The "execute" pipeline... Figure 12 The process is schematically represented by the release phase 705, register read phase 706, execution phase 707, and completion phase 708. The final commit phase 709 is shared with other pipelines. Other "execution" pipelines... Figure 12 The data processing device 700 is schematically represented by a release phase 710, a register read phase 711, an execution phase 712, a memory access phase 713, and a completion phase 714. It should be noted that the access pipeline also has a memory access phase 713 that runs parallel to the execution phase 712. Access instructions labeled "A" processed by the access pipeline take precedence over instructions executed by the execution pipeline. Therefore, the data processing device 700 can be, as described above, relative to... Figures 1A to 7 This is a decoupled access execution processor of the aforementioned type. Therefore, the self-tagging capability allows this decoupled access execution processor to receive untagged instruction streams and add tags during flight.

[0055] Figure 12The diagram illustrates two storage units, both of which the renaming circuit 704 has access to. The first storage unit is the register write storage 720, and the second is the associated instruction storage 725. For each instruction processed by the renaming phase 703, if the instruction generates a result value stored in a register, the physical register is assigned as the destination register, and a new mapping is performed between the schema register (specified in the instruction) and the physical register. The renaming phase 704 also records the identifier of the instruction responsible for writing to that physical register in entry 721 of the register writer storage 720. Some instructions may have more than one destination register, and therefore multiple mappings can be generated in the renaming phase 704. Furthermore, when a single instruction is responsible for writing to several physical registers, several corresponding entries are generated in the register writer storage 720. When the source operand register is renamed, the renaming phase 704 queries the register writer storage 720 to create content for the associated instruction storage 725. Identifying the instructions written to the source operand register of the current instruction enables the renaming stage 704 to associate these "producer" instructions with the current instruction. Therefore, information obtained from the register writer storage device reveals one or more "producer" instructions that are written to the source operand register of the current instruction. Consequently, each entry 726 in the associated instruction storage device 725 provides a list of other instructions that produce at least one data value consumed by the current instruction.

[0056] The data processing apparatus 700 also includes an instruction labeling queue 730, which precedes a write buffer 731. Providing the write buffer 731 allows for potential speed differences in the operations of the renaming stage 704, the instruction labeler 732, and the instruction labeling queue 730. When the renaming stage 704 encounters an instruction of a predetermined type (in this example, a load instruction), it inserts an identifier for that load instruction into the write buffer 731. This is a mechanism for initiating the carefully crafted process of a data dependency graph, as the load instruction (in this example) is the terminal node of the data dependency graph. The instruction labeler 732 receives instruction identifiers from the instruction labeling queue 730. In the example shown, four parallel instruction labelers are provided, each receiving an instruction identifier from the instruction labeling queue 730. For each instruction identifier retrieved from the instruction tagging queue 30 by one of the instruction taggers in the set of instruction taggers 732, the instruction is written into the access / execution (A / E) tag cache 733, wherein, in this exemplary embodiment, the location in the cache corresponds to the instruction identifier, and bits are written to indicate that the instruction is tagged as an access instruction. The instruction tagger also uses the current instruction identifier to look up the associated instruction storage device 725, and when a corresponding entry is found, reads one or more instruction identifiers designated as producers in that entry. The instruction identifiers of these producer instructions are sent to the instruction tagging queue 730 via write buffer 731 for processing.

[0057] Figure 13A The associated instruction storage device (such as...) is shown. Figure 12 The example content of the associated instruction storage device 725 in the example, where such a structure is referred to here as a "traversal table". The content of the traversal table corresponds to the exemplary instruction sequence described above, and the data dependency graph is in Figure 8A and Figure 8B As shown in the image. Therefore (with) Figure 8A In comparison: I2 is listed as a producer instruction for instruction I3; I3 is a producer instruction for instruction I5; I5 is a producer instruction for instruction I9; and instructions I7 and I9 are producer instructions for instruction I10. It should be noted that instruction I10 is a load instruction and is therefore the terminal node of the data dependency graph.

[0058] Figure 13B A register writer storage device (such as...) is shown. Figure 12 An exemplary content of the register writer storage device 720, referred to in this figure as the "last writer table". It should be understood that the specific physical register mapped to by the architecture registers specified in the instructions depends on the specific configuration of the renaming phase and the availability of the physical registers when these instructions are encountered. Therefore, Figure 13B This is merely a sample printout of a specific, exemplary content from the final writer table. From Figure 13B As can be seen, at the indicated sampling point, instruction I5 is the "last writer" for physical register 26, and instruction I9 is ​​the last writer for physical register 28. Physical registers 25 and 27 can currently be mapped to architecture registers, and there are currently no valid "last writer" instructions, so they are marked with "-".

[0059] Figure 14A and Figure 14B An exemplary configuration of the instruction tag storage device and some exemplary contents of each instruction tag storage device are shown. Figure 14A In an exemplary implementation, the instruction tag storage device is arranged to store entries associated with instruction identifiers, tags, and "unprocessed" indicators. Therefore, for any given instruction, it can be determined whether a corresponding entry exists in the instruction tag storage device, and specifically, whether the instruction has been tagged. The unprocessed flag is used to prevent certain instructions from being placed in the instruction tagging queue. For example, in... Figure 12 In this implementation, this prevents the renaming phase 704 from placing instructions, along with the loads already processed by the tagging unit (thus, by being tagged in this way, it does not need to trigger a new data dependency graph fabrication process), into the write buffer 731. Additionally, it should be noted that... Figure 14A The table for I20 has an unprocessed flag instead of an "A" label. This unprocessed flag can be stored in association with some instructions that are known a priori not to be access instructions, such as branch instructions and storage in the absence of register write-back. It should be noted that if the "Access" label is set, it is not actually necessary to explicitly set the "Unprocessed" flag, because setting the access label also prevents instructions from being added to the instruction labeling queue.

[0060] Figure 14B An alternative embodiment of the instruction tag storage device is shown, wherein this example is referred to as an A / E cache, which can correspond to Figure 12 The example is the A / E tag cache 733. This is a particularly compact structure that requires storing only a limited amount of information because instruction identifiers are mapped to specific cache locations, and bits are stored at those locations to indicate that the instruction mapped to that location is marked as an access instruction. An "unprocessed" bit can also be indicated in a similar way, with the bit stored at the location mapped to by the body instruction. It should be noted that some instructions are marked as unprocessed rather than "accessed," such as branch instructions and the above example of storage in the absence of register write-back.

[0061] Figure 15A and Figure 15BThis schematically illustrates a configuration that allows tagging information to be removed from the instruction tag storage area but retained for future use. Figure 15A The diagram illustrates an example where the decoding stage 800 passes decoded instructions to the micro-operations cache 801, where the cache itself is provided with tagging information, and where this tagging information is access / execution tagging information (e.g., bits indicating whether the instruction is an access instruction). The remapper stage 802 retrieves the instructions from here. This configuration also includes two levels of instruction cache hierarchies 803 and 804, which are also arranged to store instruction information with associated tagging information. Therefore, if an instruction is evicted from the micro-operations cache, its associated tagging information can be sent to these additional levels of instruction cache hierarchies, meaning that this information can then be loaded back into the micro-operations cache at a later time without having to perform the tagging process (and data graph fabrication process) again.

[0062] Figure 15B The diagram schematically illustrates the front-end circuitry 810 preceding the processor's execution pipeline 811. Specifically, this is an implementation where no micro-operations cache exists, but an associated instruction tag cache 812 (which receives tag information from tagging circuitry such as the tagging circuitry described above) provides this tag information directly to the processor's front-end circuitry 810 to associate it with passing instructions. If the instruction tag cache 812 becomes full and entries are evicted, these entries can be sent to other levels of instruction caches 814 and 815. When the same instruction is encountered again, the tag information can be carried into the processor along with the instruction; however, it is not necessary to regenerate the tag information (and repeat the data graph fabrication process).

[0063] Figure 16 The apparatus 10 in some embodiments is illustrated schematically. Apparatus 10 includes various components related to the processing of load requests in a data processing apparatus, which may be, for example, the one referenced above. Figure 2 , Figure 4 and / or Figure 5 One of the data processing devices in the aforementioned data processing apparatus. For example, in... Figure 16 As can be seen from this, the only components shown here are those related to the processing of load requests, and those skilled in the art will generally understand the context of such a device and can incorporate such load processing circuitry. Figure 2 , Figure 4 and / or Figure 5 In the example. Figure 16An incoming load request is shown received by address generation circuitry 110, which is configured to generate the address required for the corresponding load request. It should be noted that the address generation circuitry can be a dedicated arrangement of circuitry for generating addresses, or it can also be provided by a conventional arithmetic logic unit (ALU) capable of performing integer arithmetic related to address generation. In the latter case, in one embodiment, the decoder can divide the load instruction into two separate micro-operations: one micro-operation performs address calculations derived from the specific addressing mode used, and the other micro-operation performs the actual access specified by the "load" instruction. In this case, once the address generation micro-operation has been performed, the "resolved" address of the "load" instruction is written. Figure 16 The "Pending" Load Buffer (PLB) is shown. It should also be noted that requests may arrive at this buffer out of sequence. Load requests arrive at the Pending Load Buffer (PLB) circuit 120, which in this example is arranged as a FIFO buffer, and therefore, in Figure 16 In the illustration, individual pending load requests can be considered to enter at the top of PLB 120 and progressively enter the dual-track system through the indicated positions, eventually exiting and being passed to coalescing circuit 130. Of course, physical movement of entries in the FIFO typically does not occur; instead, this positional progression is handled by referring to the identifier of each entry. In one function, coalescing circuit 130 forwards load requests from PLB 120 to load processing circuit 140, allowing these load requests to be executed and the corresponding data items, which constitute their bodies, to be retrieved from the memory system. Figure 16 The illustration only explicitly shows the L1 cache 160 of the memory system. However, the coalescing circuit 130 also plays another role in the system, namely, determining whether at least two pending load requests are related to memory addresses that are sufficiently close to each other so that loading processing efficiency can be improved by coalescing these at least two pending load requests into a single load request, based on the pending loads held in PLB 120. This efficient proximity of the corresponding memory addresses is referred to herein as existing when the "address proximity condition" is met. Although this address proximity condition may be defined differently depending on the specific implementation of this technology, Figure 16In the example, this address proximity condition is defined with reference to L1 cache 160, specifically with reference to its cache line size. In other words, coalescing circuit 130 examines the memory address of a pending load assigned to be buffered in PLB 120 and determines whether at least two pending load requests relate to the same cache line. If so, those at least two pending load requests are coalesced by coalescing circuit 130. Part of this action of coalescing circuit 130 includes suppressing the forwarding of all pending load requests except for one of the at least two pending load requests found to satisfy the “address proximity condition” defined by the cache line size. The feedback path from coalescing circuit 130 to PLB 120 is schematically illustrated here. Furthermore, coalescing circuit 130 also generates a corresponding signal that is transmitted to de-coalescing circuit 150. When load processing circuit 140 has triggered a retrieval of data from the memory system (e.g., from L1 cache 160), the data is passed to de-coalescing circuit 150. By receiving a signal from the coalescing circuit 130, the decoupling circuit 150 knows that not only should the data item specified by the load request executed by the load processing circuit 140 be passed as a requested data item, but also the data item specified by at least one other pending load request (whose forwarding to the load processing circuit 140 is suppressed by the coalescing circuit 130) should be extracted and passed as at least one other requested data item. For example, in the case of the cache line length from which data is returned from the L1 cache 160, the decoupling circuit 150 extracts multiple data items to be returned from that cache line in this case.

[0064] Figure 17 schematically shown Figure 16 The apparatus 10, in which valid examples of inputs, processing, and outputs are superimposed. Address generation circuitry 110 is shown to receive a load request that identifies the schema register R20 as the address where a load should occur. Address generation circuitry 110 then determines that schema register R20 (currently) corresponds to physical address "21" and adds a pending load with that address information to PLB 120. PLB 120 is a FIFO buffer structure, therefore the latest pending load request is added to the first entry (at the top in this figure). It should be noted that PLB 120 is typically fully full because entries exist in all possible storage locations, but different states can be maintained for each individual entry, as will be discussed in more detail below. Additionally, it should be noted that only these specific entries are explicitly shown because they are relevant to this discussion. Figure 17 A subset of the entries in PLB 120. Therefore, in Figure 17The sampling printout of the contents of PLB 120 explicitly shows four entries, corresponding to memory address locations 21, 8, 5, and 3 respectively. Additional information or metadata, such as the data access type, format, and access size information corresponding to each entry, can also be stored in the pending load buffer. If needed, this metadata can be shared with the de-coalescing circuitry to retrieve relevant data items from the data returned from memory.

[0065] The coalescing circuit 130 monitors the contents of PLB 120 and determines which requests will be forwarded to the load processing circuit 140. As the contents of PLB 120 progress, the pending load request accessing address 3 becomes the oldest valid pending load request in PLB 120, and the coalescing circuit 130 forwards this request to the load processing circuit 140, thereby marking the entry's status indicator as "in flight" (IF). The "in flight" status means that the entry in PLB 120 for this pending load request is typically held in PLB 120 until the load has been processed and the requested data returned, allowing the entry to be marked as invalid. However, other states of entries in PLB 120 are also used to support this technique. The coalescing circuit 130 monitors and compares the memory addresses that constitute the subjects of the corresponding pending load requests held in PLB 120, specifically identifying multiple entries in PLB 120 that are associated with memory addresses that are close enough to allow "coalescing" of these load requests to occur. Figure 17 In the example, coalescing circuitry 130 is arranged to determine whether multiple pending load requests in PLB 120 relate to memory addresses within the cache line size used in the memory system and specifically in L1 cache 160. Figure 17 In the exemplary sampling printout shown, coalescing circuit 130 determines that two additional pending load requests in PLB 120 (i.e., those pending load requests accessing memory addresses 5 and 8) satisfy their address proximity requirements because the data items retrieved from memory addresses 3, 5, and 8 will be in the same cache line. Therefore, coalescing circuit 130 marks the pending load requests related to memory addresses 5 and 8 as "invalid" and sends an indication to de-coalescing circuit 150 that these three pending load requests have been grouped together in this manner.

[0066] After forwarding the pending load request related to memory address 3, load processing circuit 140 accesses the memory system (including L1 data cache 160) to perform the required load. The cache line returned from L1 data cache 160 includes multiple data items, including those referenced by memory addresses 3, 5, and 8. The data corresponding to the cache line is passed to (or at least accessed by) de-aggregating circuit 150. In the absence of a signal from coalescing circuit 130, de-aggregating circuit 150 will only fetch the data item corresponding to memory address 3; however, if de-aggregating circuit 150 has received an indication from coalescing circuit 130 that the pending load requests related to memory addresses 3, 5, and 8 have been coalesced, de-aggregating circuit 150 fetches the data items corresponding to all three memory addresses from the returned data of the cache line. De-aggregating circuit 150 receives the required data from coalescing circuit 130, which, in response, causes the entry corresponding to the pending load request for memory address 3 to be marked as invalid. Therefore, when the entry reaches the header of PLB 120, the entry is deleted (or at least allowed to be overwritten). Similarly, when the entries corresponding to addresses 5 and 8 reach the header of PLB 120, these entries are similarly deleted (or at least allowed to be overwritten). It should be noted that if the process of handling the load request for the coalescing is interrupted, the corresponding entries can be restored, wherein the entry corresponding to memory address 3 is changed from being in flight to being valid, and the entries corresponding to memory addresses 5 and 8 are changed from being invalid to being valid.

[0067] Figure 18 Schematic illustration based on relative Figure 16 and Figure 17 An exemplary implementation based on the principles illustrated. References have been made. Figure 16 and Figure 17 Discussion Figure 18 Various components in the device. These components are... Figure 18 The same reference numerals are used to identify them. Instruction queue 310, fed into register read circuit 320 and address generation circuit 110, is shown. Therefore, by identifying the sequence of load requests in instruction queue 310, the memory addresses associated with these load requests are determined, and a corresponding entry for each load request is added to PLB 120. Figure 18 Further details of the coalescing circuit 130 are shown below. Figure 18In an exemplary embodiment, the de-coalescing circuit 130 is shown to include a trial proximity check circuit 331, an address proximity check circuit 332, and a hazard detection circuit 333. The trial proximity check circuit 331 and the address proximity check circuit 332 determine in a two-stage process whether multiple entries in the PLB 120 are associated with addresses that are sufficiently close so that their corresponding loads can be advantageously coalesced. Essentially, the trial proximity check circuit 331 performs a coarse comparison, while the address proximity check circuit 332 performs a more precise comparison. The coarser nature of the comparison performed by the trial proximity check circuit 331 allows the check to be performed more quickly, and thus updates the state of the corresponding entries in the PLB 120 more rapidly (temporarily). After performing an initial experimental proximity check (which in some implementations employs a CPU cycle (depending on the PLB size)), the "first" pending load request (i.e., at the head of PLB 120) is dispatched to the load processing unit 341 that initiates memory access. This "first" pending load request has been compared with subsequent pending load requests in the queue of the FIFO PLB 120. Figure 18 In the illustrative exemplary illustration, the memory system accessed by the load processing unit 341 for this purpose includes TLB 342 (including lookup and fault-checking circuitry), L1 cache 160, and the remainder of memory system 365 (accessed in the event of an L1 miss). While this access continues, the coalescing circuit updates any other entries in PLB 120 (which are potential matches in a "hold" state (i.e., by trial proximity check)) and sends information identifying these candidates to address proximity check circuit 332, which performs a more detailed check to determine whether the remaining address bits of a potential match are the same as the address bits of an outgoing load processed by the load processing unit 341. When address proximity check 332 does not find a (sufficiently close) match, the coalescing circuit restores these relevant pending load requests in PLB 120 to a valid state. In other words, these loading requests will then proceed further through PLB 120, where they can be compared with other loading requests to obtain address proximity, and (in the absence of compression before these loading requests reach the head of the PLB queue) these loading requests are passed to the loading processing unit 241 when they reach the head of the PLB queue 120.

[0068] Conversely, if address proximity check 332 finds a match, the coalescing circuitry changes these relevant pending load requests in PLB 120 from held to invalid, and passes information about each “compressed” load to de-coalescing circuitry 150, allowing the desired result to be retrieved from the cache accordingly. This information may include: the load ID, its offset within the cache line; the size of the request; and the ID of the outgoing load it depends on. It should be noted that although the coalescing circuitry spends additional time (e.g., two CPU cycles) performing these actions relative to other load requests (compressed in the example above), this is still less than the typical access time of the L1 cache, meaning that the latency of its operation is effectively hidden. The only case where this latency is not hidden is when other load requests are temporarily held (due to an experimental proximity match), but subsequently discovered by a (full) address proximity test that these other load requests are not a perfect match.

[0069] Load requests issued by load processing unit 341 access TLB 342 to perform the necessary lookups (for translation from virtual to physical addressing) and to respond appropriately to any faults. It should be noted that various types of L1 caches (e.g., virtually indexed or physically indexed) can be provided, and therefore, access to TLB 342 can occur before or after an L1 cache access. When an L1 data cache access is performed and (as a result of a cache hit or through further access to the remainder of memory system 365) the contents of the relevant cache line are returned, data read and path multiplexing circuitry 343 processes the cache line data and passes its contents to de-coalescing circuitry 150 (whose contents are accessible by this de-coalescing circuitry). The de-coalescing circuitry then extracts the required data items (as a result of a load request that includes coalescing multiple data items from one cache line). Referring to the above example of a decoupled access execution processor, these data items can be placed in buffer 350 (which may, for example, correspond to...) Figure 2 Decoupling access buffer 110 Figure 4 Decoupling access buffer 234 or Figure 5 The decoupled access buffer 311 can also be used to send these data items to the result cache 370 and / or the "execution" portion of the full processor (such as...). Figure 4 The example access results cache 236 and execution part 220).

[0070] Figure 18The coalescing circuit 331 is also schematically shown to include a hazard detection circuit 333, which forms part of a coherence mechanism that the device supports in a wider data processing system (of which the device forms part). These coherence mechanisms allow multiple master devices in the system to access and modify data items in shared areas of memory in a manner that will be generally familiar to those skilled in the art. The hazard detection circuit is arranged to receive write notifications from external devices (e.g., another master device accessing memory shared with it). These write notifications may, for example, come from snooping requests exchanged in a multi-master system. Thus, when the coalescing circuit passes a load request to the load processing unit 341 (for a specific cache line to be accessed), the hazard detection circuit 333 of the coalescing circuit tracks the access until it is completed, and if a write notification relating to the cache line is received while the cache line is still in flight, the hazard detection circuit takes remedial action. If an external device waits for an acknowledgment signal before proceeding with a write operation, and the sorting rules dictate that the local load being executed should complete first, the hazard detection circuitry delays sending the corresponding acknowledgment signal until a cache line has been retrieved.

[0071] The hazard detection circuit 333 can also take action relative to the contents of PLB 120. For example, when a sequencing rule dictates that an access notified by an external device should be completed before local loading, but local loading has already been processed by the loading processing unit (either by its own capability or by coalescing with at least one other loading request), the hazard detection circuit restores the entry in the pending loading buffer circuit. This can be achieved by changing the entry's "in flight" or "invalid" status back to valid, or by adding the corresponding loading request to the pending loading buffer. The hazard detection circuit 333 prevents the forwarding of loading requests to the loading processing circuit until it is known that the modification indicated by the write notification has been completed. Furthermore, the hazard detection circuit 333 sends a signal to the decoupling circuit notifying that the relevant results for the related loading request should not be returned.

[0072] Figure 19 Examples such as Figure 18The example shown is a valid example of a two-stage address comparison check performed in the coalescing circuit. Here, the exemplary assumption for which the comparison is being performed is that the base memory address (i.e., the valid pending load request corresponding to the head of the pending load buffer) is “261167”. It should be noted that this example is given in decimal notation only for readability purposes, and the principle can be readily converted to a typical binary implementation. In the first “experimental” phase 331, the numbers [2:1] of this address are compared with other addresses related to the pending load request in the PLB, and thus other addresses that also have the number “16” are determined to be experimentally matched. The set of four addresses thus selected causes the status of their pending load requests in the PLB to be updated to “hold”. Next, in the second “full check” phase 332, the numbers [5:3] of the base address are compared with other addresses related to the pending load request in the PLB. In this example, it is determined which of these addresses also has the number “261”. Those that do not match cause the status of their entries in the PLB to be restored to “valid”. Those entries that do match will have their status updated to "invalid" in the PLB, as these entries will be coalesced. Therefore, in the example shown, the coalescing request sent to the de-coalescing circuitry indicates a base request to access address 261167, and the result of this request should also be used to retrieve data items at addresses 261162, 261160, and 261163. It should be understood that this address information does not need to be explicitly transmitted, but can be transmitted in a more compact form, such as using an indicator of the base load ID and the corresponding offset within the cache line.

[0073] Figure 20 The contents of a pending load buffer as content evolves with an exemplary set of content being processed, according to some embodiments, are illustrated. A staggered print of the contents of the pending load buffer and a series of actions 1000-1006 are shown at eight consecutive time points AH. The buffer entries are shown as vertically stacked in the diagram, with the head of the buffer (i.e., holding the oldest entry) at the top and the tail of the buffer (i.e., holding the newest entry) at the bottom. Content A shows a load associated with address 74, which has reached the head of the buffer. This entry is marked invalid (I), and therefore action 1000 discards the invalid entry from the head of the buffer, resulting in content B. Next, action 1001 performs a trial proximity check, and therefore the head entry and any entries that might perfectly match in the address proximity check are marked "Hold" (H). It should be noted that in content C, this set of pending load requests includes "Load 3", "Load 5", "Load 8", and additional loads in the entries between Load 5 and Load 8. This is only for readability purposes; the entries, Figure 20All other entries except for "Load 3", "Load 5", and "Load 8" are not explicitly named. Due to the (full) address proximity check performed as action 1002, content D remains in the pending load buffer, where the entry at the header is marked "In Flight" (IF) (because it has been forwarded to the load processing circuitry), and requests that meet the address proximity condition are marked "Invalid" (I) because they have been aggregated. It should be noted that requests found to be mismatched in entries between Load 5 and Load 8 during the address proximity check are reset to "Valid" (V)—see content D. The next action 1003 relates to a received write notification that corresponds to (and replaces) a load of at least one aggregated load based on the aggregated loads published by Load 3, and therefore, the load is compressed (discarding any results generated in the load processing circuitry) and recovered in the PLB by marking the load as valid again. Content E is produced. Then, a valid pending load request exists at the head of the queue, and action 1004 initiates loading again (forwarding the request to the load processing circuit), and the entry in the PLB is marked as in flight (content F). In this attempt, "Load 3" completes successfully, returning the result of the load request from the decoupling circuit, along with those corresponding to "Load 5" and "Load 8," and then action 1005 marks the "Load 3" request as invalid (see content G). Finally, action 1006 discards the invalid request at the head of the queue, resulting in content H. It should be noted that the entries for "Load 5" and "Load 8" will also be simply discarded upon reaching the head of the queue.

[0074] Figure 21The sequence of steps taken according to some embodiments of the method is shown. The sequence begins at step 1010, where the address required for the load request is generated. At step 1011, the pending load request is buffered in a pending load buffer circuit. At step 1012, the pending load request (which has reached the head of the queue formed by the pending load buffer) is forwarded to the load processing circuit for execution. Then at step 1013, it is determined whether one or more subsequent load requests in the pending load buffer satisfy the address proximity condition relative to the just-issued load request. When the address proximity condition is satisfied, the process continues to step 1014, where forwarding of one or more subsequent load requests that satisfy the address proximity condition to the load processing circuit is suppressed. However, if the address proximity condition is not satisfied at step 1013, the process continues to step 1015. The process also continues from step 1014 to step 1015. At step 1015, a set of data items identified by the forwarded load request is retrieved from the memory system. At step 1016, the data item identified by the load request itself is returned as the result of the load request. If the address proximity condition is not met at step 1013, the process continues from step 1016 to step 1018, which completes the sequence of steps. However, if the address proximity condition is met at step 1013, the process continues from step 1016 through step 1017, in which additional data items corresponding to the one or more subsequent load requests are returned. The process then ends at step 1018.

[0075] Figure 22 A sequence of instructions according to some embodiments is shown, comprising a pilot instruction 1100 followed by a plurality of additional (other) instructions 1101. The pilot instruction 1100 is provided according to the present invention to give processor information relating to the subsequent instructions 1101, and in particular to indicate for each subsequent instruction whether it is considered an "execution" instruction or an "access" instruction. This classification purpose in the context of a decoupled access execution processor is described above with reference to the foregoing figures illustrating the principles of a decoupled access execution processor (and examples thereof) according to the present invention, the discussion of classifying instructions as "execution" instructions or "access" instructions, and examples of data dependency graphs. Figure 22 In the example, it can be seen that the guidance instruction 1100 basically comprises two parts. A first "opcode" part, specifically encoded to identify the instruction as a guidance instruction of this type to the device's decoding circuitry, and another part providing information related to the classification (access or execution) of subsequent instructions in that group. Furthermore, in Figure 22In the example, it can be seen that the information in instruction 1100 is explicitly presented (i.e., in terms of immediate value), where 0 indicates an access instruction and 1 indicates an execution instruction. It should be noted that, as mentioned above, the set of instructions 1101 to which these access / execution flags are applied may immediately follow the pilot instruction 1100, or, especially for timing purposes, one or more other instructions (not shown) may exist in the instruction sequence between the pilot instruction 1100 and the first instruction in the set of instructions 1101.

[0076] Figure 23 The decoding circuit 1110 in some embodiments is illustrated schematically. This decoding circuit may be, for example, Figure 2 Decoding circuit 102 in Figure 4 Decoding circuit 204 in Figure 5 Decoding circuit 302 in Figure 9 The decoding part of circuit 501 in the middle, Figure 12 The decoding circuit 702 and / or Figure 15A The decoding circuit 800 is in the middle. The decoding circuit 1110 is in Figure 23 The diagram is shown as including an opcode recognition circuit 1111, circuitry for performing additional decoding operations 1112, and an access / execution flag circuit 1113. Those skilled in the art will understand that, in order to convey points relevant to the discussion of this technology, the decoding circuit 1110 is shown only at a relatively high level of abstraction. Therefore, for clarity only, many components of a typical modern decoding circuit are not shown in the diagram. A sequence of instructions (i.e., the acquired instructions) is received by the decoding circuit 1110, and the opcode recognition circuit 1111 identifies the guiding instructions of this technology through specific opcodes that form part of the instructions. When one of these instructions is identified, the opcode recognition circuit 1111 signals the access / execution flag circuit 1113 to notify of the situation and also transmits access / execution information encoded in the instructions. Figure 23 In an exemplary embodiment, the opcode recognition circuit 1111 is arranged to recognize Figure 22 The type of guidance instruction shown is used, and therefore, explicit access / execution information provided as part of that instruction is then directly passed to the access / execution marking circuit 1113. This explicit access / execution information is stored in a marking buffer 1114, which forms part of the access / execution marking circuit 1113. In this way, Figure 22The relevant flags for the subsequent set of instructions 1101 are maintained by the decoding circuit 1110, and then applied when the subsequent instruction sequence is received. The application of these flags is performed by a separate decoding operation circuit 1112, which receives the relevant flags for each subsequent instruction. Therefore, the output of the decoding circuit 1110 is based on whether the decoded instruction has a "access" type or "execute" type flag. It should be noted that the decoding circuit 1110 is arranged with a default flag, which here means that the processor defaults to treating instructions as "access" (unless these instructions have a specific type, in which case the processor requests to forward them to a specific part of the processor for other reasons, which is the only way to execute these specific instructions).

[0077] Figure 24 The apparatus 1120 in some exemplary embodiments is illustrated schematically. Acquisition circuitry 1121 receives instructions retrieved from a memory system and provides these instructions to decoding circuitry 1122, which performs a decoding operation, typically as described above. Figure 23 As described. Figure 24 As shown, the memory system includes (at least) instruction caches 1130 and 1131 to strive to avoid as much of the full latency associated with retrieving instructions from their original storage locations in memory. Figure 24 Another feature of the device 1120 is a micro-operation cache 1123, in which micro-operations resulting from instruction decoding are temporarily stored. The issuing circuit 1124 retrieves instructions from the micro-operation cache 1123 (if stored there) to issue instructions to one of the execution circuit 1125 and the access execution circuit 1126. The access execution circuit 1126 includes a decoupled access buffer 1127, which the execution circuit 1125 has access to. An additional memory system 1128 is also shown (i.e., in addition to instruction caches 1130 and 1131, and possibly including, for example, one or more shared caches and / or system caches preceding the actual memory). Therefore, it should be understood that... Figure 24 The execution circuit 1125, access execution circuit 1126, and decoupling access buffer 1127 shown can be considered as any of the examples of these components described above with reference to the foregoing figures.

[0078] refer to Figure 24In the micro-operation cache 1123, it should be noted that each entry in the micro-operation cache may have an associated additional tag (A or E) indicating whether the entry will be processed as an access instruction or an execution instruction (micro-operation). According to this technology, the decoding circuit 1123 is arranged based on the classification of instructions following the lead instruction to apply the tag to the decoded instructions (and / or their equivalent micro-operations) stored in the micro-operation cache 1123. Therefore, when the dispatch circuit 1124 accesses an entry in the micro-operation cache 1123, the dispatch circuit can also be provided with the associated classification (tag) information, and thus these micro-operations can be directed to the appropriate execution circuit 1125 or 1126 on this basis. Instruction caches 1130 and 1131 may also store associated classification information (tags) (as generated by the decoding circuit 1122) applied to entries in the micro-operation cache 1123, and thus these tags can be preserved when entries are evicted from the micro-operation cache to these illustrated levels of the instruction cache hierarchy.

[0079] Figure 25 The apparatus 1160 in some exemplary embodiments is illustrated schematically. Acquisition circuitry 1161 receives instructions retrieved from memory system 1168 and provides these instructions to decoding circuitry 1162, which performs a decoding operation, typically as described above. Figure 23 The device also includes a register renaming circuit 1163 that performs a register renaming operation to allow out-of-order instruction execution. Therefore, the remapped (renamed) instructions are passed to a issuing circuit 1164, which issues instructions to either an execution circuit 1165 or an access execution circuit 1166. The access execution circuit 1166 includes a decoupled access buffer 1167, which the execution circuit 1165 has access to. It should be understood that... Figure 25 The execution circuit 1165, access execution circuit 1166, and decoupling access buffer 1167 shown can be considered as any of the examples of these components described above with reference to the foregoing figures. Figure 25 Three sets of physical registers, 1169, 1170, and 1171, are also shown. Although in Figure 25The registers are shown separately, but these should be understood as a set of physical registers, and the grouping shown is not physical. The three subsets shown are used by renaming circuit 1163 for instructions, which processes them based on whether a given instruction is an "access" instruction or an "execute" instruction. When decoding circuit 1162 encounters a guide instruction according to the present technology, it generates control signals to modify the renaming operation of register renaming circuit 1163, such that the register set is used for the "guided" subsequent instructions, depending on the type of those subsequent instructions. Here, register 1171 holds a value generated by an "access" instruction and consumed only by other "access" instructions; register 1170 holds a value generated by an "access" instruction and consumed by an "execute" instruction; and register 1169 holds a value generated by an "execute" instruction and consumed only by other "execute" instructions.

[0080] Figures 26A to 26C The structure of the guidance instructions according to this technology in some embodiments is illustrated schematically. Figure 26A In this context, instructions are presented as including the opcode, formatting information, and access / execution (A / E) information about one or more subsequent instructions. Figure 26A In the example, the formatting information is binary, where a value of 0 indicates that the AE information is immediate (i.e., normal), and in... Figure 22 In this manner, each bit value in the set of AE information corresponds to a subsequent instruction, indicating its type. Conversely, a format value of 1 indicates that the AE information is compressed. This compression can be fixed and predetermined, so the decoding circuit does not need additional information from the instruction to interpret the instruction (by properly decompressing the instruction). Figure 26B An example is shown where the format information includes two binary bits. (Similar to...) Figure 26A In this case, the first value (00 here) indicates that the AE information is immediate (i.e., ordinary), directly indicating the classification of the subsequent instruction sequence. The three other possible values ​​of the binary pair indicate which of the three different compression schemes (#1, #2, or #3) has been used to encode the AE information in the instructions. In this example, compression scheme #1 (indicated by format information 01) is Run-Length Encoding (RLE), such that, for example, the pattern “AAAAAAEEEAAAAA” is logically represented in the AE information as {6A, 3E, 5A}. Run-Length Encoding (RLE) is known and not described in more detail here—any known RLE procedure and representation of AE information can be applied by those skilled in the art. Figure 26B In the example, the format information "10" (compression scheme #2) indicates a compression scheme according to which the pattern "AAAEEAAAAAEEEEEE" is presented as {A, 3, 2, 5, 6} in the AE information. Figure 26B The example does not use possible compression scheme #3, but in practice, more bits (within its available range) can be used in the instruction encoding to indicate more compression schemes as needed. Figure 26C The example shows that the instruction includes opcode information, AE information, and format / reordering information. Therefore, the format / reordering information indicates the compression scheme used (or not used) (such as in...). Figure 26A and Figure 26B (In the example), but there is another indication (e.g., by a separate single bit) as to whether a known reordering (fixed arrangement) was applied to the bits before compression was applied (or not applied), such as before any compression scheme was applied. This reordering can be applied when the instructions are created, or it can be applied subsequently by the compiler if the compiler changes the order of the instructions. The compiler may do this for any other reason, but it may be done explicitly to allow grouping of access and execution instructions to facilitate compression and thus improve the compression ratio.

[0081] Figure 27 The decoding circuit 1140 in some embodiments is schematically shown. This can be the decoding circuit of the example above or any of those in the figure. The figure illustrates how to receive, process, and decode via the decoding circuit. Figures 26A to 26C The instruction 1141 is a formatted instruction in the shown format. Instruction 1141 is received by decoding circuit 1141, and the opcode portion is routed to opcode recognition circuit 1142. Format information (and reordering information, if present) and AE information are routed to decompression / reordering circuit 1142. Opcode recognition circuit 1142 provides control information to decompression / reordering circuit 1142 to ensure the correct application of the instruction type, particularly the nature of the formatting information (see, for example...). Figures 26A to 26C (Example). Then, the decompression / reordering circuit 1142 decompresses the AE information (if needed) and performs a reverse reordering (if needed) to generate the required decompressed A / E tags for at least one subsequent instruction. It should be understood that, generally for efficiency reasons, as many subsequent instructions as possible are tagged with the given pilot instruction (within the available coding space).

[0082] Figure 28This is a flowchart illustrating a sequence of steps taken by a decoding circuit according to some implementation methods. This can be a decoding circuit of either the example above or any of the diagrams. At step 1200, the decoding circuit receives the next instruction, and at step 1201, it determines whether the instruction is one of the A / E guidance instructions of the present technology. If not, the flow continues to step 1202, where the decoding circuit performs "normal" decoding of the instruction as needed (since this is typically the case for most instructions received by the decoding circuit) so that the device performs its general data processing operations. However, when an A / E guidance instruction is encountered, the flow continues to step 1203, where AE information is extracted from the instruction. Then, at step 1204, this AE guidance (i.e., the labeling or classification of individual instructions) is applied to relevant subsequent instructions for decoupled access execution performed by the device. For more details on this decoupled access execution, please refer to any of the examples above. The flow returns to step 1200.

[0083] Figure 29 This is a flowchart illustrating the sequence of steps taken by a decoding circuit according to some implementation methods when the guidance instruction also includes compressed AE information. This can be the decoding circuit of the example above or any of the diagrams. The process can be considered to begin at step 1250, in which the decoding circuit receives the next instruction to be decoded. Then, at step 1251, it is determined whether the instruction is an A / E guidance instruction according to the present technology, and as... Figure 28 If not, the process continues through step 1252 so that the instruction is decoded "normally," and the process returns to step 1250. If an A / E guidance instruction is encountered, the process continues to step 1253, where it is further determined whether the instruction instructs the AE information to be compressed and / or reordered. If so, the process continues through step 1254 so that the AE information is decompressed, where it should be understood that such decompression may include decompression and / or reordering, as detailed above. Figures 26A to 26C and Figure 27 The process then proceeds from step 1253 (without compression / reordering) or from step 1254 (with compression / reordering) to step 1255 to extract the original, plain / uncompressed / reordered AE information. Then, at step 1256, this AE guidance is applied to the relevant subsequent instructions for decoupling access execution instructions. Again, for more details regarding this decoupling access execution, please refer to any of the examples above. The process then returns to step 1250.

[0084] Figure 30A specific implementation of a usable simulator is illustrated. While the previously described embodiments implement the invention in terms of means and methods for operating specific processing hardware supporting the technologies involved, it is also possible to provide an instruction execution environment according to the embodiments described herein, which is implemented using a computer program. Such computer programs are generally referred to as simulators, in part because they provide a software-based implementation of a hardware architecture. Types of simulator computer programs include emulators, virtual machines, models, and binary converters, including dynamic binary converters. Typically, the simulator implementation can run on a host processor 1330 supporting the simulator program 1310, optionally running a host operating system 1320. In some arrangements, multiple emulation layers may exist between the hardware and the provided instruction execution environment and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors were required to provide simulator implementations that execute at a reasonable speed, but this approach may be reasonable in certain situations, such as when it is desirable to run code native to another processor for compatibility or reuse reasons. For example, the simulator implementation may provide additional functionality to the instruction execution environment that is not supported by the host processor hardware, or provide an instruction execution environment that is typically associated with a different hardware architecture. An overview of the simulation is given in the following literature: “Some Efficient Architecture Simulation Techniques”, Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0085] With respect to embodiments previously described with reference to specific hardware constructions or features, in simulated embodiments, equivalent functionality may be provided by suitable software constructions or features. For example, specific circuitry may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or cache memory may be implemented as software data structures in simulated embodiments. One or more hardware elements referenced in the previously described embodiments are present in an arrangement on host hardware (e.g., host processor 1330), and where appropriate, some simulated embodiments may utilize the host hardware.

[0086] The simulator program 1310 may be stored on a computer-readable storage medium (which may be a non-transitory medium) and provides a program interface (instruction execution environment) to the target code 1300, which is identical to the application programming interface of the hardware architecture being modeled by the simulator program 1310. Therefore, in such embodiments, the program instructions of the target code 1300 include the aforementioned novel guiding instructions for providing A / E markings, and these program instructions can be executed from within the instruction execution environment using the simulator program 1310, enabling a host computer 1330, which does not actually possess the hardware features described above, to emulate these features.

[0087] In summary, a general overview apparatus and method for data processing are disclosed. The apparatus includes a first instruction execution circuit, a second instruction execution circuit, and a decoupled access buffer. Instructions in an ordered sequence are issued to one of the first and second instruction execution circuits for execution, depending on whether the instruction has a first type tag or a second type tag. The instruction with the first type tag is an access-related instruction that determines at least one feature of a load operation for retrieving a data value based on a memory address. The execution of the instruction with the first type tag performed by the first instruction execution circuit takes precedence over the execution of the instruction with the second type tag performed by the second instruction execution circuit. The data value retrieved from memory is stored in the decoupled access buffer as a result of the execution of these first type instructions. Once the data value required for executing a pending second type instruction is in the decoupled access buffer, the second instruction execution circuit retrieves the data value from the decoupled access buffer and executes the pending instruction.

[0088] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0089] While exemplary embodiments have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, features of dependent claims may be combined with features of independent claims in various ways without departing from the scope of the invention.

Claims

1. A data processing apparatus, the data processing apparatus comprising: A publishing circuit, the publishing circuit being used to publish instructions for out-of-order execution relative to an ordered sequence of instructions; First instruction execution circuit and second instruction execution circuit; and Decoupled access buffer, The issuing circuit, in response to a type flag associated with an instruction, issues the instruction for execution to the first instruction execution circuit when the instruction has a first type flag, and issues the instruction for execution to the second instruction execution circuit when the instruction has a second type flag. Instructions with the first type of tag and instructions with the second type of tag originate from the ordered instruction sequence. Wherein, when the instruction is an access-related instruction, the instruction has the first type of marker, the access-related instruction determining at least one feature of a load operation for retrieving a data value based on a memory address, and wherein, when the instruction is not an access-related instruction, the instruction has the second type of marker. The data processing device is arranged such that the execution of instructions with the first type of marker performed by the first instruction execution circuit takes precedence over the execution of instructions with the second type of marker performed by the second instruction execution circuit. Furthermore, the first instruction execution circuit is arranged to store data values ​​retrieved from memory as the result of execution of the instruction with the first type tag in the decoupled access buffer, and the second instruction execution circuit responds to the data values ​​required to execute the pending instruction with the second type tag stored in the decoupled access buffer. Retrieve the data value from the decoupled access buffer and execute the pending instruction; An instruction dependency determination circuit is configured to associate a first type tag with the instruction being determined when the instruction being determined is a load instruction, and to perform a dependency chain determination process to attempt to find a dependency chain including the instruction being determined, wherein when the dependency chain leading to the load instruction is found, the first type tag is associated with the instruction being determined; A decoding circuit is configured to receive the ordered instruction sequence and perform decoding operations, wherein at least some of the decoding operations cause the instruction to be divided into more than one micro-operation definition, wherein the micro-operation definition is received by the publishing circuit. and A micro-operation cache is provided to receive and temporarily store the micro-operation definitions published by the publishing circuit, thereby eliminating the need for decoding due to the recurrence of instructions that derive the micro-operation definitions. The instruction dependency determination circuit is configured to perform the dependency chain determination process using the contents of the micro-operations cache.

2. The data processing apparatus according to claim 1, further comprising: A register renaming circuit, comprising a renaming table for storing temporary associations between schema registers specified in instructions and physical registers for maintaining temporary copies of data values. The instruction dependency determination circuit is configured to perform the dependency chain determination process using the contents of the renaming table.

3. The data processing apparatus of claim 1 further includes a decoding circuit, the decoding circuit being configured to receive the ordered instruction sequence and perform a decoding operation, wherein the decoding circuit, in response to an instruction type classification instruction in the ordered instruction sequence, associates one of a first type label and a second type label with each instruction in the subset according to a label type definition specified in the instruction type classification instruction for a subset of the ordered instruction sequence.

4. The data processing apparatus according to any of the preceding claims, wherein while execution of a first type of instruction by the first instruction execution circuit is in progress, the second instruction execution circuit is capable of entering an inactive state, in which no execution of a second type of instruction occurs.

5. The data processing apparatus of claim 4, wherein the second instruction execution circuit, in response to an activation signal from the first instruction execution circuit, exits the inactive state and continues to execute the second type of instruction.

6. The data processing apparatus of claim 5, wherein the first instruction execution circuit issues the activation signal to the second instruction execution circuit in response to the occupancy of the decoupled access buffer.

7. The data processing apparatus of claim 6, wherein the first instruction execution circuit issues the activation signal to the second instruction execution circuit in response to the occupancy of the decoupled access buffer exceeding a threshold occupancy.

8. The data processing apparatus according to any one of claims 1 to 3, wherein the second instruction execution circuit includes an execution cache for storing instructions issued by the issuing circuit to the second instruction execution circuit before instruction execution begins.

9. The data processing apparatus according to any one of claims 1 to 3, wherein the second instruction execution circuit includes a reserved station circuit for supporting a register renaming operation for out-of-order instruction execution, wherein the reserved station circuit is arranged to receive the data value from the decoupled access buffer.

10. The data processing apparatus according to any one of claims 1 to 3, wherein the second instruction execution circuitry includes a storage unit temporarily holding an entry comprising a data value to be stored in memory, and the apparatus is arranged to identify an entry in the decoupled access buffer, wherein the load address of the entry for which the data value of the entry is loaded by an executed load instruction matches the storage address of the entry in the storage unit for a storage instruction being executed; and is arranged to determine a conflict condition is true when the storage instruction is in the ordered instruction sequence preceding the load instruction.

11. The data processing apparatus of claim 10, wherein the apparatus, in response to the conflict condition, refreshes the load instruction and any subsequent instructions from the ordered instruction sequence in the first instruction execution circuit and the second instruction execution circuit.

12. The data processing apparatus of claim 10, wherein the apparatus, in response to the conflict condition, refreshes the load instruction from the ordered instruction sequence and any subsequent instructions directly or indirectly dependent on the load instruction in the first instruction execution circuit and the second instruction execution circuit.

13. A data processing method, the data processing method comprising: In contrast to ordered instruction sequences, instructions are issued for out-of-order execution. In response to a type flag associated with an instruction, the instruction is issued to a first instruction execution circuit for execution when the instruction has a first type flag, and the instruction is issued to a second instruction execution circuit for execution when the instruction has a second type flag. Instructions with the first type of tag and instructions with the second type of tag originate from the ordered instruction sequence. When the instruction is an access-related instruction, the instruction has the first type of marker, the access-related instruction determines at least one feature of a load operation for retrieving a data value based on a memory address, and when the instruction is not an access-related instruction, the instruction has the second type of marker; The execution of instructions with the first type of flag, performed by the first instruction execution circuit, takes precedence over the execution of instructions with the second type of flag, performed by the second instruction execution circuit. The data value retrieved from the memory is stored in the decoupled access buffer as the result of the execution of the instruction with the first type tag by the first instruction execution circuit; In response to the fact that the decoupled access buffer stores data values ​​required to execute a pending instruction with the second type tag, the data values ​​are retrieved from the decoupled access buffer for the second instruction execution circuit and the pending instruction is executed in the second instruction execution circuit; When the instruction being determined is a load instruction, the first type of tag is associated with the instruction being determined, and a dependency chain determination process is performed to try to find a dependency chain that includes the instruction being determined, wherein when the dependency chain leading to the load instruction is found, the first type of tag is associated with the instruction being determined; Receive the ordered sequence of instructions and perform decoding operations, wherein at least some of the decoding operations cause the instructions to be divided into more than one micro-operation definition; and The micro-operation definition is received and temporarily stored in a micro-operation cache, thus avoiding decoding due to the recurrence of the instruction that derives the micro-operation definition. The dependency chain determination process is performed using the contents of the micro-operation cache.

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