Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface, a second main surface, a first impurity region, a second impurity region, and a third impurity region. The first electrode is connected to the second and third impurity regions at the first main surface. The second electrode is connected to the first impurity region at the second main surface. The second impurity region includes the first region and a second region located between the first region and the second main surface and connected to the first region. The impurity concentration of the first region is 6 × 10⁻⁶. 16 cm ‑3 above.

Description

Technical Field

[0001] This disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2019-196257, filed on October 29, 2019. The entire contents of that Japanese Patent Application are incorporated herein by reference. Background Technology

[0002] The IV characteristics of SiC-PiN diodes are described in "High-Frequency Driven High-Power Converter Realized by Hybrid Pair of SiC-PiN Diode and Si-IEGT" (Non-Patent Document 1), published by Kazuto Takao and two others in Toshiba Review, Vol. 66, No. 5, 2011.

[0003] Existing technical documents

[0004] Non-patent literature

[0005] Non-Patent Literature 1: Kazuto Takao and two others, “High-Frequency Driven High-Power Converter Realized by Hybrid Pair of SiC-PiN Diodes and Si-IEGT,” Toshiba Review, Vol. 66, No. 5, 2011 Summary of the Invention

[0006] The silicon carbide semiconductor device disclosed herein includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has: a first main surface; a second main surface opposite to the first main surface; a first impurity region constituting at least a portion of the second main surface and having a first conductivity type; a second impurity region constituting at least a portion of the first main surface, disposed in contact with the first impurity region, and having a second conductivity type different from the first conductivity type; and a third impurity region disposed in contact with the second impurity region in a manner separated from the first impurity region, and having a first conductivity type. The first electrode is disposed in contact with both the second impurity region and the third impurity region at the first main surface. The second electrode is disposed in contact with the first impurity region at the second main surface. The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The impurity concentration of the first region is 6 × 10⁻⁶. 16 cm -3 above.

[0007] The silicon carbide semiconductor device disclosed herein includes a silicon carbide substrate, a first electrode, and a second electrode. The silicon carbide substrate has: a first main surface; a second main surface opposite to the first main surface; a first impurity region constituting at least a portion of the second main surface and having a first conductivity type; a second impurity region constituting at least a portion of the first main surface, disposed in contact with the first impurity region, and having a second conductivity type different from the first conductivity type; and a third impurity region disposed in contact with the second impurity region in a manner separated from the first impurity region, and having a first conductivity type. The first electrode is disposed in contact with both the second impurity region and the third impurity region at the first main surface. The second electrode is disposed in contact with the first impurity region at the second main surface. The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The point defect density of the first region is 6 × 10⁻⁶. 12 cm -3 above.

[0008] The method for manufacturing a silicon carbide semiconductor device disclosed herein includes the following steps: Preparing a silicon carbide substrate having: a first main surface; a second main surface opposite to the first main surface; a first impurity region constituting at least a portion of the second main surface and having a first conductivity type; a second impurity region constituting at least a portion of the first main surface, disposed in contact with the first impurity region, and having a second conductivity type different from the first conductivity type; and a third impurity region disposed in contact with the second impurity region in a manner separated from the first impurity region, and having a first conductivity type. Forming a first electrode at the first main surface, respectively, in contact with the second impurity region and the third impurity region. Forming a second electrode at the second main surface, in contact with the first impurity region. The second impurity region includes a first region and a second region located between the first region and the second main surface and in contact with the first region. The impurity concentration of the first region is 6 × 10⁻⁶. 16 cm -3 That's all. The first region was formed through ion implantation. Attached Figure Description

[0009] Figure 1 This is a cross-sectional schematic diagram showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0010] Figure 2 It is along Figure 1 A cross-sectional view of line II-II.

[0011] Figure 3 yes Figure 2 An enlarged schematic diagram of region III.

[0012] Figure 4 This is a cross-sectional schematic diagram showing the structure of the silicon carbide semiconductor device according to the second embodiment.

[0013] Figure 5 This is a cross-sectional schematic diagram showing the structure of the silicon carbide semiconductor device according to the third embodiment.

[0014] Figure 6 This is a flowchart illustrating a general method for manufacturing a silicon carbide semiconductor device according to this embodiment.

[0015] Figure 7 This is a flowchart outlining the process of preparing a silicon carbide substrate in the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0016] Figure 8 This is a cross-sectional schematic diagram showing the first step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0017] Figure 9 This is a cross-sectional schematic diagram showing the second step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0018] Figure 10 This is a cross-sectional schematic diagram showing the third step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0019] Figure 11 This is a cross-sectional schematic diagram showing the fourth step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0020] Figure 12 This is a cross-sectional schematic diagram showing the fifth step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0021] Figure 13 This is a cross-sectional schematic diagram showing the sixth step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0022] Figure 14 This is a cross-sectional schematic diagram showing the seventh step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0023] Figure 15 This is a cross-sectional schematic diagram showing the eighth step of the manufacturing method of the silicon carbide semiconductor device according to this embodiment.

[0024] Figure 16 This is a graph showing the relationship between drain current density and drain voltage in the silicon carbide semiconductor device of Sample 1.

[0025] Figure 17 This is a graph showing the relationship between drain current density and drain voltage in the silicon carbide semiconductor device of Sample 2. Detailed Implementation

[0026] [The problem this disclosure aims to solve]

[0027] The purpose of this disclosure is to provide a silicon carbide semiconductor device capable of suppressing temperature variations in diode characteristics and a method for manufacturing the silicon carbide semiconductor device.

[0028] [The Effects of This Disclosure]

[0029] According to this disclosure, a silicon carbide semiconductor device capable of suppressing temperature variations in diode characteristics and a method for manufacturing the silicon carbide semiconductor device can be provided.

[0030] [Description of embodiments of this disclosure]

[0031] First, embodiments of this disclosure will be described. In the crystallographic description of this specification, individual orientations are represented by [], group orientations by <>, individual planes by (), and group planes by {}. Negative crystallographic exponents are usually represented by a "-" (hyphen) above the number, but in this specification, negative crystallographic exponents are represented by a negative sign before the number.

[0032] (1) The silicon carbide semiconductor device 200 of this disclosure includes a silicon carbide substrate 100, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 has: a first main surface 1; a second main surface 2 opposite to the first main surface 1; a first impurity region 10 constituting at least a portion of the second main surface 2 and having a first conductivity type; a second impurity region 20 constituting at least a portion of the first main surface 1, disposed in contact with the first impurity region 10, and having a second conductivity type different from the first conductivity type; and a third impurity region 30 disposed in contact with the second impurity region 20 in a manner separated from the first impurity region 10, and having a first conductivity type. The first electrode 61 is disposed in contact with the second impurity region 20 and the third impurity region 30 at the first main surface 1. The second electrode 62 is disposed in contact with the first impurity region 10 at the second main surface 2. The second impurity region 20 includes a first region 21 and a second region 22 located between the first region 21 and the second main surface 2 and in contact with the first region 21. The impurity concentration of the first region 21 is 6 × 10⁻⁶. 16 cm -3 above.

[0033] (2) According to the silicon carbide semiconductor device 200 described in (1) above, the impurity concentration in the second region 22 can be 6 × 10⁻⁶. 16 cm -3 above.

[0034] (3) The silicon carbide semiconductor device 200 of this disclosure includes a silicon carbide substrate 100, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 has: a first main surface 1; a second main surface 2 opposite to the first main surface 1; a first impurity region 10 constituting at least a portion of the second main surface 2 and having a first conductivity type; a second impurity region 20 constituting at least a portion of the first main surface 1, disposed in contact with the first impurity region 10, and having a second conductivity type different from the first conductivity type; and a third impurity region 30 disposed in contact with the second impurity region 20 in a manner separated from the first impurity region 10, and having a first conductivity type. The first electrode 61 is disposed in contact with the second impurity region 20 and the third impurity region 30 at the first main surface 1. The second electrode 62 is disposed in contact with the first impurity region 10 at the second main surface 2. The second impurity region 20 includes a first region 21 and a second region 22 located between the first region 21 and the second main surface 2 and in contact with the first region 21. The point defect density of the first region 21 is 6 × 10⁻⁶. 12 cm -3 above.

[0035] (4) According to the silicon carbide semiconductor device 200 described in (3) above, the point defect density in the first region 21 can be 1×10⁻⁶. 14 cm -3 the following.

[0036] (5) The silicon carbide semiconductor device 200 according to any one of (1) to (4) above can be planar.

[0037] (6) According to any one of (1) to (4) above, a trench 5 may be provided on the silicon carbide substrate 100. The trench 5 may have a side surface 3 that is connected to each of the first impurity region 10, the second impurity region 20 and the third impurity region 30 and a bottom surface 4 that is connected to the side surface 3 and connected to the first impurity region 10.

[0038] (7) According to the silicon carbide semiconductor device 200 of (6) above, the shape of the trench 5 in the cross section perpendicular to the first main surface 1 can be U-shaped.

[0039] (8) According to the silicon carbide semiconductor device 200 of (6) above, in the cross section perpendicular to the first main surface 1, the shape of the trench 5 can be V-shaped.

[0040] (9) In the silicon carbide semiconductor device 200 according to any one of (1) to (8) above, the first main surface 1 may be the (000-1) surface or a surface that is inclined at an angle of less than 8° relative to the (000-1) surface.

[0041] (10) In the silicon carbide semiconductor device 200 according to any one of (1) to (9) above, the impurity concentration of the first region 21 may be higher than the impurity concentration of the second region 22.

[0042] (11) According to the silicon carbide semiconductor device 200 of (10) above, the impurity concentration of the first region 21 can be 1×10⁻⁶. 19 cm -3 the following.

[0043] (12) The method for manufacturing the silicon carbide semiconductor device 200 disclosed herein includes the following steps: Preparing a silicon carbide substrate 100, the silicon carbide substrate 100 having: a first main surface 1; a second main surface 2 opposite to the first main surface 1; a first impurity region 10 constituting at least a portion of the second main surface 2 and having a first conductivity type; a second impurity region 20 constituting at least a portion of the first main surface 1, disposed in contact with the first impurity region 10, and having a second conductivity type different from the first conductivity type; and a third impurity region 30 disposed in contact with the second impurity region 20 in a manner separated from the first impurity region 10, and having a first conductivity type. Forming a first electrode 61 at the first main surface 1, respectively in contact with the second impurity region 20 and the third impurity region 30. Forming a second electrode 62 at the second main surface 2, in contact with the first impurity region 10. The second impurity region 20 includes a first region 21 and a second region 22 located between the first region 21 and the second main surface 2 and in contact with the first region 21. The impurity concentration in region 21 is 6 × 10⁻⁶. 16 cm -3 That's all. Region 21 was formed by ion implantation.

[0044] (13) According to the manufacturing method of silicon carbide semiconductor device 200 described in (12) above, the second region 22 can be formed by ion implantation.

[0045] (14) According to the manufacturing method of silicon carbide semiconductor device 200 of (12) or (13) above, the first impurity region 10 can be formed by epitaxial growth at a temperature of 1500°C or higher and 1750°C or lower.

[0046] (15) In the manufacturing method of the silicon carbide semiconductor device 200 according to any one of (12) to (14) above, the process of preparing the silicon carbide substrate 100 may include an activation annealing process. The activation annealing process may be performed at a temperature of 1600°C or higher and 1850°C or lower.

[0047] [Details of the embodiments of this disclosure]

[0048] The embodiments of this disclosure will now be described in detail. In the following description, the same or corresponding elements will be labeled with the same reference numerals, and the same descriptions will not be repeated.

[0049] (First Implementation)

[0050] First, the structure of the silicon carbide semiconductor device 200 of the first embodiment will be described. Figure 1 This is a cross-sectional schematic diagram showing the structure of the silicon carbide semiconductor device 200 according to the first embodiment.

[0051] like Figure 1 As shown, the silicon carbide semiconductor device 200 of the first embodiment is a trench MOSFET, which mainly includes a silicon carbide substrate 100, a gate electrode 63, a gate insulating film 51, a separation insulating film 52, a first electrode 61, and a second electrode 62. The silicon carbide substrate 100 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1.

[0052] The first principal surface 1 is, for example, the {0001} surface or a surface that is offset from the {0001} surface by less than 8°. Specifically, the first principal surface 1 is, for example, the (000-1) surface or a surface that is inclined at an angle of less than 8° relative to the (000-1) surface. The first principal surface 1 may also be, for example, the (0001) surface or a surface that is inclined at an angle of less than 8° relative to the (0001) surface.

[0053] like Figure 1 As shown, the silicon carbide substrate 100 includes a first impurity region 10, a second impurity region 20, and a third impurity region 30. The first impurity region 10, for example, contains n-type impurities such as N (nitrogen) that can impart an n-type conductivity. The first impurity region 10, for example, has an n-type conductivity (first conductivity type). The first impurity region 10 constitutes at least a portion of the second main surface 2. In other words, the first impurity region 10 can constitute the entire surface of the second main surface 2, or it can constitute a portion of the second main surface 2.

[0054] The first impurity region 10 has a silicon carbide single crystal substrate 15, a buffer layer 11, a first superjunction region 12, a first bonding region 13, and a current spreading region 14. The silicon carbide single crystal substrate 15 constitutes the second main surface 2. The silicon carbide single crystal substrate 15 is, for example, made of polytype 4H hexagonal silicon carbide. The buffer layer 11 is disposed on the silicon carbide single crystal substrate 15. The buffer layer 11 is in contact with the silicon carbide single crystal substrate 15.

[0055] A first superjunction region 12 is disposed on a buffer layer 11. The first superjunction region 12 is in contact with the buffer layer 11. In the first direction 101, the width of the first superjunction region 12 is smaller than the width of the buffer layer 11. In the third direction 103, the height of the first superjunction region 12 may be greater than the width of the first superjunction region 12 in the first direction 101. The concentration of n-type impurities in the first superjunction region 12 may be lower than the concentration of n-type impurities in the buffer layer 11.

[0056] A first bonding region 13 is disposed on a first superjunction region 12. The first bonding region 13 is connected to the first superjunction region 12. The first bonding region 13 can be narrowed such that its central width is smaller than its top and bottom widths. A current extension region 14 is disposed on the first bonding region 13. The current extension region 14 is connected to the first bonding region 13. The current extension region 14 is connected to the bottom surface 4 and the side surface 3 of the trench 5.

[0057] The impurity concentration in the first impurity region 10 is, for example, 6 × 10⁻⁶. 16 cm -3 That's all. Specifically, the concentration of n-type impurities in the first superjunction region 12 of the first impurity region 10 is, for example, 6 × 10⁻⁶. 16 cm -3 The concentration of n-type impurities in the first superjunction region 12 of the first impurity region 10 can, for example, be 8 × 10⁻⁶. 16 cm -3 The above can also be 10×10 16 cm -3 above.

[0058] The concentration of n-type impurities in the first bonding region 13 of the first impurity region 10 is, for example, 6 × 10⁻⁶. 16 cm -3 The concentration of n-type impurities in the current extension region 14 of the first impurity region 10 is, for example, 6 × 10⁻⁶. 16 cm -3 The concentration of n-type impurities in the first superjunction region 12, the first junction region 13, and the current extension region 14 can, for example, be 6 × 10⁻⁶. 16 cm -3 above.

[0059] The second impurity region 20 contains, for example, p-type impurities such as Al (aluminum) that can impart a p-type conductivity. The second impurity region 20 has a p-type conductivity (second conductivity type) different from the n-type conductivity. The second impurity region 20 is disposed in contact with the first impurity region 10. The second impurity region 20 and the first impurity region 10 constitute a PN diode. The second impurity region 20 constitutes at least a portion of the first main surface 1. In other words, the second impurity region 20 can constitute the entire surface of the first main surface 1, or it can constitute a portion of the first main surface 1.

[0060] The second impurity region 20 has a first region 21 and a second region 22. The second region 22 is located between the first region 21 and the second main surface 2. The second region 22 is in contact with the first region 21. The first region 21 constitutes at least a portion of the first main surface 1. The first region 21 may, for example, have a first portion 41 and a second portion 42. The first portion 41 is located on the second portion 42. The second portion 42 is in contact with the first portion 41. The concentration of p-type impurities in the first portion 41 may be higher than the concentration of p-type impurities in the second portion 42. The second portion 42 is, for example, a channel layer. The first region 21 may also not have a first portion 41. The second region 22 may be in contact with the buffer layer 11.

[0061] The second region 22 has a second superjunction region 25, a second bonding region 24, and a third bonding region 23. The second superjunction region 25 is disposed on the buffer layer 11. The second superjunction region 25 is in contact with the buffer layer 11. In the first direction 101, the width of the second superjunction region 25 is smaller than the width of the buffer layer 11. In the third direction 103, the height of the second superjunction region 25 may be larger than the width of the second superjunction region 25 in the first direction 101.

[0062] The first superjunction region 12 and the second superjunction region 25 constitute a superjunction. The first superjunction region 12 and the second superjunction region 25 are adjacent. In the first direction 101, the first superjunction region 12 and the second superjunction region 25 are alternately arranged. The concentration of p-type impurities in the second superjunction region 25 can be the same as the concentration of n-type impurities in the first superjunction region 12. In the first direction 101, the width of the second superjunction region 25 can be the same as the width of the first superjunction region 12.

[0063] The second bonding region 24 is disposed on the second superjunction region 25. The second bonding region 24 is adjacent to the second superjunction region 25. The second bonding region 24 can be expanded such that its central width is greater than its upper and lower widths. In the first direction 101, the maximum width of the second bonding region 24 can be greater than the width of the second superjunction region 25. The second bonding region 24 can be adjacent to the first bonding region 13. In the first direction 101, the second bonding region 24 and the first bonding region 13 are alternately arranged.

[0064] The third bonding region 23 is disposed on the second bonding region 24. The third bonding region 23 is connected to both the second bonding region 24 and the first region 21. In the third direction 103, the third bonding region 23 is located between the second bonding region 24 and the first region 21. In the first direction 101, the third bonding region 23 is connected to the current extension region 14.

[0065] The impurity concentration in region 22 is 6 × 10⁻⁶. 16 cm-3 That's all. Specifically, the concentration of p-type impurities in the second superjunction region 25 of the second region 22 is 6 × 10⁻⁶. 16 cm -3 The above. The concentration of p-type impurities in the second superjunction region 25 of the second region 22 can also be 8 × 10⁻⁶. 16 cm -3 The above can also be 10×10 16 cm -3 That's all. There is no particular upper limit to the concentration of p-type impurities in the second superjunction region 25 of the second region 22, but it can be, for example, 6 × 10⁻⁶. 18 cm -3 the following.

[0066] The concentration of p-type impurities in the second junction region 24 of the second region 22 is, for example, 6 × 10⁻⁶. 16 cm -3 The concentration of p-type impurities in the third bonding region 23 of the second region 22 is, for example, 6 × 10⁻⁶. 16 cm -3 The concentration of p-type impurities in the second superjunction region 25, the second junction region 24, and the third junction region 23 can, for example, be 6 × 10⁻⁶. 16 cm -3 above.

[0067] The third impurity region 30 is disposed adjacent to the second impurity region 20 in a manner separated from the first impurity region 10. The third impurity region 30 may contain, for example, n-type impurities such as P (phosphorus) that can impart an n-type form. The third impurity region 30 may, for example, be n-type. The third impurity region 30 may, for example, be a source region. The third impurity region 30 may constitute a part of the first main surface 1. The concentration of the n-type impurities contained in the third impurity region 30 may be higher than the concentration of the p-type impurities contained in the second part 42.

[0068] The impurity concentration in region 21 is 6 × 10⁻⁶. 16 cm -3 That's all. Specifically, the concentration of p-type impurities in region 21 is 6 × 10⁻⁶. 16 cm -3 The above describes the process. The impurity concentration in the first region 21 can be higher than the impurity concentration in the second region 22. Specifically, the concentration of p-type impurities in the second part 42 of the first region 21 can be higher than the concentration of p-type impurities in the second region 22. The impurity concentration in the first region 21 can be 1 × 10⁻⁶. 19 cm -3 Specifically, the concentration of p-type impurities in the second part 42 of the first region 21 can be 1 × 10⁻⁶. 19 cm -3The concentration of p-type impurities in the second part 42 of the first region 21 can also be 8 × 10⁻⁶. 18 cm -3 The following can also be 6×10 18 cm -3 The following is a description of the lower limit of the concentration of p-type impurities in the second part 42 of the first region 21. There is no particular limitation on this lower limit, but it could be, for example, 6 × 10⁻⁶. 17 cm -3 above.

[0069] A trench 5 is provided on a silicon carbide substrate 100. The trench 5 opens on a first main surface 1. The trench 5 has a side surface 3 and a bottom surface 4. The bottom surface 4 is connected to the side surface 3. The side surface 3 is in contact with each of the first impurity region 10, the second impurity region 20, and the third impurity region 30. Specifically, the side surface 3 is in contact with each of the current extension region 14, the second portion 42, and the third impurity region 30. The bottom surface 4 is in contact with the first impurity region 10. Specifically, the bottom surface 4 is in contact with the current extension region 14.

[0070] In a cross-section perpendicular to the first main surface 1, the groove 5 can be V-shaped. A V-shaped groove 5 means that the angle θ formed by the side surface 3 of the groove 5 and the first main surface 1 is greater than 90° and less than 180°. For example, the angle θ can be greater than 115° and less than 135°.

[0071] The gate insulating film 51 is made of silicon dioxide, for example. The gate insulating film 51 is disposed inside the trench 5. The gate insulating film 51 is in contact with the first impurity region 10, the second impurity region 20, and the third impurity region 30 at the side surface 3 of the trench 5. The gate insulating film 51 is in contact with the current spreading region 14 at the bottom surface 4 of the trench 5. A channel can be formed in the second portion 42 of the second impurity region 20 in contact with the gate insulating film 51. The gate insulating film 51 is in contact with the third impurity region 30 at the first main surface 1. The thickness of the gate insulating film 51 is, for example, 40 nm or more and 150 nm or less.

[0072] A gate electrode 63 is disposed on the gate insulating film 51. It is configured to contact the gate insulating film 51. At least a portion of the gate electrode 63 is disposed inside the trench 5. The gate electrode 63 is made of a conductive material such as polysilicon doped with impurities.

[0073] The separating insulating film 52 is disposed such that it covers the gate electrode 63. The separating insulating film 52 is connected to both the gate electrode 63 and the gate insulating film 51. The separating insulating film 52 is made of, for example, an NSG (None-doped Silicate Glass) film or a PSG (Phosphorus Silicate Glass) film. The separating insulating film 52 electrically insulates the gate electrode 63 and the first electrode 61.

[0074] A first electrode 61 is disposed on a first main surface 1. The first electrode 61 is, for example, a source electrode. The first electrode 61 has an electrode layer 60 and a wiring layer 64. The electrode layer 60 is, for example, made of a material containing Ti (titanium), Al (aluminum), and Si (silicon). The electrode layer 60 may also contain Ni (nickel). The wiring layer 64 is, for example, made of a material containing Al.

[0075] The first electrode 61 is in contact with the second impurity region 20 and the third impurity region 30 at the first main surface 1. Specifically, the electrode layer 60 is in contact with the first portion 41 and the third impurity region 30 at the first main surface 1. The first electrode 61 can be configured to span the trench 5. The first electrode 61 can cover the separation insulating film 52. The first electrode 61 is electrically connected to the second impurity region 20. The first electrode 61 is electrically connected to the third impurity region 30. When the first impurity region 10 is n-type and the second impurity region 20 is p-type, the first electrode 61 functions as an anode electrode.

[0076] The second electrode 62 is disposed on the second main surface 2. The second electrode 62 is, for example, a drain electrode. The second electrode 62 is in contact with the first impurity region 10 at the second main surface 2. Specifically, the second electrode 62 is in contact with the silicon carbide single-crystal substrate 15 at the second main surface 2. The second electrode 62 is electrically connected to the first impurity region 10. When the first impurity region 10 is n-type and the second impurity region 20 is p-type, the second electrode 62 functions as a cathode electrode. The second electrode 62 is, for example, made of a material such as NiSi (nickel silicide) capable of ohmic bonding with the n-type silicon carbide single-crystal substrate 15.

[0077] It should be noted that in the silicon carbide semiconductor device 200 of the first embodiment, the withstand voltage in the reverse characteristic is, for example, 600V or more, preferably 1100V or more.

[0078] Next, the methods for determining the concentrations of p-type impurities and n-type impurities in each impurity region will be explained.

[0079] The concentrations of p-type and n-type impurities in each impurity region can be determined using SIMS (Secondary Ion Mass Spectrometry). The measuring apparatus is, for example, a Cameca secondary ion mass analyzer. The measurement interval is, for example, 0.01 μm. When the detected n-type impurity is nitrogen, the primary ion beam is cesium (Cs). The primary ion energy is 14.5 keV. The secondary ion polarity is negative. When the detected p-type impurity is aluminum or boron, the primary ion beam is oxygen (O2). The primary ion energy is 8 keV. The secondary ion polarity is positive.

[0080] Next, the method for distinguishing between p-type and n-type regions will be explained.

[0081] In the method for distinguishing between p-type and n-type regions, SCM (Scanning Capacitance Microscope) is used. The measuring device is, for example, the NanoScope IV manufactured by Bruker AXS. SCM is a method for visualizing the carrier concentration distribution in a semiconductor. Specifically, a silicon probe coated with metal is used to scan the surface of the sample. A high-frequency voltage is then applied to the sample. This excites the majority carriers, modulating the electrostatic capacitance of the system. The frequency of the high-frequency voltage applied to the sample is 100 kHz, and the voltage is 4.0 V.

[0082] Figure 2 It is along Figure 1 A cross-sectional view of line II-II. (See diagram.) Figure 2 As shown, viewed in a direction perpendicular to the second principal surface 2, the second superjunction region 25 extends, for example, along the second direction 102. From another viewpoint, the long side direction of the second superjunction region 25 is, for example, the second direction 102. The short side direction of the second superjunction region 25 is, for example, the first direction 101. Viewed in a direction perpendicular to the second principal surface 2, the second superjunction region 25 can be substantially rectangular. Viewed in a direction perpendicular to the second principal surface 2, the first superjunction region 12 can surround the second superjunction region 25.

[0083] The first direction 101 and the second direction 102 are each parallel to the second principal plane 2. The third direction 103 is perpendicular to the second principal plane 2. The first direction 101 is, for example, the <11-20> direction. The second direction 102 is, for example, the <1-100> direction. The third direction 103 is, for example, the <1-100> direction. <0001> Direction. The first direction 101 is, for example, the direction obtained by projecting the <11-20> direction onto the first principal surface 1. The second direction 102 is, for example, the direction obtained by projecting the <1-100> direction onto the first principal surface 1. The third direction 103 can be, for example, relative to... <0001> The direction in which it is tilted.

[0084] Figure 3 yes Figure 2 An enlarged schematic diagram of region III. (See attached diagram.) Figure 3 As shown, the second region 22 has point defect 9. The energy level of point defect 9 is more than 0.5 eV deeper than Ec (the energy of the bottom of the conduction band) and more than 0.4 eV higher than Ev (the energy of the top of the valence band). Point defect 9 can possess what is called Z... 1 / 2 The first defect in the center is 7 and it is called EH 6 / 7 The second defect in the center is 8. Z 1 / 2 The central energy level is Ec (the energy of the bottom of the conduction band) -0.65 eV. EH 6 / 7 The central energy level is Ec (energy of the bottom of the conduction band) - 1.55 eV. The second region 22 can have both the first defect 7 and the second defect 8, or it can have only the first defect 7, or it can have only the second defect 8.

[0085] The point defect density in region 22 is 6 × 10⁻⁶. 12 cm -3 The above. The point defect density in the second region 22 could also be, for example, 8 × 10⁻⁶. 12 cm -3 The above can also be 10×10 12 cm -3 The above. The point defect density in the second region 22 can, for example, be 1×10⁻⁶. 14 cm -3 The point defect density in the second region 22 can also be, for example, 0.8 × 10⁻⁶. 14 cm -3 Below, it can also be 0.6×10 14 cm -3 It should be noted that, in the case that the second region 22 has the first defect 7 and the second defect 8, the point defect density of the second region 22 is the sum of the point defect densities of the first defect 7 and the second defect 8.

[0086] Next, the method for determining point defect density will be explained.

[0087] Point defect density can be determined using DLTS (Deep Level Transient Spectroscopy) and / or ICTS (Isothermal Capacitance Transient Spectroscopy). In DLTS, the time-varying change in bonding capacitance is obtained by changing the temperature while maintaining a constant pulse width. In ICTS, the time-varying change in bonding capacitance is obtained by changing the pulse width while maintaining a constant temperature. Although point defect information can be obtained using either DLTS or ICTS, using both methods provides more accurate information. For example, the Phystech FT1230 can be used as the measuring device. The sample temperature is in the range of 77K to 773K, and a pulse voltage is applied to obtain the time-varying change in bonding capacitance. The pulse voltage is +20V to -20V, and the pulse width is 1μs to 60s. Fourier transform and Laplace transform of the bonding capacitance transition can yield the point defect density and its energy levels.

[0088] (Second Implementation)

[0089] Next, the structure of the silicon carbide semiconductor device 200 according to the second embodiment will be described. The silicon carbide semiconductor device 200 of the second embodiment differs from the silicon carbide semiconductor device 200 of the first embodiment in that the trench 5 has a U-shaped structure; however, the other structural features are the same as those of the silicon carbide semiconductor device 200 of the first embodiment. Hereinafter, the description will focus on the structural differences from the silicon carbide semiconductor device 200 of the first embodiment.

[0090] Figure 4 This is a cross-sectional schematic diagram showing the structure of the silicon carbide semiconductor device 200 according to the second embodiment. Figure 4 As shown, in a cross-section perpendicular to the first main surface 1, the groove 5 is U-shaped. Specifically, the groove 5 has a side surface 3 and a bottom surface 4. The angle θ between the first main surface 1 and the side surface 3 is 90°. The side surface 3 extends approximately perpendicular to the first main surface 1. The bottom surface 4 extends approximately parallel to the first main surface 1. The junction between the side surface 3 and the bottom surface 4 may also be rounded.

[0091] (Third Implementation)

[0092] Next, the structure of the silicon carbide semiconductor device 200 according to the third embodiment will be described. The silicon carbide semiconductor device 200 of the third embodiment differs from the silicon carbide semiconductor device 200 of the first embodiment in that it has a planar structure; however, its other structures are the same as those of the silicon carbide semiconductor device 200 of the first embodiment. Hereinafter, the description will focus on the structure that differs from that of the silicon carbide semiconductor device 200 of the first embodiment.

[0093] Figure 5 This is a cross-sectional schematic diagram showing the structure of the silicon carbide semiconductor device 200 according to the third embodiment. Figure 5 As shown, the silicon carbide semiconductor device 200 of the third embodiment is planar. A gate insulating film 51 is disposed on a first main surface 1. The gate insulating film 51 may be connected to the third impurity region 30, the second portion 42, and the current extension region 14 at the first main surface 1. The second portion 42 may form part of the first main surface 1. The current extension region 14 may form part of the first main surface 1. The gate electrode 63 may be facing the third impurity region 30, the second portion 42, and the current extension region 14 respectively.

[0094] (Manufacturing method of silicon carbide semiconductor device)

[0095] Next, the manufacturing method of the silicon carbide semiconductor device of this embodiment will be described.

[0096] like Figure 6 As shown, the manufacturing method of the silicon carbide semiconductor device 200 in this embodiment mainly includes the process of preparing a silicon carbide substrate (S10: Figure 6 The process of forming the first electrode (S20: Figure 6 and the process of forming the second electrode (S30: Figure 6 ).like Figure 7 As shown, the process for preparing the silicon carbide substrate (S10): Figure 6 The main process includes preparing a silicon carbide single crystal substrate (S11: Figure 7 The process of forming the second region (S12: Figure 7 ) and activation annealing process (S13: Figure 7 ).

[0097] First, the process of preparing the silicon carbide single crystal substrate is carried out (S11: Figure 7 A silicon carbide single-crystal substrate 15 is prepared by slicing, for example, a silicon carbide ingot (not shown) manufactured using a sublimation method. Figure 8As shown, the silicon carbide single-crystal substrate 15 has a third main surface 6 and a second main surface 2. The second main surface 2 is located on the opposite side of the third main surface 6. The polytype of the silicon carbide constituting the silicon carbide single-crystal substrate 15 is, for example, 4H. The polytype can also be 6H, 15R, or 3C. 6H is hexagonal. 15H is rhombohedral. 3C is cubic.

[0098] Next, a buffer layer 11 is formed. The buffer layer 11 is formed on the silicon carbide single-crystal substrate 15 using a CVD (Chemical Vapor Deposition) method, for example, a mixture of silane (SiH4) and propane (C3H8) as the feed gas and hydrogen (H2) as the carrier gas. (Refer to...) Figure 9 During epitaxial growth, n-type impurities, such as nitrogen, are introduced into the buffer layer 11.

[0099] Next, the process of forming the second region 22 is carried out (S12: Figure 7 A first epitaxial layer 70 is formed on buffer layer 11 by a CVD method, for example, using a mixture of silane and propane as the feed gas and hydrogen as the carrier gas. (Ref.) Figure 10 During epitaxial growth, n-type impurities, such as nitrogen, are introduced into the first epitaxial layer 70. The first epitaxial layer 70 has an n-type conductivity type. The concentration of n-type impurities in the first epitaxial layer 70 can be lower than the concentration of n-type impurities in the buffer layer 11.

[0100] Next, a mask layer (not shown) with openings is formed on the first epitaxial layer 70. Then, p-type impurity ions capable of imparting p-type characteristics, such as aluminum ions, are implanted into the first epitaxial layer 70. This forms a first p-type region 251 (see reference). Figure 11 In the first epitaxial layer 70, the region where the first p-type region 251 is not formed becomes the first n-type region 121. The first p-type region 251 is adjacent to the first n-type region 121. The first p-type region 251 becomes part of the second region 22.

[0101] Next, a second epitaxial layer 71 is formed. The second epitaxial layer 71 is formed on the first epitaxial layer 70 using, for example, a CVD method employing a mixture of silane and propane as the feed gas and, for example, hydrogen as the carrier gas (see reference). Figure 12 During epitaxial growth, n-type impurities, such as nitrogen, are introduced into the second epitaxial layer 71. The second epitaxial layer 71 has an n-type conductivity type.

[0102] Next, a process of implanting p-type impurity ions is performed. For example, a mask layer (not shown) with an opening is formed on the second epitaxial layer 71. Then, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the second epitaxial layer 71. This forms a second p-type region 252. The second p-type region 252 is formed in a manner connected to the first p-type region 251 (see reference). Figure 13 The second p-type region 252 becomes part of the second region 22. In the second epitaxial layer 71, the region where the second p-type region 252 is not formed becomes the second n-type region 122.

[0103] As described above, the formation process of the n-type epitaxial layer and the ion implantation process of the p-type impurities are performed alternately. This forms a superstructure having a first superjunction region 12 and a second superjunction region 25. Using the same method, a first bonding region 13, a second bonding region 24, a third bonding region 23, and a current-spreading region 14 are formed.

[0104] The second superjunction region 25, the second bonding region 24, and the third bonding region 23 constitute the second region 22. The second region 22 is formed by ion implantation. The impurity concentration of the second region 22 is 6 × 10⁻⁶. 16 cm -3 That's all. Specifically, the second superjunction region 25 is formed by ion implantation. The second bonding region 24 can be formed by ion implantation. The third bonding region 23 can be formed by ion implantation. By forming p-type impurities through ion implantation, the point defect density of the second region 22 becomes higher.

[0105] Next, an n-type epitaxial layer is formed on the current-spreading region 14 and the third bonding region 23. For the n-type epitaxial layer, p-type impurity ions, such as aluminum ions, which can impart a p-type structure, are implanted onto the surface of the n-type epitaxial layer. This forms the second portion 42 of the first region 21.

[0106] The current-extending region 14, the first junction region 13, and the first superjunction region 12 constitute the first impurity region 10. The first impurity region 10 is formed, for example, by epitaxial growth at a temperature of 1500°C or higher and 1750°C or lower. The epitaxial growth temperature of the first impurity region 10 can be, for example, 1550°C or higher, or 1600°C or higher. The epitaxial growth temperature of the first impurity region 10 can be, for example, 1725°C or lower, or 1700°C or lower. By performing epitaxial growth at a high temperature, the point defect density of the second region 22 becomes higher.

[0107] Next, n-type impurities, such as phosphorus (P), are ion implanted onto the entire surface of the epitaxial layer. This forms a third impurity region 30. Then, a mask layer (not shown) with openings is formed on the region where the first portion 41 of the first region 21 is formed. Next, p-type impurity ions, such as aluminum ions, capable of imparting p-type properties, are implanted into the third impurity region 30. This forms a first portion 41 adjoining the third impurity region 30. Through the above, a first region 21 having a first portion 41 and a second portion 42 is formed. The first region 21 can be formed by ion implantation. Specifically, the first portion 41 can be formed by ion implantation. Similarly, the second portion 42 can be formed by ion implantation.

[0108] Next, the activation annealing process (S13) is carried out. Figure 7 The activation annealing process can be performed at temperatures above 1600°C and below 1850°C. The activation annealing temperature can also be above 1650°C or above 1700°C. Alternatively, the activation annealing temperature can be below 1800°C or below 1750°C. By performing activation annealing at high temperatures, the point defect density in the second region 22 increases. The activation annealing time is, for example, approximately 30 minutes. The preferred atmosphere for activation annealing is an inert gas atmosphere, such as an Ar atmosphere.

[0109] As described above, a silicon carbide substrate 100 is prepared. The silicon carbide substrate 100 has a first main surface 1, a second main surface 2, a first impurity region 10, a second impurity region 20, and a third impurity region 30. The second main surface 2 is located opposite the first main surface 1. The first impurity region 10 constitutes at least a portion of the second main surface 2 and has a first conductivity type. The second impurity region 20 constitutes at least a portion of the first main surface 1, is disposed in contact with the first impurity region 10, and has a second conductivity type different from the first conductivity type. The third impurity region 30 is disposed in contact with the second impurity region 20 in a manner separated from the first impurity region 10, and has a first conductivity type. The second impurity region 20 includes a first region 21 and a second region 22. The second region 22 is located between the first region 21 and the second main surface 2 and is in contact with the first region 21 (see reference). Figure 14 ).

[0110] Next, the process of forming trench 5 is performed. For example, a mask (not shown) is formed on the first main surface 1, which is composed of the third impurity region 30 and the first portion 41. Using the mask, a portion of the third impurity region 30, a portion of the second portion 42, and a portion of the current extension region 14 are removed by etching. As an etching method, reactive ion etching, especially inductively coupled plasma reactive ion etching, can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF6) or a mixture of SF6 and oxygen (O2) as the reactive gas can be used. By etching, a recess having a side portion that is substantially perpendicular to the first main surface 1 and a bottom portion that is continuously disposed with respect to the side portion and substantially parallel to the first main surface 1 is formed in the area where trench 5 should be formed.

[0111] Next, thermal etching is performed in the recess. Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas with at least one type of halogen atom while a mask is formed on the first main surface 1. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere may contain, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixture of chlorine and oxygen is used as the reactive gas, and thermal etching is performed at a heat treatment temperature, for example, between 800°C and 900°C. It should be noted that the reactive gas may also include a carrier gas in addition to the aforementioned chlorine and oxygen. For example, nitrogen, argon, or helium can be used as the carrier gas.

[0112] Through the above-described thermal etching, a trench 5 is formed on the first main surface 1 of the silicon carbide substrate 100 (see reference). Figure 15 The trench 5 has a side surface 3 and a bottom surface 4. The side surface 3 is composed of a third impurity region 30, a second portion 42, and a current spreading region 14. The bottom surface 4 is composed of the current spreading region 14. The angle θ between the first main surface 1 and the side surface 3 is, for example, 115° or more and 135° or less. Then, the mask is removed from the first main surface 1.

[0113] Next, the process of forming the gate insulating film 51 is performed. For example, the gate insulating film 51 is formed by thermally oxidizing the silicon carbide substrate 100, which is in contact with the third impurity region 30, the second portion 42, the current spreading region 14, and the first portion 41. Specifically, the silicon carbide substrate 100 is heated in an oxygen-containing atmosphere, for example, at a temperature of 1300°C or higher and 1400°C or lower. As a result, the gate insulating film 51 in contact with the first main surface 1, the side surface 3, and the bottom surface 4 is formed.

[0114] Next, the silicon carbide substrate 100 can be heat-treated (NO annealing) in a nitric oxide (NO) atmosphere. During NO annealing, the silicon carbide substrate 100 is held, for example, at a temperature between 1100°C and 1400°C for about 1 hour. This introduces nitrogen atoms into the interface region between the gate insulating film 51 and the second portion 42. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

[0115] After NO annealing, Ar annealing can also be performed using argon (Ar) as the atmosphere gas. The heating temperature for Ar annealing is, for example, higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about 1 hour. As a result, the formation of interface states in the interface region between the gate insulating film 51 and the second portion 42 is further suppressed. It should be noted that other inert gases such as nitrogen can be used instead of Ar as the atmosphere gas.

[0116] Next, the process of forming the gate electrode 63 is performed. The gate electrode 63 is formed on the gate insulating film 51. The gate electrode 63 is formed, for example, by LP-CVD (Low Pressure Chemical Vapor Deposition). The gate electrode 63 is formed so as to face the third impurity region 30, the second portion 42, and the current extension region 14 respectively.

[0117] Next, the process of forming the separation insulating film 52 is performed. Specifically, the separation insulating film 52 is formed in a manner that covers the gate electrode 63 and is in contact with the gate insulating film 51. The separation insulating film 52 is formed, for example, by a CVD method. The separation insulating film 52 is, for example, a material containing silicon dioxide. A portion of the separation insulating film 52 may also be formed inside the trench 5.

[0118] Next, the process of forming the first electrode is carried out (S20: Figure 6 For example, by etching in a manner that forms openings in the separating insulating film 52 and the gate insulating film 51, the third impurity region 30 and the first portion 41 are exposed from the separating insulating film 52 and the gate insulating film 51 into the openings. Next, an electrode layer 60 is formed at the first main surface 1, in contact with the third impurity region 30 and the first portion 41. The electrode layer 60 is formed, for example, by sputtering. The electrode layer 60 is, for example, made of a material comprising Ti, Al, and Si.

[0119] Next, alloying annealing is performed. The electrode layer 60, which is in contact with the third impurity region 30 and the first portion 41, is held at a temperature of, for example, 900°C or higher and 1100°C or lower for about 5 minutes. As a result, at least a portion of the electrode layer 60 reacts with the silicon contained in the silicon carbide substrate 100 to form a silicide. As a result, an electrode layer 60 is formed that is ohmically bonded to the third impurity region 30. The electrode layer 60 may also be ohmically bonded to the first portion 41. Through the above, a first electrode 61 is formed at the first main surface 1 that is in contact with the second impurity region 20 and the third impurity region 30 respectively.

[0120] Next, the process of forming the second electrode is carried out (S30: Figure 6 For example, a second electrode 62 is formed on the second main surface 2 by sputtering. The second electrode 62 is, for example, a drain electrode. The second electrode 62 is in contact with the first impurity region 10 at the second main surface 2. The second electrode 62 is, for example, made of a material containing NiSi or TiAlSi. Based on the above, the MOSFET 200 of the first embodiment ( Figure 1 )Finish.

[0121] It should be noted that, in the above description, the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type. In this case, p-type impurities are referred to as n-type impurities and n-type impurities as p-type impurities. Furthermore, in the above description, a MOSFET is used as an example to illustrate the silicon carbide semiconductor device 200 of this disclosure, but the silicon carbide semiconductor device 200 of this disclosure is not limited to a MOSFET. The silicon carbide semiconductor device 200 of this disclosure may also be, for example, a PN diode, an IGBT (Insulated Gate Bipolar Transistor), etc.

[0122] Example

[0123] (Sample preparation)

[0124] Next, the embodiments will be described. First, a silicon carbide semiconductor device 200 of sample 1 and a silicon carbide semiconductor device 200 of sample 2 were prepared. The silicon carbide semiconductor device 200 of sample 1 is configured as a V-groove MOSFET with a superjunction structure. Specifically, the silicon carbide semiconductor device 200 of sample 1 is configured as a V-groove MOSFET of the first embodiment. In the silicon carbide semiconductor device 200 of sample 1, the concentration of p-type impurities in the second superjunction region 25 is set to 1×10⁻⁶. 17 cm -3 Furthermore, the concentration of p-type impurities in the channel region (part 2, 42) was set to 2 × 10⁻⁶. 18 cm -3In the silicon carbide semiconductor device 200 of Sample 1, the characteristic on-resistance is 0.63 mΩcm. 2 Furthermore, the withstand voltage is 1170V. The silicon carbide semiconductor device 200 of Sample 2 is configured as a V-groove MOSFET without a superstructure. In the silicon carbide semiconductor device 200 of Sample 2, the concentration of p-type impurities in the channel region (second part 42) is set to 1×10⁻⁶. 16 cm -3 .

[0125] (Evaluation Method)

[0126] Next, the diode characteristics between the drain electrode (second electrode 62) and the source electrode (first electrode 61) were measured. Specifically, the drain current density was measured while varying the drain voltage under multiple temperature conditions. In the silicon carbide semiconductor device 200 of Sample 1, the temperature conditions were set to 25°C, 50°C, 75°C, 100°C, 125°C, 150°C, and 175°C. In the silicon carbide semiconductor device 200 of Sample 2, the temperature conditions were set to 25°C, 93°C, 122°C, and 162°C.

[0127] (Evaluation Results)

[0128] Figure 16 This is a graph showing the relationship between drain current density and drain voltage in the silicon carbide semiconductor device 200 of Sample 1. Figure 17 This is a graph showing the relationship between drain current density and drain voltage in the silicon carbide semiconductor device 200 of sample 2. (See figure) Figure 17 As shown, in the silicon carbide semiconductor device 200 of sample 2, the slope of the drain current density relative to the drain voltage increases with increasing temperature. On the other hand, as... Figure 16 As shown, in the silicon carbide semiconductor device 200 of sample 1, even with increased temperature, the slope of the drain current density relative to the drain voltage did not change significantly. In other words, it was confirmed that, compared to the silicon carbide semiconductor device 200 of sample 2, the silicon carbide semiconductor device 200 of sample 1 can suppress temperature variations in diode characteristics.

[0129] It should be noted that base plane dislocations present in the silicon carbide substrate 100 sometimes become stacking defects due to the energy required for the recombination of minority carriers. If stacking defects exist in the silicon carbide semiconductor device 200, the breakdown voltage of the silicon carbide semiconductor device 200 drops significantly. To avoid the recombination of minority carriers, it is desirable to reduce the number of minority carriers. The low temperature change of the diode characteristics (i.e., low temperature change of the resistance) in the silicon carbide semiconductor device 200 of Sample 1 indicates that conductivity modulation occurs almost non-existently. Therefore, in the silicon carbide semiconductor device 200 of Sample 1, the number of minority carriers can be considered very low. Therefore, in the silicon carbide semiconductor device 200 of Sample 1, the incidental effect of suppressing the generation of stacking defects and thus suppressing the drop in breakdown voltage can be expected.

[0130] It should be considered that the embodiments and examples disclosed herein are illustrative and not restrictive in all respects. The scope of the invention is defined not by the foregoing description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0131] Explanation of reference numerals in the attached figures

[0132] 1 First main surface, 2 Second main surface, 3 Side surface, 4 Bottom surface, 5 Trench, 6 Third main surface, 7 First defect, 8 Second defect, 9 Point defect, 10 First impurity region, 11 Buffer layer, 12 First superjunction region, 13 First bonding region, 14 Current spread region, 15 Single crystal substrate, 20 Second impurity region, 21 First region, 22 Second region, 23 Third bonding region, 24 Second bonding region, 25 Second superjunction region, 30 Third impurity region, 41 First part, 4 2. Second part, 51 gate insulating film, 52 separation insulating film, 60 electrode layer, 61 first electrode, 62 second electrode, 63 gate electrode, 64 wiring layer, 70 first epitaxial layer, 71 second epitaxial layer, 100 silicon carbide substrate, 101 first direction, 102 second direction, 103 third direction, 121 first n-type region, 122 second n-type region, 200 silicon carbide semiconductor device (MOSFET), 251 first p-type region, 252 second p-type region.

Claims

1. A silicon carbide semiconductor device comprising: a first impurity region of a first conductivity type; a second impurity region of a second conductivity type different from the first conductivity type, disposed so as to be separated from the first impurity region, and having the first conductivity type; a third impurity region of the first conductivity type, disposed so as to be in contact with the second impurity region while being separated from the first impurity region; a first electrode in contact with each of the second impurity region and the third impurity region at a first main surface; and a second electrode in contact with the first impurity region at a second main surface, wherein the second impurity region includes a first region and a second region between the first region and the second main surface and in contact with the first region, wherein the first impurity region has a buffer layer and a first super junction region disposed on the buffer layer, wherein the second region has a second super junction region disposed on the buffer layer, wherein the first super junction region and the second super junction region constitute a super junction region, wherein the first super junction region is in contact with the second super junction region, wherein, in a case where a short side direction of the second super junction region parallel to the second main surface is taken as a first direction, the first super junction region and the second super junction region are alternately arranged in the first direction, wherein the second region further has a second junction region disposed on the second super junction region, a central width of the second junction region being expanded in a larger manner than respective widths of upper and lower portions, and a third junction region in contact with the second junction region and the first region, respectively, wherein a maximum width of the second junction region is larger than a width of the second super junction region in the first direction. A silicon carbide substrate has a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, and a second impurity region constituting at least a part of the first main surface, disposed in contact with the first impurity region, and having a second conductivity type different from the first conductivity type.

2. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a planar type.

3. The silicon carbide semiconductor device according to claim 1, wherein a trench is provided in the silicon carbide substrate, wherein the trench has a side surface in contact with each of the first impurity region, the second impurity region, and the third impurity region, and a bottom surface connected to the side surface and in contact with the first impurity region.

4. The silicon carbide semiconductor device according to claim 3, wherein a shape of the trench is a U shape in a cross section perpendicular to the first main surface.

5. The silicon carbide semiconductor device according to claim 3, wherein a shape of the trench is a V shape in a cross section perpendicular to the first main surface.

6. The silicon carbide semiconductor device according to claim 1, wherein the first main surface is a (000-1) surface or a surface inclined at an angle of 8° or less with respect to the (000-1) surface. The impurity concentration of the first region is 6 x 1018cm-3 16 cm -3 The impurity concentration of the second region is 6 x 1018cm-3 16 cm -3 The impurity concentration of the second region is 6 x 1018cm-3 7. The silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of the first region is higher than an impurity concentration of the second region.

8. The silicon carbide semiconductor device according to claim 7, wherein the first region has a first junction region and a second junction region, the first junction region being disposed on the buffer layer, the second junction region being disposed on the first junction region.

9. The silicon carbide semiconductor device according to claim 1, wherein, in a case where a drain current density is measured while a drain voltage is varied under a temperature condition of 25°C to 175°C, a slope of the drain current density with respect to the drain voltage becomes smaller as the temperature rises.

10. A silicon carbide semiconductor device comprising: a first impurity region of a first conductivity type; a second impurity region of a second conductivity type different from the first conductivity type, disposed so as to be separated from the first impurity region, and having the first conductivity type; a third impurity region of the first conductivity type, disposed so as to be in contact with the second impurity region while being separated from the first impurity region; a first electrode in contact with each of the second impurity region and the third impurity region at a first main surface; and a second electrode in contact with the first impurity region at a second main surface, wherein the second impurity region includes a first region and a second region between the first region and the second main surface and in contact with the first region, wherein the first impurity region has a buffer layer and a first super junction region disposed on the buffer layer, wherein the second region has a second super junction region disposed on the buffer layer, wherein the first super junction region and the second super junction region constitute a super junction region, wherein the first super junction region is in contact with the second super junction region, wherein, in a case where a short side direction of the second super junction region parallel to the second main surface is taken as a first direction, the first super junction region and the second super junction region are alternately arranged in the first direction, wherein the second region further has a second junction region disposed on the second super junction region, a central width of the second junction region being expanded in a larger manner than respective widths of upper and lower portions, and a third junction region in contact with the second junction region and the first region, respectively, wherein a maximum width of the second junction region is larger than a width of the second super junction region in the first direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The impurity concentration of the first region is 1 x 1018 19 cm -3 The following. ​ ​ The amount of change in the slope of the drain current density with respect to the drain voltage is 20 A / (cm 2 × V) or less when the temperature is raised from 25°C to 175°C. ​ A silicon carbide substrate has a first main surface, a second main surface opposite to the first main surface, a first impurity region constituting at least a part of the second main surface and having a first conductivity type, and a second impurity region constituting at least a part of the first main surface, disposed in contact with the first impurity region, and having a second conductivity type different from the first conductivity type. a third impurity region disposed so as to be continuous with the second impurity region in a manner separated from the first impurity region, and having the first conductivity type; a first electrode continuous with each of the second impurity region and the third impurity region at the first main surface; and a second electrode continuous with the first impurity region at the second main surface, the second impurity region includes a first region and a second region between the first region and the second main surface and continuous with the first region, The point defect density of the first region is 6 x 10 12 cm -3 The impurity concentration of the second region is 6 x 10 16 cm -3 above, The point defect density of the first region is 6 x 1010 12 cm -3 or more and 1 x 1010 14 cm -3 The point defect density of the second region is 6 x 1010 12 cm -3 or more and 1 x 1010 14 cm -3 or less, the second region has a second super junction region, a second junction region, and a third junction region, the second super junction region is disposed on a buffer layer that the first impurity region has, a width of the second super junction region in a first direction parallel to the second main surface and as a short side direction of the second super junction region is smaller than a width of the buffer layer, a height of the second super junction region in a third direction perpendicular to the second main surface is larger than the width of the second super junction region in the first direction, the second junction region is disposed on the second super junction region, the second junction region expands in a manner that a central width is larger than each of upper and lower widths, a maximum width of the second junction region in the first direction is larger than the width of the second super junction region, and the third junction region is continuous with each of the second junction region and the first region, the third junction region is between the second junction region and the first region in the third direction.

11. The silicon carbide semiconductor device according to claim 10, the silicon carbide semiconductor device is a planar type.

12. The silicon carbide semiconductor device according to claim 10, a trench is provided in the silicon carbide substrate, the trench has a side surface continuous with each of the first impurity region, the second impurity region, and the third impurity region, and a bottom surface continuous with the side surface and continuous with the first impurity region.

13. The silicon carbide semiconductor device according to claim 12, in a cross section perpendicular to the first main surface, a shape of the trench is a U shape.

14. The silicon carbide semiconductor device according to claim 12, in a cross section perpendicular to the first main surface, a shape of the trench is a V shape.

15. The silicon carbide semiconductor device according to claim 10, the first main surface is a (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane.

16. The silicon carbide semiconductor device according to claim 10, an impurity concentration of the first region is higher than an impurity concentration of the second region.

17. The silicon carbide semiconductor device according to claim 16, The impurity concentration of the first region is 1 x 1018 19 cm -3 The following.

18. The silicon carbide semiconductor device according to claim 10, in a case where a drain current density is measured while a drain voltage is varied under a temperature condition of 25°C to 175°C, a slope of the drain current density with respect to the drain voltage becomes smaller as the temperature rises, The amount of change in the slope of the drain current density with respect to the drain voltage is 20 A / (cm 2 × V) or less when the temperature is raised from 25°C to 175°C.

19. A manufacturing method of a silicon carbide semiconductor device, comprising: a step of preparing a silicon carbide substrate having a first main surface; a second main surface opposite to the first main surface; a first impurity region constituting at least a part of the second main surface and having a first conductivity type, a second impurity region constituting at least a part of the first main surface and provided in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a third impurity region provided in contact with the second impurity region in a manner separated from the first impurity region and having the first conductivity type; a first electrode formed at the first main surface in contact with each of the second impurity region and the third impurity region, a second electrode formed at the second main surface in contact with the first impurity region, the second impurity region includes a first region and a second region between the first region and the second main surface and in contact with the first region, the first region is formed by ion implantation, the second region has a second super junction region, a second junction region, and a third junction region, the second super junction region is provided on a buffer layer possessed by the first impurity region, a width of the second super junction region in a first direction parallel to the second main surface and as a short side direction of the second super junction region is smaller than a width of the buffer layer, a height of the second super junction region in a third direction perpendicular to the second main surface is larger than the width of the second super junction region in the first direction, the second junction region is provided on the second super junction region, the second junction region expands in a manner that a central width is larger than respective widths of upper and lower portions, a maximum width of the second junction region in the first direction is larger than the width of the second super junction region, and the third junction region is in contact with each of the second junction region and the first region, the third junction region is located between the second junction region and the first region in the third direction. The impurity concentration of the first region is 6 x 1018cm-3 16 cm -3 The above, 20. The method for manufacturing a silicon carbide semiconductor device according to claim 19, The impurity concentration of the second region is 6 x 1018cm-3 16 cm -3 The above, The point defect density of the first region is 6 x 1010 12 cm -3 The point defect density of the first region is 6 x 1010 14 cm -3 The point defect density of the first region is 6 x 1010 12 cm -3 The point defect density of the first region is 6 x 1010 14 cm -3 The point defect density of the first region is 6 x 1010 the second region is formed by ion implantation.

21. The method for manufacturing a silicon carbide semiconductor device according to claim 19 or 20, the first impurity region is formed by epitaxial growth under a temperature condition of 1500°C or higher and 1750°C or lower.

22. The method for manufacturing a silicon carbide semiconductor device according to claim 19 or 20, the process of preparing the silicon carbide substrate includes an activation annealing process, the activation annealing process is performed under a temperature condition of 1600°C or higher and 1850°C or lower.

23. The method for manufacturing a silicon carbide semiconductor device according to claim 19 or 20, a slope of a drain current density with respect to a drain voltage becomes smaller as a temperature rises in a case where the drain current density is measured while a drain voltage is varied under a temperature condition of 25°C to 175°C, ​ ​ The amount of change in the slope of the drain current density with respect to the drain voltage is 20 A / (cm 2 ×V) or less when the temperature is raised from 25°C to 175°C.

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