Precharge timing control

Abstract

This application relates to precharge timing control. An example device includes first and second memories and a precharge timing circuit. The first memory includes a first storage bank containing a first data line and a second storage bank containing a second data line. The second memory includes a third storage bank containing a third data line and a fourth storage bank containing a fourth data line. The precharge timing circuit provides first, second, third, and fourth precharge activation signals. The first, second, third, and fourth signals respectively activate the precharge of the first, second, third, and fourth data lines. The precharge timing circuit provides the first and second precharge activation signals at different times. The precharge timing circuit provides the third and fourth precharge activation signals at different times.

Description

Technical Field

[0001] This application relates to a pre-charge timing control. Background Technology

[0002] High data reliability, high memory access speed, reduced chip size, and low power consumption are the characteristics required for semiconductor memories.

[0003] In memory, information can be written to or read from individual memory cells via data lines. For example, memory can be volatile memory, such as dynamic random access memory (DRAM), static RAM (SRAM), flash memory, etc.

[0004] Data lines transmit high or low voltage regions to / from memory cells to read or write data. For example, a high voltage region might correspond to a "1" in digital data, and a low voltage might correspond to a "0". To reduce the time spent setting the data lines to high or low voltage regions for memory access operations, the data lines can be pre-charged when the memory is powered on during data transfer to / from memory cells. Pre-charging the data lines during memory initialization can result in extreme peak currents within the memory. Such extreme peak currents can have undesirable effects on memory or external devices coupled to the memory. Summary of the Invention

[0005] In one aspect, this application provides an apparatus comprising: a first memory channel including: a first memory interface; a first storage container including a first data line; and a second storage container including a second data line; a second memory channel including: a second memory interface independent of the first memory interface; a third storage container including a third data line; and a fourth storage container including a fourth data line; and a precharge timing circuit configured to provide a first precharge activation signal, a second precharge activation signal, a third precharge activation signal, and a fourth precharge activation signal, wherein the first precharge activation signal is configured to activate precharge of the first data line, the second precharge activation signal is configured to activate precharge of the second data line, the third precharge activation signal is configured to activate precharge of the third data line, and the fourth precharge activation signal is configured to activate precharge of the fourth data line, wherein the precharge timing circuit provides the first and second precharge activation signals at different times, and provides the third and fourth precharge activation signals at different times.

[0006] In another aspect, this application discloses an apparatus comprising: a first storage cell array including a first storage cell and a second storage cell; a second storage cell array including a third storage cell and a fourth storage cell; a first data line, a second data line, a third data line, and a fourth data line, respectively included in the first storage cell, the second storage cell, the third storage cell, and the fourth storage cell; a first precharge circuit, a second precharge circuit, a third precharge circuit, and a fourth precharge circuit configured to precharge the first data line, the second data line, the third data line, and the fourth data line, respectively; and a precharge timing circuit configured to provide a first precharge activation signal, a second precharge activation signal, a third precharge activation signal, and a fourth precharge activation signal to the first precharge circuit, the second precharge circuit, the third precharge circuit, and the fourth precharge circuit, respectively, wherein the precharge timing circuit is configured to provide a second precharge activation signal at least partially in response to the first precharge activation signal, and wherein the precharge timing circuit is configured to provide a fourth precharge activation signal at least partially in response to the third precharge activation signal.

[0007] In another aspect, this application further provides an apparatus comprising: a first die including a first storage group and a second storage group; a second die including a third storage group; a first data line, a second data line, and a third data line, respectively included in the first storage group, the second storage group, and the third storage group; and a first circuit located on the first die, the first circuit being configured to receive a first power-on signal and further configured to at least partially respond to the first power-on signal by providing a first precharge activation signal and a second precharge activation signal, the first precharge activation signal being configured to activate precharge of the first data line, and the second precharge activation signal being configured to activate the second data line. The data line is precharged, wherein a second precharge activation signal has a first precharge activation signal having a first delay; a second circuit located on a second die, the second circuit being configured to provide a third precharge activation signal, the third precharge activation signal being configured to activate precharge of a third data line; and a via configured to receive the second precharge activation signal from the first circuit, and further configured to provide the second precharge activation signal having a second delay to the second circuit, wherein the second circuit is configured to receive the second precharge activation signal having a second delay from the via, and further configured to provide the third precharge activation signal at least partially in response to the second activation signal having a second delay. Attached Figure Description

[0008] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 This is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4 This is a schematic diagram of a semiconductor device including a plurality of dies according to an embodiment of the present disclosure.

[0012] Figure 5 This is a layout diagram of a semiconductor device including multiple dies according to an embodiment of the present disclosure. Detailed Implementation

[0013] Various embodiments of this disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and details in which embodiments of this disclosure may be practiced. The detailed description includes sufficient detail to enable those skilled in the art to practice the embodiments of this disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0014] Information can be stored as charge on individual memory cells of a memory element. The magnitude of the charge (e.g., charge value) indicates the stored information. In some embodiments, the magnitude of the charge and thus the information on the memory cell can be determined by measuring the voltage across the memory cell and / or detecting the current from the memory cell. High voltage regions or currents can be associated with higher magnitudes of charge, while low voltages or currents can be associated with lower magnitudes of charge. High voltages (e.g., 3V, 5V) can be associated with high logic states and / or "1", while lower voltages (e.g., 0V) can be associated with low logic states and / or "0". To write a "1" to a memory cell, a memory line (e.g., a data line) can be charged to a high voltage to charge the memory cell to the appropriate level. To write a "0" to a memory cell, a memory line can be charged to a lower voltage. Although the examples described herein associate low voltages with low logic states and "0" and high voltages with high logic states and "1", it should be understood that these associations can be different without departing from the principles of this disclosure.

[0015] In some memory applications, it may be necessary to share one or more components between memory arrays and / or portions of a memory array within a memory device. For example, error correction circuitry, library logic, amplifiers, and / or input / output lines may need to be shared. Sharing one or more components can reduce chip size and / or the number of components required in the memory device. However, in some cases, sharing one or more components can increase the impedance experienced by the shared components. During some memory operations, the increased impedance can increase the rise time of one or more memory lines. That is, it can increase the time it takes for the line to charge to a higher voltage (e.g., 3V, 5V) compared to a lower voltage (e.g., 0V). For example, during a write operation where a higher charge value (e.g., writing a "1") is to be written to a memory cell, the memory line (e.g., a data line) coupled to the memory cell must be charged to a higher voltage. When the memory line is long (e.g., shared between memory arrays or portions of memory arrays), charging the memory line to a higher voltage can take a longer time. This can make writing information (e.g., data) corresponding to higher charge values ​​(e.g., "1") take longer than writing information corresponding to lower charge values ​​(e.g., "0").

[0016] To reduce the time difference between writing to higher and lower charge values, one or more pre-charge circuits can be included to pre-charge the memory lines to an appropriate voltage before writing information. One or more pre-charge circuits can be activated at different timings to reduce peak current.

[0017] Figure 1 This is a block diagram of a semiconductor device 1 according to an embodiment of the present disclosure. For example, the semiconductor device 1 may be a DRAM integrated into a single semiconductor chip. The semiconductor device 1 may be mounted on an external substrate 2, such as a memory module substrate, motherboard, etc. Figure 1 As shown, semiconductor device 1 may include memory 10 and memory 10'. Memory 10 is configurable to be accessed via memory channel (Ch_A), and memory 10' is configurable to be accessed via memory channel (Ch_B). Memory channels (Ch_A) and (Ch_B) are independent of each other. Memory 10 and memory 10' may include similar circuit systems. Therefore, some of the detailed descriptions of memory 10' are omitted for brevity. In some embodiments, semiconductor device 1 may be a chip including memories 10 and 10'.

[0018] Memory 10 includes a memory cell array 11. Memory cell array 11 includes multiple repositories for memory channels (Ch_A). Memory 10' includes a memory cell array 11'. Memory cell array 11' includes multiple repositories for memory channels (Ch_B). Each repository includes multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of word lines WL is performed by row decoder 12, and the selection of bit lines BL is performed by column decoder 13. Figure 1 In one embodiment, row decoder 12 includes a corresponding row decoder for each repository of the memory channel (Ch_A), and column decoder 13 includes a corresponding column decoder for each repository. Sensing amplifier 18 is coupled to a corresponding bit line BL and connected to a local I / O line pair LIOT / B. Data read from bit line BL is amplified by sensing amplifier 18 and provided to sub-amplifier transfer gate 19 via the complementary local data line (LIOT / B) of the memory channel (Ch_A). Sub-amplifier transfer gate 19 can act as a switch to form a conductive path between the appropriate LIOT / B and the appropriate shared complementary master data line (MIOT / B) of the memory channel (Ch_A). Read data from the memory channel (Ch_A) can be delivered via the conductive path provided by sub-amplifier transfer gate 19 through the local data line LIOT / B to the master data line MIOT / B to the read / write amplifier 15 of the memory channel (Ch_A), which provides data to the input / output (I / O) circuitry 17 of the memory channel (Ch_A). Write data received from the memory channel (Ch_A) from the IO circuit 17 is provided to the read / write amplifier 15 and, via the main data line MIOT / B, the sub-amplifier transfer gate 19, and the complementary local data line LIOT / B, to the sense amplifier 18, and written into the memory cell MC coupled to the bit line BL. The main data line MIOT / B of the memory channel (Ch_A) can be pre-charged after the memory 10 is powered on. Similarly, read data from the memory channel (Ch_B) can be provided via a conductive path provided by the sub-amplifier transfer gate 19' through the local data line LIOT / B to the main data line MIOT / B to the read / write amplifier 15' of the memory channel (Ch_B), which provides the data to the input / output (IO) circuit 17' of the memory channel (Ch_B). Write data received from the memory channel (Ch_B) from the IO circuit 17' is provided to the read / write amplifier 15' and then to the sense amplifier 18' via the main data line MIOT / B, the sub-amplifier transfer gate 19', and the complementary local data line LIOT / B, and written into the memory cell MC coupled to the bit line BL. The main data line pair MIOT / B of the memory channel (Ch_B) can be pre-charged after the memory 10' is powered on.

[0019] Turning to the explanation of the plurality of external terminals included in memory 10, the plurality of external terminals include command / address terminal 21, clock terminal 23, data terminal 24, and power terminals 25 and 26. Input signal block 41 may include command / address terminal 21. In some instances, command / address terminal 21 and signal lines coupled to command / address terminal 21 may include a first set of terminals and signal lines configured to receive command signals and a separate second set of terminals and signal lines configured to receive address signals. In other instances, terminal 21 and signal lines associated with command / address terminal 21 may include common terminals and signal lines configured to receive both command signals and address signals. Input signal block 41 may include clock terminal 23 containing an input buffer. According to one embodiment, data interface block 42 includes data terminal 24, which will be described later. Data terminal 24 may be coupled to an output buffer for memory read operations. Alternatively, data terminal 24 may be coupled to an input buffer for memory read / write access. Figure 1 Examples of dynamic random access memory (DRAM) are shown; however, any device having external terminals for signal input / output may include external terminals as embodiments of this disclosure.

[0020] Memory 10 accessed via memory channel (Ch_A) includes a memory interface. For example, the memory interface may include address / command input circuitry 31. Memory 10' accessed via memory channel (Ch_B) includes another memory interface independent of the memory interface of memory channel (Ch_A). For example, the other memory interface may include address / command input circuitry 31'. Address / command input circuitry 31 and 31' include similar circuitry. Therefore, for brevity, a detailed description of address / command input circuitry 31' is omitted. Address / command input circuitry 31 receives address signal ADD and library address signal BADD from command / address terminal 21 and transmits address signal ADD and library address signal BADD to address decoder 32. Address decoder 32 decodes address signal ADD and provides decoded row address signal XADD to row decoder 12 and decoded column address signal YADD to column decoder 13. Address decoder 32 may also receive library address signal BADD and provide library address signal BADD to row decoder 12 and column decoder 13.

[0021] Address / command input circuit 31 can receive command signals from an external source, such as a memory controller, at command / address terminal 21. Address / command input circuit 21 can provide the command signals to command decoder 34. Command decoder 34 can decode the command signals and generate various internal command signals. Internal command signals can be used to control the operation and timing of various circuits in memory 10. For example, internal command signals may include row command signals, such as activation commands for selecting word lines and column command signals, such as read or write commands for selecting bit lines.

[0022] Therefore, when an activation command is issued using a row address and a read command is supplied to a column address in a timely manner, read data is read from the memory cell MC in the memory cell array 11 specified by these row and column addresses. The read data DQ is output externally from the data terminal 24 via the read / write amplifier 15 and the I / O circuit 17. Similarly, when a write command is issued and supplied to the row and column addresses in a timely manner, and then write data DQ is supplied to the data terminal 24, the write data DQ is supplied to the memory cell array 11 via the input / output circuit 17 and the read / write amplifier 15 and written to the memory cell MC specified by the row and column addresses.

[0023] External clock signals CK_t and CK_c are supplied to clock terminals 23. These external clock signals CK_t and CK_c are complementary and supplied to clock input circuit 35. Clock input circuit 35 receives external clock signals CK_t and CK_c and generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to internal clock generator 36, and thus a phase-controlled internal clock signal ICLK is generated based on the received internal clock signal ICLK and the clock enable signal CKE from command input circuit 33. Although not limited thereto, a DLL circuit can be used as internal clock generator 36. The phase-controlled internal clock signal LCLK is supplied to input / output circuit 17 and used as a timing signal for determining the output timing of read data DQ. The internal clock signal ICLK is also supplied to timing generator 37, and thus various internal clock signals can be generated.

[0024] Power terminal 25 is supplied with power potentials VDD1, VDD2, and VSS. These power potentials VDD1, VDD2, and VSS are supplied to internal power circuitry 39. Internal power circuitry 39 generates various internal potentials VPP, VOD, VARY, VPERI, etc. Internal potential VPP is primarily used in the line decoder 12, internal potentials VOD and VARY are primarily used in the sense amplifier 18 included in the memory cell array 11, and internal potential VPERI is used in many other circuit blocks. After power detection, internal power circuitry 39 can provide a power potential (e.g., VDD2) and a power-on signal that triggers the main data line to precharge the MIOT / B. In some embodiments, internal power circuitry 39 can provide a power potential (e.g., VDD2) to read / write amplifier 15.

[0025] Power terminal 26 is supplied with power potentials VDDQ and VSSQ. These power potentials VDDQ and VSSQ are supplied to input / output circuit 17. Power potentials VDDQ and VSSQ can be the same potentials as those supplied to power terminal 25, VDD1 and VSS, respectively. However, power potentials VDDQ and VSSQ are used in input / output circuit 17 to prevent power supply noise generated by input / output circuit 17 from propagating to other circuit blocks.

[0026] Figure 2 This is a layout diagram of a portion of a semiconductor device 200 according to an embodiment of the present disclosure. Figure 2 This may be a plan view of the layout of a semiconductor device 200, including circuitry and array regions. The semiconductor device 200 may be one of the embodiments of this disclosure. Figure 1 Semiconductor device 1. Semiconductor device 200 may be a memory die, such as a DRAM die, in some embodiments of this disclosure.

[0027] Semiconductor device 200 may include multiple repositories. Figure 2 In the example shown, semiconductor device 200 includes sixteen storage libraries 201 to 216. Each library can be accessed via a corresponding main data line MIO. In semiconductor device 200, it can provide... Figure 1 In some embodiments of the semiconductor device 1, repositories 201 to 204 and 209 to 212 are included in memory cell array 11 and are accessible to MIOT / B via the main data line of memory channel (Ch_A) in memory 10. Repositories 205 to 208 and 213 to 216 are included in memory cell array 11' and are accessible to MIOT / B via the main data line of memory channel (Ch_B) in memory 10'. Each repository 201 to 216 may include one or more sections. Figure 2For example, library 201 may include sections 201a and 201b. One or more sections of each library may share one or more circuits. For instance, one or more sections may share a main amplifier (DSA) and library logic. Figure 2 For example, portions 201a and 201b of repository 201 may share the main amplifier (DSA) 261 and repository logic 281. Furthermore, the error correction circuitry (ECC) system may be shared by multiple repositories. For instance, in... Figure 2 In the example shown, one ECC may be shared by repositories 201 to 204 and 209 to 212. Another ECC may be shared by repositories 205 to 208 and 213 to 216. In some embodiments, each main amplifier DSA of each repository may be coupled to a corresponding main data line MIO. The main data line MIO of each repository may extend from each main amplifier DSA to the sub-amplifier transfer gate of each repository. In some embodiments, the sub-amplifier transfer gate may be... Figure 1 The sub-amplifier transfer gate 19 or 19'. In some embodiments, the main amplifier DSA may include read and / or write amplifiers for one or more segments of the memory and / or portions of the memory array. In some embodiments, the read and / or write amplifiers in the main amplifier (DSA) may include... Figure 1 The read and write amplifiers 15 are located within the main amplifier DSA. In some embodiments, the read and / or write amplifiers in the main amplifier DSA may include those in... Figure 1 The read and write amplifiers are located in section 15'. Figure 2 In the example shown, one or more portions of each of the repositories 201 to 216 may share read and / or write amplifiers included in the corresponding shared master amplifier DSA.

[0028] exist Figure 2In this memory, portions of each of the repositories 201 to 216 may share corresponding pre-charge circuits 241 to 256. For example, portions 201a and 201b of repository 201 may share pre-charge circuit 241. In some embodiments, pre-charge circuits 241 to 244 and 249 to 252 for corresponding repositories 201 to 204 and 209 to 212 may be housed in memory 10. In some embodiments, pre-charge circuits 241 to 244 and 249 to 252 may be housed in memory cell array 11. In some embodiments, pre-charge circuits 241 to 244 and 249 to 252 within memory 10 may be housed outside memory cell array 11. In some embodiments, pre-charge circuits 245 to 248 and 253 to 256 for corresponding repositories 205 to 208 and 213 to 216 may be housed in memory 10'. In some embodiments, pre-charge circuits 245 to 248 and 253 to 256 may be housed in memory cell array 11'. In some embodiments, precharge circuits 245 to 248 and 253 to 256 within memory 10' may be disposed outside memory cell array 11'. Precharge circuits 241 to 256 may each be coupled to data lines MIO of corresponding memory cell arrays 201 to 216, and precharge the corresponding data lines MIO to a precharge voltage when activated.

[0029] The semiconductor device 200 may further include precharge timing circuits 220A and 220B. In some embodiments, the precharge timing circuit 220A may be disposed in... Figure 1 The power supply circuit 39 is located between the read and write amplifier 15. In some embodiments, the precharge timing circuit 220A may be included in... Figure 1 The read and write amplifier 15 is located within the amplifier. In some embodiments, the precharge timing circuit 220A may be housed in... Figure 1 The read and write amplifiers 15 are located between the memory cell array 11. In some embodiments, a portion of the precharge timing circuit 220A may be included in the main amplifier DSA of the repositories 201 to 204 and 209 to 212. In some embodiments, the precharge timing circuit 220A may be located between the library logic of repositories 201 to 204 and 209 to 212.

[0030] The precharge timing circuit 220A can provide a precharge activation signal to the precharge circuits 241-244 and 249-252 for corresponding repositories 201-204 and 209-212. In some embodiments, the precharge activation signal can be a power-on signal with different corresponding delays. The precharge activation signal can be used to perform precharge operations with different timings on the main data lines MIO of repositories 201-204 and 209-212. In some embodiments, the voltage power-on circuit 240A can be included in the power supply circuit 39. In some embodiments, the precharge circuits 241-244 and 249-252 can receive a power supply potential (e.g., VDD2) from the power supply circuit, such as... Figure 1 The power supply circuit 39 or 39' shown is illustrated. The voltage-applying circuit 240A can detect whether the power supply circuit 39 has started receiving power supply potentials (e.g., VDD1 and VDD2). In response to the detection, the voltage-applying circuit 240A can provide an active power-applying signal (e.g., a positive active power-applying signal). For example, the active power-applying signal can be at a logic high level. In some embodiments, the precharge timing circuit 220A can receive power-applying signals from the voltage-applying circuit 240A for storage repositories 201 to 204 and 209 to 212 accessed via memory channels (Ch_A).

[0031] The precharge timing circuit 220A may include series-coupled delay circuits 221 to 223. In some embodiments, each of the delay circuits 221 to 223 may have a delay Δ1. The precharge timing circuit 220A may also include delay circuits 231 to 234. Delay circuits 231 to 233 may be coupled to the input nodes of delay circuits 221 to 223, respectively. Delay circuit 234 may be coupled to the output node of delay circuit 223. In some embodiments, each of the delay circuits 231 to 234 may have a delay Δ2. Delay Δ1 may be longer than delay Δ2.

[0032] exist Figure 2In this example, the precharge timing circuit 220A can provide the power-on signal received from the voltage power-on circuit 240A as a precharge activation signal to the precharge circuit 241. The precharge circuit 241 can initiate a precharge operation on the main data line MIO of the storage bank 201 in response to the precharge activation signal. The precharge timing circuit 220A can also provide the power-on signal received from the voltage power-on circuit 240A to delay circuits 221 and 231. The delay circuit 231 can provide a power-on signal delayed by a delay Δ2 as another precharge activation signal to the precharge circuit 249. The precharge circuit 249 can initiate a precharge operation on the main data line MIO of the storage bank 209 in response to the precharge activation signal, which is a power-on signal delayed by a delay Δ2. Therefore, the precharge operation on the main data line MIO of the storage bank 209 can occur after the precharge operation on the main data line MIO of the storage bank 201 has occurred.

[0033] Delay circuit 221 can provide a power-on signal delayed by delay Δ1 as another pre-charge activation signal to pre-charge circuit 242. Pre-charge circuit 242 can initiate a pre-charge operation on the main data line MIO of repository 202 in response to the power-on signal delayed by delay Δ1. Because delay Δ1 is longer than delay Δ2, the pre-charge operation on the main data line MIO of repository 202 can occur after the pre-charge operation on the main data line MIO of repository 209 has occurred. Delay circuit 232 can provide a power-on signal with a delay Δ1 further delayed by delay Δ2 to pre-charge circuit 250. Pre-charge circuit 250 can initiate a pre-charge operation on the main data line MIO of repository 210 in response to a power-on signal delayed by delay Δ1+Δ2. Therefore, the pre-charge operation on the main data line MIO of repository 210 can occur after the pre-charge operation on the main data line MIO of repository 202 has occurred.

[0034] Delay circuit 222 can provide a delayed power-on signal, further delayed by a delay Δ1, to precharge circuit 243, as well as delay circuits 223 and 233. Precharge circuit 243 and delay circuits 223 and 233 can receive a power-on signal delayed by a delay of 2 × Δ1 (Δ1 multiplied by 2) from delay circuit 222. Precharge circuit 243 can initiate a precharge operation on the main data line MIO of repository 203 in response to the power-on signal delayed by a delay of 2 × Δ1. Because a delay of 2 × Δ1 is longer than a delay of Δ1 + Δ2, the precharge operation on the main data line MIO of repository 203 can occur after the precharge operation on the main data line MIO of repository 210 has occurred. Delay circuit 233 can provide a power-on signal with a delay of 2 × Δ1, further delayed by a delay Δ2, to precharge circuit 251. The precharge circuit 251 can initiate a precharge operation on the main data line MIO of the storage bank 211 in response to a power-on signal that is delayed by (2×Δ1)+Δ2. Therefore, the precharge operation on the main data line MIO of the storage bank 211 can occur after the precharge operation on the main data line MIO of the storage bank 203 has occurred.

[0035] Delay circuit 223 can provide a delayed power-on signal, further delayed by a delay Δ1, from delay circuit 222 to precharge circuit 244 and delay circuit 234. Precharge circuit 244 and delay circuit 234 can receive a power-on signal delayed by a delay of 3 × Δ1 (Δ1 multiplied by 3) from delay circuit 223. Precharge circuit 244 can initiate a precharge operation on the main data line MIO of repository 204 in response to a power-on signal delayed by a delay of 3 × Δ1. Because a delay of 3 × Δ1 is longer than a delay of (2 × Δ1) + Δ2, the precharge operation on the main data line MIO of repository 204 can occur after the precharge operation on the main data line MIO of repository 211 has occurred. Delay circuit 234 can provide a power-on signal with a delay of 3 × Δ1, further delayed by a delay Δ2, to precharge circuit 252. The precharge circuit 252 can initiate a precharge operation on the main data line MIO of the storage bank 212 in response to a power-on signal delayed by (3×Δ1)+Δ2. Therefore, the precharge operation on the main data line MIO of the storage bank 212 can occur after the precharge operation on the main data line MIO of the storage bank 204 has occurred. Since the precharge timing circuit 220A can provide power-on signals with different delays (e.g., activating the power-on signal at different timings) to the precharge circuits 241 to 244 and 249 to 252, the precharge operation on the main data lines MIO of the storage banks 201 to 204 and 209 to 212 can be performed by the precharge circuits 241 to 244 and 249 to 252 at different timings.

[0036] In some embodiments, the pre-charge timing circuit 220B may be disposed in Figure 1The power supply circuit 39' is located between the read and write amplifier 15'. In some embodiments, the precharge timing circuit 220B may be included in... Figure 1 The read and write amplifiers are located at 15'. In some embodiments, the precharge timing circuit 220B may be located at... Figure 1 The read and write amplifiers 15' and the memory cell array 11' are located between them. In some embodiments, a portion of the precharge timing circuitry 220B may be included in the main amplifier DSA of the repositories 205 to 208 and 213 to 216. In some embodiments, the precharge timing circuitry 220B may be located between the library logic of repositories 205 to 208 and 213 to 216.

[0037] The precharge timing circuit 220B can activate precharge activation signals to precharge circuits 245-248 and 253-256 for corresponding memory banks 205-208 and 213-216. In some embodiments, the precharge activation signal can be a power-on signal with a different corresponding delay. The precharge activation signal can be used to perform precharge operations with different timings on the main data lines MIO coupled to memory banks 205-208 and 213-216. The voltage power-on circuit 240B can be included in the power supply circuit 39'. In some embodiments, the precharge circuits 245-248 and 253-256 can receive a power supply potential (e.g., VDD2) from the power supply circuit, such as... Figure 1 The power supply circuit 39 or 39' is shown in the diagram. The voltage-applying circuit 240B can detect whether the power supply circuit 39' has started receiving power supply potentials (e.g., VDD1 and VDD2). In response to the detection, the voltage-applying circuit 240B can provide an active power-applying signal. In some embodiments, the pre-charge timing circuit 220B can receive the power-applying signal for storage repositories 205 to 208 and 213 to 216 accessed via memory channels (Ch_B) from the voltage-applying circuit 240B.

[0038] Precharge timing circuits 220A and 220B include similar circuit systems. Therefore, for the sake of brevity, a detailed description of precharge timing circuit 220B is omitted. The precharge timing circuit can provide an applied power signal as a precharge timing signal to precharge circuit 248. Precharge timing circuit 220B can provide applied power signals with delays Δ1, 2×Δ1, and 3×Δ1 as precharge activation signals to precharge circuits 247, 246, and 245, respectively. Precharge timing circuit 220B can provide applied power signals with delays Δ2, Δ1+Δ2, (2×Δ1)+Δ2, and (3×Δ1)+Δ2 as precharge activation signals to precharge circuits 256, 255, 254, and 253, respectively. Because the precharge timing circuit 220B can provide received power-on signals with different delays (e.g., activating power-on signals at different timings) to the precharge circuits 245 to 248 and 253 to 256, the precharge operation of the main data lines MIO of the repositories 205 to 208 and 213 to 216 can be performed by the precharge circuits 245 to 248 and 253 to 256 at different timings. In some embodiments, Figure 1 The power supply circuits 39 and 39' can simultaneously begin receiving power supply potentials (e.g., VDD1 and VDD2). One of the pre-charge circuits 241 to 244 and 249 to 252 and one of the pre-charge circuits 245 to 248 and 253 to 256 can simultaneously perform pre-charge operations.

[0039] Figure 3 This is a layout diagram of a portion of a semiconductor device 300 according to an embodiment of the present disclosure. Figure 3 This may be a plan view of the layout of a semiconductor device 300, including circuitry and array regions. The semiconductor device 300 may be as described in some embodiments of this disclosure. Figure 1 Semiconductor device 1. Semiconductor device 300 may be a memory die, such as a DRAM die.

[0040] Semiconductor device 300 may include multiple repositories. Figure 3 In the example shown, the semiconductor device 300 includes sixteen storage repositories 301 to 316. Each repository is accessible via a corresponding main data line MIO. In some embodiments, repositories 301 to 304 and 309 to 312 included in the memory cell array 11 can be accessed by... Figure 1 The main data line of the memory channel (Ch_A) in the memory 10 of the semiconductor device 1 is accessed via MIOT / B. Repositories 305 to 308 and 213 to 216 in the memory cell array 11' are accessible via MIOT / B through the main data line of the memory channel (Ch_B) in the memory 10'. Each repository 201 to 216 may include one or more sections. Figure 3For example, repository 301 may include sections 301a and 301b. One or more sections of each repository may share one or more memory elements. For instance, one or more sections may share a main amplifier (DSA) and repository logic. Figure 3 For example, portions 301a and 301b of repository 301 may share the main amplifier (DSA) 361 and repository logic 381. Furthermore, the error correction circuitry (ECC) system may be shared by multiple repositories. For instance, in... Figure 3 In the example shown, one ECC may be shared by repositories 301 to 304 and 309 to 312. Another ECC may be shared by repositories 305 to 308 and 313 to 316. In some embodiments, each main amplifier DSA of each repository may be coupled to a corresponding main data line MIO. The main data line MIO of each repository may extend from each main amplifier DSA to the sub-amplifier transfer gate of each repository. In some embodiments, the sub-amplifier transfer gate may be... Figure 1 The sub-amplifier transfer gate 19 or 19'. In some embodiments, the main amplifier DSA may include read and / or write amplifiers for one or more segments of the memory and / or portions of the memory array. In some embodiments, the read and / or write amplifiers in the main amplifier DSA may include... Figure 1 The read and write amplifiers 15 are located within the main amplifier DSA. In some embodiments, the read and / or write amplifiers in the main amplifier DSA may include those in... Figure 1 The read and write amplifiers are located in section 15'. Figure 3 In the example shown, one or more portions of each of the repositories 301 to 316 may share read and / or write amplifiers included in the corresponding shared main amplifier DSA.

[0041] exist Figure 3 In this configuration, one or more portions of each of the repositories 301 to 316 may share corresponding pre-charge circuits 341 to 356. For example, one or more portions 301a and 301b of repository 301 may share pre-charge circuit 241.

[0042] In some embodiments, pre-charge circuits 341 to 344 and 349 to 352 for corresponding repositories 301 to 304 and 309 to 312 may be housed in memory 10. In some embodiments, pre-charge circuits 341 to 344 and 349 to 352 may be housed in memory cell array 11. In some embodiments, pre-charge circuits 341 to 344 and 349 to 352 within memory 10 may be housed outside memory cell array 11. In some embodiments, pre-charge circuits 345 to 348 and 353 to 356 for corresponding repositories 305 to 308 and 313 to 316 may be housed in memory 10'. In some embodiments, pre-charge circuits 345 to 348 and 353 to 356 may be housed in memory cell array 11'.

[0043] In some embodiments, precharge circuits 345 to 348 and 353 to 356 within memory 10' may be disposed outside memory cell array 11'. Precharge circuits 341 to 356 may each be coupled to data lines MIO of corresponding memory cell arrays 301 to 316, and precharge the corresponding data lines MIO to a precharge voltage when activated.

[0044] The semiconductor device 300 may further include a pre-charge timing circuit 320. In some embodiments, the pre-charge timing circuit 320 may be disposed near... Figure 1 The power supply circuits in areas 39 and 39'. For example, the areas may include... Figure 1 The regions between the power supply circuit 39 and the read / write amplifier 15, and between the power supply circuit 39' and the read / write amplifier 15'. In some embodiments, the precharge timing circuit 320 may be included in... Figure 1 The read and write amplifiers 15 and 15' are located within the circuit. In some embodiments, the precharge timing circuit 320 may be positioned close to the circuit. Figure 1 The regions of storage cell arrays 11 and 11'. The regions may include... Figure 1 The regions between read and write amplifiers 15 and memory cell array 11, and between read and write amplifiers 15' and memory cell array 11'. In some embodiments, a portion of precharge timing circuitry 320 may be included in the main amplifier DSA for repositories 301 to 316. In some embodiments, precharge timing circuitry 320 may be located between the library logic of repositories 301 to 316.

[0045] The precharge timing circuit 320 can provide a precharge activation signal to precharge circuits 341 to 356 for corresponding repositories 301 to 316. In some embodiments, the precharge activation signal can be a power-on signal with a different corresponding delay. The precharge activation signal can be used to perform a precharge operation with different timings on the main data lines MIO of repositories 301 to 316. In some embodiments, a voltage power-on circuit 340A for memory channels (Ch_A) can be included in power supply circuit 39. The voltage power-on circuit 340A can detect whether power supply circuit 39 has started receiving power supply potentials (e.g., VDD1 and VDD2). In response to the detection, the voltage power-on circuit 340A can provide a power-on signal in an active state. In some embodiments, the precharge timing circuit 320 can receive power-on signals for repositories 301 to 304 and 309 to 312 accessed through memory channels (Ch_A) from the voltage power-on circuit 340A. The precharge timing circuit 320 can include series-coupled delay circuits 321 to 324. In some embodiments, each of delay circuits 321 to 324 may have a delay Δ1. The pre-charge timing circuit 320 may include delay circuits 331 to 334. Delay circuits 331 to 334 are respectively coupled to the input nodes of delay circuits 321 to 324. In some embodiments, each of delay circuits 331 to 334 may have a delay Δ2. Delay Δ1 may be longer than delay Δ2. Figure 3 In this example, the pre-charge timing circuit 320 can provide the power-on signal from the voltage power-on circuit 340A to the pre-charge circuit 341 as a pre-charge activation signal. The pre-charge timing circuit 320 can provide power-on signals with delays Δ1, 2×Δ1, and 3×Δ1 as pre-charge activation signals from delay circuits 321 to 323 to pre-charge circuits 342, 343, and 344, respectively. The pre-charge timing circuit 320 can provide power-on signals with delays Δ2, Δ1+Δ2, (2×Δ1)+Δ2, and (3×Δ1)+Δ2 as pre-charge activation signals to pre-charge circuits 349, 350, 351, and 352, respectively.

[0046] In some embodiments, a voltage-applying circuit 340B for the memory channel (Ch_B) may be included in the power supply circuit 39'. The voltage-applying circuit 340B may detect whether the power supply circuit 39' has begun receiving power supply potentials (e.g., VDD1 and VDD2). In response to the detection, the voltage-applying circuit 340B may provide an active power-applying signal. In some embodiments, a pre-charge timing circuit 320 may receive from the voltage-applying circuit 340B power-applying signals for storage repositories 305 to 308 and 313 to 316 accessed via the memory channel (Ch_B). The pre-charge timing circuit 320 may include a time adjustment circuit 360. The timing adjustment circuit 360 controls the activation of the pre-charge circuits 345 to 348 and 353 to 356 for repositories 305 to 308 and 313 to 316 accessed via memory channels (Ch_B) after the activation of most (if not all) of the pre-charge circuits 341 to 344 and 349 to 352 for repositories 301 to 304 and 309 to 312 accessed via memory channels (Ch_A). Therefore, the pre-charge operation of the main data lines MIO for repositories 305 to 308 and 313 to 316 accessed via memory channels (Ch_B) can be performed after most of the pre-charge operations of the main data lines MIO for repositories 301 to 304 and 309 to 312 accessed via memory channels (Ch_A).

[0047] The timing adjustment circuit 360 can receive a power-on signal from a voltage-applying circuit 340B having some delay (e.g., delay due to a buffer that prevents signal attenuation). The timing adjustment circuit 360 can also receive a power-on signal from a voltage-applying circuit 340A having a delay from a delay circuit 324. In some embodiments, the delay may be the sum of the delays of the series-coupled delay circuits 321 to 324. The timing adjustment circuit 360 can provide an active power-on signal from the voltage-applying circuit 340B in response to an active power-on signal from the voltage-applying circuit 340A as a pre-charge activation signal. In some embodiments, Figure 1The power supply circuits 39 and 39' can simultaneously begin receiving power supply potentials (e.g., VDD1 and VDD2). In such embodiments, the precharge activation signal can be a power-on signal from a voltage-applying circuit 340A with a delay of 4 × Δ1. In some embodiments, the timing circuit 360 may include an inverting AND gate (NAND) logic circuit that receives the power-on signal from the voltage-applying circuit 340A with a delay of 4 × Δ1 and the power-on signal from a voltage-applying circuit 340B with some delay. The timing circuit 360 may also include an inverter that provides an inverted output signal of the NAND logic circuit as the precharge activation signal. The circuitry of the timing circuit 360 is not limited to a combination of logic circuits. Any variation of the circuitry that can serve as the timing circuit 360 may be included in the precharge timing circuit 320.

[0048] The precharge timing circuit 320 may include series-coupled delay circuits 325 to 327. In some embodiments, each of the delay circuits 325 to 327 may have a delay Δ1. The precharge timing circuit 320 may also include delay circuits 335 to 338. Delay circuits 335 to 337 may be coupled to the input nodes of delay circuits 325 to 327, respectively. Delay circuit 338 may be coupled to the output node of delay circuit 327. In some embodiments, each of the delay circuits 335 to 338 may have a delay Δ2. Figure 3In this example, the precharge circuit 345 may receive a precharge activation signal from the timing circuit 360. The precharge circuit 345 may initiate a precharge operation on the main data line MIO of the storage bank 305 in response to the precharge activation signal (e.g., a power-on signal from a voltage power-on circuit 340A with a delay of 4×Δ1). The timing circuit 360 may also provide the precharge activation signal to delay circuits 325 and 335. The delay circuit 335 may provide a precharge activation signal delayed by a delay of Δ2 to the precharge circuit 353. The precharge circuit 353 may initiate a precharge operation on the main data line MIO of the storage bank 313 in response to a precharge activation signal delayed by a delay of Δ2 (e.g., a power-on signal from a voltage power-on circuit 340A with a delay of (4×Δ1)+Δ2). Therefore, the precharge operation on the main data line MIO of the storage bank 313 may occur after the precharge operation on the main data line MIO of the storage bank 305 has occurred. Delay circuit 325 can provide a precharge activation signal delayed by delay Δ1 to precharge circuit 346. Precharge circuit 346 can initiate precharge operation on main data line MIO of storage bank 306 in response to a precharge activation signal delayed by delay Δ1 (e.g., a power-on signal from voltage power-on circuit 340A with a delay of 5×Δ1). Because delay Δ1 is longer than delay Δ2, precharge operation on main data line MIO of storage bank 306 can occur after precharge operation on main data line MIO of storage bank 313 has occurred. Delay circuit 336 can receive a precharge activation signal delayed by delay Δ1 from delay circuit 325. Delay circuit 336 can provide a precharge activation signal delayed by delay Δ1+Δ2 to precharge circuit 354. The precharge circuit 354 can initiate a precharge operation on the main data line MIO of the storage bank 314 in response to a precharge activation signal delayed by Δ1+Δ2 (e.g., a power-on signal from the voltage power-on circuit 340A with a delay of (5×Δ1)+Δ2). Therefore, the precharge operation on the main data line MIO of the storage bank 314 can occur after the precharge operation on the main data line MIO of the storage bank 306. The delay circuit 326 can provide a precharge activation signal delayed by 2×Δ1 to the precharge circuit 347. The precharge circuit 347 can initiate a precharge operation on the main data line MIO of the storage bank 307 in response to a precharge activation signal delayed by 2×Δ1 (e.g., a power-on signal from the voltage power-on circuit 340A with a delay of 6×Δ1). Because delay Δ1 is longer than delay Δ2, the precharge operation on the main data line MIO of the storage bank 307 can occur after the precharge operation on the main data line MIO of the storage bank 314. The delay circuit 337 can receive a precharge activation signal delayed by 2×Δ1 from the delay circuit 326. The delay circuit 337 can provide a precharge activation signal delayed by (2×Δ1)+Δ2 to the precharge circuit 355.The precharge circuit 355 can initiate a precharge operation on the main data line MIO of the storage bank 315 in response to a precharge activation signal delayed by (2×Δ1)+Δ2 (e.g., a power-on signal from the voltage power-on circuit 340A with a delay of (6×Δ1)+Δ2). Therefore, the precharge operation on the main data line MIO of the storage bank 315 can occur after the precharge operation on the main data line MIO of the storage bank 307 has occurred. The delay circuit 327 can provide a precharge activation signal delayed by 3×Δ1 to the precharge circuit 348. The precharge circuit 348 can initiate a precharge operation on the main data line MIO of the storage bank 308 in response to a precharge activation signal delayed by 3×Δ1 (e.g., a power-on signal from the voltage power-on circuit 340A with a delay of 7×Δ1). Because delay Δ1 is longer than delay Δ2, the precharge operation on the main data line MIO of the storage bank 308 can occur after the precharge operation on the main data line MIO of the storage bank 315 has occurred. Delay circuit 338 can receive a precharge activation signal delayed by 3×Δ1 from delay circuit 327. Delay circuit 338 can provide a precharge activation signal delayed by (3×Δ1)+Δ2 to precharge circuit 356. Precharge circuit 356 can initiate a precharge operation on the main data line MIO of repository 316 in response to a precharge activation signal delayed by (3×Δ1)+Δ2 (e.g., a power-on signal from voltage power-on circuit 340A with a delay of (7×Δ1)+Δ2). Therefore, the precharge operation on the main data line MIO of repository 316 can occur after the precharge operation on the main data line MIO of repository 308 has occurred.

[0049] Because when the power-on signal from voltage power-on circuit 340A is active, timing circuit 360 provides an active power-on signal from voltage power-on circuit 340B, pre-charge timing circuit 320 can provide power-on signals with different delays to pre-charge circuits 341 to 356, including providing power-on signals with longer delays to pre-charge circuits 345 to 348 and 353 to 356. Therefore, the pre-charge operation of the main data lines MIO of repositories 301 to 316 can be performed by pre-charge circuits 341 to 356 at different timings. Therefore, the peak current in semiconductor device 300 can be reduced by performing pre-charge operations on the main data lines MIO of multiple repositories at different timings.

[0050] Figure 4 This is a schematic diagram of a memory device 400 including a plurality of dies 401 according to embodiments of the present disclosure. In some embodiments of the present disclosure, one or more of the dies 401 may include Figure 1 Memory 10 Figure 2 Semiconductor devices 200 Figure 3Semiconductor device 300 or a combination thereof. In Figure 4 In some embodiments, the number of dies 401 is eight. Modifications that change the number of dies to a different number instead of a plurality of dies 401 are within the scope of this disclosure. In some embodiments, the plurality of dies 401 may be identical to each other with respect to circuit configuration and operation. For example, the plurality of dies 401 may be a stack of dies including a master die (die 0) 402 and a plurality of slave dies (die 1 to die 7) 403. In some embodiments, the plurality of dies 401 may all have the same design (e.g., including the same circuitry). Dies 401 may be configured during post-manufacturing to function as a master die or a slave die. For example, the plurality of dies 401 may be configured such that one die can function as a master die 402 and another die can function as a slave die 403. Alternatively, in some embodiments, the master die 402 and the slave die 403 may be designed and manufactured as native master dies and native slave dies.

[0051] The master die 402 may serve as one or more pads 404 coupled to the package substrate 405 via one or more bonding lines 406. One or more bonding lines 16 may be coupled to pads (not shown) of the package substrate 405. Multiple bonding pads (PADs) from each of the dies 403 may be in a floating state, decoupled from the package substrate 405. The master die 401 may communicate with each of the dies 403 via vias (e.g., through-substrate or through-silicon vias) between adjacent dies of the multiple dies 401, said vias including vias 450A and 450B. A bump electrode 408 may be disposed on the outer surface of the package substrate 408. The bump electrode 408 may be coupled to power lines or signal channels.

[0052] Figure 5 This is a layout diagram of a semiconductor device 500 including multiple dies according to an embodiment of the present disclosure. Figure 5 In this configuration, multiple dies include die (die x) 510A and die (die x+1) 510B. In some embodiments, dies 510A and 510B may be included in multiple dies 401. Each die may include multiple library groups. Figure 5In the example shown, die 510A may include library groups 501A to 508A, and die 510B may include library groups 501B to 508B. Each library group may include multiple libraries. In some embodiments, a library group may include multiple repositories of storage cell arrays 11 and 11'. Each of the multiple library groups 501A to 508A may be divided into two regions. Die 510A may also include a region 522A located across the multiple library groups 501A to 508A, between the divided two regions of each library group. In some embodiments, region 522A may include a main amplifier DSA and library logic for library groups 501A to 508A. Similarly, each of the multiple library groups 501B to 508B may be divided into two regions. Die 510B may also include a region 522B located across the multiple library groups 501B to 508B, between the divided two regions of each library group. In some embodiments, zone 522B may include a main amplifier DSA and library logic for library groups 501B to 508B.

[0053] Semiconductor device 500 may further include a precharge timing circuit 520 containing circuits 520A and 520B. In some embodiments, circuits 520A and 520B may be disposed in regions 522A and 522B, respectively. Circuit 520A may provide a precharge activation signal to precharge circuits (not shown) for corresponding library groups 501A to 508A. In some embodiments, the precharge activation signal may be a power-on signal with a different corresponding delay. The precharge activation signal may be used to perform precharge operations with different timings on the main data lines MIO of library groups 501A to 508A. In some embodiments, die 510A may include a voltage-applying circuit 540A for die 510A. Voltage-applying circuit 540A may detect whether the power supply circuits for die 510A (not shown) have started receiving power supply potentials (e.g., VDD1 and VDD2). In response to the detection, voltage-applying circuit 540A may provide a power-on signal in an active state. In some embodiments, circuit 520A may receive power-on signals for library groups 501A to 508A from voltage-on circuit 540A. Circuit 520A may include series-coupled delay circuits 541A to 543A. Circuit 520A may also include series-coupled delay circuits 544A to 547A. In some embodiments, each of delay circuits 542A to 547A may have a delay Δ, and delay circuit 541A may have a delay Δ'. Circuit 520A may provide power-on signals having delays Δ', Δ+Δ', and (2×Δ)+Δ' as pre-charge activation signals from delay circuits 541A, 542A, and 543A to pre-charge circuits (not shown) for library groups 503A, 502A, and 501A, respectively. Circuit 520A can provide power-on signals with delays Δ, 2×Δ, 3×Δ, and 4×Δ as pre-charge activation signals from delay circuits 544A, 545A, 546A, and 547A, respectively, to pre-charge circuits (not shown) for library groups 505A, 506A, 507A, and 508A. Semiconductor device 500 may further include a via 550A having one end coupled to a first die 510A and another end coupled to a second die 510B. In some embodiments, via 550A may be a via TSV 450A (e.g., through-substrate or silicon via). Via 550A may be coupled to delay circuit 547A of circuit 520A. Via 550A can receive power-on signals with delays from delay circuit 547A and provide the received power-on signals to die 510B. In some embodiments, the delay may be the sum of the delays of the series-coupled delay circuits 544A, 545A, 546A, and 547A.

[0054] In some embodiments, die 510B may include a voltage-applying circuit 540B for die 510B. The voltage-applying circuit 540B can detect whether a power supply circuit (not shown) for die 510B has begun receiving power supply potentials (e.g., VDD1 and VDD2). In response to the detection, the voltage-applying circuit 540B can provide an active power-applying signal. In some embodiments, circuit 520B can receive power-applying signals for library groups 501B to 508B from the voltage-applying circuit 540B.

[0055] Circuit 520B may include timing circuitry 560. Timing circuitry 560 may be coupled to via 550A. Timing circuitry 560 controls the timing of the pre-charge operation of the main data lines MIO (not shown) of library groups 501B to 508B on die 510B to begin after most (if not all) of the pre-charge operation of the main data lines MIO (not shown) of library groups 501A to 508A on die 510A has been activated. Therefore, the pre-charge operation of the main data lines MIO of library groups 501B to 508B on die 510B may be performed after most of the pre-charge operation of the main data lines MIO of library groups 501A to 508A on die 510A.

[0056] The timing adjustment circuit 560 can receive a power-on signal from a voltage-applying circuit 540A having a delay from a delay circuit 547A via a via 550A. The timing adjustment circuit 560 can also receive a power-on signal from a voltage-applying circuit 540B. The timing adjustment circuit 560 can provide an active power-on signal from the voltage-applying circuit 540B in response to an active power-on signal from the voltage-applying circuit 540A as a pre-charge activation signal. In some embodiments, the timing adjustment circuit 560 may include NAND logic that receives the power-on signal from the delayed voltage-applying circuit 540A via 550A and the power-on signal from the voltage-applying circuit 540B. The timing adjustment circuit 560 may also include an inverter that provides an inverted NAND logic output signal as a pre-charge activation signal. The circuitry of the timing adjustment circuit 560 is not limited to this combination of logic circuits. Any variation of the circuitry that can serve as the timing adjustment circuit 560 may be included in circuitry 520B.

[0057] Circuit 520B may include series-coupled delay circuits 541B to 543B. Circuit 520B may also include series-coupled delay circuits 544B to 547B. In some embodiments, each of delay circuits 542B to 547B may have a delay Δ, and delay circuit 541B may have a delay Δ'. Circuit 520B may provide precharge activation signals with delays Δ', Δ+Δ', and (2×Δ)+Δ' from time adjustment circuit 560 as precharge activation signals to precharge circuits (not shown) for library groups 503B, 502B, and 501B, respectively, from delay circuits 541B, 542B, and 543B. Circuit 520B can provide precharge activation signals with delays Δ, 2×Δ, 3×Δ, and 4×Δ from delay circuits 544B, 545B, 546B, and 547B, respectively, to precharge circuits (not shown) for library groups 505B, 506B, 507B, and 508B. Circuit 520B may further include a via 550B. In some embodiments, via 550B may be a via TSV 450B (e.g., through-substrate or through-silicon via). Via 550B may be coupled to delay circuit 547B. Via 550B can receive an output signal from delay circuit 547B and provide the received power-on signal to another die (die x+2) (not shown).

[0058] Because when the power-on signal from voltage power-on circuit 540A is active, timing circuit 560 can provide an active power-on signal from voltage power-on circuit 540B. Precharge timing circuit 520 can provide power-on signals with varying delays to the precharge circuits for library groups 501A to 508A and 501B to 508B, including providing power-on signals with longer delays to the precharge circuits for library groups 501B to 508B. Therefore, the precharge operation of the main data lines MIO of library groups 501A to 508A and the main data lines MIO of library groups 501B to 508B can be performed at different timings. Precharge timing circuit 520 may include circuitry that includes timing adjustment circuitry and vias in each die in a manner similar to die 510B. The main data lines MIO of the library groups of multiple dies can be precharged at different times. Therefore, the peak current within the semiconductor device 500 can be reduced by performing a pre-charge operation on the main data line MIO of multiple repository groups on multiple dies at different timings.

[0059] Although various embodiments have been disclosed in this disclosure, those skilled in the art will understand that the scope of this disclosure extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses of their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and will still fall within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined with or substituted for each other to form varied embodiments. Therefore, it is intended that the scope of at least some of this disclosure should not be limited to the specific disclosed embodiments described above.

Claims

1. A device comprising: The first memory channel includes: First memory interface; The first repository includes the first data line; and The second repository includes a second data line; The second memory channel includes: The second memory interface is independent of the first memory interface; The third repository includes a third data line; and The fourth repository includes a fourth data line; and A precharge timing circuit is configured to provide a first precharge activation signal, a second precharge activation signal, a third precharge activation signal, and a fourth precharge activation signal. The first precharge activation signal is configured to activate precharge of a first data line. The second precharge activation signal is configured to activate precharge of a second data line at least partially in response to the first precharge activation signal. The third precharge activation signal is configured to activate precharge of a third data line. The fourth precharge activation signal is configured to activate precharge of a fourth data line at least partially in response to the third precharge activation signal. The precharge timing circuit provides the first and second precharge activation signals at different times and provides the third and fourth precharge activation signals at different times.

2. The device according to claim 1, wherein the pre-charge timing circuit comprises: A first delay is configured to provide the second precharge activation signal at least partially in response to the first precharge activation signal; and The second delay is configured to provide the fourth precharge activation signal in at least a partial response to the third precharge activation signal.

3. The device of claim 2, wherein the first memory further comprises a fifth storage device coupled to the fifth data line. in, The precharge timing circuit further includes a third delay configured to provide a fifth precharge activation signal, at least partially in response to the first precharge activation signal, the fifth precharge activation signal configured to activate precharge of the fifth data line. The precharge timing circuit provides the second precharge activation signal and the fifth precharge activation signal at different times.

4. The device of claim 1, wherein the precharge timing circuit provides the first precharge activation signal, the second precharge activation signal, the third precharge activation signal, and the fourth precharge activation signal at different times from each other.

5. The device of claim 4, further comprising a time adjustment circuit configured to receive a first precharge activation signal having a delay and further configured to provide the third precharge activation signal and the fourth precharge activation signal at least in part in response to the first precharge activation signal having the delay.

6. An apparatus comprising: The first storage cell array includes a first storage repository and a second storage repository; The second storage unit array includes a third repository and a fourth repository; The first data line, the second data line, the third data line, and the fourth data line are respectively included in the first repository, the second repository, the third repository, and the fourth repository; A first pre-charging circuit, a second pre-charging circuit, a third pre-charging circuit, and a fourth pre-charging circuit are configured to pre-charge the first data line, the second data line, the third data line, and the fourth data line, respectively; and The pre-charge timing circuit is configured to provide a first pre-charge activation signal, a second pre-charge activation signal, a third pre-charge activation signal, and a fourth pre-charge activation signal to the first pre-charge circuit, the second pre-charge circuit, the third pre-charge circuit, and the fourth pre-charge circuit, respectively. The precharge timing circuit is configured to provide the second precharge activation signal in at least a partial response to the first precharge activation signal, and in, The precharge timing circuit is configured to provide the fourth precharge activation signal in at least a partial response to the third precharge activation signal.

7. The device of claim 6, wherein the pre-charge timing circuit comprises: A first circuit is configured to provide the first precharge activation signal in response to a first power-on signal; and The second circuit is configured to provide the third precharge activation signal in response to the second power-on signal.

8. The device according to claim 7, further comprising: A first power supply circuit is configured to provide a first power potential to a first pre-charge circuit and a second pre-charge circuit. The first power supply circuit includes a first voltage application circuit configured to detect when the first power supply circuit begins receiving the first power potential, and further configured to provide the first power application signal in response to the detection of receiving the first power potential. A second power supply circuit is configured to provide a second power potential to the third pre-charge circuit and the fourth pre-charge circuit. The second power supply circuit includes a second voltage-applying circuit, which is configured to detect when the second power supply circuit begins to receive the second power potential, and is further configured to provide the second power-applying signal in response to the detection of the receipt of the second power potential.

9. The device of claim 7, wherein the first circuit is configured to provide the first power-on signal having a delay, and The second circuit is configured to receive the first power-on signal having the delay from the first circuit, and is further configured to provide the third precharge activation signal at least in part in response to the first power-on signal having the delay.

10. The device of claim 9, wherein the second circuitry includes a time adjustment circuitry configured to receive the second power-on signal and the first power-on signal having the delay from the first circuitry, and further configured to provide the second power-on signal as the third precharge activation signal in at least a portion in response to the first power-on signal having the delay.

11. The device of claim 10, wherein the time adjustment circuit comprises: An inverting AND gate logic circuit, configured to receive a second power-on signal and a first power-on signal having the delay from the first circuit, and configured to provide an output signal; and An inverter configured to receive the output signal, invert the output signal, and provide an inverted output signal.

12. The device of claim 9, wherein the first circuit includes a delay circuit configured to provide the first power-on signal having the delay.

13. The device of claim 12, wherein the delay circuit is a first delay circuit, and the delay is a first delay. The first circuit includes a plurality of second delay circuits coupled in series, each including the first delay circuit, configured to provide a first power-on signal having the first delay from the first delay circuit, and The first delay is the sum of the delays of the plurality of second delay circuits.

14. The device of claim 13, wherein each of the plurality of second delay circuits has a second delay.

15. The device of claim 14, wherein the plurality of second delay circuits further comprises a third delay circuit configured to provide a second precharge activation signal as a first precharge activation signal having the second delay.

16. The apparatus of claim 15, further comprising: A fifth storage repository, located within the first storage cell array, includes a fifth data line; and The fifth pre-charging circuit is configured to pre-charge the fifth data line. The first circuit further includes a fourth delay circuit, the fourth delay circuit being configured to provide a fifth precharge activation signal as a first precharge activation signal having a third delay, and The third delay is shorter than the second delay.

17. An apparatus comprising: The first bare disk includes the first repository group and the second repository group; The second bare film includes the third repository group; The first data line, the second data line, and the third data line are respectively included in the first repository group, the second repository group, and the third repository group; as well as A first circuit, located on the first die, is configured to receive a first power-on signal and further configured to provide a first precharge activation signal and a second precharge activation signal at least partially in response to the first power-on signal, the first precharge activation signal being configured to activate precharge of the first data line and the second precharge activation signal being configured to activate precharge of the second data line, wherein the second precharge activation signal is the first precharge activation signal having a first delay. A second circuit, located on the second die, is configured to provide a third precharge activation signal, the third precharge activation signal being configured to activate the precharge of the third data line; as well as A via is configured to receive the second precharge activation signal from the first circuit, and further configured to provide the second precharge activation signal having a second delay to the second circuit. The second circuit is configured to receive the second precharge activation signal having the second delay from the via, and is further configured to provide the third precharge activation signal at least in part in response to the second precharge activation signal having the second delay.

18. The device of claim 17, wherein the second circuitry includes a time adjustment circuitry configured to receive a second power-on signal and a second precharge activation signal having the second delay, and further configured to provide the second power-on signal as the third precharge activation signal in at least a portion in response to the second precharge activation signal having the second delay.

19. The device of claim 18, wherein the time adjustment circuit comprises: An inverting AND gate logic circuit, configured to receive the second power-on signal and the second precharge activation signal having the second delay, and configured to provide an output signal; and An inverter configured to receive the output signal, invert the output signal, and provide an inverted output signal.

20. The apparatus of claim 17, further comprising: Another via is configured to receive a fourth precharge activation signal from the second circuit, and further configured to provide the fourth precharge activation signal having a third delay; and The third die is configured to receive the fourth precharge activation signal having the third delay. The fourth precharge activation signal is the third precharge activation signal with a fourth delay.

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