Three-dimensional memory, fabrication methods, and storage systems

Abstract

Embodiments of the present application provide a three-dimensional memory, a preparation method and a storage system. The three-dimensional memory may, for example, include: a first stack structure including a plurality of first stack layers, the first stack layers including a conductive layer and an interlayer insulating layer; a plurality of first contact portions penetrating part of the first stack layers from a first surface of the first stack structure and extending to the conductive layer at a respective predetermined depth, and a dummy channel structure penetrating the first stack layers from a second surface of the first stack structure opposite the first surface and extending to the conductive layer. Embodiments of the present application can provide an etching stop layer for the dummy channel structure, thereby improving the yield of the three-dimensional memory.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and more specifically, to a three-dimensional memory, a fabrication method, and a storage system. Background Technology

[0002] In 3D memory, different wafers are typically used to fabricate the memory array and the peripheral circuitry controlling the memory array. These are then bonded together to form a whole, saving overall process time. In this approach, some of the memory array fabrication can be completed from the back side, freeing up the process and design window.

[0003] However, performing this part of the process from the back side can have a certain impact on the yield of 3D memory. Summary of the Invention

[0004] The embodiments of this application provide a three-dimensional memory, a preparation method, and a storage system that can at least partially solve the above-mentioned problems existing in the prior art.

[0005] One embodiment of this application provides a three-dimensional memory, including: a first stacked structure including a plurality of first stacked layers, the first stacked layers including a conductive layer and an interlayer insulating layer; a plurality of first contacts extending from a first surface of the first stacked structure through a portion of the first stacked layers and extending to a conductive layer at a predetermined depth; and a virtual channel structure extending from a second surface of the first stacked structure opposite to the first surface through the first stacked layers and extending to the conductive layer.

[0006] In some exemplary embodiments of this application, the conductive layer includes a gate layer and a second contact portion, and the gate layer is connected to the first contact portion through the second contact portion.

[0007] In some exemplary embodiments of this application, the conductive material forming the second contact portion is the same as the conductive material forming the gate layer.

[0008] In some exemplary embodiments of this application, the gap between the projections of adjacent second contact portions on the first surface is less than a predetermined threshold.

[0009] In some exemplary embodiments of this application, on a plane perpendicular to the stacking direction of the first stacking structure, the extension length of the second contact portion along the first direction is greater than or equal to half the distance between the first contact portion connected to the second contact portion and the first contact portion adjacent to the connected first contact portion, wherein the first direction is the direction toward the adjacent first contact portion.

[0010] In some exemplary embodiments of this application, the first contact portion and the second contact portion connected thereto are formed as one unit.

[0011] In some exemplary embodiments of this application, the virtual channel structure has at least one step in the stacking direction of the first stack structure, and at least one conductor layer is in contact with the side of the step parallel to the conductor layer.

[0012] In some exemplary embodiments of this application, the virtual channel structure has at least one recess in the stacking direction of the first stack structure, and at least one conductor layer is in contact with the surface of the recess.

[0013] Another embodiment of this application provides a method for fabricating a three-dimensional memory, comprising: forming a second stacked structure on a substrate, the second stacked structure including a plurality of second stacked layers formed by stacking a gate sacrificial layer and an interlayer insulating layer; forming a plurality of contact holes extending from a first surface of the second stacked structure away from the substrate through a portion of the second stacked layers and extending to a predetermined depth of the gate sacrificial layer; removing at least a portion of the gate sacrificial layer at the bottom of each contact hole to form a recess; forming a conductive contact portion in each contact hole and the corresponding recess; and removing the substrate and forming a virtual channel structure extending from a second surface of the second stacked structure opposite to the first surface through a portion of the second stacked layers and extending to the conductive contact portion.

[0014] In some exemplary embodiments of this application, on a plane perpendicular to the stacking direction of the second stacking structure, the extension length of the recess along the second direction is positively correlated with the spacing between the contact hole and its adjacent contact hole, the second direction being the direction toward the adjacent contact hole.

[0015] In some exemplary embodiments of this application, the gap between adjacent projections of recesses on the substrate is less than a predetermined threshold.

[0016] In some exemplary embodiments of this application, on a plane perpendicular to the stacking direction of the second stack structure, the length of the recess extending along the second direction is greater than or equal to half the distance between the contact hole and its adjacent contact hole.

[0017] In some exemplary embodiments of this application, before forming the contact conductive portion, the method further includes: forming a gate gap through the second stacked structure; and forming a recessed etch stop layer by depositing a gate gap sacrificial layer in the gate gap; wherein, after forming the virtual channel structure, the method further includes: removing the gate gap sacrificial layer; removing the gate sacrificial layer of the second stacked structure through the gate gap to form a sacrificial gap; and filling the sacrificial gap with conductive material to form the gate layer of the three-dimensional memory.

[0018] In some exemplary embodiments of this application, forming a contact hole includes: forming a plurality of initial contact holes extending from a first surface of the second stacked structure through a portion of the second stacked layer, each initial contact hole extending to an interlayer insulating layer adjacent to a gate sacrificial layer of a predetermined depth and close to the first surface; depositing a first dielectric material on the sidewall of each initial contact hole, and extending each initial contact hole to the gate sacrificial layer of a predetermined depth.

[0019] In some exemplary embodiments of this application, the method further includes oxidizing the sidewalls of the contact hole to form a support layer before depositing the first dielectric material.

[0020] In some exemplary embodiments of this application, oxidizing the sidewalls of the contact hole to form a support layer includes: depositing a second dielectric material on the sidewalls of the contact hole; and oxidizing the second dielectric material to form a support layer.

[0021] Another aspect of the embodiments of this application provides a storage system, including: a three-dimensional memory as mentioned in the above embodiments; and a controller electrically connected to the three-dimensional memory for controlling the three-dimensional memory.

[0022] According to the embodiments of this application, the virtual channel structure is formed from the second surface, which can reduce the situation where the bottom of the first contact portion has a large space, resulting in poor support, and meets the support requirements of the three-dimensional memory. The design window and process window of each surface are large. The virtual channel structure extends to the conductive layer without breaking through the stacked structure, which can reduce the possibility of the virtual channel structure breaking through the stacked structure and damaging the peripheral circuit. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0024] Figure 1 These are partial cross-sectional views of three-dimensional memory devices that form virtual channel structures from the front during some manufacturing processes.

[0025] Figure 2 These are partial cross-sectional views of three-dimensional memory devices that form virtual channel structures from the back side during some manufacturing processes.

[0026] Figure 3a This is a partial cross-sectional view of a three-dimensional memory according to one embodiment of this application;

[0027] Figure 3b This is a partial cross-sectional view of another three-dimensional memory according to one embodiment of this application;

[0028] Figure 3c and Figure 3d yes Figure 3aA partially enlarged schematic diagram of the virtual channel structure in region 2;

[0029] Figure 4 This is a schematic diagram of the connection between the peripheral circuit and the memory cell array formed in a stacked structure according to one embodiment of this application;

[0030] Figure 5a and Figure 5b This is a schematic diagram showing the relationship between a recess for forming a second contact portion and a contact hole for forming a first contact portion according to one embodiment of this application.

[0031] Figure 6 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application;

[0032] Figures 7 to 20 This is a schematic diagram of a fabrication process for a three-dimensional memory according to one embodiment of this application;

[0033] Figure 21 This is a block diagram of a storage system according to one embodiment of the present application. Detailed Implementation

[0034] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first contact portion discussed herein may also be referred to as the second contact portion, the first surface may be referred to as the second surface, and vice versa.

[0036] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0037] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0038] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0041] In 3D memory, the memory array and its peripheral circuitry, such as complementary metal-oxide-semiconductor (CMOS), are fabricated separately on different wafers and then bonded together to save overall process time. In this approach, some of the memory array fabrication can be performed from the back side, freeing up process and design windows. In some processes, a stair contact (SCT) architecture can be used to expose the gate layer of the memory array. Compared to architectures that place CTs in the stepped regions of the 3D memory, the SCT architecture saves process steps and mitigates stress caused by thin film variations in the gate layer or interlayer insulating layer within the stepped regions of the 3D memory.

[0042] In SCT architecture, there are usually requirements for the size of the SCT structure to meet the process windows in forming SCTs of different depths. For example... Figure 1 As shown, if the DCH (Dummy Channel Hole) structure 112 is formed from the front, due to the large size of the SCT structure 111, there will be a large space at the bottom of the DCH structure 112 that penetrates the stacked structure 110 used to form the memory array and extends to the substrate 100 (e.g., Figure 1 As shown in the dashed box (in the diagram), the support requirement cannot be met. To meet the support requirement, as... Figure 2 As shown, a DCH structure 112 can be formed from the back of the memory array to prevent gate layer (i.e., word line) warping. See also Figure 2 The SCT structure 211 is formed from the front side of the stacked structure 210, and the DCH structure 212 is formed from the back side of the stacked structure 210. The front side of the stacked structure 210 is bonded to the CMOS structure 220. During this process, since there is no bottom etch stop layer or sacrificial layer during the formation of the DCH structure 212 on the back side, the oxide layer between the CMOS structure 220 and the stacked structure 210 is easily broken down during the deep hole etching of the gate sacrificial layer and the interlayer insulating layer in the stacked structure 210, causing damage to the CMOS structure 220.

[0043] Figure 3a and Figure 3b This is a partial cross-sectional view of a three-dimensional memory 30 according to one embodiment of this application. (See attached image.) Figure 3a and Figure 3b As shown, the three-dimensional memory 30 may include, for example, a first stacked structure 310a, a plurality of first contacts 321, and a virtual channel structure 330. The first stacked structure 310a may include, for example, a plurality of first stacked layers 311a, each of which may include, for example, a conductive layer 312 and an interlayer insulating layer 313. The plurality of first contacts 321 may extend from a first surface 314a of the first stacked structure 310a through a portion of the first stacked layers 311a and extend to a predetermined depth of the conductive layer 312. The virtual channel structure 330 may extend from a second surface 315a of the first stacked structure 310a opposite to the first surface 314a through the first stacked layer 311a and extend to the conductive layer 312.

[0044] According to the embodiments of this application, the virtual channel structure is formed from the second surface, which can reduce the situation where the bottom of the first contact portion has a large space, resulting in poor support, and meets the support requirements of the three-dimensional memory. The design window and process window of each surface are large. The virtual channel structure extends to the conductive layer without breaking through the stacked structure, which can reduce the possibility of the virtual channel structure breaking through the stacked structure and damaging the peripheral circuit.

[0045] In one embodiment of this application, see Figure 3a and Figure 3b The three-dimensional memory 30 may also include, for example, peripheral circuitry 340, which may be bonded to one side of the first stacked structure 310a. For example, the first stacked structure 310a and the peripheral circuitry 340 may be bonded to the side of the first surface 314a of the first stacked structure 310a via an interconnect layer (not shown).

[0046] In one embodiment of this application, Figure 4 This is a schematic diagram showing the connection between the peripheral circuitry 340 and the memory cell array 301 formed in the first stacked structure 310a. (See diagram below.) Figure 4 As shown, the memory cell array 301 may include, for example, one or more memory blocks BLK1 to BLK2. Each memory block BLK may have multiple memory strings (not shown), each memory string including multiple memory cells connected in series, with memory cells in the same memory layer connected to the same word line (i.e., the gate layer 3121 of the conductive layer 312). The peripheral circuitry 340 may include, for example, an address decoder 341, a page buffer 342, control logic circuitry 343, I / O circuitry 344, and a voltage generator 345.

[0047] Address decoder 341 can control word lines WL, top redundant word lines TRL, bottom redundant word lines BRL, top select word lines TSL, and bottom select word lines BSL connected to memory cell array 301 in response to control logic circuit 343. Word lines WL are connected to memory layers (not shown), top redundant word lines TRL are connected to top redundant layers (not shown), bottom redundant word lines BRL are connected to bottom redundant layers (not shown), top select word lines TSL are connected to top select layers (not shown), and bottom select word lines BSL are connected to bottom select layers (not shown). In other words, address decoder 341 can receive and decode address ADDR from control logic circuit 343, and select one of multiple memory blocks BLK1 to BLK2 in memory cell array 301 based on the decoded address ADDR. For example, one of multiple pages in the selected memory block can be selected. Each word line WL can be used to control one page. Address decoder 341 can provide the voltage required for word lines WL from voltage generator 345 to the selected word line WL in the selected memory block BLK.

[0048] Page buffer 342 can function as a write driver or a sense amplifier depending on the operating mode. For example, in a programming operation, page buffer 342 can provide a bit line voltage to the bit line BL of the memory cell array 301 corresponding to the data DATA to be programmed. The data DATA can be multiple bits of data to be programmed. In a read operation, page buffer 342 can sense the data stored in the selected memory cell via the bit line BL and output the sensed data DATA to the I / O circuit 344. Page buffer 342 may include multiple page buffers respectively connected to the bit line BL.

[0049] Control logic circuitry 343 can control address decoder 341, page buffer 342, and voltage generator 345 in response to commands CMD (e.g., programming commands and read commands) and address ADDR from I / O circuitry 344. Furthermore, control logic circuitry 343 can control the three-dimensional memory 30 to perform programming operations via a multi-step method. The multi-step method can execute programming operations multiple times to configure the desired programming state and may include pre / master programming methods, reprogramming methods, shadow programming methods, etc.

[0050] The voltage generator 345 can generate, under the control of the control logic circuit 343, the voltage required to be supplied to the word line WL, the top redundant word line TRL, the bottom redundant word line BRL, the top select word line TSL, and the bottom select word line BSL.

[0051] Those skilled in the art will understand that the operations performed by the address decoder 341, page buffer 342, control logic circuit 343, and voltage generator 345 described in this application can be executed by a processing circuit. This processing circuit may include, but is not limited to, hardware of logic circuits or a hardware / software combination of a processor executing software.

[0052] In some embodiments of this application, the conductive layer 312 may, for example, include various material portions within a region of a certain thickness where the gate layer 3121 is located.

[0053] In some embodiments of this application, see Figure 3a The conductive layer 312 includes a gate layer 3121 and a second contact portion 322. The gate layer 3121 is connected to the first contact portion 321 through the second contact portion 322. The gate layer 3121 and the second contact portion 322 are located in the same plane.

[0054] In some embodiments of this application, the first contact portion 321 and the second contact portion 322 connected thereto are formed as a single unit. In other words, during the fabrication of the three-dimensional memory 30, the first contact portion 321 and the second contact portion 322 can be formed in one process step.

[0055] In one embodiment of this application, see Figure 3a The conductive material forming the gate layer 3121 is different from the conductive material forming the first contact portion 321. For example, the conductive material forming the gate layer 3121 may be tungsten, and the conductive material forming the first contact portion 321 may be aluminum or copper.

[0056] In another embodiment of this application, see Figure 3b The conductive material forming the second contact portion 322 is the same as the conductive material forming the gate layer 3121. For example, both the conductive material forming the second contact portion 322 and the conductive material forming the gate layer 3121 are tungsten.

[0057] It should be understood that when the conductive material forming the second contact portion 322 is the same as the conductive material forming the gate layer 3121, no clear interface can be observed between the gate layer 3121 and the second contact portion 322, which can be understood as the conductive layer 312 including the gate layer 3121.

[0058] In one embodiment of this application, on a plane substantially perpendicular to the stacking direction of the first stacking structure 310a, the extension length of the second contact portion 322 along a first direction is positively correlated with the distance between the first contact portion 321 to which the second contact portion 322 is connected and the first contact portion adjacent to the connected first contact portion 321. The first direction can be, for example, the direction in which the first contact portion 321 corresponding to the second contact portion 322 faces the other first contact portions 321 adjacent to it, that is, the direction of the straight line formed by the first contact portion 321 corresponding to the second contact portion 322 and the first contact portion 321 adjacent to it. In other words, if the distance between the first contact portion 321 and the first contact portion adjacent to the first contact portion 321 is large, the extension length of the second contact portion 322 contacting the first contact portion 321 is large; if the distance between the first contact portion 321 and the first contact portion adjacent to the first contact portion 321 is small, the extension length of the second contact portion 322 contacting the first contact portion 321 is small.

[0059] For example, the first contact portion 321 corresponding to the second contact portion 322 may be, for example, a first contact portion 321 integral with the second contact portion 322.

[0060] In one embodiment of this application, the gap between the projections of adjacent second contact portions 322 onto the first surface 314a of the first stacked structure 310a is less than a predetermined threshold. This predetermined threshold may be, for example, a positive number close to 0.

[0061] For example, on a plane substantially parallel to the first surface 314a of the first stacked structure 310a (i.e., a plane substantially perpendicular to the stacking direction of the first stacked structure 310a), the cross-sectional shape of the second contact portion 322 is circular. The radius of the second contact portion 322 is greater than or equal to half the distance between the first contact portion 321 connected to the second contact portion 322 and the first contact portion 321 adjacent to the connected first contact portion 321, so that the gap between the projections of adjacent second contact portions 322 onto the first surface 314a of the first stacked structure 310a is close to 0, or there is overlap between the projections of adjacent second contact portions 322 onto the first surface 314a of the first stacked structure 310a. The distance between the first contact portion 321 and its adjacent first contact portion 321 can be, for example, the distance between the center point of the first contact portion 321 and the center point of its adjacent first contact portion 321 on a plane parallel to the substrate.

[0062] For example, Figure 5a and Figure 5b The diagram illustrates the relationship between the extension length of the recess 326 forming the second contact portion 322 along a second direction and the spacing between the contact hole 325 forming the first contact portion 321. The second direction can be, for example, the direction in which the contact hole 325 corresponding to the recess 326 faces its adjacent contact hole 325, i.e., the direction of the straight line formed by the contact hole 325 corresponding to the recess 326 and its adjacent contact hole 325. Figure 5a and Figure 5b Two rows of contact holes 325 are formed between adjacent gate slot structures 360. The distance between a contact hole 325 and its adjacent contact hole can be, for example, the distance after both the contact hole 325 and its adjacent contact hole are extended to the bottom of the first stack structure 310a, that is, the difference between the distance (A) between the central axis of the contact hole 325 and the central axis of its adjacent contact hole and the diameter (B) of the contact hole 325. In order to make each second contact portion 322 cover the first stack structure 310a as much as possible, the radius (C) of the recess 326 is greater than or equal to half of the distance (AB) between the corresponding contact hole 325 and its adjacent contact hole.

[0063] For example, the spacing between the contact hole 325 corresponding to the recess 326 and its adjacent contact hole can be, for example, the distance between the center point of the contact hole 325 corresponding to the recess 326 and the center point of its adjacent contact hole on a plane parallel to the substrate. See also Figure 5bSince C≥1 / 2(AB), the projection of the recess 326 on the first surface 314a of the first stacked structure 310a coincides, so that the projection of the second contact portion 322 formed in the recess 326 on the first surface 314a of the first stacked structure 310a coincides. This allows the projection of the second contact portion 322 on the first surface 314a of the first stacked structure 310a to cover the projection of the first stacked structure 310a, thereby reducing the possibility of the virtual channel hole penetrating the first stacked structure 310a.

[0064] For example, if the center point of the contact hole 325 corresponding to the recess 326 and the center point of the adjacent contact hole have different distance values ​​on each plane parallel to the substrate, the distance between the contact hole 325 and the adjacent contact hole can be, for example, the maximum value among the distance values ​​of the center point of the contact hole 325 corresponding to the recess 326 and the center point of the adjacent contact hole on each plane parallel to the substrate.

[0065] For example, if the center point of the contact hole 325 corresponding to the recess 326 and the center point of the adjacent different contact holes have different distance values ​​on a plane parallel to the substrate, the distance between the contact hole 325 and the adjacent contact holes can be, for example, the maximum value of the distance values ​​between the center point of the contact hole 325 corresponding to the recess 326 and the center point of the adjacent different contact holes on a plane parallel to the substrate.

[0066] It should be understood that, without departing from the teachings of this application, the recess 326 may be in other shapes, for example, and this application does not limit this.

[0067] It should be understood that, Figure 5b Taking the example of two rows of contact holes 325 formed between adjacent gate slot structures 360, the structure of the three-dimensional memory 30 is illustrated. Without departing from the teachings of this application, the number of contact holes 325 (i.e. the number of first contact portions 321) between adjacent gate slot structures 360 can be set as needed, and this application does not limit this.

[0068] It should be understood that, Figure 5b The example provided is that the contact holes 325 in the same row and the contact holes 325 in the same column are arranged in a straight line. Without departing from the teachings of this application, the contact holes 325 may also be arranged in an alternating manner, and this application does not limit this.

[0069] In one embodiment of this application, considering that the spacing between the first contact portions 321 is too large, for example, greater than the warpage value L of the gate layer 3121, the gate layer 3121 will warp, and the spacing (AB) between adjacent first contact portions 321 is ≤ L. Here, the warpage value L refers to the spacing value between the first contact portions 321 when the gate layer 3121 warps.

[0070] In one embodiment of this application, participants Figure 3a No step region is formed in the three-dimensional memory 30. The three-dimensional memory 30 leads out the gate layer 3121 (i.e. word line WL, etc.) through the SCT structure.

[0071] In some embodiments of this application, see Figure 3a The three-dimensional memory 30 may also include, for example, a sidewall insulating layer 324, which may be located, for example, on the outer wall of the first contact portion 321. For example, the sidewall insulating layer 324 may be formed, for example, by depositing a first dielectric material in a contact hole for forming the first contact portion 321. The first dielectric material may be, for example, an insulating material such as an oxide.

[0072] In some embodiments of this application, the virtual channel structure 330 may be formed, for example, by a deep hole etching process, i.e., by etching downward from the second surface 315a of the first stacked structure 310a to etch a deep hole, for example, in the shape of a cylinder, into the first stacked structure 310a, and then filling it with an insulating material.

[0073] In some embodiments of this application, see Figure 3a In region 1, at least one virtual channel structure of the three-dimensional memory 30 is in contact with a second contact portion 322, and the shape of the virtual channel structure may be, for example, cylindrical.

[0074] In other embodiments of this application, see Figure 3a In region 2, at least one virtual channel structure of the three-dimensional memory 30 is in contact with at least two second contact portions 322.

[0075] As an example, see Figure 3c The three-dimensional memory 30 has at least one virtual channel structure with at least one step 332 in the stacking direction (e.g., the Z direction) of the first stacked structure, and at least one conductive layer 312 contacts a side of the step 332 parallel to the conductive layer 312 (e.g., the first surface 3321 of the step 332). In other words, the second contact portion 322 in the conductive layer 312 contacts the first surface 3321 of the step 332. For example, the second contact portion 322 serves as an etch stop layer for the formation of the virtual channel structure, which can block the etching process from etching the portion of the first stacked layer located between the second contact portion 322 and the first surface 314a, so that the formed virtual channel structure is as follows: Figure 3c As shown.

[0076] As another example, see Figure 3dThe three-dimensional memory 30 has at least one virtual channel structure with at least one recess 333 in the stacking direction (e.g., Z direction) of the first stacked structure. At least one conductive layer 312 contacts the surface of the recess 333 (e.g., the three surfaces of the recess—first surface 3331, second surface 3332, and third surface 3333), that is, the second contact portion 322 in the conductive layer 312 contacts the surface of the recess 333. For example, the second contact portion 322 serves as an etch stop layer during the formation of the virtual channel structure. During the etching process, it blocks the etching of the portion of the first stacked layer between the second contact portion 322 and the first surface 314a. Because the etching material may laterally etch a small portion of the first stacked layer between the second contact portion 322 and the first surface 314a, the formed virtual channel structure... Figure 3d As shown.

[0077] It should be understood that, without departing from the teachings of this application, when at least one virtual channel structure of the three-dimensional memory 30 is in contact with at least two second contact portions 322, the projected shape of the virtual channel structure on the first surface 314a may be circular or other shapes, without limitation herein.

[0078] According to the embodiments of this application, the virtual channel structure is formed from the second surface, which can reduce the situation where the bottom of the first contact portion has a large space, resulting in poor support, and meets the support requirements of the three-dimensional memory. The design window and process window of each surface are large. The conductor layer can be used as an etching stop layer for the virtual channel holes used to form the virtual channel structure, which can reduce the possibility of the virtual channel structure breaking down the stacked structure and damaging the peripheral circuits.

[0079] Figure 6 This is a flowchart of a method 1000 for fabricating a three-dimensional memory 30 according to one embodiment of this application. Figure 6 As shown, this application provides a method 1000 for fabricating a three-dimensional memory 30, comprising:

[0080] Step S11: A second stacked structure is formed on the substrate. The second stacked structure includes a plurality of second stacked layers formed by stacking a gate sacrificial layer and an interlayer insulating layer.

[0081] Step S12: Forming a plurality of contact holes that extend from the first surface of the second stacked structure away from the substrate through a portion of the second stacked layer and to a predetermined depth of the gate sacrificial layer.

[0082] Step S13: Remove at least a portion of the gate sacrificial layer located at the bottom of each contact hole to form a recess.

[0083] Step S14: Form conductive contacts in each contact hole and the corresponding recess.

[0084] Step S15: Remove the substrate and form a virtual channel structure. The virtual channel structure extends from the second surface of the second stacked structure opposite to the first surface through the second stacked layer to the conductive contact.

[0085] According to the embodiments of this application, the virtual channel structure is formed from the second surface of the stacked structure, which reduces the situation where a large space at the bottom of the conductive contact leads to poor support, thus meeting the support requirements of the 3D memory. The design and process windows of each surface are also larger. The conductive contact formed through the stacked layers from the first surface of the stacked structure can serve as an etching stop layer for the virtual channel holes used to form the virtual channel structure, reducing the possibility of the virtual channel structure breaking down the stacked structure and damaging the peripheral circuits. Furthermore, the fabrication process of the 3D memory introduces virtually no unnecessary processes, requiring no additional process steps or costs, resulting in a simple process.

[0086] The following will combine Figures 7 to 20 The specific processes for each step of the above preparation method 1000 are described in detail.

[0087] Step S11

[0088] Figure 7 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after the second stacked structure 310b is formed in one embodiment of this application.

[0089] like Figure 7 As shown, step S11, forming the second stacked structure 310b on the substrate 300, may include, for example, providing the substrate 300 and forming the second stacked structure 310b on one side of the substrate 300.

[0090] In one embodiment of this application, the substrate 300 can be made of any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, etc., which are III-V compounds. For example, the substrate 300 can be selected as single-crystal silicon.

[0091] In one embodiment of this application, the substrate 300 may be, for example, a composite substrate for supporting a device structure thereon. The substrate 300 can be formed by sequentially depositing multiple layers made of different materials using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0092] The substrate 300 may include, for example, a substrate sacrificial layer, which may comprise a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may comprise any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer. Alternatively, the substrate sacrificial layer may comprise a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed therefrom, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Alternatively, the substrate sacrificial layer may comprise any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, in one embodiment of this application, an exemplary material forming the substrate sacrificial layer may be polycrystalline silicon.

[0093] In one embodiment of this application, substrate 300 has opposing first and second sides. After forming substrate 300, a second stacked structure 310b can be formed on, for example, the first side of substrate 300 by one or more thin-film deposition processes. Thin-film deposition processes may include, but are not limited to, CVD, PVD, ALD, or any combination thereof, and are not limited thereto in this application. The second stacked structure 310b may include multiple pairs of interlayer insulating layers 313 and gate sacrificial layers 316 stacked alternately on each other. For example, the second stacked structure 310b may include 64 pairs, 128 pairs, or more than 128 pairs of interlayer insulating layers 313 and gate sacrificial layers 316. In some embodiments, interlayer insulating layers 313 and gate sacrificial layers 316 may each comprise a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials used to form interlayer insulating layers 313 and gate sacrificial layers 316 may each comprise silicon oxide and silicon nitride. A silicon oxide layer may be used as interlayer insulating layer 313, while a silicon nitride layer may be used as gate sacrificial layer 316. The gate sacrificial layer 316 can then be etched away and replaced with a conductive layer comprising a conductive material. Alternatively, mutually perpendicular X and Y directions can be defined in the plane of the substrate 300 for forming the second stacked structure 310b (see [reference]). Figure 5b The direction perpendicular to the surface of the substrate 300 is defined as the Z direction. In other words, the Z direction can also be the direction of the thickness of the second stacked structure 310b.

[0094] The fabrication method of a single second stacked structure 310b has been described above. In fact, as the storage capacity requirements of the three-dimensional memory 30 continue to increase, the size of the memory stack is gradually increasing. To overcome the limitations of traditional processes, a dual-stack or multi-stack technique can be used to form a second stacked structure 310b by sequentially stacking multiple sub-stacked structures in the thickness direction (Z direction) of the stacked structure. Each sub-stacked structure may include multiple alternately stacked interlayer insulating layers 313 and gate sacrificial layers 316. The number of layers in each sub-stacked structure may be the same or different. Since the fabrication process of the single stacked structure described above is fully or partially applicable to the stacked structure comprising multiple sub-stacked structures described herein, related or similar content will not be repeated. However, those skilled in the art will understand that subsequent fabrication processes can be performed based on multi-stacked or single-stacked structures.

[0095] Step S12

[0096] Figure 8 This is a partial cross-sectional schematic diagram of the three-dimensional memory 30 after the mask layer 350 is formed in one embodiment of this application. Figure 9 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 formed in one embodiment of the present application, extending from the first surface 314b of the second stacked structure 310b away from the substrate 300 through the opening 351 of the mask layer 350. Figures 10a to 10c This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 forming the initial contact hole 323 in one embodiment of this application. Figure 11 This is a partial cross-sectional schematic diagram of the three-dimensional memory 30 after removing the mask layer 350 in one embodiment of this application. Figure 12 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after the sidewall insulating layer 324 has been formed in one embodiment of this application. Figure 13 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after the contact hole 325 is formed in one embodiment of this application.

[0097] In one embodiment of this application, such as Figure 8 As shown, the fabrication method 1000 of the three-dimensional memory 30 may further include, for example, depositing a mask layer 350 on the second stacked structure 310b. The mask layer 350 covers the second stacked structure 310b and can be used to etch contact holes 325 (see...). Figure 13 This protects other areas of the second stacked structure 310b. The mask layer 350 may be, for example, a hard mask (HM). The material of the hard mask layer may be, for example, amorphous carbon, polycrystalline silicon, alumina (Al2O3), or a metal.

[0098] In one embodiment of this application, such as Figure 9 As shown, the fabrication method 1000 of the three-dimensional memory 30 may further include, for example, patterning the mask layer 350 after forming it to form a plurality of openings 351 exposing the second stacked structure 310b. The method of patterning the mask layer 350 may include, but is not limited to, photolithography and etching. These openings 351 are used to remove a portion of the second stacked structure 310b in a subsequent process to form contact holes 325 (see...). Figure 13 ).

[0099] In one embodiment of this application, such as Figures 10a to 10c As shown, the fabrication method 1000 of the three-dimensional memory 30 may further include, for example, forming a plurality of initial contact holes extending from the first surface 314b of the second stacked structure 310b through a portion of the second stacked layer 311b, each initial contact hole extending to an interlayer insulating layer 313 adjacent to the gate sacrificial layer 316 at a predetermined depth and close to the first surface 314b of the second stacked structure 310b. Exemplarily, initial contact holes 323 are formed by etching downwards in a direction substantially perpendicular to the second stacked structure 310b (Z direction) through openings 351.

[0100] For example, the Y direction (see Figure 5b Initial contact holes 323 that are roughly aligned on the same straight line are considered as a group of initial contact holes 323. See also Figures 10a to 10c The second stacked structure 310b includes a gate sacrificial layer 316 and an interlayer insulating layer 313, wherein the layer furthest from the substrate 300 and the side closest to the substrate 300 may be, for example, the interlayer insulating layer 313.

[0101] The following example, using a second stacked structure 310b comprising eight gate sacrificial layers, illustrates the process of forming the initial contact hole 323. The process of forming the initial contact hole 323 may include, for example, the following steps: Figure 9 As shown, openings 351 are formed corresponding to the eight initial contact holes 323 respectively; as Figure 10a As shown, a first photoresist pattern 352 covering a mask layer 350 is formed on the second stacked structure 310b. The first photoresist pattern 352 exposes openings 351 in groups 1, 2, 3, and 4. Through the openings 351 in groups 1, 2, 3, and 4, an interlayer insulating layer 313 and a gate sacrificial layer 316 are etched downwards. Figure 10b As shown, the first photoresist pattern 352 is removed, and a second photoresist pattern 353 covering the mask layer 350 is formed on the second stacked structure 310b. The second photoresist pattern 353 exposes the first, second, seventh, and eighth groups of openings 351. Through the first, second, seventh, and eighth groups of openings 351, two interlayer insulating layers 313 and two gate sacrificial layers 316 are alternately etched downwards. Figure 10cAs shown, the second photoresist pattern 353 is removed, and a third photoresist pattern 354 covering the mask layer 350 is formed on the second stacked structure 310b. The third photoresist pattern 354 exposes the first group, the fourth group, the fifth group, and the eighth group of openings 351. Through the first group, the fourth group, the fifth group, and the eighth group of openings 351, four interlayer insulating layers 313 and four gate sacrificial layers 316 are alternately etched downwards to form the initial contact hole 323. In the initial contact holes 323 formed through the above process, the etching of the first group of initial contact holes 323 stops at the side of the 8th interlayer insulating layer 313 near the first surface 314b of the second stacked structure 310b, counting from the first surface 314b of the second stacked structure 310b towards the substrate 300; the etching of the second group of initial contact holes 323 stops at the side of the 4th interlayer insulating layer 313 near the first surface 314b of the second stacked structure 310b; the etching of the 3rd group of initial contact holes 323 stops at the side of the 2nd interlayer insulating layer 313 near the first surface 314b of the second stacked structure 310b; and the etching of the 4th group of initial contact holes 323 stops at the 6th interlayer insulating layer 313. The etching of the fifth set of initial contact holes 323 stops on the side of the fifth interlayer insulating layer 313 near the first surface 314b of the second stacked structure 310b. The etching of the sixth set of initial contact holes 323 stops on the side of the first interlayer insulating layer 313 near the first surface 314b of the second stacked structure 310b. The etching of the seventh set of initial contact holes 323 stops on the side of the third interlayer insulating layer 313 near the first surface 314b of the second stacked structure 310b. The etching of the eighth set of initial contact holes 323 stops on the side of the seventh interlayer insulating layer 313 near the first surface 314b of the second stacked structure 310b.

[0102] It should be understood that, for clarity, this embodiment is illustrated by taking the second stacked structure 310b containing 8 gate sacrificial layers as an example. In other embodiments, the number of gate sacrificial layers in the second stacked structure 310b (i.e. the number of second stacked layers 311b) can be adjusted as needed, for example, 16 layers, 32 layers, 64 layers, etc., and this application does not limit this.

[0103] It should be understood that, without departing from the teachings of this application, other process flows can be used to stop the etching of each group of initial contact holes 323 at different interlayer insulating layers 313. This application does not limit the formation process of the initial contact holes 323 or the specific location where the etching of each group of initial contact holes 323 stops.

[0104] It should be understood that, without departing from the teachings of this application, the number of initial contact holes 323 may be determined based on the number of second stacked layers 311b in the second stacked structure 310b, and this application does not limit this.

[0105] In one embodiment of this application, such as Figure 11 As shown, the fabrication method 1000 of the three-dimensional memory 30 may also include, for example, removing the third photoresist pattern 354 and removing the mask layer 350.

[0106] For example, the mask layer 350 is a hard mask layer. To remove the hard mask layer, a chemical mechanical polishing (CMP) process can be used, a wet etching and cleaning apparatus solution using phosphoric acid can be used, or a combination of a chemical mechanical polishing (CMP) process and a wet etching and cleaning apparatus solution using phosphoric acid can be used.

[0107] It should be understood that, without departing from the teachings of this application, the method for removing the mask layer 350 may be selected according to the material of the mask layer 350, and this application does not limit this method.

[0108] It should be understood that, without departing from the teachings of this application, the order in which the step of removing the mask layer 350 is performed can be set as needed, for example, it can be performed after the formation of the contact hole 325 or the formation of the recess 326, and this application does not limit this.

[0109] In one embodiment of this application, such as Figure 12 and Figure 13 As shown, forming a contact hole 325 may include, for example, depositing a first dielectric material on the sidewall of each initial contact hole 323 to form a sidewall insulating layer 324, and extending each initial contact hole 323 to a gate sacrificial layer 316 to a predetermined depth to form a contact hole 325.

[0110] For example, such as Figure 12 As shown, a first dielectric material is deposited on the sidewalls and bottom of the initial contact hole 323. Figure 13 As shown, the first dielectric material at the bottom of the initial contact hole 323 is removed to form a sidewall insulating layer 324, and at least one interlayer insulating layer 313 is etched downwards to extend each initial contact hole 323 to a gate sacrificial layer 316 at a predetermined depth to form a contact hole 325. The sidewall insulating layer 324 isolates the conductive contact portion 320 from the gate layer 3121 at the predetermined depth (see [reference]). Figure 3a Other gate layers 3121 besides )

[0111] Alternatively, the fabrication method 1000 of the three-dimensional memory 30 may also include, for example, oxidizing the sidewalls of the contact hole 325 to form a support layer (not shown).

[0112] For example, a second dielectric material is deposited on the sidewall of the contact hole 325; the second dielectric material is oxidized to form a support layer. The second dielectric material may be, for example, silicon nitride. The support layer on the sidewall of the contact hole 325 enhances the support of the three-dimensional memory 30.

[0113] Step S13

[0114] Figure 14 This is a partial cross-sectional schematic diagram of the three-dimensional memory 30 after the recess 326 is formed in one embodiment of this application.

[0115] like Figure 14 As shown, in one embodiment of this application, at least a portion of the gate sacrificial layer 316 located at the bottom of the contact hole 325 is removed to form a recess 326. On a plane generally parallel to the substrate 300, the extension length of the recess 326 along a second direction is greater than or equal to the extension length of the bottom of the contact hole 325 along a second direction, where the second direction is the direction in which the contact hole 325 corresponding to the recess 326 faces the contact hole adjacent to it.

[0116] For example, forming a recess 326 may include: injecting an etching material into the contact hole 325 that has a high etching ratio for the gate sacrificial layer 316 and a low etching ratio for the interlayer insulating layer, removing a portion of the gate sacrificial layer 316 at the bottom of the contact hole 325, thereby forming a recess 326.

[0117] For example, the length of the recess 326 can be controlled by controlling the etching time or etching energy, etc., but this application does not limit this.

[0118] In one embodiment of this application, on a plane perpendicular to the stacking direction of the second stacking structure, the extension length of the recess 326 along the second direction is positively correlated with the distance between the contact hole 325 corresponding to the recess 326 and its adjacent contact hole. The second direction is the direction from which the contact hole 325 corresponding to the recess 326 faces its adjacent contact hole. In other words, if the distance between the formed contact holes 325 is large, the extension length of the recess 326 is large; if the distance between the formed contact holes 325 is small, the extension length of the recess 326 is small. The extension length of the recess 326 can be determined according to the size of the distance between the formed contact holes 325.

[0119] For example, the extension length of the recess 326 along the second direction is equal to T / 2 times the distance between the contact hole 325 and the adjacent contact hole, where T is a positive number greater than or equal to 1.

[0120] Alternatively, the gap between the projections of adjacent recesses 326 onto the substrate 300 is less than a predetermined threshold. This predetermined threshold can be, for example, a positive number close to 0. In other words, there is almost no gap between the projections of adjacent recesses 326 onto the substrate 300. Typically, if the extension length of the recess 326 along the second direction is equal to T / 2 times the distance between the contact hole 325 and its adjacent contact hole, there is almost no gap between the projections of adjacent recesses 326 onto the substrate 300.

[0121] Optionally, due to factors such as process deviations, during the etching of the recess 326, if T / 2 times the distance between the contact hole 325 and its adjacent contact hole is determined as the etching length of the gate sacrificial layer 316 to be etched along the second direction, and after etching at least a portion of the gate sacrificial layer 316 located at the bottom of each contact hole according to the determined etching length to form the recess 326, gaps may still exist between the projections of adjacent recesses 326 on the substrate 300. Therefore, in some embodiments of this application, the extension length of the recess 326 along the second direction may be greater than or equal to T / 2 times the distance between the contact hole 325 and its adjacent contact hole, and the projections of adjacent recesses 326 on the substrate 300 may partially overlap, in order to reduce the possibility that the portion of the conductive contact 320 located within the recess 326 may not completely block the etching material used to form the virtual channel hole from further etching downwards due to process deviations or other reasons, thereby further reducing the possibility of etching breakdown.

[0122] For example, on a plane perpendicular to the stacking direction of the second stack structure 310b, the extension length of the recess 326 along the second direction is greater than or equal to half the distance between the contact hole 325 and its adjacent contact hole.

[0123] For example, on a plane perpendicular to the stacking direction of the second stack structure 310b, the cross-sectional shape of the recess 326 may be, for example, circular, and the radius of the recess 326 may be greater than or equal to half the distance between the contact hole 325 corresponding to the recess 326 and the adjacent contact hole.

[0124] For example, such as Figure 5a and Figure 5b As shown, the distance between contact hole 325 and its adjacent contact hole can be, for example, the distance after both contact hole 325 and its adjacent contact hole are extended to the bottom of the second stacked structure 310b, i.e., the difference between the distance (A) between the central axis of contact hole 325 and the central axis of its adjacent contact hole and the diameter (B) of the contact hole. To ensure that the portion of each conductive contact 320 located within the recess (i.e., the second contact 322) covers the second stacked structure 310b as much as possible, the radius C of the recess 326 is greater than or equal to half the distance (AB) between contact hole 325 and its adjacent contact hole. See also... Figure 5bSince C≥1 / 2(AB), the projection of the portion of each conductive contact 320 located in the recess on the first surface 314b of the second stacked structure 310b can cover the projection of the second stacked structure 310b.

[0125] Step S14

[0126] Figure 15 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after the conductive contact portion 320 is formed in one embodiment of this application.

[0127] For example, such as Figure 15 As shown, conductive material can be filled into the contact hole 325 and the recess 326 to form a conductive contact portion 320. The portion of the conductive contact portion 320 located within the contact hole 325 can be understood as the first contact portion 321 mentioned in the structural embodiments of this application, and the portion of the conductive contact portion 320 located within the recess can be understood as the second contact portion 322 mentioned in the structural embodiments of this application. The first contact portion 321 and the second contact portion 322 can form the gate layer 3121 (see...). Figure 3a This provides a conductive path. In addition, the first contact portion 321 and the gate layer 3121 are contacted through the second contact portion 322, which can increase the contact area and reduce the resistance.

[0128] In one embodiment of this application, considering that an excessive spacing between contact holes 325 would cause the gate layer 3121 to warp, for example, if the spacing between contact holes 325 is greater than the warp value L of the gate layer 3121, the gate layer 3121 will warp, and the spacing (AB) between adjacent first contact portions 321 is ≤ L. Here, the warp value L refers to the spacing value between the first contact portions 321 when the gate layer 3121 warps.

[0129] Step S15

[0130] Figure 16 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after bonding the peripheral circuit 340 in one embodiment of this application. Figure 17 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after removing the substrate 300 in one embodiment of this application. Figure 18 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after forming the virtual channel hole 331 according to one embodiment of this application. Figure 19 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after forming a virtual channel structure 330 according to one embodiment of this application. Figure 20 This is a partial cross-sectional schematic diagram of a three-dimensional memory 30 after the sacrificial gap 317 is formed according to one embodiment of this application.

[0131] In one embodiment of this application, such as Figure 16 As shown, the fabrication method 1000 of the three-dimensional memory 30 may further include, for example, bonding the second stacked structure 310b to the peripheral circuit 340 on the side where the first surface 314b of the second stacked structure 310b is located. For example, the second stacked structure 310b may be bonded to the peripheral circuit 240 through an interconnect layer (not shown).

[0132] Exemplarily, the second stacked structure 310b can be fabricated on the first wafer, and the peripheral circuitry 340 can be fabricated on the second wafer. The first wafer and the second wafer are bonded together so that the peripheral circuitry 340 is electrically connected to the memory cell array 301 in the second stacked structure 310b (see [link]). Figure 4 ).

[0133] In one embodiment of this application, such as Figure 17 As shown, substrate 300 (e.g., silicon substrate) can be removed, for example, by wet etching with tetramethylammonium hydroxide (TMAH), which automatically stops when a material different from substrate 300 is reached.

[0134] It should be understood that, without departing from the teachings of this application, the method and materials for removing the substrate 300 may be selected according to the substrate 300 material, and this application does not impose any restrictions in this regard.

[0135] In one embodiment of this application, forming the virtual channel structure 330 may include, for example: Figure 18 As shown, a virtual channel hole 331 is formed from the second surface 315b of the second stacked structure 310b, which is opposite to the first surface 314b of the second stacked structure 310b, through the second stacked layer 311b, and extending to the conductive contact portion 320; as Figure 19 As shown, at least one support material is filled into the virtual channel hole 331 to form a virtual channel structure 330.

[0136] For example, virtual channel holes 331 can be formed by etching. Virtual channel holes 331 refer to channel holes that do not subsequently form memory cells. Virtual channel holes 331 mainly serve as support pillars through the filling of other film layers.

[0137] It should be understood that, without departing from the teachings of this application, those skilled in the art can form the above-mentioned virtual channel hole 331 using other processes, and this application does not limit this.

[0138] For example, in order to improve the supporting effect of the virtual channel structure 330, the two adjacent rows of the virtual channel structure 330 can be staggered in the X direction to increase the distribution density of the virtual channel structure 330.

[0139] For example, multiple support materials with different hardnesses can be filled into the virtual channel hole 331.

[0140] It should be understood that, without departing from the teachings of this application, the supporting materials may be, for example, polycrystalline silicon, silicon oxide, etc., and this application does not limit them.

[0141] For example, the cross-section of the virtual channel structure 330 in a direction generally parallel to the first surface 314b of the second stack structure 310b may be, for example, circular, elliptical or other shapes.

[0142] In one embodiment of this application, the method 1000 for fabricating the three-dimensional memory 30 may further include, for example: Figure 20 As shown, the gate sacrificial layer 316 in the second stacked structure 310b is removed to form a sacrificial gap 317; as Figure 3a and Figure 3b As shown, conductive material is filled in the sacrificial gap 317 to form the gate layer 3121 of the three-dimensional memory 30.

[0143] In one embodiment of this application, the method 1000 for fabricating the three-dimensional memory 30 may further include, for example, forming a gate gap (not shown) penetrating the second stacked structure 310b before forming the conductive contact portion 320; and forming an etch stop layer for the recess 326 by depositing a gate gap sacrificial layer (not shown) in the gate gap. The step of removing the gate sacrificial layer 316 in the second stacked structure 310b to form a sacrificial gap 317 may include, for example, removing the gate gap sacrificial layer; and removing the gate sacrificial layer 316 of the second stacked structure 310b through the gate gap to form the sacrificial gap 317. In other words, to avoid the second contact portion 322 formed through the recess 326 affecting the etching process for forming the gate gap, the gate gap can be formed first, and a gate gap sacrificial layer can be formed in the gate gap. When it is necessary to remove the gate sacrificial layer 316, the gate gap can then be opened.

[0144] It should be understood that, without departing from the teachings of this application, the gate gap sacrificial layer may be formed of materials such as polysilicon or carbide, and this application does not limit this.

[0145] In one embodiment of this application, the method 1000 for fabricating the three-dimensional memory 30 may further include, for example, forming an insulating sidewall in the gate gap after forming the gate layer 3121, and forming a poly or other conductive material covering the insulating sidewall to form a gate gap structure 360 ​​(see...). Figure 5b The gate gap structure 360 ​​can serve as a common source electrode, contacting other material layers that serve as source electrode layers.

[0146] In another embodiment of this application, the method 1000 for fabricating the three-dimensional memory 30 may, for example, include filling the gate gaps with insulating material after forming the gate layer 3121.

[0147] It should be understood that after the fabrication of structures such as the channel structure (not shown) and conductive contact 320 within the stacked structure of the three-dimensional memory is completed in the second stacked structure 310b, and the gate sacrificial layer 316 is replaced, the second stacked structure 310b becomes... Figure 3a and Figure 3b The first stacked structure 310a shown is illustrated.

[0148] Figure 21 This is a block diagram of a storage system according to an embodiment of this application. For example... Figure 21 As shown, the storage system 40 includes a three-dimensional memory 30 and a controller 31. The controller 31 is electrically connected to the three-dimensional memory 30 and is used to control the three-dimensional memory 30.

[0149] The three-dimensional memory 30 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be described again in this application.

[0150] The controller 31 can control the three-dimensional memory 30 via channel CH, and the three-dimensional memory 30 can perform operations based on the control of the controller 31 in response to requests from the host 50. The three-dimensional memory 30 can receive commands CMD and addresses ADDR from the controller 31 via channel CH and access the region selected from the memory cell array in response to the address. In other words, the three-dimensional memory 30 can perform internal operations corresponding to commands on the region selected by the address.

[0151] According to the embodiments of this application, the virtual channel structure is formed from the second surface of the stacked structure, which reduces the situation where a large space at the bottom of the conductive contact leads to poor support, thus meeting the support requirements of the three-dimensional memory. The design and process windows of each surface are large. The conductive contact formed through the stacked layers from the first surface of the stacked structure can serve as an etching stop layer for the virtual channel holes used to form the virtual channel structure, reducing the possibility of the virtual channel structure breaking down the stacked structure and damaging the peripheral circuits. Furthermore, the fabrication process of the three-dimensional memory introduces virtually no unnecessary processes, requiring no additional process steps or costs, resulting in a simple process.

[0152] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. For example, various well regions may be formed in the substrate as needed. Furthermore, the materials of the layers described are merely exemplary.

[0153] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that, include: A first stacked structure includes alternating conductive layers and interlayer insulating layers along a second direction, wherein the conductive layers include a first conductive layer and a second conductive layer located at different levels; The first contact portion extends from the first surface of the first stacked structure through the plurality of conductive layers and the plurality of interlayer insulating layers and extends to the first conductive layer and is connected to the first conductive layer. A first virtual channel structure extends from a second surface of the first stacked structure opposite to the first surface through a plurality of conductive layers and a plurality of interlayer insulating layers to the first conductive layer; The third contact portion extends from the first surface of the first stacked structure through a portion of the conductive layer and a portion of the interlayer insulating layer, and extends to the second conductive layer and connects to the second conductive layer. as well as The second virtual channel structure extends from the second surface of the first stacked structure through a portion of the conductive layer and a portion of the interlayer insulating layer and extends to the second conductive layer; The first conductive layer includes a first gate layer and a second contact portion. The first gate layer is connected to the first contact portion through the second contact portion. The second contact portion extends along a first direction. The first virtual channel structure extends to the second contact portion. The extension length of the second contact portion is greater than the dimension of the first virtual channel structure near the second contact portion along the first direction. The first direction is perpendicular to the second direction.

2. The three-dimensional memory according to claim 1, wherein, The first virtual channel structure and the first contact portion are not completely aligned along the second direction.

3. The three-dimensional memory according to claim 2, wherein, The extension length of the second contact portion along the first direction is greater than or equal to half the distance between the first contact portion and the third contact portion.

4. The three-dimensional memory according to claim 1, wherein, The conductive material forming the second contact portion is the same as the conductive material forming the first gate layer.

5. The three-dimensional memory according to claim 1, wherein, The first contact portion and the second contact portion connected thereto are formed as one unit.

6. The three-dimensional memory according to any one of claims 1 to 5, wherein, The first virtual channel structure has at least one step in the stacking direction of the first stack structure, and at least one of the conductive layers is in contact with the side of the step parallel to the conductive layer.

7. The three-dimensional memory according to any one of claims 1 to 5, wherein, The first virtual channel structure has at least one recess in the stacking direction of the first stack structure, and at least one of the conductive layers is in contact with the surface of the recess.

8. A method for fabricating a three-dimensional memory, characterized in that, include: A second stacked structure is formed on a substrate. The second stacked structure includes a plurality of stacked layers formed along a second direction by stacking a gate sacrificial layer and an interlayer insulating layer. The gate sacrificial layer includes a first gate sacrificial layer and a second gate sacrificial layer located at different levels. A plurality of first contact holes are formed, extending from a first surface of the second stacked structure away from the substrate through a plurality of stacked layers and respectively to the first gate sacrificial layer, and a plurality of second contact holes respectively to the second gate sacrificial layer; At least a portion of the first gate sacrificial layer located at the bottom of each of the first contact holes is removed to form a first recess, and at least a portion of the second gate sacrificial layer located at the bottom of each of the second contact holes is removed to form a second recess; A first conductive contact portion is formed in each of the first contact holes and the first recess corresponding to the first contact hole, and a second conductive contact portion is formed in each of the second contact holes and the second recess corresponding to the second contact hole; as well as The substrate is removed to form a first virtual channel structure and a second virtual channel structure. The first virtual channel structure extends from the second surface of the second stacked structure opposite to the first surface through the stacked layer to the first conductive contact. The second virtual channel structure extends from the second surface of the second stacked structure through the stacked layer to the second conductive contact. Wherein, the first conductive contact extends along a first direction, the first virtual channel structure extends to the first conductive contact, the extension length of the first conductive contact is greater than the dimension of the first virtual channel structure near the end of the first conductive contact along the first direction, and the first direction is perpendicular to the second direction.

9. The method according to claim 8, wherein, On a plane perpendicular to the stacking direction of the second stacked structure, the extension length of the first recess along the second direction is positively correlated with the spacing between the first contact hole and its adjacent contact hole, the second direction being the direction toward the adjacent contact hole.

10. The method according to claim 8, wherein, On a plane perpendicular to the stacking direction of the second stack structure, the first recess extends along the second direction for a length greater than or equal to half the distance between the first contact hole and its adjacent contact hole.

11. The method according to claim 8, wherein, Before forming the first conductive contact portion, the method further includes: Forming a gate gap that penetrates the second stacked structure; and An etch stop layer for the first recess is formed by depositing a gate gap sacrificial layer in the gate gap; After forming the first virtual channel structure, the method further includes: Remove the gate gap sacrificial layer; The first gate sacrificial layer of the second stacked structure is removed through the gate gap to form a sacrificial gap; and Conductive material is filled within the sacrificial gap to form the gate layer of the three-dimensional memory.

12. The method according to claim 8, wherein, Forming the first contact hole includes: A plurality of initial contact holes are formed through a portion of the stacked layers from the first surface of the second stacked structure, each of the initial contact holes extending to an interlayer insulating layer adjacent to the first gate sacrificial layer and close to the first surface; A first dielectric material is deposited on the sidewall of each initial contact hole, and each initial contact hole extends to the first gate sacrificial layer.

13. The method according to claim 12, wherein, Before depositing the first dielectric material, the method further includes: The sidewall of the first contact hole is oxidized to form a support layer.

14. The method according to claim 13, wherein, The oxidation of the sidewall of the first contact hole to form the support layer includes: A second dielectric material is deposited on the sidewall of the first contact hole; and The second dielectric material is oxidized to form the support layer.

15. A storage system, characterized in that, include: The three-dimensional memory as described in any one of claims 1 to 7; as well as A controller, electrically connected to the three-dimensional memory, is used to control the three-dimensional memory.

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