Electrostatic discharge (ESD) protection structure, ESD protection circuit, chip

Abstract

This disclosure relates to the field of semiconductor technology, and proposes an electrostatic discharge (ESD) protection circuit, an ESD protection structure, and a chip. The ESD protection circuit includes: a first PNP transistor, a first NPN transistor, and a control circuit. The emitter of the first PNP transistor is connected to a first signal terminal, the base is connected to a first node, and the collector is connected to a second node, wherein the first signal terminal is connected to the first node. The emitter of the first NPN transistor is connected to a second signal terminal, the base is connected to the second node, and the collector is connected to the first node. The control circuit is connected to the first signal terminal, the second signal terminal, and the first node, and is used to connect a low-level signal terminal of the first and second signal terminals to the first node based on the signals from the first and second signal terminals. This ESD protection circuit has high stability.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. Background Technology

[0002] Chips typically require an electrostatic discharge (ESD) protection circuit to discharge static electricity from the chip and prevent damage to the internal circuitry.

[0003] In related technologies, electrostatic discharge (ESD) protection circuits are used to conduct when static electricity occurs at the signal terminals of a chip, in order to release the static electricity at those signal terminals. However, in existing technologies, there are cases where ESD protection circuits conduct abnormally, thereby affecting the normal use of the chip.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] According to one aspect of this disclosure, an electrostatic discharge (ESD) protection circuit is provided, comprising: a first PNP transistor, a first NPN transistor, and a control circuit. The emitter of the first PNP transistor is connected to a first signal terminal, the base is connected to a first node, and the collector is connected to a second node, wherein the first signal terminal is connected to the first node; the emitter of the first NPN transistor is connected to a second signal terminal, the base is connected to the second node, and the collector is connected to the first node; the control circuit is connected to the first signal terminal, the second signal terminal, and the first node, and is used to connect a low-level signal terminal of the first signal terminal and the second signal terminal to the first node according to the signals from the first signal terminal and the second signal terminal.

[0006] In one exemplary embodiment of this disclosure, the electrostatic protection circuit further includes: a second PNP transistor and a second NPN transistor, wherein the emitter of the second PNP transistor is connected to a second signal terminal, the base is connected to a third node, and the collector is connected to a fourth node; the emitter of the second NPN transistor is connected to the first signal terminal, the base is connected to the fourth node, and the collector is connected to the third node; the control circuit is also connected to the third node and is used to connect a low-level signal terminal of the first signal terminal and the second signal terminal to the third node according to the signals of the first signal terminal and the second signal terminal.

[0007] In one exemplary embodiment of this disclosure, the control circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has its first terminal connected to the first node, its second terminal connected to the second signal terminal, and its gate connected to the fifth node. The second transistor has its first terminal connected to the second signal terminal, its second terminal connected to the fifth node, and its gate connected to the first signal terminal. The third transistor has its first terminal connected to the first signal terminal, its second terminal connected to the fifth node, and its gate connected to the second signal terminal. The fourth transistor has its first terminal connected to the third node, its second terminal connected to the first signal terminal, and its gate connected to the fifth node. The first and fourth transistors are both g-NMOS transistors, and the second and third transistors are both N-type transistors.

[0008] In one exemplary embodiment of this disclosure, the control circuit includes: a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to the second signal terminal, the second terminal is connected to the fifth node, and the gate is connected to the first signal terminal; the first terminal of the sixth transistor is connected to the first signal terminal, the second terminal is connected to the fifth node, and the gate is connected to the second signal terminal; wherein the fifth node is connected to the first node, and the fifth transistor and the sixth transistor are N-type transistors.

[0009] In one exemplary embodiment of this disclosure, the electrostatic protection circuit further includes: at least one first diode, wherein the at least one first diode is connected in series between the first node and the fifth node, and the first node is connected to the anode of the first diode, and the fifth node is connected to the cathode of the first diode.

[0010] In one exemplary embodiment of this disclosure, the electrostatic discharge protection circuit further includes: a second PNP transistor, a second NPN transistor, a second diode, and a third diode. The emitter of the second PNP transistor is connected to a second signal terminal, the base is connected to a third node, and the collector is connected to a fourth node. The emitter of the second NPN transistor is connected to the first signal terminal, the base is connected to the fourth node, and the collector is connected to the third node. The third node is connected to the first node. The anode of the second diode is connected to the first signal terminal, and the cathode is connected to the first node. The anode of the third diode is connected to the second signal terminal, and the cathode is connected to the third node.

[0011] In one exemplary embodiment of this disclosure, the electrostatic discharge protection circuit further includes: a fourth diode, a second PNP transistor, a second NPN transistor, and a fifth diode. The anode of the fourth diode is connected to the second signal terminal, and the cathode is connected to the first signal terminal. The emitter of the second PNP transistor is connected to the first signal terminal, the base is connected to the third node, and the collector is connected to the fourth node. The emitter of the second NPN transistor is connected to the third signal terminal, the base is connected to the fourth node, and the collector is connected to the third node. The anode of the fifth diode is connected to the third signal terminal, and the cathode is connected to the first signal terminal. The control circuit is also connected to the third node and is used to connect a low-level signal terminal of the first signal terminal and the third signal terminal to the third node according to the signals from the first signal terminal and the third signal terminal.

[0012] In one exemplary embodiment of this disclosure, the control circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a seventh transistor, and an eighth transistor. The first transistor has its first terminal connected to the first node, its second terminal connected to the second signal terminal, and its gate connected to the fifth node. The second transistor has its first terminal connected to the second signal terminal and the fifth node, and its gate connected to the first signal terminal. The third transistor has its first terminal connected to the first signal terminal, its second terminal connected to the fifth node, and its gate connected to the second signal terminal. The fourth transistor has its first terminal connected to the third node, its second terminal connected to the third signal terminal, and its gate connected to the sixth node. The seventh transistor has its first terminal connected to the third signal terminal, its second terminal connected to the sixth node, and its gate connected to the first signal terminal. The eighth transistor has its first terminal connected to the first signal terminal, its second terminal connected to the sixth node, and its gate connected to the third signal terminal. The first and fourth transistors are both g-NMOS transistors, and the second, third, seventh, and eighth transistors are all N-type transistors.

[0013] According to one aspect of this disclosure, an electrostatic discharge (ESD) protection structure is provided, the ESD protection structure including the aforementioned ESD protection circuit. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first P-type doped portion, a first N-type doped portion, a second N-type doped portion, a third N-type doped portion, a first gate insulating layer, a first gate layer, and a gating circuit. The first P-type well is located within the semiconductor substrate; the first N-type well is located within the semiconductor substrate; the first P-type doped portion is located within the first N-type well and electrically connected to a first signal terminal of the ESD protection structure; the first N-type doped portion is located within the first N-type well, spaced apart from the first P-type doped portion, and electrically connected to the first signal terminal of the ESD protection structure; the second N-type doped portion is located within the first P-type well and electrically connected to the first signal terminal of the ESD protection structure. The electrostatic discharge (ESD) protection structure includes a second signal terminal; a portion of the third N-type doped portion is located within the first P-type well, and a portion is located within the first N-type well; a first gate insulating layer is located on the side of the first P-type well facing away from the semiconductor substrate, and the orthographic projection of the first gate insulating layer on the semiconductor substrate is at least partially located between the orthographic projection of the third N-type doped portion on the semiconductor substrate and the orthographic projection of the second N-type doped portion on the semiconductor substrate; a first gate layer is located on the side of the first gate insulating layer facing away from the semiconductor substrate; a gating circuit connects the first signal terminal, the second signal terminal, and the first gate layer of the ESD protection structure, and is used to connect the first gate layer to the low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

[0014] In one exemplary embodiment of this disclosure, the electrostatic discharge (ESD) protection structure further includes: a second N-type well, a second P-type doped portion, a fourth N-type doped portion, a fifth N-type doped portion, a sixth N-type doped portion, a second gate insulating layer, and a second gate layer. The second N-type well is located on the side of the first P-type well away from the first N-type well. The second P-type doped portion is located within the second N-type well and is electrically connected to a second signal terminal of the ESD protection structure. The fourth N-type doped portion is located within the second N-type well, spaced apart from the second P-type doped portion, and electrically connected to a second signal terminal of the ESD protection structure. The fifth N-type doped portion is located within the first P-type well, spaced apart from the second N-type doped portion, and electrically connected to a first signal terminal of the ESD protection structure. The sixth N-type doped portion is partially located within the first P-type well and partially within the second N-type well; the second gate insulating layer is located on the side of the first P-type well away from the semiconductor substrate, and the orthogonal projection of the second gate insulating layer on the semiconductor substrate is at least partially located between the orthogonal projections of the fifth N-type doped portion and the sixth N-type doped portion on the semiconductor substrate; the second gate layer is located on the side of the second gate insulating layer away from the semiconductor substrate; the gating circuit is also connected to the second gate layer for connecting the second gate layer to a low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

[0015] In one exemplary embodiment of this disclosure, the gating circuit includes: a second transistor and a third transistor, wherein the first terminal of the second transistor is connected to the second signal terminal, the second terminal is connected to the first gate layer and the second gate layer, and the gate is connected to the first signal terminal; the first terminal of the third transistor is connected to the first signal terminal, the second terminal is connected to the first gate layer and the second gate layer, and the gate is connected to the second signal terminal.

[0016] According to one aspect of this disclosure, an electrostatic discharge (ESD) protection structure is provided, the ESD protection structure including the aforementioned ESD protection circuit, the ESD protection structure comprising: a semiconductor substrate, a first P-type well, a first N-type well, a second doped well, a first P-type doped portion, a first N-type doped portion, a second N-type doped portion, a second P-type doped portion, a third N-type doped portion, and a gating circuit, wherein the first P-type well is located within the semiconductor substrate; the first N-type well is located within the semiconductor substrate; the second doped well is located within the semiconductor substrate; the first P-type doped portion is located within the first N-type well and is electrically connected to a first signal terminal of the ESD protection structure; the first N-type doped portion is located within the first P-type well; and a gating circuit. The first N-type doped portion is located within the first P-type doped portion and is spaced apart from the first P-type doped portion; the second N-type doped portion is located within the first P-type doped portion and is electrically connected to the second signal terminal of the electrostatic protection structure; the second P-type doped portion is located within the second doped well and is electrically connected to the first N-type doped portion; the third N-type doped portion is located within the second doped well and is spaced apart from the second P-type doped portion; a gating circuit is connected to the first signal terminal, the second signal terminal, and the third N-type doped portion of the electrostatic protection structure, and is used to connect the third N-type doped portion to the low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

[0017] In one exemplary embodiment of this disclosure, the electrostatic protection structure includes a plurality of second doped wells, a plurality of second P-type doped portions, and a plurality of third N-type doped portions; the plurality of second doped wells are spaced apart, and the plurality of second P-type doped portions are arranged one-to-one with the plurality of second doped wells, with each second P-type doped portion located within its corresponding second doped well; the plurality of third N-type doped portions are arranged one-to-one with the plurality of second doped wells, with each third N-type doped portion located within its corresponding second doped well; the first N-type doped portion is electrically connected to any one of the plurality of second P-type doped portions; the plurality of second doped wells are connected in series via the second P-type doped portions and the third N-type doped portions located therewith, and in two adjacent second doped wells, the second P-type doped portions and the third N-type doped portions located in different second doped wells are electrically connected; the plurality of second doped wells include a tail second doped well, the tail second doped well being connected to the first N-type doped portion via the remaining second doped wells, and the gating circuit is connected to the third N-type doped portion in the tail second doped well.

[0018] In one exemplary embodiment of this disclosure, the electrostatic protection structure further includes: a third P-type well, a second N-type well, a third P-type doped portion, a fourth N-type doped portion, a fifth N-type doped portion, a fourth P-type doped portion, and a fifth P-type doped portion. The third P-type well is located within the semiconductor substrate and between the first P-type well and the second doped well. The second N-type well is located within the semiconductor substrate and between the third P-type well and the second doped well. The third P-type doped portion is located within the second N-type well and is electrically connected to the second signal terminal of the electrostatic protection structure. The fourth N-type doped portion... The fourth N-type doped portion is electrically connected to the first N-type doped portion, which is located within the second N-type well and spaced apart from the third P-type doped portion; the fifth N-type doped portion is located within the third P-type well and is electrically connected to the first signal terminal of the electrostatic protection structure; the fourth P-type doped portion is located within the third P-type well, spaced apart from the fifth N-type doped portion, and is electrically connected to the first signal terminal of the electrostatic protection structure; the fifth P-type doped portion is located within the first P-type well, spaced apart from the second N-type doped portion, and is electrically connected to the second signal terminal of the electrostatic protection structure.

[0019] In one exemplary embodiment of this disclosure, the gating circuit includes: a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to the second signal terminal, the second terminal is connected to the third N-type doped portion, and the gate is connected to the first signal terminal; the first terminal of the sixth transistor is connected to the first signal terminal, the second terminal is connected to the third N-type doped portion, and the gate is connected to the second signal terminal; wherein the fifth node is connected to the first node, and the fifth transistor and the sixth transistor are N-type transistors.

[0020] According to one aspect of this disclosure, an electrostatic discharge (ESD) protection structure is provided, the ESD protection structure including the aforementioned ESD protection circuit. The ESD protection structure includes: a semiconductor substrate, a first P-type well, an N-type deep well, a first N-type well, a first P-type doped portion, a first N-type doped portion, a second N-type doped portion, a third N-type doped portion, a first gate insulating layer, a first gate layer, and a first gate circuit. The first P-type well is located within the semiconductor substrate; the N-type deep well is located within the semiconductor substrate; the first N-type well is located within the semiconductor substrate, with a portion situated between the N-type deep well and the first P-type well, and a portion situated within the N-type deep well; the first P-type doped portion is located within the N-type deep well and electrically connected to a first signal terminal of the ESD protection structure; the first N-type doped portion is located within the N-type deep well, spaced apart from the first P-type doped portion, and electrically connected to the first signal terminal of the ESD protection structure; the second N-type doped portion is located within the first P-type well and electrically connected to a second signal terminal of the ESD protection structure; a portion of the third N-type doped portion is located within the first P-type deep well, and a portion is located within the first P-type deep well. The first N-type well is described above; a first gate insulating layer is located on the side of the first P-type well away from the semiconductor substrate, and the orthographic projection of the first gate insulating layer on the semiconductor substrate is at least partially located between the orthographic projection of the third N-type doped portion on the semiconductor substrate and the orthographic projection of the second N-type doped portion on the semiconductor substrate; a first gate layer is located on the side of the first gate insulating layer away from the semiconductor substrate; a first gating circuit connects the first signal terminal, the second signal terminal, and the first gate layer of the electrostatic protection structure, and is used to connect the first gate layer to the low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

[0021] In one exemplary embodiment of this disclosure, the electrostatic discharge (ESD) protection structure further includes: a second P-type well, a second P-type doped portion, a fourth N-type doped portion, a fifth N-type doped portion, a second gate insulating layer, a second gate layer, a second gating circuit, a third P-type doped portion, and a fourth P-type doped portion. The second P-type well is located within the N-type deep well. The second P-type doped portion is located within the N-type deep well, spaced apart from the first N-type doped portion and the first P-type doped portion, and electrically connected to a first signal terminal of the ESD protection structure. The fourth N-type doped portion is located within the second P-type well and electrically connected to a third signal terminal of the ESD protection structure. A portion of the fifth N-type doped portion is located within the second P-type well, and a portion is located within the N-type deep well. The second gate insulating layer is located on the side of the second P-type well facing away from the semiconductor substrate, and the orthogonal projection of the second gate insulating layer onto the semiconductor substrate is at least... A portion is located between the orthographic projection of the fourth N-type doped portion on the semiconductor substrate and the orthographic projection of the fifth N-type doped portion on the semiconductor substrate; the second gate layer is located on the side of the second gate insulating layer away from the semiconductor substrate; the second gating circuit connects the first signal terminal, the third signal terminal, and the second gate layer of the electrostatic protection structure, and is used to connect the second gate layer to the low-level signal terminal of the first signal terminal and the third signal terminal according to the signals of the first signal terminal and the third signal terminal; the third P-type doped portion is located in the first P-type well, spaced apart from the second N-type doped portion and the third N-type doped portion, and electrically connected to the second signal terminal of the electrostatic protection structure; the fourth P-type doped portion is located in the second P-type well, spaced apart from the fourth N-type doped portion and the fifth N-type doped portion, and electrically connected to the third signal terminal of the electrostatic protection structure.

[0022] In one exemplary embodiment of this disclosure, the first gating circuit includes: a second transistor and a third transistor. The first terminal of the second transistor is connected to the second signal terminal, the second terminal is connected to the first gate layer, and the gate is connected to the first signal terminal. The first terminal of the third transistor is connected to the first signal terminal, the second terminal is connected to the first gate layer, and the gate is connected to the second signal terminal. The second gating circuit includes: a seventh transistor and an eighth transistor. The first terminal of the seventh transistor is connected to the third signal terminal, the second terminal is connected to the second gate layer, and the gate is connected to the first signal terminal. The first terminal of the eighth transistor is connected to the first signal terminal, the second terminal is connected to the second gate layer, and the gate is connected to the third signal terminal. The second, third, seventh, and eighth transistors are all N-type transistors.

[0023] According to one aspect of this disclosure, a chip is provided that includes the electrostatic discharge protection circuit described above.

[0024] According to one aspect of this disclosure, a chip is provided that includes the electrostatic discharge protection structure described above.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 This is a schematic diagram of an exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0028] Figure 2 This is a schematic diagram of another exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0029] Figure 3 This is a schematic diagram of another exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0030] Figure 4 This is a schematic diagram of another exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0031] Figure 5 This is a schematic diagram of another exemplary embodiment of the electrostatic discharge protection circuit disclosed herein;

[0032] Figure 6 This is a top view of an exemplary embodiment of the electrostatic protection structure disclosed herein;

[0033] Figure 7 for Figure 6 The cross-sectional view of the electrostatic protection structure shown along the dashed line AA.

[0034] Figure 8 A top view of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0035] Figure 9 for Figure 8 The cross-sectional view of the electrostatic protection structure shown along the dashed line AA.

[0036] Figure 10 This is a schematic diagram of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0037] Figure 11 A top view of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0038] Figure 12 for Figure 11 The cross-sectional view of the electrostatic protection structure shown along the dashed line AA.

[0039] Figure 13 A top view of another exemplary embodiment of the electrostatic protection structure disclosed herein;

[0040] Figure 14 for Figure 13 The cross-sectional view of the electrostatic protection structure shown along the dashed line AA.

[0041] Figure 15 This is a schematic diagram of the structure in an exemplary embodiment of the present chip;

[0042] Figure 16 This is a schematic diagram of the structure in another exemplary embodiment of the present invention chip. Detailed Implementation

[0043] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0044] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the icon's arrangement is flipped so that it is upside down, the component described as "up" will become the component described as "down." Other relative terms such as "high," "low," "top," "bottom," "left," and "right" also have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally located on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0045] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0046] This exemplary embodiment first provides an electrostatic discharge protection circuit, such as Figure 1The diagram shown is a schematic representation of an exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit includes: a first PNP transistor QN1, a first NPN transistor QP1, and a control circuit 1. The emitter of the first PNP transistor QN1 is connected to a first signal terminal V1, its base is connected to a first node N1, and its collector is connected to a second node N2. The first signal terminal V1 is connected to the first node N1. The emitter of the first NPN transistor QP1 is connected to a second signal terminal V2, its base is connected to the second node N2, and its collector is connected to the first node N1. The control circuit 1 is connected to the first signal terminal V1, the second signal terminal V2, and the first node N1, and is used to connect the low-level signal terminal of the first signal terminal V1 and the second signal terminal V2 to the first node N1 according to the signals from the first signal terminal V1 and the second signal terminal V2.

[0047] like Figure 1 As shown, the control circuit 1 may include: a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 has its first terminal connected to the first node N1, its second terminal connected to the second signal terminal V2, and its gate connected to the fifth node N5. The second transistor T2 has its first terminal connected to the second signal terminal V2, its second terminal connected to the fifth node N5, and its gate connected to the first signal terminal V1. The third transistor T3 has its first terminal connected to the first signal terminal V1, its second terminal connected to the fifth node N5, and its gate connected to the second signal terminal V2. The first transistor T1 is an gg-NMOS (gate-grounded NMOS), and the second transistor T2 and the third transistor T3 are both N-type transistors. The first transistor T1, as an gg-NMOS, contains a parasitic NPN transistor. The first terminal of the first transistor T1 forms the collector of this parasitic NPN transistor, the channel region forms the base of this parasitic NPN transistor, and the second terminal forms the emitter of this parasitic NPN transistor. The second transistor T2 and the third transistor T3 connect the low-potential signal terminals of the first signal terminal V1 and the second signal terminal V2 to the gate of the first transistor T1, so as to ground the gate of the first transistor T1.

[0048] In this exemplary embodiment, when static electricity occurs on the first signal terminal V1, the first signal terminal V1 becomes high-level, while the second signal terminal V2 remains low-level. The second signal terminal V2 inputs a low-level signal to the gate of the first transistor T1, causing the parasitic NPN transistor in the first transistor T1 to conduct firstly, thereby controlling the circuit 1 to connect the second signal terminal V2 to the first node N1. Thus, the first signal terminal V1-first node N1-second signal terminal V2 can form an auxiliary trigger current path for the electrostatic discharge protection circuit. This auxiliary trigger current path allows a potential difference to be formed between the emitter and base of the first PNP transistor QN1 and the first NPN transistor QP1, thereby triggering the first PNP transistor QN1 and the first NPN transistor QP1 to conduct. The conducting first PNP transistor QN1 and the first NPN transistor QP1 form a positive feedback circuit, thereby allowing the electrostatic discharge protection circuit to quickly release the static electricity on the first signal terminal V1 to the second signal terminal V2. Because this electrostatic discharge (ESD) protection circuit can assist in triggering the first PNP transistor QN1 and the first NPN transistor QP1 to conduct via an auxiliary trigger current path, it exhibits a smaller trigger voltage and a faster start-up speed. Furthermore, since the auxiliary trigger current path is only formed when the first signal terminal V1 is high and the second signal terminal V2 is low, the risk of false triggering is reduced, thus enhancing the circuit's stability.

[0049] It should be understood that in other exemplary embodiments, the control circuit 1 may also have other structures, such as Figure 2 The diagram shown is a structural schematic of another exemplary embodiment of the electrostatic discharge protection circuit of this disclosure. The control circuit 1 may include: a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is connected to the second signal terminal V2, the second terminal is connected to the fifth node N5, and the gate is connected to the first signal terminal V1. The first terminal of the sixth transistor T6 is connected to the first signal terminal V1, the second terminal is connected to the fifth node N5, and the gate is connected to the second signal terminal V2. The fifth node N5 is connected to the first node N1, and the fifth transistor T5 and the sixth transistor T6 are N-type transistors.

[0050] In this exemplary embodiment, as Figure 3 The diagram shown is a structural schematic of another exemplary embodiment of the electrostatic discharge protection circuit of this disclosure. Based on Figure 1 The electrostatic discharge protection circuit shown is as follows: Figure 3The electrostatic discharge protection circuit shown may further include: a second PNP transistor QN2 and a second NPN transistor QP2. The emitter of the second PNP transistor QN2 is connected to the second signal terminal V2, the base is connected to the third node N3, and the collector is connected to the fourth node N4. The emitter of the second NPN transistor QP2 is connected to the first signal terminal V1, the base is connected to the fourth node N4, and the collector is connected to the third node N3. The control circuit 1 is also connected to the third node N3 and is used to connect the low-level signal terminal of the first signal terminal V1 and the second signal terminal V2 to the third node N3 according to the signals of the first signal terminal V1 and the second signal terminal V2.

[0051] In this exemplary embodiment, as Figure 3 As shown, the control circuit 1 may include: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The first transistor T1 has its first terminal connected to the first node N1, its second terminal connected to the second signal terminal V2, and its gate connected to the fifth node N5. The second transistor T2 has its first terminal connected to the second signal terminal V2, its second terminal connected to the fifth node N5, and its gate connected to the first signal terminal V1. The third transistor T3 has its first terminal connected to the first signal terminal V1, its second terminal connected to the fifth node N5, and its gate connected to the second signal terminal V2. The fourth transistor T4 has its first terminal connected to the third node N3, its second terminal connected to the first signal terminal V1, and its gate connected to the fifth node N5. The first transistor T1 and the fourth transistor T4 are both g-NMOS transistors, and the second transistor T2 and the third transistor T3 are both N-type transistors. In this gg-NMOS transistor, the first transistor T1 contains a parasitic NPN transistor. The first terminal of the first transistor T1 forms the collector of this parasitic NPN transistor, the channel region forms its base, and the second terminal forms its emitter. Similarly, the fourth transistor T4 contains another parasitic NPN transistor. The first terminal of the fourth transistor T4 forms its collector, the channel region forms its base, and the second terminal forms its emitter. The second transistor T2 and the third transistor T3 connect the low-potential signal terminals of the first signal terminal V1 and the second signal terminal V2 to the fifth node N5, thus grounding the gates of the first transistor T1 and the fourth transistor T4.

[0052] In this exemplary embodiment, when static electricity occurs on the second signal terminal V2, the second signal terminal V2 becomes high, while the first signal terminal V1 remains low. The first signal terminal V1 inputs a low-level signal to the gate of the fourth transistor T4, causing the parasitic NPN transistor in the fourth transistor T4 to conduct first, thereby controlling the circuit 1 to connect the first signal terminal V1 to the third node N3. Thus, the second signal terminal V2-the third node N3-the first signal terminal V1 can form an auxiliary trigger current path for the electrostatic discharge protection circuit. This auxiliary trigger current path allows a potential difference to be formed between the emitter and base of the second PNP transistor QN2 and the second NPN transistor QP2, thereby triggering the second PNP transistor QN2 and the second NPN transistor QP2 to conduct. The conducting second PNP transistor QN2 and the second NPN transistor QP2 form a positive feedback circuit, thereby allowing the electrostatic discharge protection circuit to quickly release the static electricity on the second signal terminal V2 to the first signal terminal V1. This electrostatic discharge protection circuit can achieve bidirectional electrostatic discharge from the first signal terminal V1 and the second signal terminal V2.

[0053] like Figure 1 , 2 As shown in Figure 3, the electrostatic protection circuit may further include a first resistor R1, which is connected between the first signal terminal V1 and the first node N1. Figure 3 As shown, the electrostatic discharge protection circuit may further include a second resistor R2, which can be connected between the second signal terminal V2 and the third node N3. The first resistor R1 increases the voltage difference between the first signal terminal V1 and the first node N1 when the auxiliary trigger current path is conducting, thereby increasing the turn-on speed of the first PNP transistor QN1. The second resistor R2 increases the voltage difference between the second signal terminal V2 and the third node N3 when the auxiliary trigger current path is conducting, thereby increasing the turn-on speed of the second PNP transistor QN2.

[0054] It should be understood that in other exemplary embodiments, the first resistor R1 and the second resistor R2 can be replaced with other components with resistors, for example, the first resistor R1 and the second resistor R2 can be replaced with diodes. Furthermore, in other exemplary embodiments, the second node N2 can also be connected to the second signal terminal V2, and the fourth node N4 can also be connected to the first signal terminal V1. For example, as... Figure 4The diagram shown is a structural schematic of another exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit may include: a first PNP transistor QN1, a first NPN transistor QP1, a second PNP transistor QN2, a second NPN transistor QP2, a second diode D2, a third diode D3, and a control circuit 1. The emitter of the first PNP transistor QN1 is connected to a first signal terminal V1, the base is connected to a first node N1, and the collector is connected to a second node N2; the emitter of the first NPN transistor QP1 is connected to a second signal terminal V2, the base is connected to the second node N2, and the collector is connected to the first node N1; the second PNP transistor QN1... The emitter of a first NPN transistor QN2 is connected to the second signal terminal V2, the base is connected to the third node N3, and the collector is connected to the fourth node N4; the emitter of a second NPN transistor QP2 is connected to the first signal terminal V1, the base is connected to the fourth node N4, and the collector is connected to the third node N3; wherein, the third node N3 is connected to the first node N1; the anode of a second diode D2 is connected to the first signal terminal V1, and the cathode is connected to the first node N1; the anode of a third diode D3 is connected to the second signal terminal V2, and the cathode is connected to the third node N3. A control circuit 1 is connected to the first signal terminal V1, the second signal terminal V2, and the first node N1, and is used to connect the low-level signal terminal of the first signal terminal V1 and the second signal terminal V2 to the first node N1 according to the signals from the first signal terminal V1 and the second signal terminal V2.

[0055] In this exemplary embodiment, as Figure 4 As shown, the control circuit 1 may include: a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is connected to the second signal terminal V2, the second terminal is connected to the fifth node N5, and the gate is connected to the first signal terminal V1. The first terminal of the sixth transistor T6 is connected to the first signal terminal V1, the second terminal is connected to the fifth node N5, and the gate is connected to the second signal terminal V2. The fifth node N5 is connected to the first node N1, and the fifth transistor T5 and the sixth transistor T6 are N-type transistors.

[0056] In this exemplary embodiment, when static electricity occurs on the first signal terminal V1, the first signal terminal V1 becomes high, while the second signal terminal V2 remains low. The control circuit 1 connects the second signal terminal V2 to the first node N1. Thus, the first signal terminal V1 - first node N1 - second signal terminal V2 can form an auxiliary trigger current path for the electrostatic discharge protection circuit. This auxiliary trigger current path allows a potential difference to be formed between the emitter and base of the first PNP transistor QN1 and the first NPN transistor QP1, thereby triggering the first PNP transistor QN1 and the first NPN transistor QP1 to conduct. The conducting first PNP transistor QN1 and the first NPN transistor QP1 form a positive feedback circuit, allowing the electrostatic discharge protection circuit to quickly release static electricity from the first signal terminal V1 to the second signal terminal V2. When static electricity occurs on the second signal terminal V2, the second signal terminal V2 becomes high, while the first signal terminal V1 remains low. The control circuit 1 connects the first signal terminal V1 to the third node N3. Thus, the second signal terminal V2 - the third node N3 - the first signal terminal V1 can form an auxiliary trigger current path for this electrostatic discharge (ESD) protection circuit. This auxiliary trigger current path allows a potential difference to be formed between the emitter and base of the second PNP transistor QN2 and the second NPN transistor QP2, thereby triggering the conduction of the second PNP transistor QN2 and the second NPN transistor QP2. The conducting second PNP transistor QN2 and the second NPN transistor QP2 form a positive feedback circuit, thereby enabling the ESD protection circuit to quickly release the static electricity on the second signal terminal V2 to the first signal terminal V1. This ESD protection circuit can achieve bidirectional ESD release between the first signal terminal V1 and the second signal terminal V2.

[0057] In this exemplary embodiment, as Figure 4 As shown, the electrostatic discharge (ESD) protection circuit may further include: at least one first diode D1, which is connected in series between the first node N1 and the fifth node N5, with the first node N1 connected to the anode of the first diode D1 and the fifth node N5 connected to the cathode of the first diode D1. When ESD occurs at the first signal terminal V1, the series-connected first diodes D1 can increase the voltage difference between the second signal terminal V2 and the first node N1 when the auxiliary trigger current path is turned on, thereby increasing the turn-on speed of the first NPN transistor QP1. When ESD occurs at the second signal terminal V2, the series-connected first diodes D1 can increase the voltage difference between the first signal terminal V1 and the third node N3 when the auxiliary trigger current path is turned on, thereby increasing the turn-on speed of the second NPN transistor QP2.

[0058] like Figure 4As shown, the electrostatic protection circuit may also include a third resistor R3 and a fourth resistor R4. The third resistor R3 may be connected between the second signal terminal V2 and the second node N2, and the fourth resistor R4 may be connected between the first signal terminal V1 and the fourth node N4.

[0059] In this exemplary embodiment, as Figure 5 The diagram shown is a schematic representation of another exemplary embodiment of the electrostatic discharge (ESD) protection circuit of this disclosure. The ESD protection circuit may include: a first PNP transistor QN1, a first NPN transistor QP1, a second PNP transistor QN2, a second NPN transistor QP2, a fourth diode D4, a fifth diode D5, and a control circuit 1. The emitter of the first PNP transistor QN1 is connected to the first signal terminal V1, the base is connected to the first node N1, and the collector is connected to the second node N2; the emitter of the first NPN transistor QP1 is connected to the second signal terminal V2, the base is connected to the second node N2, and the collector is connected to the first node N1. The anode of the fourth diode D4 is connected to the second signal terminal V2, and the cathode is connected to the first signal terminal V1. The emitter of the second PNP transistor QN2 is connected to the first signal terminal V1, the base is connected to the third node N3, and the collector is connected to the fourth node N4; the emitter of the second NPN transistor QP2 is connected to the third signal terminal V3, the base is connected to the fourth node N4, and the collector is connected to the third node N3. The anode of the fifth diode D5 is connected to the third signal terminal V3, and the cathode is connected to the first signal terminal V1. Control circuit 1 is connected to the first signal terminal V1, the second signal terminal V2, the third signal terminal V3, the first node N1, and the third node N3. It is used to connect the low-level signal terminals of the first signal terminals V1 and V2 to the first node N1 based on the signals from the first signal terminals V1 and V2, and to connect the low-level signal terminals of the first signal terminals V1 and V3 to the third node N3 based on the signals from the first signal terminals V1 and V3.

[0060] In this exemplary embodiment, the first PNP transistor QN1 and the first NPN transistor QP1 can form an electrostatic discharge path from the first signal terminal V1 to the second signal terminal V2, and the fourth diode D4 can form an electrostatic discharge path from the second signal terminal V2 to the first signal terminal V1. The second PNP transistor QN2 and the second NPN transistor QP2 can form an electrostatic discharge path from the first signal terminal V1 to the third signal terminal V3, and the fifth diode D5 can form an electrostatic discharge path from the third signal terminal V3 to the first signal terminal V1.

[0061] In this exemplary embodiment, as Figure 5As shown, the electrostatic discharge circuit may further include: a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first resistor R1 may be connected between the first signal terminal V1 and the first node N1, the second resistor R2 may be connected between the first signal terminal V1 and the third node N3, the third resistor R3 may be connected between the second signal terminal V2 and the second node N2, and the fourth resistor R4 may be connected between the third signal terminal V3 and the fourth node N4.

[0062] In this exemplary embodiment, as Figure 5 As shown, the control circuit 1 may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a seventh transistor T7, and an eighth transistor T8. The first transistor T1 has its first terminal connected to the first node N1, its second terminal connected to the second signal terminal V2, and its gate connected to the fifth node N5; the second transistor T2 has its first terminal connected to the second signal terminal V2, its second terminal connected to the fifth node N5, and its gate connected to the first signal terminal V1; the third transistor T3 has its first terminal connected to the first signal terminal V1, its second terminal connected to the fifth node N5, and its gate connected to the second signal terminal V2; the fourth transistor T4 has its first terminal connected to the third node N3, its second terminal connected to the third signal terminal V3, and its gate connected to the sixth node N6; the seventh transistor T7 has its first terminal connected to the third signal terminal V3, its second terminal connected to the sixth node N6, and its gate connected to the first signal terminal V1; the eighth transistor T8 has its first terminal connected to the first signal terminal V1, its second terminal connected to the sixth node, and its gate connected to the third signal terminal V3; wherein, the first transistor T1 and the fourth transistor T4 can both be g-NMOS, and the second transistor T2, the third transistor T3, the seventh transistor T7, and the eighth transistor T8 can all be N-type transistors. A parasitic NPN transistor is parasitic in the first transistor T1 of the gg-NMOS. The first terminal of the first transistor T1 forms the collector of the parasitic NPN transistor, the channel region forms the base of the parasitic NPN transistor, and the second terminal forms the emitter of the parasitic NPN transistor. Another parasitic NPN transistor is parasitic in the fourth transistor T4 of the gg-NMOS. The first terminal of the fourth transistor T4 forms the collector of the parasitic NPN transistor, the channel region forms the base of the parasitic NPN transistor, and the second terminal forms the emitter of the parasitic NPN transistor.

[0063] This exemplary embodiment also provides an electrostatic protection structure, such as Figure 6 , 7 As shown, Figure 6 This is a top view of an exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 7 for Figure 6The diagram shows a cross-sectional view of the electrostatic discharge (ESD) protection structure along the dashed line AA. The ESD protection structure may include: a semiconductor substrate Sub, a first P-type well PW1, a first N-type well NW1, a first P-type doped portion P1, a first N-type doped portion N1, a second N-type doped portion N2, a third N-type doped portion N3, a first gate insulating layer 3, a first gate layer 4, and a gating circuit CR. The first P-type well PW1 is located within the semiconductor substrate Sub; the first N-type well NW1 is located within the semiconductor substrate Sub; the first P-type doped portion P1 is located within the first N-type well NW1 and is electrically connected to the first signal terminal V1 of the ESD protection structure; the first N-type doped portion N1 is located within the first N-type well NW1 and is spaced apart from the first P-type doped portion P1, and is electrically connected to the first signal terminal V1 of the ESD protection structure; the second N-type doped portion N2 is located within the first P-type well PW1 and is electrically connected to the second signal terminal V2 of the ESD protection structure. A portion of the third N-type doped portion N3 is located within the first P-type well PW1, and a portion is located within the first N-type well NW1. The first gate insulating layer 3 is located on the side of the first P-type well PW1 facing away from the semiconductor substrate Sub, and the orthographic projection of the first gate insulating layer 3 onto the semiconductor substrate Sub is at least partially located between the orthographic projection of the third N-type doped portion N3 onto the semiconductor substrate Sub and the orthographic projection of the second N-type doped portion N2 onto the semiconductor substrate Sub. The first gate layer 4 is located on the side of the first gate insulating layer 3 facing away from the semiconductor substrate Sub. The gating circuit CR connects the first signal terminal V1, the second signal terminal V2, and the first gate layer 4 of the electrostatic protection structure, and is used to connect the first gate layer 4 to the low-level signal terminal of the first signal terminal V1 and the second signal terminal V2 according to the signals from the first signal terminal V1 and the second signal terminal V2. The first gate layer may include one or more conductive layers; for example, the first gate layer may include a copper layer, a molybdenum layer, etc. The semiconductor substrate Sub can be either a P-type semiconductor or an N-type semiconductor.

[0064] This electrostatic protection structure can be formed Figure 1The electrostatic discharge (ESD) protection circuit is shown. The first P-type doped portion P1 forms the emitter of the first PNP transistor QN1, the first N-type well NW1 forms the base of the first PNP transistor QN1, and the first P-type well PW1 forms the collector of the first PNP transistor QN1. The second N-type doped portion N2 forms the emitter of the first NPN transistor QP1, the first P-type well PW1 forms the base of the first NPN transistor QP1, and the first N-type well NW1 forms the collector of the first NPN transistor QP1. A portion 71 of the first P-type well PW1 located below the first gate layer 4 forms the channel region of the first transistor T1, the first gate layer 4 forms the gate of the first transistor T1, the third N-type doped portion N3 forms the first electrode of the first transistor, and the second N-type doped portion N2 forms the second electrode of the first transistor. Simultaneously, the third N-type doped portion N3 can form the collector of the parasitic NPN transistor in the first transistor T1, a portion of the structure 71 of the first P-type well PW1 can form the base of the parasitic NPN transistor in the first transistor T1, and the second N-type doped portion N2 can form the emitter of the parasitic NPN transistor in the first transistor T1. When the gate voltage of the first transistor T1 is low, a large number of holes accumulate in the portion of the structure 71 of the first P-type well PW1, allowing the parasitic NPN transistor in the first transistor T1 to conduct at a lower trigger voltage. It should be noted that the doping concentration of the portion of the structure 71 of the first P-type well PW1 can be greater than the doping concentration of the first P-type well PW1 itself; this setting can reduce the impedance of the parasitic NPN transistor in the first transistor T1. The first N-type well NW1 itself can also have a first resistor R1.

[0065] In this exemplary embodiment, the gating circuit CR may include: such as Figure 1 The second transistor T2 and the third transistor T3 are shown. The first terminal of the second transistor T2 is connected to the second signal terminal V2, the second terminal is connected to the first gate layer 4, and the gate is connected to the first signal terminal V1; the first terminal of the third transistor T3 is connected to the first signal terminal V1, the second terminal is connected to the first gate layer 4, and the gate is connected to the second signal terminal V2; wherein, the second transistor T2 and the third transistor T3 are both N-type transistors.

[0066] like Figure 8 , 9 As shown, Figure 8 This is a top view of another exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 9 for Figure 8 The diagram shows a cross-sectional view of the electrostatic protection structure along the dashed line AA. Figure 6 , 7Based on the electrostatic discharge (ESD) protection structure shown, the ESD protection structure may further include: a second N-type well NW2, a second P-type doped portion P2, a fourth N-type doped portion N4, a fifth N-type doped portion N5, a sixth N-type doped portion N6, a second gate insulating layer 5, and a second gate layer 6. The second N-type well NW2 is located on the side of the first P-type well PW1 away from the first N-type well NW1; the second P-type doped portion P2 is located within the second N-type well NW2 and is electrically connected to the second signal terminal V2 of the ESD protection structure; the fourth N-type doped portion N4 is located within the second N-type well NW2, spaced apart from the second P-type doped portion P2, and is electrically connected to the second signal terminal V2 of the ESD protection structure; the fifth N-type doped portion N5 is located within the first P-type well PW1, spaced apart from the second N-type doped portion N2, and is electrically connected to the first signal terminal V1 of the ESD protection structure; part of the sixth N-type doped portion N6 is located within the first P-type well PW1, and part is located within the second N-type well NW2. Inside; the second gate insulating layer 5 is located on the side of the first P-type well PW1 away from the semiconductor substrate Sub, and the orthogonal projection of the second gate insulating layer 5 on the semiconductor substrate Sub is at least partially located between the orthogonal projection of the fifth N-type doped part N5 on the semiconductor substrate Sub and the orthogonal projection of the sixth N-type doped part N6 on the semiconductor substrate Sub; the second gate layer 6 is located on the side of the second gate insulating layer 5 away from the semiconductor substrate Sub; the gating circuit CR can also be connected to the second gate layer 6 for connecting the second gate layer 6 to the low-level signal terminal of the first signal terminal V1 and the second signal terminal V2 according to the signals of the first signal terminal V1 and the second signal terminal V2.

[0067] Figure 8 The electrostatic protection structure shown can be formed Figure 3The electrostatic discharge (ESD) protection circuit is shown. The second P-type doped portion P2 forms the emitter of the second PNP transistor QN2, the second N-type well NW2 forms the base of the second PNP transistor QN2, and the first P-type well PW1 forms the collector of the second PNP transistor QN2. The fifth N-type doped portion N5 forms the emitter of the second NPN transistor QP2, the first P-type well PW1 forms the base of the second NPN transistor QP2, and the second N-type well NW2 forms the collector of the second NPN transistor QP2. A portion 72 of the first P-type well PW1 located below the second gate layer 6 forms the channel region of the fourth transistor T4, the second gate layer 6 forms the gate of the fourth transistor T4, the sixth N-type doped portion N6 forms the first electrode of the fourth transistor T4, and the fifth N-type doped portion N5 forms the second electrode of the fourth transistor. Simultaneously, the sixth N-type doped portion N6 can form the collector of the parasitic NPN transistor in the fourth transistor T4, a portion of the structure 72 of the first P-type well PW1 can form the base of the parasitic NPN transistor in the fourth transistor T4, and the fifth N-type doped portion N5 can form the emitter of the parasitic NPN transistor in the fourth transistor T4. When the gate voltage of the fourth transistor T4 is low, a large number of holes accumulate in the portion of the structure 72 of the first P-type well PW1, allowing the parasitic NPN transistor in the fourth transistor T4 to conduct at a lower trigger voltage. It should be noted that the doping concentration of the portion of the structure 72 of the first P-type well PW1 can be greater than the doping concentration of the first P-type well PW1 itself; this setting can reduce the impedance of the parasitic NPN transistor in the fourth transistor T4. The second N-type well NW2 itself can also have a second resistor R2.

[0068] like Figure 10 The diagram shown is a structural schematic of another exemplary embodiment of the electrostatic protection structure of this disclosure. Figure 10 The electrostatic protection structure shown is Figure 9 Compared to the electrostatic protection structure shown, Figure 10 The electrostatic protection structure shown can be equipped with two gating circuits CR, which provide drive signals to the first gate layer 4 and the second gate layer 6 respectively.

[0069] like Figure 11 , 12 As shown, Figure 11 This is a top view of another exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 12 for Figure 11The diagram shows a cross-sectional view of the electrostatic discharge (ESD) protection structure along the dashed line AA. The ESD protection structure may include: a semiconductor substrate Sub, a first P-type well PW1, a first N-type well NW1, a second doped well XW, a first P-type doped portion P1, a first N-type doped portion N1, a second N-type doped portion N2, a second P-type doped portion P2, a third N-type doped portion N3, and a gating circuit CR. The first P-type well PW1 is located within the semiconductor substrate Sub; the first N-type well NW1 is located within the semiconductor substrate Sub; the second doped well XW is located within the semiconductor substrate Sub; the first P-type doped portion P1 is located within the first N-type well NW1 and is electrically connected to the first signal terminal V1 of the ESD protection structure; the first N-type doped portion N1 is located within the first N-type well NW1 and is connected to the first signal terminal V1 of the ESD protection structure. A P-type doped portion P1 is spaced apart; a second N-type doped portion N2 is located within the first P-type well PW1 and electrically connected to the second signal terminal V2 of the electrostatic protection structure; a second P-type doped portion P2 is located within the second doped well XW and electrically connected to the first N-type doped portion N1; a third N-type doped portion N3 is located within the second doped well XW and spaced apart from the second P-type doped portion P2; a gating circuit CR connects the first signal terminal V1, the second signal terminal V2, and the third N-type doped portion N3 of the electrostatic protection structure, and is used to connect the third N-type doped portion N3 to the low-level signal terminal of the first signal terminal V1 and the second signal terminal V2 according to the signals of the first signal terminal V1 and the second signal terminal V2. The semiconductor substrate Sub can be either a P-type semiconductor or an N-type semiconductor.

[0070] In this exemplary embodiment, as Figure 11 , 12As shown, the electrostatic discharge (ESD) protection structure may include a plurality of second doped wells XW, a plurality of second P-type doped portions P2, and a plurality of third N-type doped portions N3; the plurality of second doped wells XW are spaced apart, and the plurality of second P-type doped portions P2 are arranged in a one-to-one correspondence with the plurality of second doped wells XW, with each second P-type doped portion P2 located within its corresponding second doped well XW; the plurality of third N-type doped portions N3 are arranged in a one-to-one correspondence with the plurality of second doped wells XW, with each third N-type doped portion N3 located within its corresponding second doped well XW; the first N-type doped portion N1 is electrically connected to the plurality of second doped wells XW. Any one of the second P-type doped portions P2; a plurality of second doped wells XW are connected in series via the second P-type doped portion P2 and the third N-type doped portion N3 located therein, and in two adjacent connected second doped wells XW, the second P-type doped portion P2 and the third N-type doped portion N3 located in different second doped wells XW are electrically connected; the plurality of second doped wells XW includes a tail second doped well XW, the tail second doped well XW is connected to the first N-type doped portion N1 through the remaining second doped wells XW, and the gating circuit is connected to the third N-type doped portion N3 in the tail second doped well XW.

[0071] In this exemplary embodiment, as Figure 11 , 12 As shown, the electrostatic discharge (ESD) protection structure may further include: a third P-type well PW3, a second N-type well NW2, a third P-type doped portion P3, a fourth N-type doped portion N4, a fifth N-type doped portion N5, a fourth P-type doped portion P4, and a fifth P-type doped portion P5. The third P-type well PW3 is located within the semiconductor substrate Sub and between the first P-type well PW1 and the second doped well XW. The second N-type well NW2 is located within the semiconductor substrate Sub and between the third P-type well PW3 and the second doped well XW. The third P-type doped portion P3 is located within the second N-type well NW2 and is electrically connected to the second signal terminal V2 of the ESD protection structure. The fourth N-type doped portion N4... The fourth N-type doped part N4 is located within the second N-type well NW2 and is spaced apart from the third P-type doped part P3. The fifth N-type doped part N5 is located within the third P-type well PW3 and is electrically connected to the first signal terminal V1 of the electrostatic protection structure. The fourth P-type doped part P4 is located within the third P-type well PW3 and is spaced apart from the fifth N-type doped part N5. The fifth P-type doped part P5 is located within the first P-type well PW1 and is spaced apart from the second N-type doped part N2. The fifth P-type doped part P5 is located within the first P-type well PW1 and is spaced apart from the second N-type doped part N2. The fifth P-type doped part P5 is electrically connected to the second signal terminal V2 of the electrostatic protection structure.

[0072] Figure 11The electrostatic protection structure shown can be formed Figure 4 The electrostatic discharge (ESD) protection circuit shown includes a first P-type doped portion P1 forming the emitter of a first PNP transistor QN1, a first N-type well NW1 forming the base of the first PNP transistor QN1, and a first P-type well PW1 forming the collector of the first PNP transistor QN1. A second N-type doped portion N2 forming the emitter of a first NPN transistor QP1, a first P-type well PW1 forming the base of the first NPN transistor QP1, and a first N-type well NW1 forming the collector of the first NPN transistor QP1. The first P-type doped portion P1 forming the anode of a second diode D2, and the first N-type doped portion N1 forming the cathode of the second diode D2. The third P-type doped portion P3 can be used to form the emitter of the second PNP transistor QN2, the second N-type well NW2 can be used to form the base of the second PNP transistor QN2, and the third P-type well PW3 can be used to form the collector of the second PNP transistor QN2. The fifth N-type doped portion N5 can be used to form the emitter of the second NPN transistor QP2, the third P-type well PW3 can be used to form the base of the second NPN transistor QP2, and the second N-type well NW2 can be used to form the collector of the second NPN transistor QP2. The third P-type doped portion P3 can be used to form the anode of the third diode D3, and the fourth N-type doped portion N4 can be used to form the cathode of the third diode D3. The first P-type well PW1 can itself have a third resistor R3, the third P-type well PW3 can itself have a fourth resistor R4, the first N-type well NW1 can itself have a first resistor R1, and the second N-type well NW2 can itself have a second resistor R2. The second P-type doped part P2 can be used to form the anode of the first diode D1, and the third N-type doped part N3 can be used to form the cathode of the first diode D1.

[0073] It should be understood that the fifth P-type doped part P5 is used for connection. Figure 4 The second signal terminal V2 and the second node N2, and the fourth P-type doped part P4 are used for connection. Figure 4 The first signal terminal V1 and the fourth node in the example. In other exemplary embodiments, Figure 4 The second signal terminal V2 and the second node N2 in the electrostatic protection circuit shown can also be left unconnected. Correspondingly, Figure 11 The electrostatic protection structure shown may also omit the fifth P-type doped part P5. Figure 4 The first signal terminal V1 and the fourth node in the electrostatic protection circuit shown can also be left unconnected. Correspondingly, Figure 11 The electrostatic protection structure shown may also omit the fourth P-type doped portion P4. In this exemplary embodiment, the second doped well XW can be either a P-type well or an N-type well. Furthermore, Figure 11The electrostatic discharge protection structure shown can also omit the third P-type well PW3, the second N-type well NW2, the third P-type doped section P3, the fourth N-type doped section N4, the fifth N-type doped section N5, and the fourth P-type doped section P4. Correspondingly, Figure 11 The remaining structure of the electrostatic protection structure shown can form a unidirectional electrostatic discharge circuit.

[0074] In this exemplary embodiment, the gating circuit CR may include: such as Figure 4 The fifth and sixth transistors shown have the following configurations: the first terminal of the fifth transistor is connected to the second signal terminal, the second terminal is connected to the third N-type doped region, and the gate is connected to the first signal terminal; the first terminal of the sixth transistor is connected to the first signal terminal, the second terminal is connected to the third N-type doped region, and the gate is connected to the second signal terminal; wherein, the fifth node is connected to the first node, and the fifth and sixth transistors are N-type transistors.

[0075] In this exemplary embodiment, as Figure 13 , 14 As shown, Figure 13 This is a top view of another exemplary embodiment of the electrostatic protection structure disclosed herein. Figure 14 for Figure 13The diagram shows a cross-sectional view of the electrostatic discharge (ESD) protection structure along the dashed line AA. The ESD protection structure may include: a semiconductor substrate Sub, a first P-type well PW1, an N-type deep well DNW, a first N-type well NW1, a first P-type doped portion P1, a first N-type doped portion N1, a second N-type doped portion N2, a third N-type doped portion N3, a first gate insulating layer 3, a first gate layer 4, and a first gating circuit CR1. A first P-type well PW1 is located within the semiconductor substrate Sub; an N-type deep well DNW is located within the semiconductor substrate Sub; a first N-type well NW1 is located within the semiconductor substrate Sub, with a portion of the first N-type well NW1 situated between the N-type deep well DNW and the first P-type well PW1, and a portion of the first N-type well NW1 situated within the N-type deep well DNW; a first P-type doped portion P1 is located within the N-type deep well DNW and electrically connected to the first signal terminal V1 of the electrostatic protection structure; a first N-type doped portion N1 is located within the N-type deep well DNW, spaced apart from the first P-type doped portion P1, and electrically connected to the first signal terminal V1 of the electrostatic protection structure; a second N-type doped portion N2 is located within the first P-type well PW1 and electrically connected to the second signal terminal V2 of the electrostatic protection structure; a portion of the third N-type doped portion N3 is situated within the first P-type deep well PW1. The first gate insulating layer 3 is located within the P-type well PW1 and partially within the first N-type well NW1; the first gate insulating layer 3 is located on the side of the first P-type well PW1 away from the semiconductor substrate Sub, and the orthogonal projection of the first gate insulating layer 3 on the semiconductor substrate Sub is at least partially located between the orthogonal projection of the third N-type doped portion N3 on the semiconductor substrate Sub and the orthogonal projection of the second N-type doped portion N2 on the semiconductor substrate Sub; the first gate layer 4 is located on the side of the first gate insulating layer 3 away from the semiconductor substrate Sub; the first gating circuit CR1 connects the first signal terminal V1, the second signal terminal V2, and the first gate layer 4 of the electrostatic protection structure, and is used to connect the first gate layer 4 to the low-level signal terminal of the first signal terminal V1 and the second signal terminal V2 according to the signals of the first signal terminal V1 and the second signal terminal V2.

[0076] In this exemplary embodiment, as Figure 13 , 14As shown, the electrostatic protection structure may further include: a second P-type well PW2, a second P-type doped portion P2, a fourth N-type doped portion N4, a fifth N-type doped portion N5, a second gate insulating layer 5, a second gate layer 6, a second gating circuit CR2, a third P-type doped portion P3, and a fourth P-type doped portion P4. The second P-type well PW2 is located within the N-type deep well DNW; the second P-type doped portion P2 is located within the N-type deep well DNW, spaced apart from the first N-type doped portion N1 and the first P-type doped portion P1, and electrically connected to the first signal terminal V1 of the electrostatic protection structure; the fourth N-type doped portion N4 is located within the second P-type well PW2 and electrically connected to the third signal terminal V3 of the electrostatic protection structure; a portion of the fifth N-type doped portion N5 is located within the second P-type well PW2, and a portion is located within the N-type deep well DNW; the second gate insulating layer 5 is located on the side of the second P-type well PW2 facing away from the semiconductor substrate Sub, and the orthographic projection of the second gate insulating layer 5 on the semiconductor substrate Sub is at least partially located on the orthographic projection of the fourth N-type doped portion N4 on the semiconductor substrate Sub and the orthographic projection of the fifth N-type doped portion N5 on the semiconductor substrate Sub. Between the orthogonal projections on the Sub; the second gate layer 6 is located on the side of the second gate insulating layer 5 facing away from the semiconductor substrate Sub; the second gating circuit CR2 connects the first signal terminal V1, the third signal terminal V3, and the second gate layer 6 of the electrostatic protection structure, and is used to connect the second gate layer 6 to the low-level signal terminal of the first signal terminal V1 and the third signal terminal V3 according to the signals of the first signal terminal V1 and the third signal terminal V3; the third P-type doped part P3 is located in the first P-type well PW1, spaced apart from the second N-type doped part N2 and the third N-type doped part N3, and is electrically connected to the second signal terminal V2 of the electrostatic protection structure; the fourth P-type doped part P4 is located in the second P-type well PW2, spaced apart from the fourth N-type doped part N4 and the fifth N-type doped part N5, and is electrically connected to the third signal terminal V3 of the electrostatic protection structure.

[0077] Figure 13 The electrostatic protection structure shown can be formed Figure 5The electrostatic discharge (ESD) protection circuit is shown. In this circuit, the first P-type doped portion P1 forms the emitter of a first PNP transistor QN1, the N-type deep well DNW forms the base of QN1, and the first P-type well PW1 forms the collector. Similarly, the second N-type doped portion N2 forms the emitter of a first NPN transistor QP1, the first P-type well PW1 forms the base, and the N-type deep well DNW forms the collector. Likewise, the second P-type doped portion P2 forms the emitter of a second PNP transistor QN2, the N-type deep well DNW forms the base, and the second P-type well PW2 forms the collector. The fourth N-type doped portion N4 can be used to form the emitter of the second NPN transistor QP2, the second P-type well PW2 can be used to form the base of the second NPN transistor QP2, and the N-type deep well DNW can be used to form the collector of the second NPN transistor QP2. The third P-type doped portion P3 can be used to form the anode of the fourth diode D4, and the first N-type doped portion N1 can be used to form the cathode of the fourth diode D4. The fourth P-type doped portion P4 can be used to form the anode of the fifth diode D5, and the first N-type doped portion N1 can be used to form the cathode of the fifth diode D5. A portion 71 of the first P-type well PW1 located below the first gate layer 4 can be used to form the channel region of the first transistor T1. The first gate layer 4 can be used to form the gate of the first transistor T1. The third N-type doped portion N3 can form the collector of the parasitic NPN transistor in the first transistor T1. The portion 71 of the first P-type well PW1 can form the base of the parasitic NPN transistor in the first transistor T1. The second N-type doped portion N2 can form the emitter of the parasitic NPN transistor in the first transistor T1. When the gate voltage of the first transistor T1 is low, a large number of holes accumulate in the portion 71 of the first P-type well PW1, allowing the parasitic NPN transistor in the first transistor T1 to conduct at a lower trigger voltage. It should be noted that the doping concentration of the portion 71 of the first P-type well PW1 can be greater than the doping concentration of the first P-type well PW1 itself; this setting can reduce the impedance of the parasitic NPN transistor in the first transistor T1. The portion 72 of the second P-type well PW2 located below the second gate layer 6 can be used to form the channel region of the fourth transistor T4, and the second gate layer 6 can be used to form the gate of the fourth transistor T4. The fifth N-type doped portion N5 can form the collector of the parasitic NPN transistor in the fourth transistor T4, the portion 72 of the second P-type well PW2 can form the base of the parasitic NPN transistor in the fourth transistor T4, and the fourth N-type doped portion N4 can form the emitter of the parasitic NPN transistor in the fourth transistor T4.When the gate voltage of the fourth transistor T4 is low, a large number of holes accumulate in a portion of structure 72 of the second P-type well PW2, allowing the parasitic NPN transistor in the fourth transistor T4 to conduct at a lower trigger voltage. It should be noted that the doping concentration of the portion of structure 72 of the second P-type well PW2 can be greater than the doping concentration of the second P-type well PW2 itself; this setting can reduce the impedance of the parasitic NPN transistor in the fourth transistor T4. Furthermore, the first P-type well PW1 can have a third resistor R3, the N-type deep well DNW can have a first resistor R1 and a second resistor R2, and the second P-type well PW2 can have a fourth resistor R4.

[0078] In this exemplary embodiment, the first gating circuit CR1 may include: Figure 5 The second transistor and the third transistor shown have their first terminal connected to the second signal terminal, their second terminal connected to the first gate layer, and their gate connected to the first signal terminal; the first terminal of the third transistor is connected to the first signal terminal, its second terminal connected to the first gate layer, and its gate connected to the second signal terminal. The second gating circuit CR2 may include: Figure 5 The seventh and eighth transistors shown have their first terminal connected to the third signal terminal, their second terminal connected to the second gate layer, and their gate connected to the first signal terminal; the eighth transistor has its first terminal connected to the first signal terminal, its second terminal connected to the second gate layer, and its gate connected to the third signal terminal; wherein the second, third, seventh, and eighth transistors are all N-type transistors.

[0079] It should be understood that in other exemplary embodiments, Figure 13 The electrostatic discharge (ESD) protection structure shown may also omit the second P-type well PW2, the second P-type doped portion P2, the fourth N-type doped portion N4, the fifth N-type doped portion N5, the second gate insulating layer 5, the second gate layer 6, the second gating circuit CR2, and the fourth P-type doped portion P4. Correspondingly, Figure 13 The remaining structure of the electrostatic protection structure shown can form a bidirectional electrostatic discharge circuit connected between the first signal terminal V1 and the second signal terminal V2.

[0080] It should be noted that, in the above exemplary embodiments, the doping concentration of the N-type doped portion (e.g., the first N-type doped portion) is greater than the doping concentration of the N-type doped well (e.g., the first N-type doped well). The doping concentration of the P-type doped portion (e.g., the first P-type doped portion) is greater than the doping concentration of the P-type doped well (e.g., the first P-type doped well). Furthermore, in the above exemplary embodiments, the relative positional relationships of the doped portions within the same doped well can be as follows: Figure 6-14 As shown. It should be understood that in other exemplary embodiments, the relative positional relationship of the doped portions in the same doped well may be configured in other ways.

[0081] This exemplary embodiment also provides a chip that may include the electrostatic discharge protection junction circuit described above. For example... Figure 15 The diagram shown is a structural schematic of an exemplary embodiment of the present chip. The chip includes a high-level power supply terminal VDD, a low-level power supply terminal VSS, a signal transmission terminal I / O, and internal circuitry 7. The chip may also include... Figure 1 , 2 Any of the electrostatic protection circuits shown in 3 and 4. For example... Figure 15 As shown, the chip may include three electrostatic discharge (ESD) protection circuits 81, 82, and 83. The first signal terminal V1 of ESD protection circuit 81 can be connected to a signal transmission I / O terminal, and the second signal terminal V2 of ESD protection circuit 81 can be connected to a high-level power supply terminal VDD. The first signal terminal V1 of ESD protection circuit 82 can be connected to a low-level power supply terminal VSS, and the second signal terminal V2 of ESD protection circuit 82 can be connected to a signal transmission I / O terminal. The first signal terminal V1 of ESD protection circuit 83 can be connected to a low-level power supply terminal VSS, and the second signal terminal V2 of ESD protection circuit 83 can be connected to a high-level power supply terminal VDD. Figure 16 The diagram shown is a structural schematic of another exemplary embodiment of this chip. The chip may include a high-level power supply terminal VDD, a low-level power supply terminal VSS, a signal transmission terminal I / O, internal circuitry 7, and... Figure 5 The electrostatic discharge (ESD) protection circuit 8 is shown. The first signal terminal V1 of the ESD protection circuit 8 can be connected to the high-level power supply terminal VDD, the second signal terminal V2 can be connected to the signal transmission terminal I / O, and the third signal terminal V3 can be connected to the low-level power supply terminal VSS. This chip can be any chip, such as a memory chip, and the signal transmission terminal can be either a signal input terminal or a signal output terminal.

[0082] This exemplary embodiment also provides a chip including the electrostatic discharge (ESD) protection structure described above. The chip may also include a high-level power supply terminal VDD, a low-level power supply terminal VSS, a signal transmission terminal (I / O), and internal circuitry 7. The connection method between the signal terminal and the ESD protection structure in this chip can be the same as the connection method between the signal terminal and the ESD protection circuit in the aforementioned chip.

[0083] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0084] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. An electrostatic discharge protection circuit, characterized in that, The electrostatic protection circuit includes: The first PNP transistor has its emitter connected to a first signal terminal, its base connected to a first node, and its collector connected to a second node, wherein the first signal terminal is connected to the first node; The first NPN transistor has its emitter connected to the second signal terminal, its base connected to the second node, and its collector connected to the first node. A control circuit, connected to the first signal terminal, the second signal terminal, and the first node, is used to connect the low-level signal terminal of the first signal terminal and the second signal terminal to the first node according to the signals of the first signal terminal and the second signal terminal. The second PNP transistor has its emitter connected to the second signal terminal, its base connected to the third node, and its collector connected to the fourth node. The second NPN transistor has its emitter connected to the first signal terminal, its base connected to the fourth node, and its collector connected to the third node. The control circuit is also connected to the third node, and is used to connect the low-level signal terminal of the first signal terminal and the second signal terminal to the third node according to the signals of the first signal terminal and the second signal terminal.

2. The electrostatic discharge protection circuit according to claim 1, characterized in that, The control circuit includes: The first transistor has a first terminal connected to the first node, a second terminal connected to the second signal terminal, and a gate connected to the fifth node. The second transistor has its first terminal connected to the second signal terminal, its second terminal connected to the fifth node, and its gate connected to the first signal terminal. The third transistor has its first terminal connected to the first signal terminal, its second terminal connected to the fifth node, and its gate connected to the second signal terminal. The fourth transistor has its first terminal connected to the third node, its second terminal connected to the first signal terminal, and its gate connected to the fifth node. The first and fourth transistors are both gg-NMOS, and the second and third transistors are both N-type transistors.

3. The electrostatic discharge protection circuit according to claim 1, characterized in that, The control circuit includes: The fifth transistor has its first terminal connected to the second signal terminal, its second terminal connected to the fifth node, and its gate connected to the first signal terminal. The sixth transistor has its first terminal connected to the first signal terminal, its second terminal connected to the fifth node, and its gate connected to the second signal terminal. The fifth node is connected to the first node, and the fifth transistor and the sixth transistor are N-type transistors.

4. The electrostatic protection circuit according to claim 3, characterized in that, The electrostatic protection circuit also includes: At least one first diode is connected in series between the first node and the fifth node, with the first node connected to the anode of the first diode and the fifth node connected to the cathode of the first diode.

5. The electrostatic discharge protection circuit according to claim 4, characterized in that, The electrostatic protection circuit also includes: The second PNP transistor has its emitter connected to the second signal terminal, its base connected to the third node, and its collector connected to the fourth node. The second NPN transistor has its emitter connected to the first signal terminal, its base connected to the fourth node, and its collector connected to the third node. The third node is connected to the first node; The second diode has its anode connected to the first signal terminal and its cathode connected to the first node. The third diode has its anode connected to the second signal terminal and its cathode connected to the third node.

6. The electrostatic discharge protection circuit according to claim 1, characterized in that, The electrostatic protection circuit also includes: The fourth diode has its anode connected to the second signal terminal and its cathode connected to the first signal terminal. The second PNP transistor has its emitter connected to the first signal terminal, its base connected to the third node, and its collector connected to the fourth node. The second NPN transistor has its emitter connected to the third signal terminal, its base connected to the fourth node, and its collector connected to the third node. The fifth diode has its anode connected to the third signal terminal and its cathode connected to the first signal terminal. The control circuit is also connected to the third node and is used to connect the low-level signal terminal of the first signal terminal and the third signal terminal to the third node according to the signals of the first signal terminal and the third signal terminal.

7. The electrostatic discharge protection circuit according to claim 6, characterized in that, The control circuit includes: The first transistor has a first terminal connected to the first node, a second terminal connected to the second signal terminal, and a gate connected to the fifth node. The second transistor has its first terminal connected to the second signal terminal, its second terminal connected to the fifth node, and its gate connected to the first signal terminal. The third transistor has its first terminal connected to the first signal terminal, its second terminal connected to the fifth node, and its gate connected to the second signal terminal. The fourth transistor has its first terminal connected to the third node, its second terminal connected to the third signal terminal, and its gate connected to the sixth node. The seventh transistor has its first terminal connected to the third signal terminal, its second terminal connected to the sixth node, and its gate connected to the first signal terminal. The eighth transistor has its first terminal connected to the first signal terminal, its second terminal connected to the sixth node, and its gate connected to the third signal terminal. Among them, the first transistor and the fourth transistor are both gg-NMOS, and the second transistor, the third transistor, the seventh transistor, and the eighth transistor are all N-type transistors.

8. An electrostatic protection structure, characterized in that, The electrostatic protection structure includes the electrostatic protection circuit as described in claim 1, wherein the electrostatic protection structure comprises: Semiconductor substrate; A first P-type well is located within the semiconductor substrate; A first N-type well is located within the semiconductor substrate; The first P-type doped portion is located inside the first N-type well and is electrically connected to the first signal terminal of the electrostatic protection structure. The first N-type doped portion is located in the first N-type well, spaced apart from the first P-type doped portion, and electrically connected to the first signal terminal of the electrostatic protection structure. The second N-type doped portion is located within the first P-type well and is electrically connected to the second signal terminal of the electrostatic protection structure. The third N-type doped portion is partially located within the first P-type well and partially located within the first N-type well; A first gate insulating layer is located on the side of the first P-type well away from the semiconductor substrate, and the orthographic projection of the first gate insulating layer on the semiconductor substrate is at least partially located between the orthographic projection of the third N-type doped portion on the semiconductor substrate and the orthographic projection of the second N-type doped portion on the semiconductor substrate. The first gate layer is located on the side of the first gate insulating layer that is away from the semiconductor substrate; A selection circuit is connected to the first signal terminal, the second signal terminal, and the first gate layer of the electrostatic protection structure, and is used to connect the first gate layer to the low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

9. The electrostatic protection structure according to claim 8, characterized in that, The electrostatic protection structure also includes: The second N-type well is located on the side of the first P-type well that is away from the first N-type well; The second P-type doped portion is located within the second N-type well and is electrically connected to the second signal terminal of the electrostatic protection structure. The fourth N-type doped portion is located within the second N-type well, spaced apart from the second P-type doped portion, and electrically connected to the second signal terminal of the electrostatic protection structure; The fifth N-type doped section is located in the first P-type well, spaced apart from the second N-type doped section, and electrically connected to the first signal terminal of the electrostatic protection structure; The sixth N-type doped portion is partially located within the first P-type well and partially located within the second N-type well; The second gate insulating layer is located on the side of the first P-type well away from the semiconductor substrate, and the orthogonal projection of the second gate insulating layer on the semiconductor substrate is at least partially located between the orthogonal projection of the fifth N-type doped portion on the semiconductor substrate and the orthogonal projection of the sixth N-type doped portion on the semiconductor substrate. The second gate layer is located on the side of the second gate insulating layer that is away from the semiconductor substrate; The gating circuit is also connected to the second gate layer, and is used to connect the second gate layer to the low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

10. The electrostatic protection structure according to claim 9, characterized in that, The gating circuit includes: The second transistor has a first terminal connected to the second signal terminal, a second terminal connected to the first gate layer and the second gate layer, and a gate connected to the first signal terminal. The third transistor has a first terminal connected to the first signal terminal, a second terminal connected to the first gate layer and the second gate layer, and a gate connected to the second signal terminal.

11. An electrostatic protection structure, characterized in that, The electrostatic protection structure includes the electrostatic protection circuit as described in claim 1, wherein the electrostatic protection structure comprises: Semiconductor substrate; A first P-type well is located within the semiconductor substrate; A first N-type well is located within the semiconductor substrate; A second doped well is located within the semiconductor substrate; The first P-type doped portion is located inside the first N-type well and is electrically connected to the first signal terminal of the electrostatic protection structure. The first N-type doped portion is located within the first N-type well and is spaced apart from the first P-type doped portion; The second N-type doped portion is located within the first P-type well and is electrically connected to the second signal terminal of the electrostatic protection structure. The second P-type doped portion is located within the second doped well and is electrically connected to the first N-type doped portion; The third N-type doped portion is located within the second doped well and is spaced apart from the second P-type doped portion; A selection circuit is connected to the first signal terminal, the second signal terminal, and the third N-type doped part of the electrostatic protection structure, and is used to connect the third N-type doped part to the low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

12. The electrostatic protection structure according to claim 11, characterized in that, The electrostatic protection structure includes a plurality of second doped wells, a plurality of second P-type doped portions, and a plurality of third N-type doped portions; Multiple second doped wells are spaced apart, and multiple second P-type doped portions are arranged in one-to-one correspondence with multiple second doped wells, with the second P-type doped portions located in their corresponding second doped wells; Each of the third N-type doped portions is disposed in a one-to-one correspondence with a plurality of second doped wells, and the third N-type doped portion is located in the corresponding second doped well; The first N-type doped portion is electrically connected to any one of the plurality of second P-type doped portions; Multiple second doped wells are connected in series via second P-type doped portions and third N-type doped portions located therein. In two adjacent connected second doped wells, the second P-type doped portions and third N-type doped portions located in different second doped wells are electrically connected. The plurality of second doped wells include a tail second doped well, which is connected to the first N-type doped section through the remaining second doped wells, and the gating circuit is connected to a third N-type doped section in the tail second doped well.

13. The electrostatic protection structure according to claim 11, characterized in that, The electrostatic protection structure also includes: The third P-type well is located within the semiconductor substrate and between the first P-type well and the second doped well; The second N-type well is located within the semiconductor substrate and between the third P-type well and the second doped well; The third P-type doped portion is located within the second N-type well and is electrically connected to the second signal terminal of the electrostatic protection structure. The fourth N-type doped portion is located within the second N-type well and is spaced apart from the third P-type doped portion. The fourth N-type doped portion is electrically connected to the first N-type doped portion. The fifth N-type doped section is located inside the third P-type well, and the fifth N-type doped section is electrically connected to the first signal terminal of the electrostatic protection structure. The fourth P-type doped section is located within the third P-type well, spaced apart from the fifth N-type doped section, and electrically connected to the first signal terminal of the electrostatic protection structure. The fifth P-type doped portion is located within the first P-type well, spaced apart from the second N-type doped portion, and electrically connected to the second signal terminal of the electrostatic protection structure.

14. The electrostatic protection structure according to claim 11, characterized in that, The gating circuit includes: The fifth transistor has its first terminal connected to the second signal terminal, its second terminal connected to the third N-type doped portion, and its gate connected to the first signal terminal. The sixth transistor has its first terminal connected to the first signal terminal, its second terminal connected to the third N-type doped portion, and its gate connected to the second signal terminal. The fifth node is connected to the first node, and the fifth transistor and the sixth transistor are N-type transistors.

15. An electrostatic protection structure, characterized in that, The electrostatic protection structure includes the electrostatic protection circuit as described in claim 1, wherein the electrostatic protection structure comprises: Semiconductor substrate; A first P-type well is located within the semiconductor substrate; An N-type deep well is located within the semiconductor substrate; The first N-type well is located within the semiconductor substrate, partially between the N-type deep well and the first P-type well, and partially within the N-type deep well; The first P-type doped portion is located inside the N-type deep well and is electrically connected to the first signal terminal of the electrostatic protection structure. The first N-type doped portion is located in the N-type deep well, spaced apart from the first P-type doped portion, and electrically connected to the first signal terminal of the electrostatic protection structure; The second N-type doped portion is located within the first P-type well and is electrically connected to the second signal terminal of the electrostatic protection structure. The third N-type doped portion is partially located within the first P-type well and partially located within the first N-type well; A first gate insulating layer is located on the side of the first P-type well away from the semiconductor substrate, and the orthographic projection of the first gate insulating layer on the semiconductor substrate is at least partially located between the orthographic projection of the third N-type doped portion on the semiconductor substrate and the orthographic projection of the second N-type doped portion on the semiconductor substrate. The first gate layer is located on the side of the first gate insulating layer that is away from the semiconductor substrate; A first gating circuit is connected to the first signal terminal, the second signal terminal, and the first gate layer of the electrostatic protection structure, and is used to connect the first gate layer to the low-level signal terminal of the first signal terminal and the second signal terminal according to the signals of the first signal terminal and the second signal terminal.

16. The electrostatic protection structure according to claim 15, characterized in that, The electrostatic protection structure also includes: The second P-type well is located inside the N-type deep well; The second P-type doped portion is located in the N-type deep well, spaced apart from the first N-type doped portion and the first P-type doped portion, and is electrically connected to the first signal terminal of the electrostatic protection structure. The fourth N-type doped section is located inside the second P-type well and is electrically connected to the third signal terminal of the electrostatic protection structure; The fifth N-type doped portion is partially located within the second P-type well and partially located within the N-type deep well; The second gate insulating layer is located on the side of the second P-type well away from the semiconductor substrate, and the orthogonal projection of the second gate insulating layer on the semiconductor substrate is at least partially located between the orthogonal projection of the fourth N-type doped portion on the semiconductor substrate and the orthogonal projection of the fifth N-type doped portion on the semiconductor substrate. The second gate layer is located on the side of the second gate insulating layer that is away from the semiconductor substrate; The second gating circuit is connected to the first signal terminal, the third signal terminal, and the second gate layer of the electrostatic protection structure, and is used to connect the second gate layer to the low-level signal terminal of the first signal terminal and the third signal terminal according to the signals of the first signal terminal and the third signal terminal. The third P-type doped portion is located in the first P-type well, spaced apart from the second N-type doped portion and the third N-type doped portion, and is electrically connected to the second signal terminal of the electrostatic protection structure; The fourth P-type doped portion is located within the second P-type well, spaced apart from the fourth N-type doped portion and the fifth N-type doped portion, and is electrically connected to the third signal terminal of the electrostatic protection structure.

17. The electrostatic protection structure according to claim 16, characterized in that, The first gating circuit includes: The second transistor has a first terminal connected to the second signal terminal, a second terminal connected to the first gate layer, and a gate connected to the first signal terminal. The third transistor has a first terminal connected to the first signal terminal, a second terminal connected to the first gate layer, and a gate connected to the second signal terminal. The second gating circuit includes: The seventh transistor has its first terminal connected to the third signal terminal, its second terminal connected to the second gate layer, and its gate connected to the first signal terminal. The eighth transistor has its first terminal connected to the first signal terminal, its second terminal connected to the second gate layer, and its gate connected to the third signal terminal. Among them, the second transistor, the third transistor, the seventh transistor, and the eighth transistor are all N-type transistors.

18. A chip, characterized in that, Includes the electrostatic protection circuit as described in any one of claims 1-7.

19. A chip, characterized in that, Includes the electrostatic protection structure as described in any one of claims 8-17.

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