Three-dimensional memory and its fabrication method

Abstract

This application provides a three-dimensional memory and a method for fabricating the same. The method for fabricating the three-dimensional memory includes: forming a stacked structure along a first direction, wherein a plurality of channel structures are penetrated through the stacked structure; forming a top select gate cutout along a second direction penetrating the stacked structure, wherein the channel structures are distributed on both sides of the top select gate cutout, the second direction being perpendicular to the first direction; and forming a fill layer within the top select gate cutout, wherein the fill layer has at least partially exposed conductive layers.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method. Background Technology

[0002] In recent years, with the rapid development of integrated circuit technology, people have increasingly higher requirements for the performance of memory in integrated circuits. 3D NAND is an emerging memory device that overcomes the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage cells. It can achieve excellent precision, support high storage capacity in a small space, and thus effectively reduce cost and energy consumption.

[0003] In 3D NAND fabrication, a stacked structure is typically formed, within which a channel array with storage functionality is created. This channel array, along with the stacked structure, is divided into multiple parts by gate line slots formed in subsequent processes. In a conventional 3D NAND structure, a nine-row channel structure (referred to as a "9-hole channel array") is positioned between two gate line slots. These nine rows of channels correspond to a top select gate (TSG) and are divided into two parts by a top select gate cutout to form different core blocks in subsequent processes. The top select gate cutout is typically filled with an insulating oxide material and can be used as a barrier channel for the top select gate.

[0004] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0005] This application provides a method for fabricating a three-dimensional memory. The method includes: forming a stacked structure along a first direction, wherein a plurality of channel structures are penetrated through the stacked structure; forming a top select gate cutout along a second direction penetrating the stacked structure, wherein the channel structures are distributed on both sides of the top select gate cutout, the second direction being perpendicular to the first direction; and forming a fill layer within the top select gate cutout, wherein the fill layer has at least partially exposed conductive layers.

[0006] In one embodiment, the stacked structure has a first surface, the top selection gate cutout is located on the side of the stacked structure near the first surface, and the step of forming the fill layer includes: sequentially forming an insulating layer, an adhesive layer, and a conductive layer within the top selection gate cutout, wherein the side of the conductive layer near the first surface is exposed.

[0007] In one embodiment, a plurality of the channel structures are arranged in rows parallel to the second direction, and the method further includes: forming a grid line slot through the stacked structure, wherein the grid line slot divides the stacked structure into a plurality of stacked portions, and the number of rows of the channel structures located between the grid line slot and the adjacent top select gate cutout is the same as the number of rows of the channel structures located between each pair of adjacent top select gate cutouts.

[0008] In one embodiment, each of the stacked portions includes a core region and a step region, the channel structure is located in the core region, and the step region is covered with a step region dielectric layer, wherein the step of forming the top selection gate cutout includes: removing a portion of the core region and removing a portion of the step region dielectric layer to form the top selection gate cutout.

[0009] In one embodiment, the method further includes: removing a portion of the filling layer located in the core region to form a void, and filling the void with an etch stop layer, wherein a portion of the conductive layer located in the step region dielectric layer is exposed.

[0010] In one embodiment, the channel structure has a functional layer and a channel layer, wherein the top selected gate cut-out penetrates the functional layer of the adjacent channel structure and exposes at least a portion of the channel layer, wherein, during the formation of the fill layer, the insulating layer covers the exposed portion of the channel layer.

[0011] In one embodiment, the filling layer includes: a first filling layer portion located in the step region and a second filling layer portion located in the core region, wherein the maximum dimension of the first filling layer portion along a third direction is greater than the maximum dimension of the second filling layer portion in the same direction, wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0012] In one embodiment, the method further includes: forming a channel contact portion on the side of the channel structure near the etch stop layer, wherein the channel contact portion contacts the channel structure, or a portion of the channel contact portion contacts the channel structure and another portion contacts the etch stop layer.

[0013] This application also provides a three-dimensional memory, comprising: a stacked structure; a plurality of channel structures extending through a portion of the stacked structure along a first direction; and a filling layer extending through the stacked structure along a second direction and having a conductive layer, wherein the first direction and the second direction are perpendicular.

[0014] In one embodiment, a plurality of the channel structures are arranged in rows parallel to the second direction, the number of the fill layers includes a plurality, and the three-dimensional memory further includes: a gate wire slot structure penetrating the stacked structure, wherein the number of rows of the channel structures located between the gate wire slot structure and the adjacent fill layer is the same as the number of rows of the channel structures located between pairs of adjacent fill layers.

[0015] In one embodiment, the filler layer includes an insulating layer, an adhesive layer, and a conductive layer, wherein the conductive layer is located on the side of the insulating layer away from the channel structure, and the adhesive layer is located between the conductive layer and the insulating layer.

[0016] In one embodiment, the channel structure has a functional layer and a channel layer, and the filling layer penetrates the functional layer and contacts the channel layer.

[0017] In one embodiment, the stacked structure includes a core region and a stepped region, the portion of the stacked structure located in the core region having the channel structure through it, the portion located in the stepped region being covered by a stepped region dielectric layer, and the filler layer having the portion of the stacked structure located in the core region and extending into the stepped region dielectric layer.

[0018] In one embodiment, the filling layer includes: a first filling layer portion located in the step region and a second filling layer portion located in the core region, wherein the maximum dimension of the first filling layer portion along a third direction is greater than the maximum dimension of the second filling layer portion in the same direction, wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0019] In one embodiment, the second filling layer portion includes an end and a connecting portion, the connecting portion connecting the end and the first filling layer portion, the conductive layer extending from the second filling layer portion to the end, and the maximum dimension of the end along the third direction being greater than the maximum dimension of the second filling layer portion in the same direction.

[0020] In one embodiment, the three-dimensional memory further includes: an etch stop layer covering the first fill layer portion; and a channel contact portion located on the side of the channel structure near the etch stop layer, wherein the channel contact portion contacts the channel structure, or a portion of the channel contact portion contacts the channel structure and another portion contacts the etch stop layer.

[0021] In one embodiment, the three-dimensional memory further includes a conductive contact portion connected to a conductive layer within the end portion.

[0022] The three-dimensional memory and its fabrication method provided in this application can have at least one of the following beneficial effects:

[0023] According to some embodiments of this application, forming a fill layer with an insulating layer and a conductive layer in the top selected gate cutout can effectively suppress current leakage and intrinsic leakage caused by coupling between memory strings.

[0024] According to some embodiments of this application, increasing the end size of the top selection grid cutout can improve the landing displacement problem of the conductive post connected thereto.

[0025] According to some embodiments of this application, covering the fill layer with an etch stop layer can prevent short circuits between the conductive material in the fill layer and the channel contact due to displacement of the channel contact. Attached Figure Description

[0026] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0027] Figures 1 to 5 These are schematic diagrams illustrating the fabrication process of three-dimensional memory in some implementation methods;

[0028] Figure 6 These are schematic diagrams of a three-dimensional memory according to embodiments of this application under different operating states;

[0029] Figure 7 A flowchart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application is shown schematically; and

[0030] Figures 8 to 17 This is a schematic diagram of the fabrication method of a three-dimensional memory according to an exemplary embodiment of this application. Detailed Implementation

[0031] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first portion of the top selection gate cutout discussed in this application may also be referred to as the second portion of the top selection gate cutout, and the first direction may also be referred to as the second direction, and vice versa.

[0033] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the laminated structure depicted in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar expressions used herein are used as terms of approximation, not as terms of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0034] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0035] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] The features, principles and other aspects of this application are described in detail below.

[0038] Figure 1 This is a schematic diagram of the fabrication process of a three-dimensional memory according to some implementation methods. Figure 2 yes Figure 1 A sectional view along section AA. (e.g.) Figure 1 and Figure 2As shown, a stacked structure 120 perpendicular or substantially perpendicular to the substrate 110 can be formed on the substrate 110. The stacked structure 120 can be divided into multiple stacked portions by gate line slots 130. Exemplarily, multiple channel structures 140 extending through the stacked structure 120 and into the substrate 110 can be formed, as well as top select gate cutouts 150 located between the channel structures 140. The channel structures 140 along... x The channels are arranged in rows, and multiple rows form a channel array. In some embodiments, the grid slot 130 can divide the 9 rows of channels into independent parts to form a 9-hole channel array, and the top selected grid cutout 150 can be located in the 5th row of the 9 rows of channels.

[0039] The inventors of this application discovered that 3D NAND with a 9-channel array structure in y There are multiple grid line slots 130 in the direction, and the top selected grid cutout is located on the 5th row of channels, both of which make... y The density of the effective channel structure 140 in the direction is reduced. With the development of integrated circuits, there is a desire to obtain three-dimensional memories with higher integration density and larger storage capacity in a smaller space, thus requiring the formation of more row channels between the two gate gaps. To improve... y Regarding the density of the effective channel structure 140 in the directional direction, the industry has successively proposed layout methods for channel arrays with 12, 16, 20, or even more holes, as well as wavy top selection grid cutouts. However, the wavy top selection grid cutout requires a reduction in the critical dimensions of the channel structure 140, which will pose a challenge to the fabrication of channel structures 140 with higher layers.

[0040] The inventors of this application also discovered that, as Figures 3 to 5 As shown, in some embodiments, channel arrays with 12, 16, 20, or even more holes can be formed. Due to the small spacing between adjacent rows of channel structures, the formed top select gate cutout 210 cuts off a portion of the adjacent rows of channel structures 220, thus disrupting the integrity of the channel structure 220 and transforming it from a ring gate structure into a gate structure resembling an "Ω". During the formation of the top select gate cutout 210, due to process limitations, the top select gate cutout 210 often cuts into the channel layer within the channel structure 220. If this channel layer is not completely cut off, on the one hand, the charge control capability of the channel structure 220 with the Ω gate structure is weaker than that of the channel structure 220' with the ring gate structure, and the intrinsic current leakage is higher than that of the channel structure 220'. On the other hand, for example, when performing a read operation on a memory string of a three-dimensional memory, the top select gate voltage of the unselected memory string 302 is coupled to the selected memory string 301 (e.g., ...). Figure 5 (a) and Figure 5 As shown by the dashed circle in (b) of the diagram, where Figure 5 (b) in the middle is Figure 5(The equivalent circuit diagram corresponding to (a) in the diagram) causes this part of the channel to open, increasing the leakage current. It should be noted that the memory string described in this application may include multiple memory cell transistors, where the memory cell is part of the channel structure 220 and is formed at the intersection of the gate layer and the channel structure 220. The gate gap structure and the top select gate structure can jointly divide the memory into multiple slice memories. The channel structure 220 with the Ω gate structure located in two adjacent slice memories and the memory cells at the intersection of the same gate layer respectively form memory strings 301 and 302.

[0041] This application proposes a three-dimensional memory and a method for manufacturing the same, which can at least partially improve or solve the above-mentioned problems. While increasing the effective channel structure density, it can suppress current leakage and intrinsic leakage caused by coupling between memory strings. Figure 6 These are schematic diagrams of the three-dimensional memory according to embodiments of this application under different operating states, such as... Figure 6 As shown, during the read operation (such as...) Figure 6 As shown in (a) above, a turn-on voltage V can be applied to the selected memory string 301. pass V pass For example, at 6.5V, the voltage on the unselected memory string 302 can remain at 0V. During programming operations (such as...) Figure 6 As shown in (b)), a power supply voltage Vcc can be applied to the selected memory string 301, while the voltage on the unselected memory string 302 remains at 0V. During the erase operation (e.g....), Figure 6 As shown in (c), the voltage on the selected memory string 301 and the unselected memory string 302 can be kept dynamically changing.

[0042] Figure 7 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an embodiment of this application. For example... Figure 7 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, comprising:

[0043] Step S1100: A stacked structure is formed along the first direction, wherein a plurality of channel structures are penetrated in the stacked structure.

[0044] Step S1200: A top selection gate cutout is formed along a second direction through the stacked structure, wherein channel structures are distributed on both sides of the top selection gate cutout, and the second direction is perpendicular to the first direction; and

[0045] Step S1300: A fill layer is formed within the top selected gate cutout, wherein the fill layer has at least partially exposed conductive layers.

[0046] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some steps shown may be performed simultaneously or in a manner different from [the steps described in the original text]. Figure 7 The execution is performed in the order shown.

[0047] Figures 8 to 17 This is a schematic diagram of the fabrication method 1000 of the three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 8 to 17 The above steps S1100 to S1300 are further described.

[0048] Step S1100: A stacked structure is formed along a first direction, wherein multiple channels are penetrated through the stacked structure. structure.

[0049] like Figure 8 As shown, in step S1100, a stacked structure 320 may be formed on the substrate 310. The stacked structure 320 may be formed by alternating layers of dielectric layer 321 and sacrificial layer 322. In some embodiments, the material of the substrate 310 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. In some embodiments, the substrate 310 may include a substrate 311 and a composite layer 312 located on the substrate 311, wherein the substrate 311 has a certain thickness and can serve as a structural support for the device structure (e.g., the stacked structure 320) formed thereon. In other embodiments, the substrate 310 is located below the stacked structure 320, and a semiconductor layer may be formed on the upper side of the stacked structure 320, and the substrate 310 will be completely removed.

[0050] In some embodiments, the stacked structure 320 may be included in a direction perpendicular to or substantially perpendicular to the substrate 210. z Multiple dielectric layers 321 and multiple sacrificial layers 322 are alternately stacked in the same etching direction (first direction). Under the same etching conditions, the sacrificial layer 322 and the dielectric layer 321 can have a high etching selectivity so that when the sacrificial layer 322 is removed in a subsequent process, the dielectric layer 221 is hardly removed. In some examples, the material used for the sacrificial layer 222 includes, for example, silicon nitride, and the material used for the dielectric layer 321 includes silicon oxide.

[0051] For example, a stacked structure 320 may be formed on a substrate 310 by alternately forming a plurality of sacrificial layers 322 and dielectric layers 321 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0052] It should be understood that the number of layers in the stacking structure 320 is not limited to the number shown in the figure. Rather, the number of stacking layers and the stacking height of the stacking structure 320 can be designed according to actual needs. This application does not make any specific limitations in this regard.

[0053] Figure 9 A schematic diagram of the process for forming a channel structure 330 in a three-dimensional memory according to an embodiment of this application, and Figure 10 for Figure 9 A schematic diagram along section BB. (Combined with...) Figure 9 and Figure 10 As shown, multiple channel structures 330 can be formed in the stacked structure 320. In some embodiments, the channel structures 330 are along... x The first direction / second direction is arranged in multiple rows, with the rows parallel to each other; along y The channels are arranged in multiple columns in a direction / third direction, and the columns are parallel to each other. Exemplarily, a method of forming the channel structure 330 may include first forming a channel via within the stacked structure 320, and then sequentially forming a barrier layer, a charge trapping layer, a tunneling layer, and a channel layer 331 within the channel via to form the channel structure 330. Exemplarily, the barrier layer, charge trapping layer, and tunneling layer may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. In some examples, the channel layer 331 can be used to transport the desired charge (electrons or holes). The material of the channel layer 331 includes p-type doped polysilicon. The space defined by the channel layer 331 may be filled with a channel filler material, such as silicon oxide or silicon oxynitride. In some embodiments, the channel structure 330 also includes a channel plug 332 that interconnects the channel structure 330 to an external circuit. Exemplarily, the material of the channel plug 332 may include polysilicon.

[0054] For example, a barrier layer, a charge trapping layer, and a tunneling layer may be deposited sequentially using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof), after which a channel layer 331 may be deposited on the side of the tunneling layer away from the channel hole.

[0055] In some embodiments, a stepped structure is also included. Optionally, a patterned mask is used from the top side of the stacked structure 320 (along...) z (Direction) Repeated etch-trimming processes are performed on dielectric layer 321 and sacrificial layer 322 to form a stepped structure. In some examples, after the stepped structure is formed, the gaps left by etching away a portion of the stacked structure 320 can be filled with insulating material to form a stepped dielectric layer covering the stepped structure within the gaps.

[0056] In some embodiments, gate line slots (not shown) may be formed through the stacked structure 320 and extending into the substrate 310. The gate line slots may be formed by repeated etch-trimming processes, such as photolithography and etching. Exemplarily, the gate line slots may divide the stacked structure 320 into multiple stacked portions, each of which may include, for example, an array of channels with 12, 16, 20, or even more vias. In some embodiments, the sacrificial layer 322 may be removed via the gate line slots, and the gate layer 323 may be filled into the voids formed after the removal of the sacrificial layer 322. The dielectric layer 321 and the gate layer 323 are alternately stacked on the substrate 310 to form a stacked structure 320'. It is understood that the region of the stacked structure 320' with the channel structure 330 may be a core region, and the region where the step structure is located in the stacked structure 320' may be a step region.

[0057] For example, the sacrificial layer 322 may be removed using a wet etching process, and the gate layer 323 may be formed using one or more thin film deposition processes (such as ALD, CVD, PVD or combinations thereof).

[0058] Step S1200: A top selective gate cutout is formed along the second direction through the stacked structure, wherein the channel structure is divided into... The second direction is perpendicular to the first direction, and the two sides of the top selected grid cut are arranged.

[0059] like Figure 11 and Figure 12 As shown, a top selection gate cutout can be formed on the upper side of the stacked structure 320'. The top selection gate cutout may include a first portion 340 and a second portion 350. Exemplarily, the first portion 340 of the top selection gate cutout extends along the stacked structure 320'. x Extending in a direction and parallel to the rows arranged in the channel structure 330. The stacked structure 320' includes along... x The core region and stepped region are arranged in an oriented manner. The portion of the stacked structure 320' located in the core region is penetrated by the channel structure 330, and the portion located in the stepped region is covered by a stepped region dielectric layer (not shown). The first portion 340 of the top selection gate cutout is located in the core region, and the second portion 350 of the top selection gate is located in the stepped region and extends into the stepped region dielectric layer. z It is connected to at least one gate layer 323 in the opposite direction. Figure 12 The top selection gate cutout first section 340 shown is in z It is connected to the three-layer gate layer 323 in the direction.

[0060] In some embodiments, a first portion 340 of the top select gate notch is formed between rows of channel structures 330 and adjoins the channel structures 330 of adjacent rows. Exemplarily, a portion of the upper side of the channel structure 330 may be etched to remove the functional layer portion above it, exposing the channel layer 331. The step of forming the first portion 340 of the top select gate notch further includes etching the stacked structure 320' adjacent to the channel layer 331. It is understood that the exposed portion of the channel layer 331 is located within the first portion 340 of the top select gate notch. Exemplarily, a combination of photolithography and etching processes may be used to repeatedly etch the stacked structure 320' and the channel structure 330 to form the first portion 340 of the top select gate notch.

[0061] In some implementations, the top selected gate cutout first portion 340 is along... x The direction extends through the portion of the stacked structure 320' located within the core region. A top selection gate cutout extends to the portion of the stacked structure 320' located within the stepped region and the portion within the stepped region dielectric layer, forming a second portion 350 of the top selection gate cutout. Exemplarily, the first portion 340 of the top selection gate cutout and the second portion 350 of the top selection gate cutout can be completed in the same process. The second portion 350 of the top selection gate cutout may include an end and a connecting portion, the connecting portion connecting the end and the first portion 340 of the top selection gate cutout. A dimension (along its length) may be formed at its end. y The structure (in the direction) is larger than the size of the first top selection gate notch 340 to facilitate the landing of conductive pillars formed in subsequent processes. For example, the projection shape of the first top selection gate notch 340 on the substrate 310 is rectangular, and the projection shape of the second portion 350 of the top selection gate notch on the substrate 310 is circular, the radius of which is larger than the width of the rectangle (along the direction). y (Direction). Alternatively, the projection shape of the first top selected gate notch 340 onto the substrate 310 is rectangular, and the projection shape of the second portion 350 of the top selected gate notch onto the substrate 310 is a combination of a rectangle and a circle, wherein the radius of the circle is greater than the width of the rectangle (along the direction). y direction).

[0062] Step S1300: A fill layer is formed within the top selected gate cutout, wherein the fill layer has at least partially exposed... Conductive layer.

[0063] Figures 13 to 14 This is a schematic diagram of the process for forming a filling layer 360 in a three-dimensional memory according to an embodiment of this application. (In conjunction with...) Figure 13 and Figure 14 As shown, an insulating layer 361, an adhesive layer 362, and a conductive layer 363 can be sequentially filled into the first portion 340 of the top selectable gate cutout.

[0064] In some embodiments, an insulating layer 361, an adhesive layer 362, and a conductive layer 363 may be sequentially formed on the bottom and sidewalls of the top selected gate cutout first portion 340 using, for example, a thin-film deposition process. Exemplarily, the insulating layer 361 may be made of, for example, silicon oxide or a high-dielectric-constant material to reduce the capacitance of the filler layer 360. The adhesive layer 362 may be made of, for example, titanium, titanium nitride, tantalum, tantalum nitride, or any combination thereof. The conductive layer 363 may be made of, for example, tungsten, cobalt, copper, aluminum, or any combination thereof. The adhesive layer serves two purposes: firstly, it provides deposition sites during the deposition of the conductive layer 363; secondly, it serves to bond the conductive layer 363 to the insulating layer 361.

[0065] For example, a chemical mechanical polishing (CMP) process can be used to polish the upper surface of the filler layer 360 (along... z The direction is flattened. In the context of this invention, some steps, such as flattening, surface cleaning, and slag removal, are omitted from the manufacturing method of the stacked structure 320, the first portion 340 of the top selection grid cutout, etc. These are not the focus of this invention and will not be described in detail here. Those skilled in the art can add or remove steps in the manufacturing method of this invention as needed.

[0066] In some embodiments, a portion of the fill layer 360 is also located within the second portion 350 of the top selection gate cutout, and forms a continuous fill structure with a portion of the fill layer 360 located within the first portion 340 of the top selection gate cutout.

[0067] like Figure 15 As shown, in some embodiments, a portion of the upper side of the filler layer 360 is removed to form a groove, the removed portion being located in the core region. An insulating material can then be filled into the groove to form an etch stop layer 370. Exemplarily, the groove can be formed using, for example, an etching process, and the etch stop layer 370 can be formed using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof). The insulating material filling the groove may, for example, include oxides.

[0068] like Figure 16 As shown, in some embodiments, a word line contact 380 is also formed in the stepped region. Exemplarily, one end of the word line contact 380 may be connected to the gate layer 323 in the stacked structure 320', and the other end may be connected to an external interconnect structure to form an electrical connection.

[0069] like Figure 17As shown, in some embodiments, a channel recess may be formed on the upper side of the stacked structure 320', and a conductive material may be filled within the channel recess to form a channel contact 390. A portion of the channel contact 390 may be located on the channel structure 330 and connected to the channel plug 332, while the remainder of the channel contact 390 is located on the etch stop layer 370. It is understood that the etch stop layer 370 isolates the channel contact 390 from the fill layer 360, preventing short circuits between them. Exemplarily, the other side of the channel contact 390 may be electrically connected to a back-end interconnect structure (Array BEOL) and, based on the back-end interconnect structure, electrically connected to a peripheral circuit wafer.

[0070] In other embodiments, the channel contact portion 390 may be located entirely on the upper side of the channel structure 330 and connected to the channel plug 332. It should be noted that a channel contact portion 390 may be formed on the upper side of each channel structure 330 for connection thereto. Figure 17 The trench contact portion 390 on the trench structure 330 connected to the filler layer 360 is shown only as an example.

[0071] For example, a combination of photolithography and etching processes can be used to form the channel groove, and one or more thin film deposition processes such as ALD, CVD, PVD or combinations thereof can be used to form the channel contact portion 390.

[0072] Another aspect of this application provides a three-dimensional memory. This three-dimensional memory can be fabricated using the fabrication methods described in any of the above embodiments.

[0073] Continue to refer to Figure 16 and Figure 17 The three-dimensional memory includes a stacked structure 320', a plurality of channel structures 330, and a fill layer 360. Exemplarily, the channel structures 330 extend through the stacked structure 320', and the channel structures 330 are arranged parallel to each other and along... x Multiple rows extending in the first / second direction. The fill layer also extends 360 degrees. x The direction extends through the stacked structure 320', and the filling layer 360 contains a conductive layer 363.

[0074] In some embodiments, the number of fill layers 360 includes multiple layers, and the three-dimensional memory also includes gate line slot structures extending through the stack structure 320'. The number of rows of channel structures 330 located between the gate line slot structures and adjacent fill layers 360 is the same as the number of rows of channel structures 330 located between pairs of adjacent fill layers 360. The fill layers 360 and the gate line slot structures can divide the three-dimensional memory into multiple slice memories.

[0075] In some embodiments, the filler layer 360 comprises an insulating layer 361, an adhesive layer 362, and a conductive layer 363 stacked sequentially. The conductive layer 363 is located on the side of the insulating layer 361 away from the channel structure 330, and the adhesive layer 362 is located between the conductive layer 363 and the insulating layer 361. The adhesive layer 362 serves to connect the insulating layer 361 and the conductive layer 363, provides deposition sites during the deposition of the conductive layer 363, and prevents the diffusion of conductive material forming the conductive layer.

[0076] In some embodiments, the channel structure 330 has a functional layer and a channel layer, and a filler layer 360 penetrates the functional layer and contacts the channel layer. The filler layer 360 contains a conductive material that can suppress current leakage caused by voltage coupling in the Ω-gate structure channel structure 330.

[0077] In some embodiments, the laminated structure 320' includes a core region and a stepped region. The portion of the laminated structure 320' located in the core region is penetrated by the channel structure 330, and the portion located in the stepped region is covered by a stepped region dielectric layer. A filler layer 360 penetrates the core region and extends into the stepped region dielectric layer. The portion of the filler layer 360 located in the stepped region is a first filler layer portion, and the portion located in the core region is a second filler layer portion. The first filler layer portion is oriented along a third direction (…). Figure 16 middle y The maximum dimension of the first filling layer portion in the same direction is greater than the maximum dimension of the second filling layer portion in the same direction. The second filling layer portion includes an end and a connecting portion, the connecting portion connecting the end and the first filling layer portion, and the conductive layer 363 can extend from the second filling layer portion to the end. The maximum dimension of the end in a third direction is greater than the maximum dimension of the second filling layer portion in the same direction.

[0078] In some embodiments, the portion of the conductive layer 363 located at the aforementioned end is connected to the conductive contact portion, and the slice memory can be controlled by applying different voltages to the conductive contact portion.

[0079] In some embodiments, the width of the end of the fill layer 360 (along...) y The width of the filler layer 360 is greater than the width of the rest of the filler layer 360 in the direction of the filler layer 360. The projection shape of the end of the filler layer 360 onto the substrate 310 includes a circle or a combination of a rectangle and a circle, and the projection shape of the rest of the filler layer 360 onto the substrate 310, excluding the end, includes a rectangle.

[0080] In some embodiments, the system also includes an etch stop layer covering a portion of the filler layer 360 located within the core region, and a channel contact 390 located on the channel structure 330 and connected to the channel plug 332. In other embodiments, a portion of the channel contact 390 is located on the channel structure 330, and the remainder is located on the etch stop layer.

[0081] In some embodiments, a word line contact is also included, one end of which can be connected to the gate layer 323 in the stacked structure 320', and the other end can be connected to an external interconnect structure.

[0082] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0083] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, comprising: A stacked structure is formed along a first direction, wherein a plurality of channel structures are penetrated in the stacked structure; A top selection gate cutout is formed along a second direction through the stacked structure, wherein the channel structure is distributed on both sides of the top selection gate cutout, and the second direction is perpendicular to the first direction; and A filler layer is formed within the top selected gate cutout, wherein the filler layer has at least a partially exposed conductive layer.

2. The method according to claim 1, wherein, The stacked structure has a first surface, and the top selection gate notch is located on the side of the stacked structure closer to the first surface. The steps for forming the filling layer include: An insulating layer, an adhesive layer, and a conductive layer are sequentially formed within the top selected gate cutout, wherein the side of the conductive layer closest to the first surface is exposed.

3. The method according to claim 2, wherein, The method further includes arranging multiple channel structures in rows parallel to the second direction, and the arrangement of these channel structures in a row. A grid line slot is formed that runs through the stacked structure, wherein the grid line slot divides the stacked structure into multiple stacked portions, and the number of rows of the channel structure located between the grid line slot and the adjacent top select gate cutout is the same as the number of rows of the channel structure located between each pair of adjacent top select gate cutouts.

4. The method according to claim 3, wherein, Each of the stacked portions includes a core region and a stepped region, the channel structure being located in the core region, and the stepped region being covered by a stepped region dielectric layer. The step of forming the top selection grid cutout includes: A portion of the core region and a portion of the step region dielectric layer are removed to form the top selection gate cutout.

5. The method according to claim 4, further comprising: A portion of the filling layer located in the core region is removed to form a void, and an etching stop layer is filled into the void, wherein the portion of the conductive layer located in the step region dielectric layer is exposed.

6. The method according to claim 4, wherein, The channel structure has a functional layer and a channel layer, and the top selected gate cut-out penetrates the functional layer of the adjacent channel structure and exposes at least a portion of the channel layer. During the formation of the fill layer, the insulating layer covers the exposed portion of the channel layer.

7. The method according to claim 4, wherein, The filling layer includes: a first filling layer portion located in the stepped area and a second filling layer portion located in the core area. The maximum dimension of the first filling layer portion along a third direction is greater than the maximum dimension of the second filling layer portion in the same direction, wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

8. The method according to claim 5, further comprising: A channel contact portion is formed on the side of the channel structure near the etching stop layer. The channel contact portion is in contact with the channel structure, or a portion of the channel contact portion is in contact with the channel structure and another portion is in contact with the etching stop layer.

9. A three-dimensional memory, comprising: Layered structure; Multiple channel structures, the channel structures penetrating a portion of the stacked structure along a first direction; as well as The top selected gate cut structure extends through the stacked structure along a second direction and has a conductive layer, wherein the first direction and the second direction are perpendicular.

10. The three-dimensional memory according to claim 9, wherein, The plurality of said channel structures are arranged in rows parallel to the second direction, and the number of said top selection gate cutout structures includes multiple, and The three-dimensional memory also includes: A gate line slot structure running through the stacked structure, wherein the number of rows of the channel structure located between the gate line slot structure and the adjacent top select gate cutout structure is the same as the number of rows of the channel structure located between each pair of adjacent top select gate cutout structures.

11. The three-dimensional memory according to claim 9, wherein, The top selection gate cutout structure includes: An insulating layer, an adhesive layer, and a conductive layer are provided, wherein the conductive layer is located on the side of the insulating layer away from the channel structure, and the adhesive layer is located between the conductive layer and the insulating layer.

12. The three-dimensional memory according to claim 9, wherein, The channel structure has a functional layer and a channel layer, and the top selected gate cutout structure penetrates the functional layer and contacts the channel layer.

13. The three-dimensional memory according to claim 10, wherein, The stacked structure includes a core region and a stepped region. The portion of the stacked structure located in the core region is penetrated by the channel structure, the portion located in the stepped region is covered by a stepped region dielectric layer, and the top selected gate cutout structure penetrates the portion of the stacked structure located in the core region and extends into the stepped region dielectric layer.

14. The three-dimensional memory according to claim 13, wherein, The top selection gate cutout structure includes: a first top selection gate cutout structure portion located in the stepped area and a second top selection gate cutout structure portion located in the core area. The maximum dimension of the first top selection gate cutout structure portion along a third direction is greater than the maximum dimension of the second top selection gate cutout structure portion in the same direction, wherein the third direction is perpendicular to the first direction and perpendicular to the second direction.

15. The three-dimensional memory according to claim 14, wherein, The second top selection gate cutout structure portion includes an end and a connecting portion, the connecting portion connecting the end and the first top selection gate cutout structure portion, the conductive layer extending from the second top selection gate cutout structure portion to the end, and the maximum dimension of the end along the third direction being greater than the maximum dimension of the second top selection gate cutout structure portion in the same direction.

16. The three-dimensional memory according to claim 15, further comprising: An etch stop layer is applied to the first top selected gate cutout structure portion; as well as The channel contact portion is located on the side of the channel structure closest to the etch stop layer. The channel contact portion is in contact with the channel structure, or a portion of the channel contact portion is in contact with the channel structure and another portion is in contact with the etching stop layer.

17. The three-dimensional memory according to claim 15, further comprising: The conductive contact portion is connected to the conductive layer within the end portion.

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